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[PATCH] Simplify migrate_page_add
[linux-2.6/sactl.git] / drivers / serial / 8250_pci.c
blob2a912153321e47345d9e11ea1698467993d41817
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
28
29 #include <asm/byteorder.h>
30 #include <asm/io.h>
31
32 #include "8250.h"
33
34 #undef SERIAL_DEBUG_PCI
35
36 /*
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
40 * < 0 - error
41 */
42 struct pci_serial_quirk {
43 u32 vendor;
44 u32 device;
45 u32 subvendor;
46 u32 subdevice;
47 int (*init)(struct pci_dev *dev);
48 int (*setup)(struct serial_private *, struct pciserial_board *,
49 struct uart_port *, int);
50 void (*exit)(struct pci_dev *dev);
51 };
52
53 #define PCI_NUM_BAR_RESOURCES 6
54
55 struct serial_private {
56 struct pci_dev *dev;
57 unsigned int nr;
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
60 int line[0];
61 };
62
63 static void moan_device(const char *str, struct pci_dev *dev)
64 {
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72 }
73
74 static int
75 setup_port(struct serial_private *priv, struct uart_port *port,
76 int bar, int offset, int regshift)
77 {
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
84 base = pci_resource_start(dev, bar);
85
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
94 port->iotype = UPIO_MEM;
95 port->iobase = 0;
96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
99 } else {
100 port->iotype = UPIO_PORT;
101 port->iobase = base + offset;
102 port->mapbase = 0;
103 port->membase = NULL;
104 port->regshift = 0;
105 }
106 return 0;
107 }
108
109 /*
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
112 */
113 static int
114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
115 struct uart_port *port, int idx)
116 {
117 unsigned int bar, offset = board->first_offset;
118
119 bar = FL_GET_BASE(board->flags);
120 if (idx < 4)
121 bar += idx;
122 else {
123 bar = 4;
124 offset += (idx - 4) * board->uart_offset;
125 }
126
127 return setup_port(priv, port, bar, offset, board->reg_shift);
128 }
129
130 /*
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
136 */
137 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
138 {
139 int rc = 0;
140
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
146 rc = 3;
147 break;
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
149 rc = 2;
150 break;
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
152 rc = 4;
153 break;
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
155 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
156 rc = 1;
157 break;
158 }
159
160 return rc;
161 }
162
163 /*
164 * HP's Diva chip puts the 4th/5th serial port further out, and
165 * some serial ports are supposed to be hidden on certain models.
166 */
167 static int
168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
169 struct uart_port *port, int idx)
170 {
171 unsigned int offset = board->first_offset;
172 unsigned int bar = FL_GET_BASE(board->flags);
173
174 switch (priv->dev->subsystem_device) {
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 if (idx == 3)
177 idx++;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
180 if (idx > 0)
181 idx++;
182 if (idx > 2)
183 idx++;
184 break;
185 }
186 if (idx > 2)
187 offset = 0x18;
188
189 offset += idx * board->uart_offset;
190
191 return setup_port(priv, port, bar, offset, board->reg_shift);
192 }
193
194 /*
195 * Added for EKF Intel i960 serial boards
196 */
197 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
198 {
199 unsigned long oldval;
200
201 if (!(dev->subsystem_device & 0x1000))
202 return -ENODEV;
203
204 /* is firmware started? */
205 pci_read_config_dword(dev, 0x44, (void*) &oldval);
206 if (oldval == 0x00001000L) { /* RESET value */
207 printk(KERN_DEBUG "Local i960 firmware missing");
208 return -ENODEV;
209 }
210 return 0;
211 }
212
213 /*
214 * Some PCI serial cards using the PLX 9050 PCI interface chip require
215 * that the card interrupt be explicitly enabled or disabled. This
216 * seems to be mainly needed on card using the PLX which also use I/O
217 * mapped memory.
218 */
219 static int __devinit pci_plx9050_init(struct pci_dev *dev)
220 {
221 u8 irq_config;
222 void __iomem *p;
223
224 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
225 moan_device("no memory in bar 0", dev);
226 return 0;
227 }
228
229 irq_config = 0x41;
230 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
231 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
232 irq_config = 0x43;
233 }
234 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
235 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
236 /*
237 * As the megawolf cards have the int pins active
238 * high, and have 2 UART chips, both ints must be
239 * enabled on the 9050. Also, the UARTS are set in
240 * 16450 mode by default, so we have to enable the
241 * 16C950 'enhanced' mode so that we can use the
242 * deep FIFOs
243 */
244 irq_config = 0x5b;
245 }
246
247 /*
248 * enable/disable interrupts
249 */
250 p = ioremap(pci_resource_start(dev, 0), 0x80);
251 if (p == NULL)
252 return -ENOMEM;
253 writel(irq_config, p + 0x4c);
254
255 /*
256 * Read the register back to ensure that it took effect.
257 */
258 readl(p + 0x4c);
259 iounmap(p);
260
261 return 0;
262 }
263
264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
265 {
266 u8 __iomem *p;
267
268 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
269 return;
270
271 /*
272 * disable interrupts
273 */
274 p = ioremap(pci_resource_start(dev, 0), 0x80);
275 if (p != NULL) {
276 writel(0, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283 }
284 }
285
286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
287 static int
288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
289 struct uart_port *port, int idx)
290 {
291 unsigned int bar, offset = board->first_offset;
292
293 bar = 0;
294
295 if (idx < 4) {
296 /* first four channels map to 0, 0x100, 0x200, 0x300 */
297 offset += idx * board->uart_offset;
298 } else if (idx < 8) {
299 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
300 offset += idx * board->uart_offset + 0xC00;
301 } else /* we have only 8 ports on PMC-OCTALPRO */
302 return 1;
303
304 return setup_port(priv, port, bar, offset, board->reg_shift);
305 }
306
307 /*
308 * This does initialization for PMC OCTALPRO cards:
309 * maps the device memory, resets the UARTs (needed, bc
310 * if the module is removed and inserted again, the card
311 * is in the sleep mode) and enables global interrupt.
312 */
313
314 /* global control register offset for SBS PMC-OctalPro */
315 #define OCT_REG_CR_OFF 0x500
316
317 static int __devinit sbs_init(struct pci_dev *dev)
318 {
319 u8 __iomem *p;
320
321 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
322
323 if (p == NULL)
324 return -ENOMEM;
325 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
326 writeb(0x10,p + OCT_REG_CR_OFF);
327 udelay(50);
328 writeb(0x0,p + OCT_REG_CR_OFF);
329
330 /* Set bit-2 (INTENABLE) of Control Register */
331 writeb(0x4, p + OCT_REG_CR_OFF);
332 iounmap(p);
333
334 return 0;
335 }
336
337 /*
338 * Disables the global interrupt of PMC-OctalPro
339 */
340
341 static void __devexit sbs_exit(struct pci_dev *dev)
342 {
343 u8 __iomem *p;
344
345 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
346 if (p != NULL) {
347 writeb(0, p + OCT_REG_CR_OFF);
348 }
349 iounmap(p);
350 }
351
352 /*
353 * SIIG serial cards have an PCI interface chip which also controls
354 * the UART clocking frequency. Each UART can be clocked independently
355 * (except cards equiped with 4 UARTs) and initial clocking settings
356 * are stored in the EEPROM chip. It can cause problems because this
357 * version of serial driver doesn't support differently clocked UART's
358 * on single PCI card. To prevent this, initialization functions set
359 * high frequency clocking for all UART's on given card. It is safe (I
360 * hope) because it doesn't touch EEPROM settings to prevent conflicts
361 * with other OSes (like M$ DOS).
362 *
363 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
364 *
365 * There is two family of SIIG serial cards with different PCI
366 * interface chip and different configuration methods:
367 * - 10x cards have control registers in IO and/or memory space;
368 * - 20x cards have control registers in standard PCI configuration space.
369 *
370 * Note: all 10x cards have PCI device ids 0x10..
371 * all 20x cards have PCI device ids 0x20..
372 *
373 * There are also Quartet Serial cards which use Oxford Semiconductor
374 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
375 *
376 * Note: some SIIG cards are probed by the parport_serial object.
377 */
378
379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
381
382 static int pci_siig10x_init(struct pci_dev *dev)
383 {
384 u16 data;
385 void __iomem *p;
386
387 switch (dev->device & 0xfff8) {
388 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
389 data = 0xffdf;
390 break;
391 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
392 data = 0xf7ff;
393 break;
394 default: /* 1S1P, 4S */
395 data = 0xfffb;
396 break;
397 }
398
399 p = ioremap(pci_resource_start(dev, 0), 0x80);
400 if (p == NULL)
401 return -ENOMEM;
402
403 writew(readw(p + 0x28) & data, p + 0x28);
404 readw(p + 0x28);
405 iounmap(p);
406 return 0;
407 }
408
409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
411
412 static int pci_siig20x_init(struct pci_dev *dev)
413 {
414 u8 data;
415
416 /* Change clock frequency for the first UART. */
417 pci_read_config_byte(dev, 0x6f, &data);
418 pci_write_config_byte(dev, 0x6f, data & 0xef);
419
420 /* If this card has 2 UART, we have to do the same with second UART. */
421 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
422 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
423 pci_read_config_byte(dev, 0x73, &data);
424 pci_write_config_byte(dev, 0x73, data & 0xef);
425 }
426 return 0;
427 }
428
429 static int pci_siig_init(struct pci_dev *dev)
430 {
431 unsigned int type = dev->device & 0xff00;
432
433 if (type == 0x1000)
434 return pci_siig10x_init(dev);
435 else if (type == 0x2000)
436 return pci_siig20x_init(dev);
437
438 moan_device("Unknown SIIG card", dev);
439 return -ENODEV;
440 }
441
442 /*
443 * Timedia has an explosion of boards, and to avoid the PCI table from
444 * growing *huge*, we use this function to collapse some 70 entries
445 * in the PCI table into one, for sanity's and compactness's sake.
446 */
447 static unsigned short timedia_single_port[] = {
448 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
449 };
450
451 static unsigned short timedia_dual_port[] = {
452 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
453 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
454 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
455 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
456 0xD079, 0
457 };
458
459 static unsigned short timedia_quad_port[] = {
460 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
461 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
462 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
463 0xB157, 0
464 };
465
466 static unsigned short timedia_eight_port[] = {
467 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
468 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
469 };
470
471 static const struct timedia_struct {
472 int num;
473 unsigned short *ids;
474 } timedia_data[] = {
475 { 1, timedia_single_port },
476 { 2, timedia_dual_port },
477 { 4, timedia_quad_port },
478 { 8, timedia_eight_port },
479 { 0, NULL }
480 };
481
482 static int __devinit pci_timedia_init(struct pci_dev *dev)
483 {
484 unsigned short *ids;
485 int i, j;
486
487 for (i = 0; timedia_data[i].num; i++) {
488 ids = timedia_data[i].ids;
489 for (j = 0; ids[j]; j++)
490 if (dev->subsystem_device == ids[j])
491 return timedia_data[i].num;
492 }
493 return 0;
494 }
495
496 /*
497 * Timedia/SUNIX uses a mixture of BARs and offsets
498 * Ugh, this is ugly as all hell --- TYT
499 */
500 static int
501 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
502 struct uart_port *port, int idx)
503 {
504 unsigned int bar = 0, offset = board->first_offset;
505
506 switch (idx) {
507 case 0:
508 bar = 0;
509 break;
510 case 1:
511 offset = board->uart_offset;
512 bar = 0;
513 break;
514 case 2:
515 bar = 1;
516 break;
517 case 3:
518 offset = board->uart_offset;
519 /* FALLTHROUGH */
520 case 4: /* BAR 2 */
521 case 5: /* BAR 3 */
522 case 6: /* BAR 4 */
523 case 7: /* BAR 5 */
524 bar = idx - 2;
525 }
526
527 return setup_port(priv, port, bar, offset, board->reg_shift);
528 }
529
530 /*
531 * Some Titan cards are also a little weird
532 */
533 static int
534 titan_400l_800l_setup(struct serial_private *priv,
535 struct pciserial_board *board,
536 struct uart_port *port, int idx)
537 {
538 unsigned int bar, offset = board->first_offset;
539
540 switch (idx) {
541 case 0:
542 bar = 1;
543 break;
544 case 1:
545 bar = 2;
546 break;
547 default:
548 bar = 4;
549 offset = (idx - 2) * board->uart_offset;
550 }
551
552 return setup_port(priv, port, bar, offset, board->reg_shift);
553 }
554
555 static int __devinit pci_xircom_init(struct pci_dev *dev)
556 {
557 msleep(100);
558 return 0;
559 }
560
561 static int __devinit pci_netmos_init(struct pci_dev *dev)
562 {
563 /* subdevice 0x00PS means <P> parallel, <S> serial */
564 unsigned int num_serial = dev->subsystem_device & 0xf;
565
566 if (num_serial == 0)
567 return -ENODEV;
568 return num_serial;
569 }
570
571 static int
572 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
573 struct uart_port *port, int idx)
574 {
575 unsigned int bar, offset = board->first_offset, maxnr;
576
577 bar = FL_GET_BASE(board->flags);
578 if (board->flags & FL_BASE_BARS)
579 bar += idx;
580 else
581 offset += idx * board->uart_offset;
582
583 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
584 (8 << board->reg_shift);
585
586 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
587 return 1;
588
589 return setup_port(priv, port, bar, offset, board->reg_shift);
590 }
591
592 /* This should be in linux/pci_ids.h */
593 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
594 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
595 #define PCI_DEVICE_ID_OCTPRO 0x0001
596 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
597 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
598 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
599 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
600
601 /*
602 * Master list of serial port init/setup/exit quirks.
603 * This does not describe the general nature of the port.
604 * (ie, baud base, number and location of ports, etc)
605 *
606 * This list is ordered alphabetically by vendor then device.
607 * Specific entries must come before more generic entries.
608 */
609 static struct pci_serial_quirk pci_serial_quirks[] = {
610 /*
611 * AFAVLAB cards.
612 * It is not clear whether this applies to all products.
613 */
614 {
615 .vendor = PCI_VENDOR_ID_AFAVLAB,
616 .device = PCI_ANY_ID,
617 .subvendor = PCI_ANY_ID,
618 .subdevice = PCI_ANY_ID,
619 .setup = afavlab_setup,
620 },
621 /*
622 * HP Diva
623 */
624 {
625 .vendor = PCI_VENDOR_ID_HP,
626 .device = PCI_DEVICE_ID_HP_DIVA,
627 .subvendor = PCI_ANY_ID,
628 .subdevice = PCI_ANY_ID,
629 .init = pci_hp_diva_init,
630 .setup = pci_hp_diva_setup,
631 },
632 /*
633 * Intel
634 */
635 {
636 .vendor = PCI_VENDOR_ID_INTEL,
637 .device = PCI_DEVICE_ID_INTEL_80960_RP,
638 .subvendor = 0xe4bf,
639 .subdevice = PCI_ANY_ID,
640 .init = pci_inteli960ni_init,
641 .setup = pci_default_setup,
642 },
643 /*
644 * Panacom
645 */
646 {
647 .vendor = PCI_VENDOR_ID_PANACOM,
648 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
649 .subvendor = PCI_ANY_ID,
650 .subdevice = PCI_ANY_ID,
651 .init = pci_plx9050_init,
652 .setup = pci_default_setup,
653 .exit = __devexit_p(pci_plx9050_exit),
654 },
655 {
656 .vendor = PCI_VENDOR_ID_PANACOM,
657 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
658 .subvendor = PCI_ANY_ID,
659 .subdevice = PCI_ANY_ID,
660 .init = pci_plx9050_init,
661 .setup = pci_default_setup,
662 .exit = __devexit_p(pci_plx9050_exit),
663 },
664 /*
665 * PLX
666 */
667 {
668 .vendor = PCI_VENDOR_ID_PLX,
669 .device = PCI_DEVICE_ID_PLX_9050,
670 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
671 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
672 .init = pci_plx9050_init,
673 .setup = pci_default_setup,
674 .exit = __devexit_p(pci_plx9050_exit),
675 },
676 {
677 .vendor = PCI_VENDOR_ID_PLX,
678 .device = PCI_DEVICE_ID_PLX_9050,
679 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
680 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
681 .init = pci_plx9050_init,
682 .setup = pci_default_setup,
683 .exit = __devexit_p(pci_plx9050_exit),
684 },
685 {
686 .vendor = PCI_VENDOR_ID_PLX,
687 .device = PCI_DEVICE_ID_PLX_ROMULUS,
688 .subvendor = PCI_VENDOR_ID_PLX,
689 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
690 .init = pci_plx9050_init,
691 .setup = pci_default_setup,
692 .exit = __devexit_p(pci_plx9050_exit),
693 },
694 /*
695 * SBS Technologies, Inc., PMC-OCTALPRO 232
696 */
697 {
698 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
699 .device = PCI_DEVICE_ID_OCTPRO,
700 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
701 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
702 .init = sbs_init,
703 .setup = sbs_setup,
704 .exit = __devexit_p(sbs_exit),
705 },
706 /*
707 * SBS Technologies, Inc., PMC-OCTALPRO 422
708 */
709 {
710 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
711 .device = PCI_DEVICE_ID_OCTPRO,
712 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
713 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
714 .init = sbs_init,
715 .setup = sbs_setup,
716 .exit = __devexit_p(sbs_exit),
717 },
718 /*
719 * SBS Technologies, Inc., P-Octal 232
720 */
721 {
722 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
723 .device = PCI_DEVICE_ID_OCTPRO,
724 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
725 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
726 .init = sbs_init,
727 .setup = sbs_setup,
728 .exit = __devexit_p(sbs_exit),
729 },
730 /*
731 * SBS Technologies, Inc., P-Octal 422
732 */
733 {
734 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
735 .device = PCI_DEVICE_ID_OCTPRO,
736 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
737 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
738 .init = sbs_init,
739 .setup = sbs_setup,
740 .exit = __devexit_p(sbs_exit),
741 },
742 /*
743 * SIIG cards.
744 */
745 {
746 .vendor = PCI_VENDOR_ID_SIIG,
747 .device = PCI_ANY_ID,
748 .subvendor = PCI_ANY_ID,
749 .subdevice = PCI_ANY_ID,
750 .init = pci_siig_init,
751 .setup = pci_default_setup,
752 },
753 /*
754 * Titan cards
755 */
756 {
757 .vendor = PCI_VENDOR_ID_TITAN,
758 .device = PCI_DEVICE_ID_TITAN_400L,
759 .subvendor = PCI_ANY_ID,
760 .subdevice = PCI_ANY_ID,
761 .setup = titan_400l_800l_setup,
762 },
763 {
764 .vendor = PCI_VENDOR_ID_TITAN,
765 .device = PCI_DEVICE_ID_TITAN_800L,
766 .subvendor = PCI_ANY_ID,
767 .subdevice = PCI_ANY_ID,
768 .setup = titan_400l_800l_setup,
769 },
770 /*
771 * Timedia cards
772 */
773 {
774 .vendor = PCI_VENDOR_ID_TIMEDIA,
775 .device = PCI_DEVICE_ID_TIMEDIA_1889,
776 .subvendor = PCI_VENDOR_ID_TIMEDIA,
777 .subdevice = PCI_ANY_ID,
778 .init = pci_timedia_init,
779 .setup = pci_timedia_setup,
780 },
781 {
782 .vendor = PCI_VENDOR_ID_TIMEDIA,
783 .device = PCI_ANY_ID,
784 .subvendor = PCI_ANY_ID,
785 .subdevice = PCI_ANY_ID,
786 .setup = pci_timedia_setup,
787 },
788 /*
789 * Xircom cards
790 */
791 {
792 .vendor = PCI_VENDOR_ID_XIRCOM,
793 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
794 .subvendor = PCI_ANY_ID,
795 .subdevice = PCI_ANY_ID,
796 .init = pci_xircom_init,
797 .setup = pci_default_setup,
798 },
799 /*
800 * Netmos cards
801 */
802 {
803 .vendor = PCI_VENDOR_ID_NETMOS,
804 .device = PCI_ANY_ID,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .init = pci_netmos_init,
808 .setup = pci_default_setup,
809 },
810 /*
811 * Default "match everything" terminator entry
812 */
813 {
814 .vendor = PCI_ANY_ID,
815 .device = PCI_ANY_ID,
816 .subvendor = PCI_ANY_ID,
817 .subdevice = PCI_ANY_ID,
818 .setup = pci_default_setup,
819 }
820 };
821
822 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
823 {
824 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
825 }
826
827 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
828 {
829 struct pci_serial_quirk *quirk;
830
831 for (quirk = pci_serial_quirks; ; quirk++)
832 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
833 quirk_id_matches(quirk->device, dev->device) &&
834 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
835 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
836 break;
837 return quirk;
838 }
839
840 static inline int get_pci_irq(struct pci_dev *dev,
841 struct pciserial_board *board)
842 {
843 if (board->flags & FL_NOIRQ)
844 return 0;
845 else
846 return dev->irq;
847 }
848
849 /*
850 * This is the configuration table for all of the PCI serial boards
851 * which we support. It is directly indexed by the pci_board_num_t enum
852 * value, which is encoded in the pci_device_id PCI probe table's
853 * driver_data member.
854 *
855 * The makeup of these names are:
856 * pbn_bn{_bt}_n_baud{_offsetinhex}
857 *
858 * bn = PCI BAR number
859 * bt = Index using PCI BARs
860 * n = number of serial ports
861 * baud = baud rate
862 * offsetinhex = offset for each sequential port (in hex)
863 *
864 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
865 *
866 * Please note: in theory if n = 1, _bt infix should make no difference.
867 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
868 */
869 enum pci_board_num_t {
870 pbn_default = 0,
871
872 pbn_b0_1_115200,
873 pbn_b0_2_115200,
874 pbn_b0_4_115200,
875 pbn_b0_5_115200,
876
877 pbn_b0_1_921600,
878 pbn_b0_2_921600,
879 pbn_b0_4_921600,
880
881 pbn_b0_2_1130000,
882
883 pbn_b0_4_1152000,
884
885 pbn_b0_2_1843200,
886 pbn_b0_4_1843200,
887
888 pbn_b0_2_1843200_200,
889 pbn_b0_4_1843200_200,
890 pbn_b0_8_1843200_200,
891
892 pbn_b0_bt_1_115200,
893 pbn_b0_bt_2_115200,
894 pbn_b0_bt_8_115200,
895
896 pbn_b0_bt_1_460800,
897 pbn_b0_bt_2_460800,
898 pbn_b0_bt_4_460800,
899
900 pbn_b0_bt_1_921600,
901 pbn_b0_bt_2_921600,
902 pbn_b0_bt_4_921600,
903 pbn_b0_bt_8_921600,
904
905 pbn_b1_1_115200,
906 pbn_b1_2_115200,
907 pbn_b1_4_115200,
908 pbn_b1_8_115200,
909
910 pbn_b1_1_921600,
911 pbn_b1_2_921600,
912 pbn_b1_4_921600,
913 pbn_b1_8_921600,
914
915 pbn_b1_2_1250000,
916
917 pbn_b1_bt_2_921600,
918
919 pbn_b1_1_1382400,
920 pbn_b1_2_1382400,
921 pbn_b1_4_1382400,
922 pbn_b1_8_1382400,
923
924 pbn_b2_1_115200,
925 pbn_b2_8_115200,
926
927 pbn_b2_1_460800,
928 pbn_b2_4_460800,
929 pbn_b2_8_460800,
930 pbn_b2_16_460800,
931
932 pbn_b2_1_921600,
933 pbn_b2_4_921600,
934 pbn_b2_8_921600,
935
936 pbn_b2_bt_1_115200,
937 pbn_b2_bt_2_115200,
938 pbn_b2_bt_4_115200,
939
940 pbn_b2_bt_2_921600,
941 pbn_b2_bt_4_921600,
942
943 pbn_b3_2_115200,
944 pbn_b3_4_115200,
945 pbn_b3_8_115200,
946
947 /*
948 * Board-specific versions.
949 */
950 pbn_panacom,
951 pbn_panacom2,
952 pbn_panacom4,
953 pbn_exsys_4055,
954 pbn_plx_romulus,
955 pbn_oxsemi,
956 pbn_intel_i960,
957 pbn_sgi_ioc3,
958 pbn_nec_nile4,
959 pbn_computone_4,
960 pbn_computone_6,
961 pbn_computone_8,
962 pbn_sbsxrsio,
963 pbn_exar_XR17C152,
964 pbn_exar_XR17C154,
965 pbn_exar_XR17C158,
966 };
967
968 /*
969 * uart_offset - the space between channels
970 * reg_shift - describes how the UART registers are mapped
971 * to PCI memory by the card.
972 * For example IER register on SBS, Inc. PMC-OctPro is located at
973 * offset 0x10 from the UART base, while UART_IER is defined as 1
974 * in include/linux/serial_reg.h,
975 * see first lines of serial_in() and serial_out() in 8250.c
976 */
977
978 static struct pciserial_board pci_boards[] __devinitdata = {
979 [pbn_default] = {
980 .flags = FL_BASE0,
981 .num_ports = 1,
982 .base_baud = 115200,
983 .uart_offset = 8,
984 },
985 [pbn_b0_1_115200] = {
986 .flags = FL_BASE0,
987 .num_ports = 1,
988 .base_baud = 115200,
989 .uart_offset = 8,
990 },
991 [pbn_b0_2_115200] = {
992 .flags = FL_BASE0,
993 .num_ports = 2,
994 .base_baud = 115200,
995 .uart_offset = 8,
996 },
997 [pbn_b0_4_115200] = {
998 .flags = FL_BASE0,
999 .num_ports = 4,
1000 .base_baud = 115200,
1001 .uart_offset = 8,
1002 },
1003 [pbn_b0_5_115200] = {
1004 .flags = FL_BASE0,
1005 .num_ports = 5,
1006 .base_baud = 115200,
1007 .uart_offset = 8,
1008 },
1009
1010 [pbn_b0_1_921600] = {
1011 .flags = FL_BASE0,
1012 .num_ports = 1,
1013 .base_baud = 921600,
1014 .uart_offset = 8,
1015 },
1016 [pbn_b0_2_921600] = {
1017 .flags = FL_BASE0,
1018 .num_ports = 2,
1019 .base_baud = 921600,
1020 .uart_offset = 8,
1021 },
1022 [pbn_b0_4_921600] = {
1023 .flags = FL_BASE0,
1024 .num_ports = 4,
1025 .base_baud = 921600,
1026 .uart_offset = 8,
1027 },
1028
1029 [pbn_b0_2_1130000] = {
1030 .flags = FL_BASE0,
1031 .num_ports = 2,
1032 .base_baud = 1130000,
1033 .uart_offset = 8,
1034 },
1035
1036 [pbn_b0_4_1152000] = {
1037 .flags = FL_BASE0,
1038 .num_ports = 4,
1039 .base_baud = 1152000,
1040 .uart_offset = 8,
1041 },
1042
1043 [pbn_b0_2_1843200] = {
1044 .flags = FL_BASE0,
1045 .num_ports = 2,
1046 .base_baud = 1843200,
1047 .uart_offset = 8,
1048 },
1049 [pbn_b0_4_1843200] = {
1050 .flags = FL_BASE0,
1051 .num_ports = 4,
1052 .base_baud = 1843200,
1053 .uart_offset = 8,
1054 },
1055
1056 [pbn_b0_2_1843200_200] = {
1057 .flags = FL_BASE0,
1058 .num_ports = 2,
1059 .base_baud = 1843200,
1060 .uart_offset = 0x200,
1061 },
1062 [pbn_b0_4_1843200_200] = {
1063 .flags = FL_BASE0,
1064 .num_ports = 4,
1065 .base_baud = 1843200,
1066 .uart_offset = 0x200,
1067 },
1068 [pbn_b0_8_1843200_200] = {
1069 .flags = FL_BASE0,
1070 .num_ports = 8,
1071 .base_baud = 1843200,
1072 .uart_offset = 0x200,
1073 },
1074
1075 [pbn_b0_bt_1_115200] = {
1076 .flags = FL_BASE0|FL_BASE_BARS,
1077 .num_ports = 1,
1078 .base_baud = 115200,
1079 .uart_offset = 8,
1080 },
1081 [pbn_b0_bt_2_115200] = {
1082 .flags = FL_BASE0|FL_BASE_BARS,
1083 .num_ports = 2,
1084 .base_baud = 115200,
1085 .uart_offset = 8,
1086 },
1087 [pbn_b0_bt_8_115200] = {
1088 .flags = FL_BASE0|FL_BASE_BARS,
1089 .num_ports = 8,
1090 .base_baud = 115200,
1091 .uart_offset = 8,
1092 },
1093
1094 [pbn_b0_bt_1_460800] = {
1095 .flags = FL_BASE0|FL_BASE_BARS,
1096 .num_ports = 1,
1097 .base_baud = 460800,
1098 .uart_offset = 8,
1099 },
1100 [pbn_b0_bt_2_460800] = {
1101 .flags = FL_BASE0|FL_BASE_BARS,
1102 .num_ports = 2,
1103 .base_baud = 460800,
1104 .uart_offset = 8,
1105 },
1106 [pbn_b0_bt_4_460800] = {
1107 .flags = FL_BASE0|FL_BASE_BARS,
1108 .num_ports = 4,
1109 .base_baud = 460800,
1110 .uart_offset = 8,
1111 },
1112
1113 [pbn_b0_bt_1_921600] = {
1114 .flags = FL_BASE0|FL_BASE_BARS,
1115 .num_ports = 1,
1116 .base_baud = 921600,
1117 .uart_offset = 8,
1118 },
1119 [pbn_b0_bt_2_921600] = {
1120 .flags = FL_BASE0|FL_BASE_BARS,
1121 .num_ports = 2,
1122 .base_baud = 921600,
1123 .uart_offset = 8,
1124 },
1125 [pbn_b0_bt_4_921600] = {
1126 .flags = FL_BASE0|FL_BASE_BARS,
1127 .num_ports = 4,
1128 .base_baud = 921600,
1129 .uart_offset = 8,
1130 },
1131 [pbn_b0_bt_8_921600] = {
1132 .flags = FL_BASE0|FL_BASE_BARS,
1133 .num_ports = 8,
1134 .base_baud = 921600,
1135 .uart_offset = 8,
1136 },
1137
1138 [pbn_b1_1_115200] = {
1139 .flags = FL_BASE1,
1140 .num_ports = 1,
1141 .base_baud = 115200,
1142 .uart_offset = 8,
1143 },
1144 [pbn_b1_2_115200] = {
1145 .flags = FL_BASE1,
1146 .num_ports = 2,
1147 .base_baud = 115200,
1148 .uart_offset = 8,
1149 },
1150 [pbn_b1_4_115200] = {
1151 .flags = FL_BASE1,
1152 .num_ports = 4,
1153 .base_baud = 115200,
1154 .uart_offset = 8,
1155 },
1156 [pbn_b1_8_115200] = {
1157 .flags = FL_BASE1,
1158 .num_ports = 8,
1159 .base_baud = 115200,
1160 .uart_offset = 8,
1161 },
1162
1163 [pbn_b1_1_921600] = {
1164 .flags = FL_BASE1,
1165 .num_ports = 1,
1166 .base_baud = 921600,
1167 .uart_offset = 8,
1168 },
1169 [pbn_b1_2_921600] = {
1170 .flags = FL_BASE1,
1171 .num_ports = 2,
1172 .base_baud = 921600,
1173 .uart_offset = 8,
1174 },
1175 [pbn_b1_4_921600] = {
1176 .flags = FL_BASE1,
1177 .num_ports = 4,
1178 .base_baud = 921600,
1179 .uart_offset = 8,
1180 },
1181 [pbn_b1_8_921600] = {
1182 .flags = FL_BASE1,
1183 .num_ports = 8,
1184 .base_baud = 921600,
1185 .uart_offset = 8,
1186 },
1187 [pbn_b1_2_1250000] = {
1188 .flags = FL_BASE1,
1189 .num_ports = 2,
1190 .base_baud = 1250000,
1191 .uart_offset = 8,
1192 },
1193
1194 [pbn_b1_bt_2_921600] = {
1195 .flags = FL_BASE1|FL_BASE_BARS,
1196 .num_ports = 2,
1197 .base_baud = 921600,
1198 .uart_offset = 8,
1199 },
1200
1201 [pbn_b1_1_1382400] = {
1202 .flags = FL_BASE1,
1203 .num_ports = 1,
1204 .base_baud = 1382400,
1205 .uart_offset = 8,
1206 },
1207 [pbn_b1_2_1382400] = {
1208 .flags = FL_BASE1,
1209 .num_ports = 2,
1210 .base_baud = 1382400,
1211 .uart_offset = 8,
1212 },
1213 [pbn_b1_4_1382400] = {
1214 .flags = FL_BASE1,
1215 .num_ports = 4,
1216 .base_baud = 1382400,
1217 .uart_offset = 8,
1218 },
1219 [pbn_b1_8_1382400] = {
1220 .flags = FL_BASE1,
1221 .num_ports = 8,
1222 .base_baud = 1382400,
1223 .uart_offset = 8,
1224 },
1225
1226 [pbn_b2_1_115200] = {
1227 .flags = FL_BASE2,
1228 .num_ports = 1,
1229 .base_baud = 115200,
1230 .uart_offset = 8,
1231 },
1232 [pbn_b2_8_115200] = {
1233 .flags = FL_BASE2,
1234 .num_ports = 8,
1235 .base_baud = 115200,
1236 .uart_offset = 8,
1237 },
1238
1239 [pbn_b2_1_460800] = {
1240 .flags = FL_BASE2,
1241 .num_ports = 1,
1242 .base_baud = 460800,
1243 .uart_offset = 8,
1244 },
1245 [pbn_b2_4_460800] = {
1246 .flags = FL_BASE2,
1247 .num_ports = 4,
1248 .base_baud = 460800,
1249 .uart_offset = 8,
1250 },
1251 [pbn_b2_8_460800] = {
1252 .flags = FL_BASE2,
1253 .num_ports = 8,
1254 .base_baud = 460800,
1255 .uart_offset = 8,
1256 },
1257 [pbn_b2_16_460800] = {
1258 .flags = FL_BASE2,
1259 .num_ports = 16,
1260 .base_baud = 460800,
1261 .uart_offset = 8,
1262 },
1263
1264 [pbn_b2_1_921600] = {
1265 .flags = FL_BASE2,
1266 .num_ports = 1,
1267 .base_baud = 921600,
1268 .uart_offset = 8,
1269 },
1270 [pbn_b2_4_921600] = {
1271 .flags = FL_BASE2,
1272 .num_ports = 4,
1273 .base_baud = 921600,
1274 .uart_offset = 8,
1275 },
1276 [pbn_b2_8_921600] = {
1277 .flags = FL_BASE2,
1278 .num_ports = 8,
1279 .base_baud = 921600,
1280 .uart_offset = 8,
1281 },
1282
1283 [pbn_b2_bt_1_115200] = {
1284 .flags = FL_BASE2|FL_BASE_BARS,
1285 .num_ports = 1,
1286 .base_baud = 115200,
1287 .uart_offset = 8,
1288 },
1289 [pbn_b2_bt_2_115200] = {
1290 .flags = FL_BASE2|FL_BASE_BARS,
1291 .num_ports = 2,
1292 .base_baud = 115200,
1293 .uart_offset = 8,
1294 },
1295 [pbn_b2_bt_4_115200] = {
1296 .flags = FL_BASE2|FL_BASE_BARS,
1297 .num_ports = 4,
1298 .base_baud = 115200,
1299 .uart_offset = 8,
1300 },
1301
1302 [pbn_b2_bt_2_921600] = {
1303 .flags = FL_BASE2|FL_BASE_BARS,
1304 .num_ports = 2,
1305 .base_baud = 921600,
1306 .uart_offset = 8,
1307 },
1308 [pbn_b2_bt_4_921600] = {
1309 .flags = FL_BASE2|FL_BASE_BARS,
1310 .num_ports = 4,
1311 .base_baud = 921600,
1312 .uart_offset = 8,
1313 },
1314
1315 [pbn_b3_2_115200] = {
1316 .flags = FL_BASE3,
1317 .num_ports = 2,
1318 .base_baud = 115200,
1319 .uart_offset = 8,
1320 },
1321 [pbn_b3_4_115200] = {
1322 .flags = FL_BASE3,
1323 .num_ports = 4,
1324 .base_baud = 115200,
1325 .uart_offset = 8,
1326 },
1327 [pbn_b3_8_115200] = {
1328 .flags = FL_BASE3,
1329 .num_ports = 8,
1330 .base_baud = 115200,
1331 .uart_offset = 8,
1332 },
1333
1334 /*
1335 * Entries following this are board-specific.
1336 */
1337
1338 /*
1339 * Panacom - IOMEM
1340 */
1341 [pbn_panacom] = {
1342 .flags = FL_BASE2,
1343 .num_ports = 2,
1344 .base_baud = 921600,
1345 .uart_offset = 0x400,
1346 .reg_shift = 7,
1347 },
1348 [pbn_panacom2] = {
1349 .flags = FL_BASE2|FL_BASE_BARS,
1350 .num_ports = 2,
1351 .base_baud = 921600,
1352 .uart_offset = 0x400,
1353 .reg_shift = 7,
1354 },
1355 [pbn_panacom4] = {
1356 .flags = FL_BASE2|FL_BASE_BARS,
1357 .num_ports = 4,
1358 .base_baud = 921600,
1359 .uart_offset = 0x400,
1360 .reg_shift = 7,
1361 },
1362
1363 [pbn_exsys_4055] = {
1364 .flags = FL_BASE2,
1365 .num_ports = 4,
1366 .base_baud = 115200,
1367 .uart_offset = 8,
1368 },
1369
1370 /* I think this entry is broken - the first_offset looks wrong --rmk */
1371 [pbn_plx_romulus] = {
1372 .flags = FL_BASE2,
1373 .num_ports = 4,
1374 .base_baud = 921600,
1375 .uart_offset = 8 << 2,
1376 .reg_shift = 2,
1377 .first_offset = 0x03,
1378 },
1379
1380 /*
1381 * This board uses the size of PCI Base region 0 to
1382 * signal now many ports are available
1383 */
1384 [pbn_oxsemi] = {
1385 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1386 .num_ports = 32,
1387 .base_baud = 115200,
1388 .uart_offset = 8,
1389 },
1390
1391 /*
1392 * EKF addition for i960 Boards form EKF with serial port.
1393 * Max 256 ports.
1394 */
1395 [pbn_intel_i960] = {
1396 .flags = FL_BASE0,
1397 .num_ports = 32,
1398 .base_baud = 921600,
1399 .uart_offset = 8 << 2,
1400 .reg_shift = 2,
1401 .first_offset = 0x10000,
1402 },
1403 [pbn_sgi_ioc3] = {
1404 .flags = FL_BASE0|FL_NOIRQ,
1405 .num_ports = 1,
1406 .base_baud = 458333,
1407 .uart_offset = 8,
1408 .reg_shift = 0,
1409 .first_offset = 0x20178,
1410 },
1411
1412 /*
1413 * NEC Vrc-5074 (Nile 4) builtin UART.
1414 */
1415 [pbn_nec_nile4] = {
1416 .flags = FL_BASE0,
1417 .num_ports = 1,
1418 .base_baud = 520833,
1419 .uart_offset = 8 << 3,
1420 .reg_shift = 3,
1421 .first_offset = 0x300,
1422 },
1423
1424 /*
1425 * Computone - uses IOMEM.
1426 */
1427 [pbn_computone_4] = {
1428 .flags = FL_BASE0,
1429 .num_ports = 4,
1430 .base_baud = 921600,
1431 .uart_offset = 0x40,
1432 .reg_shift = 2,
1433 .first_offset = 0x200,
1434 },
1435 [pbn_computone_6] = {
1436 .flags = FL_BASE0,
1437 .num_ports = 6,
1438 .base_baud = 921600,
1439 .uart_offset = 0x40,
1440 .reg_shift = 2,
1441 .first_offset = 0x200,
1442 },
1443 [pbn_computone_8] = {
1444 .flags = FL_BASE0,
1445 .num_ports = 8,
1446 .base_baud = 921600,
1447 .uart_offset = 0x40,
1448 .reg_shift = 2,
1449 .first_offset = 0x200,
1450 },
1451 [pbn_sbsxrsio] = {
1452 .flags = FL_BASE0,
1453 .num_ports = 8,
1454 .base_baud = 460800,
1455 .uart_offset = 256,
1456 .reg_shift = 4,
1457 },
1458 /*
1459 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1460 * Only basic 16550A support.
1461 * XR17C15[24] are not tested, but they should work.
1462 */
1463 [pbn_exar_XR17C152] = {
1464 .flags = FL_BASE0,
1465 .num_ports = 2,
1466 .base_baud = 921600,
1467 .uart_offset = 0x200,
1468 },
1469 [pbn_exar_XR17C154] = {
1470 .flags = FL_BASE0,
1471 .num_ports = 4,
1472 .base_baud = 921600,
1473 .uart_offset = 0x200,
1474 },
1475 [pbn_exar_XR17C158] = {
1476 .flags = FL_BASE0,
1477 .num_ports = 8,
1478 .base_baud = 921600,
1479 .uart_offset = 0x200,
1480 },
1481 };
1482
1483 /*
1484 * Given a complete unknown PCI device, try to use some heuristics to
1485 * guess what the configuration might be, based on the pitiful PCI
1486 * serial specs. Returns 0 on success, 1 on failure.
1487 */
1488 static int __devinit
1489 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1490 {
1491 int num_iomem, num_port, first_port = -1, i;
1492
1493 /*
1494 * If it is not a communications device or the programming
1495 * interface is greater than 6, give up.
1496 *
1497 * (Should we try to make guesses for multiport serial devices
1498 * later?)
1499 */
1500 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1501 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1502 (dev->class & 0xff) > 6)
1503 return -ENODEV;
1504
1505 num_iomem = num_port = 0;
1506 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1507 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1508 num_port++;
1509 if (first_port == -1)
1510 first_port = i;
1511 }
1512 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1513 num_iomem++;
1514 }
1515
1516 /*
1517 * If there is 1 or 0 iomem regions, and exactly one port,
1518 * use it. We guess the number of ports based on the IO
1519 * region size.
1520 */
1521 if (num_iomem <= 1 && num_port == 1) {
1522 board->flags = first_port;
1523 board->num_ports = pci_resource_len(dev, first_port) / 8;
1524 return 0;
1525 }
1526
1527 /*
1528 * Now guess if we've got a board which indexes by BARs.
1529 * Each IO BAR should be 8 bytes, and they should follow
1530 * consecutively.
1531 */
1532 first_port = -1;
1533 num_port = 0;
1534 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1535 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1536 pci_resource_len(dev, i) == 8 &&
1537 (first_port == -1 || (first_port + num_port) == i)) {
1538 num_port++;
1539 if (first_port == -1)
1540 first_port = i;
1541 }
1542 }
1543
1544 if (num_port > 1) {
1545 board->flags = first_port | FL_BASE_BARS;
1546 board->num_ports = num_port;
1547 return 0;
1548 }
1549
1550 return -ENODEV;
1551 }
1552
1553 static inline int
1554 serial_pci_matches(struct pciserial_board *board,
1555 struct pciserial_board *guessed)
1556 {
1557 return
1558 board->num_ports == guessed->num_ports &&
1559 board->base_baud == guessed->base_baud &&
1560 board->uart_offset == guessed->uart_offset &&
1561 board->reg_shift == guessed->reg_shift &&
1562 board->first_offset == guessed->first_offset;
1563 }
1564
1565 struct serial_private *
1566 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1567 {
1568 struct uart_port serial_port;
1569 struct serial_private *priv;
1570 struct pci_serial_quirk *quirk;
1571 int rc, nr_ports, i;
1572
1573 nr_ports = board->num_ports;
1574
1575 /*
1576 * Find an init and setup quirks.
1577 */
1578 quirk = find_quirk(dev);
1579
1580 /*
1581 * Run the new-style initialization function.
1582 * The initialization function returns:
1583 * <0 - error
1584 * 0 - use board->num_ports
1585 * >0 - number of ports
1586 */
1587 if (quirk->init) {
1588 rc = quirk->init(dev);
1589 if (rc < 0) {
1590 priv = ERR_PTR(rc);
1591 goto err_out;
1592 }
1593 if (rc)
1594 nr_ports = rc;
1595 }
1596
1597 priv = kmalloc(sizeof(struct serial_private) +
1598 sizeof(unsigned int) * nr_ports,
1599 GFP_KERNEL);
1600 if (!priv) {
1601 priv = ERR_PTR(-ENOMEM);
1602 goto err_deinit;
1603 }
1604
1605 memset(priv, 0, sizeof(struct serial_private) +
1606 sizeof(unsigned int) * nr_ports);
1607
1608 priv->dev = dev;
1609 priv->quirk = quirk;
1610
1611 memset(&serial_port, 0, sizeof(struct uart_port));
1612 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1613 serial_port.uartclk = board->base_baud * 16;
1614 serial_port.irq = get_pci_irq(dev, board);
1615 serial_port.dev = &dev->dev;
1616
1617 for (i = 0; i < nr_ports; i++) {
1618 if (quirk->setup(priv, board, &serial_port, i))
1619 break;
1620
1621 #ifdef SERIAL_DEBUG_PCI
1622 printk("Setup PCI port: port %x, irq %d, type %d\n",
1623 serial_port.iobase, serial_port.irq, serial_port.iotype);
1624 #endif
1625
1626 priv->line[i] = serial8250_register_port(&serial_port);
1627 if (priv->line[i] < 0) {
1628 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1629 break;
1630 }
1631 }
1632
1633 priv->nr = i;
1634
1635 return priv;
1636
1637 err_deinit:
1638 if (quirk->exit)
1639 quirk->exit(dev);
1640 err_out:
1641 return priv;
1642 }
1643 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1644
1645 void pciserial_remove_ports(struct serial_private *priv)
1646 {
1647 struct pci_serial_quirk *quirk;
1648 int i;
1649
1650 for (i = 0; i < priv->nr; i++)
1651 serial8250_unregister_port(priv->line[i]);
1652
1653 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1654 if (priv->remapped_bar[i])
1655 iounmap(priv->remapped_bar[i]);
1656 priv->remapped_bar[i] = NULL;
1657 }
1658
1659 /*
1660 * Find the exit quirks.
1661 */
1662 quirk = find_quirk(priv->dev);
1663 if (quirk->exit)
1664 quirk->exit(priv->dev);
1665
1666 kfree(priv);
1667 }
1668 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1669
1670 void pciserial_suspend_ports(struct serial_private *priv)
1671 {
1672 int i;
1673
1674 for (i = 0; i < priv->nr; i++)
1675 if (priv->line[i] >= 0)
1676 serial8250_suspend_port(priv->line[i]);
1677 }
1678 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1679
1680 void pciserial_resume_ports(struct serial_private *priv)
1681 {
1682 int i;
1683
1684 /*
1685 * Ensure that the board is correctly configured.
1686 */
1687 if (priv->quirk->init)
1688 priv->quirk->init(priv->dev);
1689
1690 for (i = 0; i < priv->nr; i++)
1691 if (priv->line[i] >= 0)
1692 serial8250_resume_port(priv->line[i]);
1693 }
1694 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1695
1696 /*
1697 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1698 * to the arrangement of serial ports on a PCI card.
1699 */
1700 static int __devinit
1701 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1702 {
1703 struct serial_private *priv;
1704 struct pciserial_board *board, tmp;
1705 int rc;
1706
1707 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1708 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1709 ent->driver_data);
1710 return -EINVAL;
1711 }
1712
1713 board = &pci_boards[ent->driver_data];
1714
1715 rc = pci_enable_device(dev);
1716 if (rc)
1717 return rc;
1718
1719 if (ent->driver_data == pbn_default) {
1720 /*
1721 * Use a copy of the pci_board entry for this;
1722 * avoid changing entries in the table.
1723 */
1724 memcpy(&tmp, board, sizeof(struct pciserial_board));
1725 board = &tmp;
1726
1727 /*
1728 * We matched one of our class entries. Try to
1729 * determine the parameters of this board.
1730 */
1731 rc = serial_pci_guess_board(dev, board);
1732 if (rc)
1733 goto disable;
1734 } else {
1735 /*
1736 * We matched an explicit entry. If we are able to
1737 * detect this boards settings with our heuristic,
1738 * then we no longer need this entry.
1739 */
1740 memcpy(&tmp, &pci_boards[pbn_default],
1741 sizeof(struct pciserial_board));
1742 rc = serial_pci_guess_board(dev, &tmp);
1743 if (rc == 0 && serial_pci_matches(board, &tmp))
1744 moan_device("Redundant entry in serial pci_table.",
1745 dev);
1746 }
1747
1748 priv = pciserial_init_ports(dev, board);
1749 if (!IS_ERR(priv)) {
1750 pci_set_drvdata(dev, priv);
1751 return 0;
1752 }
1753
1754 rc = PTR_ERR(priv);
1755
1756 disable:
1757 pci_disable_device(dev);
1758 return rc;
1759 }
1760
1761 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1762 {
1763 struct serial_private *priv = pci_get_drvdata(dev);
1764
1765 pci_set_drvdata(dev, NULL);
1766
1767 pciserial_remove_ports(priv);
1768
1769 pci_disable_device(dev);
1770 }
1771
1772 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1773 {
1774 struct serial_private *priv = pci_get_drvdata(dev);
1775
1776 if (priv)
1777 pciserial_suspend_ports(priv);
1778
1779 pci_save_state(dev);
1780 pci_set_power_state(dev, pci_choose_state(dev, state));
1781 return 0;
1782 }
1783
1784 static int pciserial_resume_one(struct pci_dev *dev)
1785 {
1786 struct serial_private *priv = pci_get_drvdata(dev);
1787
1788 pci_set_power_state(dev, PCI_D0);
1789 pci_restore_state(dev);
1790
1791 if (priv) {
1792 /*
1793 * The device may have been disabled. Re-enable it.
1794 */
1795 pci_enable_device(dev);
1796
1797 pciserial_resume_ports(priv);
1798 }
1799 return 0;
1800 }
1801
1802 static struct pci_device_id serial_pci_tbl[] = {
1803 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1804 PCI_SUBVENDOR_ID_CONNECT_TECH,
1805 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1806 pbn_b1_8_1382400 },
1807 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1808 PCI_SUBVENDOR_ID_CONNECT_TECH,
1809 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1810 pbn_b1_4_1382400 },
1811 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1812 PCI_SUBVENDOR_ID_CONNECT_TECH,
1813 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1814 pbn_b1_2_1382400 },
1815 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1816 PCI_SUBVENDOR_ID_CONNECT_TECH,
1817 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1818 pbn_b1_8_1382400 },
1819 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1820 PCI_SUBVENDOR_ID_CONNECT_TECH,
1821 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1822 pbn_b1_4_1382400 },
1823 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1824 PCI_SUBVENDOR_ID_CONNECT_TECH,
1825 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1826 pbn_b1_2_1382400 },
1827 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1828 PCI_SUBVENDOR_ID_CONNECT_TECH,
1829 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1830 pbn_b1_8_921600 },
1831 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1832 PCI_SUBVENDOR_ID_CONNECT_TECH,
1833 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1834 pbn_b1_8_921600 },
1835 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1836 PCI_SUBVENDOR_ID_CONNECT_TECH,
1837 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1838 pbn_b1_4_921600 },
1839 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1840 PCI_SUBVENDOR_ID_CONNECT_TECH,
1841 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1842 pbn_b1_4_921600 },
1843 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1844 PCI_SUBVENDOR_ID_CONNECT_TECH,
1845 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1846 pbn_b1_2_921600 },
1847 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1848 PCI_SUBVENDOR_ID_CONNECT_TECH,
1849 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1850 pbn_b1_8_921600 },
1851 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1852 PCI_SUBVENDOR_ID_CONNECT_TECH,
1853 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1854 pbn_b1_8_921600 },
1855 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1856 PCI_SUBVENDOR_ID_CONNECT_TECH,
1857 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1858 pbn_b1_4_921600 },
1859 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1860 PCI_SUBVENDOR_ID_CONNECT_TECH,
1861 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1862 pbn_b1_2_1250000 },
1863 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1864 PCI_SUBVENDOR_ID_CONNECT_TECH,
1865 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1866 pbn_b0_2_1843200 },
1867 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1868 PCI_SUBVENDOR_ID_CONNECT_TECH,
1869 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1870 pbn_b0_4_1843200 },
1871 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1872 PCI_SUBVENDOR_ID_CONNECT_TECH,
1873 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1874 pbn_b0_2_1843200_200 },
1875 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1876 PCI_SUBVENDOR_ID_CONNECT_TECH,
1877 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1878 pbn_b0_4_1843200_200 },
1879 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1880 PCI_SUBVENDOR_ID_CONNECT_TECH,
1881 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1882 pbn_b0_8_1843200_200 },
1883 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1884 PCI_SUBVENDOR_ID_CONNECT_TECH,
1885 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1886 pbn_b0_2_1843200_200 },
1887 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1888 PCI_SUBVENDOR_ID_CONNECT_TECH,
1889 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1890 pbn_b0_4_1843200_200 },
1891 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1892 PCI_SUBVENDOR_ID_CONNECT_TECH,
1893 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1894 pbn_b0_8_1843200_200 },
1895 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1896 PCI_SUBVENDOR_ID_CONNECT_TECH,
1897 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1898 pbn_b0_2_1843200_200 },
1899 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1900 PCI_SUBVENDOR_ID_CONNECT_TECH,
1901 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1902 pbn_b0_4_1843200_200 },
1903 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1904 PCI_SUBVENDOR_ID_CONNECT_TECH,
1905 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1906 pbn_b0_8_1843200_200 },
1907 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1908 PCI_SUBVENDOR_ID_CONNECT_TECH,
1909 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1910 pbn_b0_2_1843200_200 },
1911 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1912 PCI_SUBVENDOR_ID_CONNECT_TECH,
1913 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1914 pbn_b0_4_1843200_200 },
1915 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1916 PCI_SUBVENDOR_ID_CONNECT_TECH,
1917 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1918 pbn_b0_8_1843200_200 },
1919
1920 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1922 pbn_b2_bt_1_115200 },
1923 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1925 pbn_b2_bt_2_115200 },
1926 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1928 pbn_b2_bt_4_115200 },
1929 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1931 pbn_b2_bt_2_115200 },
1932 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1934 pbn_b2_bt_4_115200 },
1935 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1937 pbn_b2_8_115200 },
1938 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1940 pbn_b2_8_115200 },
1941
1942 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1944 pbn_b2_bt_2_115200 },
1945 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1947 pbn_b2_bt_2_921600 },
1948 /*
1949 * VScom SPCOM800, from sl@s.pl
1950 */
1951 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1953 pbn_b2_8_921600 },
1954 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1956 pbn_b2_4_921600 },
1957 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1958 PCI_SUBVENDOR_ID_KEYSPAN,
1959 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1960 pbn_panacom },
1961 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1963 pbn_panacom4 },
1964 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1966 pbn_panacom2 },
1967 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1968 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1969 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1970 pbn_b2_4_460800 },
1971 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1972 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1973 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1974 pbn_b2_8_460800 },
1975 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1976 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1977 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1978 pbn_b2_16_460800 },
1979 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1980 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1981 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1982 pbn_b2_16_460800 },
1983 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1984 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1985 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1986 pbn_b2_4_460800 },
1987 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1988 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1989 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1990 pbn_b2_8_460800 },
1991 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1992 PCI_SUBVENDOR_ID_EXSYS,
1993 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
1994 pbn_exsys_4055 },
1995 /*
1996 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1997 * (Exoray@isys.ca)
1998 */
1999 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2000 0x10b5, 0x106a, 0, 0,
2001 pbn_plx_romulus },
2002 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004 pbn_b1_4_115200 },
2005 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007 pbn_b1_2_115200 },
2008 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010 pbn_b1_8_115200 },
2011 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013 pbn_b1_8_115200 },
2014 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2015 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2016 pbn_b0_4_921600 },
2017 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2018 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2019 pbn_b0_4_1152000 },
2020
2021 /*
2022 * The below card is a little controversial since it is the
2023 * subject of a PCI vendor/device ID clash. (See
2024 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2025 * For now just used the hex ID 0x950a.
2026 */
2027 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2029 pbn_b0_2_1130000 },
2030 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2032 pbn_b0_4_115200 },
2033 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2035 pbn_b0_bt_2_921600 },
2036
2037 /*
2038 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2039 * from skokodyn@yahoo.com
2040 */
2041 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2042 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2043 pbn_sbsxrsio },
2044 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2045 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2046 pbn_sbsxrsio },
2047 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2048 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2049 pbn_sbsxrsio },
2050 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2051 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2052 pbn_sbsxrsio },
2053
2054 /*
2055 * Digitan DS560-558, from jimd@esoft.com
2056 */
2057 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2059 pbn_b1_1_115200 },
2060
2061 /*
2062 * Titan Electronic cards
2063 * The 400L and 800L have a custom setup quirk.
2064 */
2065 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2067 pbn_b0_1_921600 },
2068 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2070 pbn_b0_2_921600 },
2071 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2073 pbn_b0_4_921600 },
2074 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2076 pbn_b0_4_921600 },
2077 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2079 pbn_b1_1_921600 },
2080 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2082 pbn_b1_bt_2_921600 },
2083 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085 pbn_b0_bt_4_921600 },
2086 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2088 pbn_b0_bt_8_921600 },
2089
2090 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2092 pbn_b2_1_460800 },
2093 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2095 pbn_b2_1_460800 },
2096 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2098 pbn_b2_1_460800 },
2099 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2101 pbn_b2_bt_2_921600 },
2102 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2104 pbn_b2_bt_2_921600 },
2105 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107 pbn_b2_bt_2_921600 },
2108 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110 pbn_b2_bt_4_921600 },
2111 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2113 pbn_b2_bt_4_921600 },
2114 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2116 pbn_b2_bt_4_921600 },
2117 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2119 pbn_b0_1_921600 },
2120 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2122 pbn_b0_1_921600 },
2123 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2125 pbn_b0_1_921600 },
2126 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2128 pbn_b0_bt_2_921600 },
2129 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131 pbn_b0_bt_2_921600 },
2132 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134 pbn_b0_bt_2_921600 },
2135 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137 pbn_b0_bt_4_921600 },
2138 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2140 pbn_b0_bt_4_921600 },
2141 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2143 pbn_b0_bt_4_921600 },
2144
2145 /*
2146 * Computone devices submitted by Doug McNash dmcnash@computone.com
2147 */
2148 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2149 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2150 0, 0, pbn_computone_4 },
2151 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2152 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2153 0, 0, pbn_computone_8 },
2154 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2155 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2156 0, 0, pbn_computone_6 },
2157
2158 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2160 pbn_oxsemi },
2161 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2162 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2163 pbn_b0_bt_1_921600 },
2164
2165 /*
2166 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2167 */
2168 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2170 pbn_b0_bt_8_115200 },
2171 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2173 pbn_b0_bt_8_115200 },
2174
2175 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2177 pbn_b0_bt_2_115200 },
2178 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2180 pbn_b0_bt_2_115200 },
2181 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2183 pbn_b0_bt_2_115200 },
2184 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2186 pbn_b0_bt_4_460800 },
2187 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189 pbn_b0_bt_4_460800 },
2190 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2192 pbn_b0_bt_2_460800 },
2193 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2195 pbn_b0_bt_2_460800 },
2196 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2198 pbn_b0_bt_2_460800 },
2199 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2201 pbn_b0_bt_1_115200 },
2202 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2204 pbn_b0_bt_1_460800 },
2205
2206 /*
2207 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2208 */
2209 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2211 pbn_b1_1_1382400 },
2212
2213 /*
2214 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2215 */
2216 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2218 pbn_b1_1_1382400 },
2219
2220 /*
2221 * RAStel 2 port modem, gerg@moreton.com.au
2222 */
2223 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2225 pbn_b2_bt_2_115200 },
2226
2227 /*
2228 * EKF addition for i960 Boards form EKF with serial port
2229 */
2230 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2231 0xE4BF, PCI_ANY_ID, 0, 0,
2232 pbn_intel_i960 },
2233
2234 /*
2235 * Xircom Cardbus/Ethernet combos
2236 */
2237 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2239 pbn_b0_1_115200 },
2240 /*
2241 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2242 */
2243 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2245 pbn_b0_1_115200 },
2246
2247 /*
2248 * Untested PCI modems, sent in from various folks...
2249 */
2250
2251 /*
2252 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2253 */
2254 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2255 0x1048, 0x1500, 0, 0,
2256 pbn_b1_1_115200 },
2257
2258 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2259 0xFF00, 0, 0, 0,
2260 pbn_sgi_ioc3 },
2261
2262 /*
2263 * HP Diva card
2264 */
2265 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2266 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2267 pbn_b1_1_115200 },
2268 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2270 pbn_b0_5_115200 },
2271 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2273 pbn_b2_1_115200 },
2274
2275 /*
2276 * NEC Vrc-5074 (Nile 4) builtin UART.
2277 */
2278 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2280 pbn_nec_nile4 },
2281
2282 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2284 pbn_b3_2_115200 },
2285 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2287 pbn_b3_4_115200 },
2288 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2290 pbn_b3_8_115200 },
2291
2292 /*
2293 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2294 */
2295 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2296 PCI_ANY_ID, PCI_ANY_ID,
2297 0,
2298 0, pbn_exar_XR17C152 },
2299 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2300 PCI_ANY_ID, PCI_ANY_ID,
2301 0,
2302 0, pbn_exar_XR17C154 },
2303 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2304 PCI_ANY_ID, PCI_ANY_ID,
2305 0,
2306 0, pbn_exar_XR17C158 },
2307
2308 /*
2309 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2310 */
2311 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2313 pbn_b0_1_115200 },
2314
2315 /*
2316 * These entries match devices with class COMMUNICATION_SERIAL,
2317 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2318 */
2319 { PCI_ANY_ID, PCI_ANY_ID,
2320 PCI_ANY_ID, PCI_ANY_ID,
2321 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2322 0xffff00, pbn_default },
2323 { PCI_ANY_ID, PCI_ANY_ID,
2324 PCI_ANY_ID, PCI_ANY_ID,
2325 PCI_CLASS_COMMUNICATION_MODEM << 8,
2326 0xffff00, pbn_default },
2327 { PCI_ANY_ID, PCI_ANY_ID,
2328 PCI_ANY_ID, PCI_ANY_ID,
2329 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2330 0xffff00, pbn_default },
2331 { 0, }
2332 };
2333
2334 static struct pci_driver serial_pci_driver = {
2335 .name = "serial",
2336 .probe = pciserial_init_one,
2337 .remove = __devexit_p(pciserial_remove_one),
2338 .suspend = pciserial_suspend_one,
2339 .resume = pciserial_resume_one,
2340 .id_table = serial_pci_tbl,
2341 };
2342
2343 static int __init serial8250_pci_init(void)
2344 {
2345 return pci_register_driver(&serial_pci_driver);
2346 }
2347
2348 static void __exit serial8250_pci_exit(void)
2349 {
2350 pci_unregister_driver(&serial_pci_driver);
2351 }
2352
2353 module_init(serial8250_pci_init);
2354 module_exit(serial8250_pci_exit);
2355
2356 MODULE_LICENSE("GPL");
2357 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2358 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
SocketAccessConTroL development