2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.01"
56 AHCI_MAX_SG
= 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY
= 0xffffffff,
58 AHCI_USE_CLUSTERING
= 0,
59 AHCI_CMD_SLOT_SZ
= 32 * 32,
61 AHCI_CMD_TBL_HDR
= 0x80,
62 AHCI_CMD_TBL_CDB
= 0x40,
63 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR
+ (AHCI_MAX_SG
* 16),
64 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_SZ
+
66 AHCI_IRQ_ON_SG
= (1 << 31),
67 AHCI_CMD_ATAPI
= (1 << 5),
68 AHCI_CMD_WRITE
= (1 << 6),
70 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
74 /* global controller registers */
75 HOST_CAP
= 0x00, /* host capabilities */
76 HOST_CTL
= 0x04, /* global host control */
77 HOST_IRQ_STAT
= 0x08, /* interrupt status */
78 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
82 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
87 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
89 /* registers for each SATA port */
90 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT
= 0x10, /* interrupt status */
95 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
96 PORT_CMD
= 0x18, /* port command */
97 PORT_TFDATA
= 0x20, /* taskfile data */
98 PORT_SIG
= 0x24, /* device TF signature */
99 PORT_CMD_ISSUE
= 0x38, /* command issue */
100 PORT_SCR
= 0x28, /* SATA phy register block */
101 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
116 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
126 PORT_IRQ_FATAL
= PORT_IRQ_TF_ERR
|
128 PORT_IRQ_HBUS_DATA_ERR
|
130 DEF_PORT_IRQ
= PORT_IRQ_FATAL
| PORT_IRQ_PHYRDY
|
131 PORT_IRQ_CONNECT
| PORT_IRQ_SG_DONE
|
132 PORT_IRQ_UNK_FIS
| PORT_IRQ_SDB_FIS
|
133 PORT_IRQ_DMAS_FIS
| PORT_IRQ_PIOS_FIS
|
134 PORT_IRQ_D2H_REG_FIS
,
137 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
138 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
139 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
140 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
141 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
142 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
144 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
145 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
146 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
148 /* hpriv->flags bits */
149 AHCI_FLAG_MSI
= (1 << 0),
152 struct ahci_cmd_hdr
{
167 struct ahci_host_priv
{
169 u32 cap
; /* cache of HOST_CAP register */
170 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
173 struct ahci_port_priv
{
174 struct ahci_cmd_hdr
*cmd_slot
;
175 dma_addr_t cmd_slot_dma
;
177 dma_addr_t cmd_tbl_dma
;
178 struct ahci_sg
*cmd_tbl_sg
;
180 dma_addr_t rx_fis_dma
;
183 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
184 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
185 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
186 static int ahci_qc_issue(struct ata_queued_cmd
*qc
);
187 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
188 static void ahci_phy_reset(struct ata_port
*ap
);
189 static void ahci_irq_clear(struct ata_port
*ap
);
190 static void ahci_eng_timeout(struct ata_port
*ap
);
191 static int ahci_port_start(struct ata_port
*ap
);
192 static void ahci_port_stop(struct ata_port
*ap
);
193 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
194 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
195 static u8
ahci_check_status(struct ata_port
*ap
);
196 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
);
197 static void ahci_remove_one (struct pci_dev
*pdev
);
199 static Scsi_Host_Template ahci_sht
= {
200 .module
= THIS_MODULE
,
202 .ioctl
= ata_scsi_ioctl
,
203 .queuecommand
= ata_scsi_queuecmd
,
204 .eh_strategy_handler
= ata_scsi_error
,
205 .can_queue
= ATA_DEF_QUEUE
,
206 .this_id
= ATA_SHT_THIS_ID
,
207 .sg_tablesize
= AHCI_MAX_SG
,
208 .max_sectors
= ATA_MAX_SECTORS
,
209 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
210 .emulated
= ATA_SHT_EMULATED
,
211 .use_clustering
= AHCI_USE_CLUSTERING
,
212 .proc_name
= DRV_NAME
,
213 .dma_boundary
= AHCI_DMA_BOUNDARY
,
214 .slave_configure
= ata_scsi_slave_config
,
215 .bios_param
= ata_std_bios_param
,
219 static const struct ata_port_operations ahci_ops
= {
220 .port_disable
= ata_port_disable
,
222 .check_status
= ahci_check_status
,
223 .check_altstatus
= ahci_check_status
,
224 .dev_select
= ata_noop_dev_select
,
226 .tf_read
= ahci_tf_read
,
228 .phy_reset
= ahci_phy_reset
,
230 .qc_prep
= ahci_qc_prep
,
231 .qc_issue
= ahci_qc_issue
,
233 .eng_timeout
= ahci_eng_timeout
,
235 .irq_handler
= ahci_interrupt
,
236 .irq_clear
= ahci_irq_clear
,
238 .scr_read
= ahci_scr_read
,
239 .scr_write
= ahci_scr_write
,
241 .port_start
= ahci_port_start
,
242 .port_stop
= ahci_port_stop
,
245 static struct ata_port_info ahci_port_info
[] = {
249 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
250 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
|
252 .pio_mask
= 0x1f, /* pio0-4 */
253 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
254 .port_ops
= &ahci_ops
,
258 static struct pci_device_id ahci_pci_tbl
[] = {
259 { PCI_VENDOR_ID_INTEL
, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
260 board_ahci
}, /* ICH6 */
261 { PCI_VENDOR_ID_INTEL
, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
262 board_ahci
}, /* ICH6M */
263 { PCI_VENDOR_ID_INTEL
, 0x27c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
264 board_ahci
}, /* ICH7 */
265 { PCI_VENDOR_ID_INTEL
, 0x27c5, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
266 board_ahci
}, /* ICH7M */
267 { PCI_VENDOR_ID_INTEL
, 0x27c3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
268 board_ahci
}, /* ICH7R */
269 { PCI_VENDOR_ID_AL
, 0x5288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
270 board_ahci
}, /* ULi M5288 */
271 { PCI_VENDOR_ID_INTEL
, 0x2681, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
272 board_ahci
}, /* ESB2 */
273 { PCI_VENDOR_ID_INTEL
, 0x2682, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
274 board_ahci
}, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL
, 0x2683, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
276 board_ahci
}, /* ESB2 */
277 { PCI_VENDOR_ID_INTEL
, 0x27c6, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
278 board_ahci
}, /* ICH7-M DH */
279 { } /* terminate list */
283 static struct pci_driver ahci_pci_driver
= {
285 .id_table
= ahci_pci_tbl
,
286 .probe
= ahci_init_one
,
287 .remove
= ahci_remove_one
,
291 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
293 return base
+ 0x100 + (port
* 0x80);
296 static inline void __iomem
*ahci_port_base (void __iomem
*base
, unsigned int port
)
298 return (void __iomem
*) ahci_port_base_ul((unsigned long)base
, port
);
301 static int ahci_port_start(struct ata_port
*ap
)
303 struct device
*dev
= ap
->host_set
->dev
;
304 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
305 struct ahci_port_priv
*pp
;
306 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
307 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
312 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
315 memset(pp
, 0, sizeof(*pp
));
317 rc
= ata_pad_alloc(ap
, dev
);
323 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
325 ata_pad_free(ap
, dev
);
329 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
332 * First item in chunk of DMA memory: 32-slot command table,
333 * 32 bytes each in size
336 pp
->cmd_slot_dma
= mem_dma
;
338 mem
+= AHCI_CMD_SLOT_SZ
;
339 mem_dma
+= AHCI_CMD_SLOT_SZ
;
342 * Second item: Received-FIS area
345 pp
->rx_fis_dma
= mem_dma
;
347 mem
+= AHCI_RX_FIS_SZ
;
348 mem_dma
+= AHCI_RX_FIS_SZ
;
351 * Third item: data area for storing a single command
352 * and its scatter-gather table
355 pp
->cmd_tbl_dma
= mem_dma
;
357 pp
->cmd_tbl_sg
= mem
+ AHCI_CMD_TBL_HDR
;
359 ap
->private_data
= pp
;
361 if (hpriv
->cap
& HOST_CAP_64
)
362 writel((pp
->cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
363 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
364 readl(port_mmio
+ PORT_LST_ADDR
); /* flush */
366 if (hpriv
->cap
& HOST_CAP_64
)
367 writel((pp
->rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
368 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
369 readl(port_mmio
+ PORT_FIS_ADDR
); /* flush */
371 writel(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
372 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
373 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
374 readl(port_mmio
+ PORT_CMD
); /* flush */
380 static void ahci_port_stop(struct ata_port
*ap
)
382 struct device
*dev
= ap
->host_set
->dev
;
383 struct ahci_port_priv
*pp
= ap
->private_data
;
384 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
385 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
388 tmp
= readl(port_mmio
+ PORT_CMD
);
389 tmp
&= ~(PORT_CMD_START
| PORT_CMD_FIS_RX
);
390 writel(tmp
, port_mmio
+ PORT_CMD
);
391 readl(port_mmio
+ PORT_CMD
); /* flush */
393 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
394 * this is slightly incorrect.
398 ap
->private_data
= NULL
;
399 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
400 pp
->cmd_slot
, pp
->cmd_slot_dma
);
401 ata_pad_free(ap
, dev
);
405 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
410 case SCR_STATUS
: sc_reg
= 0; break;
411 case SCR_CONTROL
: sc_reg
= 1; break;
412 case SCR_ERROR
: sc_reg
= 2; break;
413 case SCR_ACTIVE
: sc_reg
= 3; break;
418 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
422 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
428 case SCR_STATUS
: sc_reg
= 0; break;
429 case SCR_CONTROL
: sc_reg
= 1; break;
430 case SCR_ERROR
: sc_reg
= 2; break;
431 case SCR_ACTIVE
: sc_reg
= 3; break;
436 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
439 static void ahci_phy_reset(struct ata_port
*ap
)
441 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
442 struct ata_taskfile tf
;
443 struct ata_device
*dev
= &ap
->device
[0];
446 __sata_phy_reset(ap
);
448 if (ap
->flags
& ATA_FLAG_PORT_DISABLED
)
451 tmp
= readl(port_mmio
+ PORT_SIG
);
452 tf
.lbah
= (tmp
>> 24) & 0xff;
453 tf
.lbam
= (tmp
>> 16) & 0xff;
454 tf
.lbal
= (tmp
>> 8) & 0xff;
455 tf
.nsect
= (tmp
) & 0xff;
457 dev
->class = ata_dev_classify(&tf
);
458 if (!ata_dev_present(dev
))
459 ata_port_disable(ap
);
462 static u8
ahci_check_status(struct ata_port
*ap
)
464 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
466 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
469 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
471 struct ahci_port_priv
*pp
= ap
->private_data
;
472 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
474 ata_tf_from_fis(d2h_fis
, tf
);
477 static void ahci_fill_sg(struct ata_queued_cmd
*qc
)
479 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
480 struct scatterlist
*sg
;
481 struct ahci_sg
*ahci_sg
;
486 * Next, the S/G list.
488 ahci_sg
= pp
->cmd_tbl_sg
;
489 ata_for_each_sg(sg
, qc
) {
490 dma_addr_t addr
= sg_dma_address(sg
);
491 u32 sg_len
= sg_dma_len(sg
);
493 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
494 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
495 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
500 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
502 struct ata_port
*ap
= qc
->ap
;
503 struct ahci_port_priv
*pp
= ap
->private_data
;
505 const u32 cmd_fis_len
= 5; /* five dwords */
508 * Fill in command slot information (currently only one slot,
509 * slot 0, is currently since we don't do queueing)
512 opts
= (qc
->n_elem
<< 16) | cmd_fis_len
;
513 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
514 opts
|= AHCI_CMD_WRITE
;
515 if (is_atapi_taskfile(&qc
->tf
))
516 opts
|= AHCI_CMD_ATAPI
;
518 pp
->cmd_slot
[0].opts
= cpu_to_le32(opts
);
519 pp
->cmd_slot
[0].status
= 0;
520 pp
->cmd_slot
[0].tbl_addr
= cpu_to_le32(pp
->cmd_tbl_dma
& 0xffffffff);
521 pp
->cmd_slot
[0].tbl_addr_hi
= cpu_to_le32((pp
->cmd_tbl_dma
>> 16) >> 16);
524 * Fill in command table information. First, the header,
525 * a SATA Register - Host to Device command FIS.
527 ata_tf_to_fis(&qc
->tf
, pp
->cmd_tbl
, 0);
528 if (opts
& AHCI_CMD_ATAPI
) {
529 memset(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
530 memcpy(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, ap
->cdb_len
);
533 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
539 static void ahci_intr_error(struct ata_port
*ap
, u32 irq_stat
)
541 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
542 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
547 tmp
= readl(port_mmio
+ PORT_CMD
);
548 tmp
&= ~PORT_CMD_START
;
549 writel(tmp
, port_mmio
+ PORT_CMD
);
551 /* wait for engine to stop. TODO: this could be
552 * as long as 500 msec
556 tmp
= readl(port_mmio
+ PORT_CMD
);
557 if ((tmp
& PORT_CMD_LIST_ON
) == 0)
562 /* clear SATA phy error, if any */
563 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
564 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
566 /* if DRQ/BSY is set, device needs to be reset.
567 * if so, issue COMRESET
569 tmp
= readl(port_mmio
+ PORT_TFDATA
);
570 if (tmp
& (ATA_BUSY
| ATA_DRQ
)) {
571 writel(0x301, port_mmio
+ PORT_SCR_CTL
);
572 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
574 writel(0x300, port_mmio
+ PORT_SCR_CTL
);
575 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
579 tmp
= readl(port_mmio
+ PORT_CMD
);
580 tmp
|= PORT_CMD_START
;
581 writel(tmp
, port_mmio
+ PORT_CMD
);
582 readl(port_mmio
+ PORT_CMD
); /* flush */
584 printk(KERN_WARNING
"ata%u: error occurred, port reset\n", ap
->id
);
587 static void ahci_eng_timeout(struct ata_port
*ap
)
589 struct ata_host_set
*host_set
= ap
->host_set
;
590 void __iomem
*mmio
= host_set
->mmio_base
;
591 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
592 struct ata_queued_cmd
*qc
;
597 spin_lock_irqsave(&host_set
->lock
, flags
);
599 ahci_intr_error(ap
, readl(port_mmio
+ PORT_IRQ_STAT
));
601 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
603 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
606 /* hack alert! We cannot use the supplied completion
607 * function from inside the ->eh_strategy_handler() thread.
608 * libata is the only user of ->eh_strategy_handler() in
609 * any kernel, so the default scsi_done() assumes it is
610 * not being called from the SCSI EH.
612 qc
->scsidone
= scsi_finish_command
;
613 ata_qc_complete(qc
, AC_ERR_OTHER
);
616 spin_unlock_irqrestore(&host_set
->lock
, flags
);
619 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
621 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
622 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
623 u32 status
, serr
, ci
;
625 serr
= readl(port_mmio
+ PORT_SCR_ERR
);
626 writel(serr
, port_mmio
+ PORT_SCR_ERR
);
628 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
629 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
631 ci
= readl(port_mmio
+ PORT_CMD_ISSUE
);
632 if (likely((ci
& 0x1) == 0)) {
634 ata_qc_complete(qc
, 0);
639 if (status
& PORT_IRQ_FATAL
) {
640 ahci_intr_error(ap
, status
);
642 ata_qc_complete(qc
, AC_ERR_OTHER
);
648 static void ahci_irq_clear(struct ata_port
*ap
)
653 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
655 struct ata_host_set
*host_set
= dev_instance
;
656 struct ahci_host_priv
*hpriv
;
657 unsigned int i
, handled
= 0;
659 u32 irq_stat
, irq_ack
= 0;
663 hpriv
= host_set
->private_data
;
664 mmio
= host_set
->mmio_base
;
666 /* sigh. 0xffffffff is a valid return from h/w */
667 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
668 irq_stat
&= hpriv
->port_map
;
672 spin_lock(&host_set
->lock
);
674 for (i
= 0; i
< host_set
->n_ports
; i
++) {
677 if (!(irq_stat
& (1 << i
)))
680 ap
= host_set
->ports
[i
];
682 struct ata_queued_cmd
*qc
;
683 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
684 if (!ahci_host_intr(ap
, qc
))
685 if (ata_ratelimit()) {
686 struct pci_dev
*pdev
=
687 to_pci_dev(ap
->host_set
->dev
);
688 dev_printk(KERN_WARNING
, &pdev
->dev
,
689 "unhandled interrupt on port %u\n",
693 VPRINTK("port %u\n", i
);
695 VPRINTK("port %u (no irq)\n", i
);
696 if (ata_ratelimit()) {
697 struct pci_dev
*pdev
=
698 to_pci_dev(ap
->host_set
->dev
);
699 dev_printk(KERN_WARNING
, &pdev
->dev
,
700 "interrupt on disabled port %u\n", i
);
708 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
712 spin_unlock(&host_set
->lock
);
716 return IRQ_RETVAL(handled
);
719 static int ahci_qc_issue(struct ata_queued_cmd
*qc
)
721 struct ata_port
*ap
= qc
->ap
;
722 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
724 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
725 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
730 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
731 unsigned int port_idx
)
733 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
734 base
= ahci_port_base_ul(base
, port_idx
);
735 VPRINTK("base now==0x%lx\n", base
);
737 port
->cmd_addr
= base
;
738 port
->scr_addr
= base
+ PORT_SCR
;
743 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
745 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
746 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
747 void __iomem
*mmio
= probe_ent
->mmio_base
;
750 unsigned int i
, j
, using_dac
;
752 void __iomem
*port_mmio
;
754 cap_save
= readl(mmio
+ HOST_CAP
);
755 cap_save
&= ( (1<<28) | (1<<17) );
756 cap_save
|= (1 << 27);
758 /* global controller reset */
759 tmp
= readl(mmio
+ HOST_CTL
);
760 if ((tmp
& HOST_RESET
) == 0) {
761 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
762 readl(mmio
+ HOST_CTL
); /* flush */
765 /* reset must complete within 1 second, or
766 * the hardware should be considered fried.
770 tmp
= readl(mmio
+ HOST_CTL
);
771 if (tmp
& HOST_RESET
) {
772 dev_printk(KERN_ERR
, &pdev
->dev
,
773 "controller reset failed (0x%x)\n", tmp
);
777 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
778 (void) readl(mmio
+ HOST_CTL
); /* flush */
779 writel(cap_save
, mmio
+ HOST_CAP
);
780 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
781 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
783 pci_read_config_word(pdev
, 0x92, &tmp16
);
785 pci_write_config_word(pdev
, 0x92, tmp16
);
787 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
788 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
789 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
791 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
792 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
794 using_dac
= hpriv
->cap
& HOST_CAP_64
;
796 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
797 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
799 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
801 dev_printk(KERN_ERR
, &pdev
->dev
,
802 "64-bit DMA enable failed\n");
807 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
809 dev_printk(KERN_ERR
, &pdev
->dev
,
810 "32-bit DMA enable failed\n");
813 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
815 dev_printk(KERN_ERR
, &pdev
->dev
,
816 "32-bit consistent DMA enable failed\n");
821 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
822 #if 0 /* BIOSen initialize this incorrectly */
823 if (!(hpriv
->port_map
& (1 << i
)))
827 port_mmio
= ahci_port_base(mmio
, i
);
828 VPRINTK("mmio %p port_mmio %p\n", mmio
, port_mmio
);
830 ahci_setup_port(&probe_ent
->port
[i
],
831 (unsigned long) mmio
, i
);
833 /* make sure port is not active */
834 tmp
= readl(port_mmio
+ PORT_CMD
);
835 VPRINTK("PORT_CMD 0x%x\n", tmp
);
836 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
837 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
838 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
839 PORT_CMD_FIS_RX
| PORT_CMD_START
);
840 writel(tmp
, port_mmio
+ PORT_CMD
);
841 readl(port_mmio
+ PORT_CMD
); /* flush */
843 /* spec says 500 msecs for each bit, so
844 * this is slightly incorrect.
849 writel(PORT_CMD_SPIN_UP
, port_mmio
+ PORT_CMD
);
854 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
855 if ((tmp
& 0xf) == 0x3)
860 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
861 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
862 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
864 /* ack any pending irq events for this port */
865 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
866 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
868 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
870 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
872 /* set irq mask (enables interrupts) */
873 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
876 tmp
= readl(mmio
+ HOST_CTL
);
877 VPRINTK("HOST_CTL 0x%x\n", tmp
);
878 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
879 tmp
= readl(mmio
+ HOST_CTL
);
880 VPRINTK("HOST_CTL 0x%x\n", tmp
);
882 pci_set_master(pdev
);
887 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
889 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
890 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
891 void __iomem
*mmio
= probe_ent
->mmio_base
;
892 u32 vers
, cap
, impl
, speed
;
897 vers
= readl(mmio
+ HOST_VERSION
);
899 impl
= hpriv
->port_map
;
901 speed
= (cap
>> 20) & 0xf;
909 pci_read_config_word(pdev
, 0x0a, &cc
);
912 else if (cc
== 0x0106)
914 else if (cc
== 0x0104)
919 dev_printk(KERN_INFO
, &pdev
->dev
,
920 "AHCI %02x%02x.%02x%02x "
921 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
929 ((cap
>> 8) & 0x1f) + 1,
935 dev_printk(KERN_INFO
, &pdev
->dev
,
941 cap
& (1 << 31) ? "64bit " : "",
942 cap
& (1 << 30) ? "ncq " : "",
943 cap
& (1 << 28) ? "ilck " : "",
944 cap
& (1 << 27) ? "stag " : "",
945 cap
& (1 << 26) ? "pm " : "",
946 cap
& (1 << 25) ? "led " : "",
948 cap
& (1 << 24) ? "clo " : "",
949 cap
& (1 << 19) ? "nz " : "",
950 cap
& (1 << 18) ? "only " : "",
951 cap
& (1 << 17) ? "pmp " : "",
952 cap
& (1 << 15) ? "pio " : "",
953 cap
& (1 << 14) ? "slum " : "",
954 cap
& (1 << 13) ? "part " : ""
958 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
960 static int printed_version
;
961 struct ata_probe_ent
*probe_ent
= NULL
;
962 struct ahci_host_priv
*hpriv
;
964 void __iomem
*mmio_base
;
965 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
966 int have_msi
, pci_dev_busy
= 0;
971 if (!printed_version
++)
972 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
974 rc
= pci_enable_device(pdev
);
978 rc
= pci_request_regions(pdev
, DRV_NAME
);
984 if (pci_enable_msi(pdev
) == 0)
991 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
992 if (probe_ent
== NULL
) {
997 memset(probe_ent
, 0, sizeof(*probe_ent
));
998 probe_ent
->dev
= pci_dev_to_dev(pdev
);
999 INIT_LIST_HEAD(&probe_ent
->node
);
1001 mmio_base
= pci_iomap(pdev
, AHCI_PCI_BAR
, 0);
1002 if (mmio_base
== NULL
) {
1004 goto err_out_free_ent
;
1006 base
= (unsigned long) mmio_base
;
1008 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1011 goto err_out_iounmap
;
1013 memset(hpriv
, 0, sizeof(*hpriv
));
1015 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1016 probe_ent
->host_flags
= ahci_port_info
[board_idx
].host_flags
;
1017 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1018 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1019 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1021 probe_ent
->irq
= pdev
->irq
;
1022 probe_ent
->irq_flags
= SA_SHIRQ
;
1023 probe_ent
->mmio_base
= mmio_base
;
1024 probe_ent
->private_data
= hpriv
;
1027 hpriv
->flags
|= AHCI_FLAG_MSI
;
1029 /* initialize adapter */
1030 rc
= ahci_host_init(probe_ent
);
1034 ahci_print_info(probe_ent
);
1036 /* FIXME: check ata_device_add return value */
1037 ata_device_add(probe_ent
);
1045 pci_iounmap(pdev
, mmio_base
);
1050 pci_disable_msi(pdev
);
1053 pci_release_regions(pdev
);
1056 pci_disable_device(pdev
);
1060 static void ahci_remove_one (struct pci_dev
*pdev
)
1062 struct device
*dev
= pci_dev_to_dev(pdev
);
1063 struct ata_host_set
*host_set
= dev_get_drvdata(dev
);
1064 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
1065 struct ata_port
*ap
;
1069 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1070 ap
= host_set
->ports
[i
];
1072 scsi_remove_host(ap
->host
);
1075 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1076 free_irq(host_set
->irq
, host_set
);
1078 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1079 ap
= host_set
->ports
[i
];
1081 ata_scsi_release(ap
->host
);
1082 scsi_host_put(ap
->host
);
1086 pci_iounmap(pdev
, host_set
->mmio_base
);
1090 pci_disable_msi(pdev
);
1093 pci_release_regions(pdev
);
1094 pci_disable_device(pdev
);
1095 dev_set_drvdata(dev
, NULL
);
1098 static int __init
ahci_init(void)
1100 return pci_module_init(&ahci_pci_driver
);
1103 static void __exit
ahci_exit(void)
1105 pci_unregister_driver(&ahci_pci_driver
);
1109 MODULE_AUTHOR("Jeff Garzik");
1110 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1111 MODULE_LICENSE("GPL");
1112 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1113 MODULE_VERSION(DRV_VERSION
);
1115 module_init(ahci_init
);
1116 module_exit(ahci_exit
);