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[PATCH] orinoco: bump version to 0.15
[linux-2.6/sactl.git] / drivers / scsi / ncr53c8xx.h
blob0e4e46a01336530dc4204b1f1a7a8f86b9500896
1 /******************************************************************************
2 ** Device driver for the PCI-SCSI NCR538XX controller family.
3 **
4 ** Copyright (C) 1994 Wolfgang Stanglmeier
5 ** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
6 **
7 ** This program is free software; you can redistribute it and/or modify
8 ** it under the terms of the GNU General Public License as published by
9 ** the Free Software Foundation; either version 2 of the License, or
10 ** (at your option) any later version.
11 **
12 ** This program is distributed in the hope that it will be useful,
13 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ** GNU General Public License for more details.
16 **
17 ** You should have received a copy of the GNU General Public License
18 ** along with this program; if not, write to the Free Software
19 ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 **
21 **-----------------------------------------------------------------------------
22 **
23 ** This driver has been ported to Linux from the FreeBSD NCR53C8XX driver
24 ** and is currently maintained by
25 **
26 ** Gerard Roudier <groudier@free.fr>
27 **
28 ** Being given that this driver originates from the FreeBSD version, and
29 ** in order to keep synergy on both, any suggested enhancements and corrections
30 ** received on Linux are automatically a potential candidate for the FreeBSD
31 ** version.
32 **
33 ** The original driver has been written for 386bsd and FreeBSD by
34 ** Wolfgang Stanglmeier <wolf@cologne.de>
35 ** Stefan Esser <se@mi.Uni-Koeln.de>
36 **
37 ** And has been ported to NetBSD by
38 ** Charles M. Hannum <mycroft@gnu.ai.mit.edu>
39 **
40 ** NVRAM detection and reading.
41 ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
42 **
43 ** Added support for MIPS big endian systems.
44 ** Carsten Langgaard, carstenl@mips.com
45 ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
46 **
47 ** Added support for HP PARISC big endian systems.
48 ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
49 **
50 *******************************************************************************
51 */
52
53 #ifndef NCR53C8XX_H
54 #define NCR53C8XX_H
55
56 #include <linux/config.h>
57 #include <scsi/scsi_host.h>
58
59 #include <linux/config.h>
60
61 /*
62 ** If you want a driver as small as possible, donnot define the
63 ** following options.
64 */
65 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
66 #define SCSI_NCR_DEBUG_INFO_SUPPORT
67
68 /*
69 ** To disable integrity checking, do not define the
70 ** following option.
71 */
72 #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
73 # define SCSI_NCR_ENABLE_INTEGRITY_CHECK
74 #endif
75
76 /* ---------------------------------------------------------------------
77 ** Take into account kernel configured parameters.
78 ** Most of these options can be overridden at startup by a command line.
79 ** ---------------------------------------------------------------------
80 */
81
82 /*
83 * For Ultra2 and Ultra3 SCSI support option, use special features.
84 *
85 * Value (default) means:
86 * bit 0 : all features enabled, except:
87 * bit 1 : PCI Write And Invalidate.
88 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
89 *
90 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
91 * enabled by the driver.
92 */
93 #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
94
95 #define SCSI_NCR_MAX_SYNC (80)
96
97 /*
98 * Allow tags from 2 to 256, default 8
99 */
100 #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
101 #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
102 #define SCSI_NCR_MAX_TAGS (2)
103 #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
104 #define SCSI_NCR_MAX_TAGS (256)
105 #else
106 #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
107 #endif
108 #else
109 #define SCSI_NCR_MAX_TAGS (8)
110 #endif
111
112 /*
113 * Allow tagged command queuing support if configured with default number
114 * of tags set to max (see above).
115 */
116 #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
117 #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
118 #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
119 #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
120 #else
121 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
122 #endif
123
124 /*
125 * Immediate arbitration
126 */
127 #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
128 #define SCSI_NCR_IARB_SUPPORT
129 #endif
130
131 /*
132 * Sync transfer frequency at startup.
133 * Allow from 5Mhz to 80Mhz default 20 Mhz.
134 */
135 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
136 #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
137 #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
138 #undef CONFIG_SCSI_NCR53C8XX_SYNC
139 #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
140 #endif
141
142 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
143 #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
144 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
145 #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
146 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
147 #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
148 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
149 #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
150 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
151 #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
152 #else
153 #define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
154 #endif
155
156 /*
157 * Disallow disconnections at boot-up
158 */
159 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
160 #define SCSI_NCR_SETUP_DISCONNECTION (0)
161 #else
162 #define SCSI_NCR_SETUP_DISCONNECTION (1)
163 #endif
164
165 /*
166 * Force synchronous negotiation for all targets
167 */
168 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
169 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
170 #else
171 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
172 #endif
173
174 /*
175 * Disable master parity checking (flawed hardwares need that)
176 */
177 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
178 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
179 #else
180 #define SCSI_NCR_SETUP_MASTER_PARITY (1)
181 #endif
182
183 /*
184 * Disable scsi parity checking (flawed devices may need that)
185 */
186 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
187 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
188 #else
189 #define SCSI_NCR_SETUP_SCSI_PARITY (1)
190 #endif
191
192 /*
193 * Settle time after reset at boot-up
194 */
195 #define SCSI_NCR_SETUP_SETTLE_TIME (2)
196
197 /*
198 ** Bridge quirks work-around option defaulted to 1.
199 */
200 #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
201 #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
202 #endif
203
204 /*
205 ** Work-around common bridge misbehaviour.
206 **
207 ** - Do not flush posted writes in the opposite
208 ** direction on read.
209 ** - May reorder DMA writes to memory.
210 **
211 ** This option should not affect performances
212 ** significantly, so it is the default.
213 */
214 #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
215 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
216 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
217 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
218
219 /*
220 ** Same as option 1, but also deal with
221 ** misconfigured interrupts.
222 **
223 ** - Edge triggerred instead of level sensitive.
224 ** - No interrupt line connected.
225 ** - IRQ number misconfigured.
226 **
227 ** If no interrupt is delivered, the driver will
228 ** catch the interrupt conditions 10 times per
229 ** second. No need to say that this option is
230 ** not recommended.
231 */
232 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
233 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
234 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
235 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
236 #define SCSI_NCR_PCIQ_BROKEN_INTR
237
238 /*
239 ** Some bridge designers decided to flush
240 ** everything prior to deliver the interrupt.
241 ** This option tries to deal with such a
242 ** behaviour.
243 */
244 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
245 #define SCSI_NCR_PCIQ_SYNC_ON_INTR
246 #endif
247
248 /*
249 ** Other parameters not configurable with "make config"
250 ** Avoid to change these constants, unless you know what you are doing.
251 */
252
253 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
254 #define SCSI_NCR_MAX_SCATTER (127)
255 #define SCSI_NCR_MAX_TARGET (16)
256
257 /*
258 ** Compute some desirable value for CAN_QUEUE
259 ** and CMD_PER_LUN.
260 ** The driver will use lower values if these
261 ** ones appear to be too large.
262 */
263 #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
264 #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
265
266 #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
267 #define SCSI_NCR_TIMER_INTERVAL (HZ)
268
269 #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
270 #define SCSI_NCR_MAX_LUN (16)
271 #else
272 #define SCSI_NCR_MAX_LUN (1)
273 #endif
274
275 /*
276 * IO functions definition for big/little endian CPU support.
277 * For now, the NCR is only supported in little endian addressing mode,
278 */
279
280 #ifdef __BIG_ENDIAN
281
282 #define inw_l2b inw
283 #define inl_l2b inl
284 #define outw_b2l outw
285 #define outl_b2l outl
286
287 #define readb_raw readb
288 #define writeb_raw writeb
289
290 #if defined(SCSI_NCR_BIG_ENDIAN)
291 #define readw_l2b __raw_readw
292 #define readl_l2b __raw_readl
293 #define writew_b2l __raw_writew
294 #define writel_b2l __raw_writel
295 #define readw_raw __raw_readw
296 #define readl_raw __raw_readl
297 #define writew_raw __raw_writew
298 #define writel_raw __raw_writel
299 #else /* Other big-endian */
300 #define readw_l2b readw
301 #define readl_l2b readl
302 #define writew_b2l writew
303 #define writel_b2l writel
304 #define readw_raw readw
305 #define readl_raw readl
306 #define writew_raw writew
307 #define writel_raw writel
308 #endif
309
310 #else /* little endian */
311
312 #define inw_raw inw
313 #define inl_raw inl
314 #define outw_raw outw
315 #define outl_raw outl
316
317 #define readb_raw readb
318 #define readw_raw readw
319 #define readl_raw readl
320 #define writeb_raw writeb
321 #define writew_raw writew
322 #define writel_raw writel
323
324 #endif
325
326 #if !defined(__hppa__) && !defined(__mips__)
327 #ifdef SCSI_NCR_BIG_ENDIAN
328 #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
329 #endif
330 #endif
331
332 #define MEMORY_BARRIER() mb()
333
334
335 /*
336 * If the NCR uses big endian addressing mode over the
337 * PCI, actual io register addresses for byte and word
338 * accesses must be changed according to lane routing.
339 * Btw, ncr_offb() and ncr_offw() macros only apply to
340 * constants and so donnot generate bloated code.
341 */
342
343 #if defined(SCSI_NCR_BIG_ENDIAN)
344
345 #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
346 #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
347
348 #else
349
350 #define ncr_offb(o) (o)
351 #define ncr_offw(o) (o)
352
353 #endif
354
355 /*
356 * If the CPU and the NCR use same endian-ness addressing,
357 * no byte reordering is needed for script patching.
358 * Macro cpu_to_scr() is to be used for script patching.
359 * Macro scr_to_cpu() is to be used for getting a DWORD
360 * from the script.
361 */
362
363 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
364
365 #define cpu_to_scr(dw) cpu_to_le32(dw)
366 #define scr_to_cpu(dw) le32_to_cpu(dw)
367
368 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
369
370 #define cpu_to_scr(dw) cpu_to_be32(dw)
371 #define scr_to_cpu(dw) be32_to_cpu(dw)
372
373 #else
374
375 #define cpu_to_scr(dw) (dw)
376 #define scr_to_cpu(dw) (dw)
377
378 #endif
379
380 /*
381 * Access to the controller chip.
382 *
383 * If the CPU and the NCR use same endian-ness addressing,
384 * no byte reordering is needed for accessing chip io
385 * registers. Functions suffixed by '_raw' are assumed
386 * to access the chip over the PCI without doing byte
387 * reordering. Functions suffixed by '_l2b' are
388 * assumed to perform little-endian to big-endian byte
389 * reordering, those suffixed by '_b2l' blah, blah,
390 * blah, ...
391 */
392
393 /*
394 * MEMORY mapped IO input / output
395 */
396
397 #define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o))
398 #define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
399
400 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
401
402 #define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o))
403 #define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o))
404
405 #define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
406 #define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o))
407
408 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
409
410 #define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o))
411 #define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o))
412
413 #define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
414 #define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o))
415
416 #else
417
418 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
419 /* Only 8 or 32 bit transfers allowed */
420 #define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
421 #else
422 #define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o))
423 #endif
424 #define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o))
425
426 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
427 /* Only 8 or 32 bit transfers allowed */
428 #define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
429 #else
430 #define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
431 #endif
432 #define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o))
433
434 #endif
435
436 #define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
437 #define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
438 #define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
439
440 #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
441 #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
442 #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
443
444 /*
445 * Set bit field ON, OFF
446 */
447
448 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
449 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
450 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
451 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
452 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
453 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
454
455 /*
456 * We normally want the chip to have a consistent view
457 * of driver internal data structures when we restart it.
458 * Thus these macros.
459 */
460 #define OUTL_DSP(v) \
461 do { \
462 MEMORY_BARRIER(); \
463 OUTL (nc_dsp, (v)); \
464 } while (0)
465
466 #define OUTONB_STD() \
467 do { \
468 MEMORY_BARRIER(); \
469 OUTONB (nc_dcntl, (STD|NOCOM)); \
470 } while (0)
471
472
473 /*
474 ** NCR53C8XX devices features table.
475 */
476 struct ncr_chip {
477 unsigned short revision_id;
478 unsigned char burst_max; /* log-base-2 of max burst */
479 unsigned char offset_max;
480 unsigned char nr_divisor;
481 unsigned int features;
482 #define FE_LED0 (1<<0)
483 #define FE_WIDE (1<<1) /* Wide data transfers */
484 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
485 #define FE_DBLR (1<<4) /* Clock doubler present */
486 #define FE_QUAD (1<<5) /* Clock quadrupler present */
487 #define FE_ERL (1<<6) /* Enable read line */
488 #define FE_CLSE (1<<7) /* Cache line size enable */
489 #define FE_WRIE (1<<8) /* Write & Invalidate enable */
490 #define FE_ERMP (1<<9) /* Enable read multiple */
491 #define FE_BOF (1<<10) /* Burst opcode fetch */
492 #define FE_DFS (1<<11) /* DMA fifo size */
493 #define FE_PFEN (1<<12) /* Prefetch enable */
494 #define FE_LDSTR (1<<13) /* Load/Store supported */
495 #define FE_RAM (1<<14) /* On chip RAM present */
496 #define FE_VARCLK (1<<15) /* SCSI clock may vary */
497 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
498 #define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
499 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
500 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
501 #define FE_LEDC (1<<20) /* Hardware control of LED */
502 #define FE_DIFF (1<<21) /* Support Differential SCSI */
503 #define FE_66MHZ (1<<23) /* 66MHz PCI Support */
504 #define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
505 #define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
506 #define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
507 #define FE_EHP (1<<27) /* 720: Even host parity */
508 #define FE_MUX (1<<28) /* 720: Multiplexed bus */
509 #define FE_EA (1<<29) /* 720: Enable Ack */
510
511 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
512 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
513 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
514 };
515
516
517 /*
518 ** Driver setup structure.
519 **
520 ** This structure is initialized from linux config options.
521 ** It can be overridden at boot-up by the boot command line.
522 */
523 #define SCSI_NCR_MAX_EXCLUDES 8
524 struct ncr_driver_setup {
525 u8 master_parity;
526 u8 scsi_parity;
527 u8 disconnection;
528 u8 special_features;
529 u8 force_sync_nego;
530 u8 reverse_probe;
531 u8 pci_fix_up;
532 u8 use_nvram;
533 u8 verbose;
534 u8 default_tags;
535 u16 default_sync;
536 u16 debug;
537 u8 burst_max;
538 u8 led_pin;
539 u8 max_wide;
540 u8 settle_delay;
541 u8 diff_support;
542 u8 irqm;
543 u8 bus_check;
544 u8 optimize;
545 u8 recovery;
546 u8 host_id;
547 u16 iarb;
548 u32 excludes[SCSI_NCR_MAX_EXCLUDES];
549 char tag_ctrl[100];
550 };
551
552 /*
553 ** Initial setup.
554 ** Can be overriden at startup by a command line.
555 */
556 #define SCSI_NCR_DRIVER_SETUP \
557 { \
558 SCSI_NCR_SETUP_MASTER_PARITY, \
559 SCSI_NCR_SETUP_SCSI_PARITY, \
560 SCSI_NCR_SETUP_DISCONNECTION, \
561 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
562 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
563 0, \
564 0, \
565 1, \
566 0, \
567 SCSI_NCR_SETUP_DEFAULT_TAGS, \
568 SCSI_NCR_SETUP_DEFAULT_SYNC, \
569 0x00, \
570 7, \
571 0, \
572 1, \
573 SCSI_NCR_SETUP_SETTLE_TIME, \
574 0, \
575 0, \
576 1, \
577 0, \
578 0, \
579 255, \
580 0x00 \
581 }
582
583 /*
584 ** Boot fail safe setup.
585 ** Override initial setup from boot command line:
586 ** ncr53c8xx=safe:y
587 */
588 #define SCSI_NCR_DRIVER_SAFE_SETUP \
589 { \
590 0, \
591 1, \
592 0, \
593 0, \
594 0, \
595 0, \
596 0, \
597 1, \
598 2, \
599 0, \
600 255, \
601 0x00, \
602 255, \
603 0, \
604 0, \
605 10, \
606 1, \
607 1, \
608 1, \
609 0, \
610 0, \
611 255 \
612 }
613
614 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
615
616 /*-----------------------------------------------------------------
617 **
618 ** The ncr 53c810 register structure.
619 **
620 **-----------------------------------------------------------------
621 */
622
623 struct ncr_reg {
624 /*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
625
626 /*01*/ u8 nc_scntl1; /* no reset */
627 #define ISCON 0x10 /* connected to scsi */
628 #define CRST 0x08 /* force reset */
629 #define IARB 0x02 /* immediate arbitration */
630
631 /*02*/ u8 nc_scntl2; /* no disconnect expected */
632 #define SDU 0x80 /* cmd: disconnect will raise error */
633 #define CHM 0x40 /* sta: chained mode */
634 #define WSS 0x08 /* sta: wide scsi send [W]*/
635 #define WSR 0x01 /* sta: wide scsi received [W]*/
636
637 /*03*/ u8 nc_scntl3; /* cnf system clock dependent */
638 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
639 #define ULTRA 0x80 /* cmd: ULTRA enable */
640 /* bits 0-2, 7 rsvd for C1010 */
641
642 /*04*/ u8 nc_scid; /* cnf host adapter scsi address */
643 #define RRE 0x40 /* r/w:e enable response to resel. */
644 #define SRE 0x20 /* r/w:e enable response to select */
645
646 /*05*/ u8 nc_sxfer; /* ### Sync speed and count */
647 /* bits 6-7 rsvd for C1010 */
648
649 /*06*/ u8 nc_sdid; /* ### Destination-ID */
650
651 /*07*/ u8 nc_gpreg; /* ??? IO-Pins */
652
653 /*08*/ u8 nc_sfbr; /* ### First byte in phase */
654
655 /*09*/ u8 nc_socl;
656 #define CREQ 0x80 /* r/w: SCSI-REQ */
657 #define CACK 0x40 /* r/w: SCSI-ACK */
658 #define CBSY 0x20 /* r/w: SCSI-BSY */
659 #define CSEL 0x10 /* r/w: SCSI-SEL */
660 #define CATN 0x08 /* r/w: SCSI-ATN */
661 #define CMSG 0x04 /* r/w: SCSI-MSG */
662 #define CC_D 0x02 /* r/w: SCSI-C_D */
663 #define CI_O 0x01 /* r/w: SCSI-I_O */
664
665 /*0a*/ u8 nc_ssid;
666
667 /*0b*/ u8 nc_sbcl;
668
669 /*0c*/ u8 nc_dstat;
670 #define DFE 0x80 /* sta: dma fifo empty */
671 #define MDPE 0x40 /* int: master data parity error */
672 #define BF 0x20 /* int: script: bus fault */
673 #define ABRT 0x10 /* int: script: command aborted */
674 #define SSI 0x08 /* int: script: single step */
675 #define SIR 0x04 /* int: script: interrupt instruct. */
676 #define IID 0x01 /* int: script: illegal instruct. */
677
678 /*0d*/ u8 nc_sstat0;
679 #define ILF 0x80 /* sta: data in SIDL register lsb */
680 #define ORF 0x40 /* sta: data in SODR register lsb */
681 #define OLF 0x20 /* sta: data in SODL register lsb */
682 #define AIP 0x10 /* sta: arbitration in progress */
683 #define LOA 0x08 /* sta: arbitration lost */
684 #define WOA 0x04 /* sta: arbitration won */
685 #define IRST 0x02 /* sta: scsi reset signal */
686 #define SDP 0x01 /* sta: scsi parity signal */
687
688 /*0e*/ u8 nc_sstat1;
689 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
690
691 /*0f*/ u8 nc_sstat2;
692 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
693 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
694 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
695 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
696 #define LDSC 0x02 /* sta: disconnect & reconnect */
697
698 /*10*/ u8 nc_dsa; /* --> Base page */
699 /*11*/ u8 nc_dsa1;
700 /*12*/ u8 nc_dsa2;
701 /*13*/ u8 nc_dsa3;
702
703 /*14*/ u8 nc_istat; /* --> Main Command and status */
704 #define CABRT 0x80 /* cmd: abort current operation */
705 #define SRST 0x40 /* mod: reset chip */
706 #define SIGP 0x20 /* r/w: message from host to ncr */
707 #define SEM 0x10 /* r/w: message between host + ncr */
708 #define CON 0x08 /* sta: connected to scsi */
709 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
710 #define SIP 0x02 /* sta: scsi-interrupt */
711 #define DIP 0x01 /* sta: host/script interrupt */
712
713 /*15*/ u8 nc_istat1; /* 896 and later cores only */
714 #define FLSH 0x04 /* sta: chip is flushing */
715 #define SRUN 0x02 /* sta: scripts are running */
716 #define SIRQD 0x01 /* r/w: disable INT pin */
717
718 /*16*/ u8 nc_mbox0; /* 896 and later cores only */
719 /*17*/ u8 nc_mbox1; /* 896 and later cores only */
720
721 /*18*/ u8 nc_ctest0;
722 #define EHP 0x04 /* 720 even host parity */
723 /*19*/ u8 nc_ctest1;
724
725 /*1a*/ u8 nc_ctest2;
726 #define CSIGP 0x40
727 /* bits 0-2,7 rsvd for C1010 */
728
729 /*1b*/ u8 nc_ctest3;
730 #define FLF 0x08 /* cmd: flush dma fifo */
731 #define CLF 0x04 /* cmd: clear dma fifo */
732 #define FM 0x02 /* mod: fetch pin mode */
733 #define WRIE 0x01 /* mod: write and invalidate enable */
734 /* bits 4-7 rsvd for C1010 */
735
736 /*1c*/ u32 nc_temp; /* ### Temporary stack */
737
738 /*20*/ u8 nc_dfifo;
739 /*21*/ u8 nc_ctest4;
740 #define MUX 0x80 /* 720 host bus multiplex mode */
741 #define BDIS 0x80 /* mod: burst disable */
742 #define MPEE 0x08 /* mod: master parity error enable */
743
744 /*22*/ u8 nc_ctest5;
745 #define DFS 0x20 /* mod: dma fifo size */
746 /* bits 0-1, 3-7 rsvd for C1010 */
747 /*23*/ u8 nc_ctest6;
748
749 /*24*/ u32 nc_dbc; /* ### Byte count and command */
750 /*28*/ u32 nc_dnad; /* ### Next command register */
751 /*2c*/ u32 nc_dsp; /* --> Script Pointer */
752 /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
753
754 /*34*/ u8 nc_scratcha; /* Temporary register a */
755 /*35*/ u8 nc_scratcha1;
756 /*36*/ u8 nc_scratcha2;
757 /*37*/ u8 nc_scratcha3;
758
759 /*38*/ u8 nc_dmode;
760 #define BL_2 0x80 /* mod: burst length shift value +2 */
761 #define BL_1 0x40 /* mod: burst length shift value +1 */
762 #define ERL 0x08 /* mod: enable read line */
763 #define ERMP 0x04 /* mod: enable read multiple */
764 #define BOF 0x02 /* mod: burst op code fetch */
765
766 /*39*/ u8 nc_dien;
767 /*3a*/ u8 nc_sbr;
768
769 /*3b*/ u8 nc_dcntl; /* --> Script execution control */
770 #define CLSE 0x80 /* mod: cache line size enable */
771 #define PFF 0x40 /* cmd: pre-fetch flush */
772 #define PFEN 0x20 /* mod: pre-fetch enable */
773 #define EA 0x20 /* mod: 720 enable-ack */
774 #define SSM 0x10 /* mod: single step mode */
775 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
776 #define STD 0x04 /* cmd: start dma mode */
777 #define IRQD 0x02 /* mod: irq disable */
778 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
779 /* bits 0-1 rsvd for C1010 */
780
781 /*3c*/ u32 nc_adder;
782
783 /*40*/ u16 nc_sien; /* -->: interrupt enable */
784 /*42*/ u16 nc_sist; /* <--: interrupt status */
785 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
786 #define STO 0x0400/* sta: timeout (select) */
787 #define GEN 0x0200/* sta: timeout (general) */
788 #define HTH 0x0100/* sta: timeout (handshake) */
789 #define MA 0x80 /* sta: phase mismatch */
790 #define CMP 0x40 /* sta: arbitration complete */
791 #define SEL 0x20 /* sta: selected by another device */
792 #define RSL 0x10 /* sta: reselected by another device*/
793 #define SGE 0x08 /* sta: gross error (over/underflow)*/
794 #define UDC 0x04 /* sta: unexpected disconnect */
795 #define RST 0x02 /* sta: scsi bus reset detected */
796 #define PAR 0x01 /* sta: scsi parity error */
797
798 /*44*/ u8 nc_slpar;
799 /*45*/ u8 nc_swide;
800 /*46*/ u8 nc_macntl;
801 /*47*/ u8 nc_gpcntl;
802 /*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
803 /*49*/ u8 nc_stime1; /* cmd: timeout user defined */
804 /*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
805
806 /*4c*/ u8 nc_stest0;
807
808 /*4d*/ u8 nc_stest1;
809 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
810 #define DBLEN 0x08 /* clock doubler running */
811 #define DBLSEL 0x04 /* clock doubler selected */
812
813
814 /*4e*/ u8 nc_stest2;
815 #define ROF 0x40 /* reset scsi offset (after gross error!) */
816 #define DIF 0x20 /* 720 SCSI differential mode */
817 #define EXT 0x02 /* extended filtering */
818
819 /*4f*/ u8 nc_stest3;
820 #define TE 0x80 /* c: tolerAnt enable */
821 #define HSC 0x20 /* c: Halt SCSI Clock */
822 #define CSF 0x02 /* c: clear scsi fifo */
823
824 /*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
825 /*52*/ u8 nc_stest4;
826 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
827 #define SMODE_HVD 0x40 /* High Voltage Differential */
828 #define SMODE_SE 0x80 /* Single Ended */
829 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
830 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
831 /* bits 0-5 rsvd for C1010 */
832
833 /*53*/ u8 nc_53_;
834 /*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
835 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
836 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
837 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
838 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
839 #define DISFC 0x10 /* Disable Auto FIFO Clear */
840 #define DILS 0x02 /* Disable Internal Load/Store */
841 #define DPR 0x01 /* Disable Pipe Req */
842
843 /*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
844 #define ZMOD 0x80 /* High Impedance Mode */
845 #define DIC 0x10 /* Disable Internal Cycles */
846 #define DDAC 0x08 /* Disable Dual Address Cycle */
847 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
848 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
849 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
850
851 /*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
852 /*5a*/ u16 nc_5a_;
853
854 /*5c*/ u8 nc_scr0; /* Working register B */
855 /*5d*/ u8 nc_scr1; /* */
856 /*5e*/ u8 nc_scr2; /* */
857 /*5f*/ u8 nc_scr3; /* */
858
859 /*60*/ u8 nc_scrx[64]; /* Working register C-R */
860 /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
861 /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
862 /*a8*/ u32 nc_sfs; /* Script Fetch Selector */
863 /*ac*/ u32 nc_drs; /* DSA Relative Selector */
864 /*b0*/ u32 nc_sbms; /* Static Block Move Selector */
865 /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
866 /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
867 /*bc*/ u16 nc_scntl4; /* C1010 only */
868 #define U3EN 0x80 /* Enable Ultra 3 */
869 #define AIPEN 0x40 /* Allow check upper byte lanes */
870 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
871 transfer edge */
872 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
873 transfer edge */
874
875 /*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
876 /*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
877
878 /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
879 /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
880 /*c8*/ u8 nc_rbc; /* Remaining Byte Count */
881 /*c9*/ u8 nc_rbc1; /* */
882 /*ca*/ u8 nc_rbc2; /* */
883 /*cb*/ u8 nc_rbc3; /* */
884
885 /*cc*/ u8 nc_ua; /* Updated Address */
886 /*cd*/ u8 nc_ua1; /* */
887 /*ce*/ u8 nc_ua2; /* */
888 /*cf*/ u8 nc_ua3; /* */
889 /*d0*/ u32 nc_esa; /* Entry Storage Address */
890 /*d4*/ u8 nc_ia; /* Instruction Address */
891 /*d5*/ u8 nc_ia1;
892 /*d6*/ u8 nc_ia2;
893 /*d7*/ u8 nc_ia3;
894 /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
895 /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
896
897 /* Following for C1010 only */
898 /*e0*/ u16 nc_crcpad; /* CRC Value */
899 /*e2*/ u8 nc_crccntl0; /* CRC control register */
900 #define SNDCRC 0x10 /* Send CRC Request */
901 /*e3*/ u8 nc_crccntl1; /* CRC control register */
902 /*e4*/ u32 nc_crcdata; /* CRC data register */
903 /*e8*/ u32 nc_e8_; /* rsvd */
904 /*ec*/ u32 nc_ec_; /* rsvd */
905 /*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
906
907 };
908
909 /*-----------------------------------------------------------
910 **
911 ** Utility macros for the script.
912 **
913 **-----------------------------------------------------------
914 */
915
916 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
917 #define REG(r) REGJ (nc_, r)
918
919 typedef u32 ncrcmd;
920
921 /*-----------------------------------------------------------
922 **
923 ** SCSI phases
924 **
925 ** DT phases illegal for ncr driver.
926 **
927 **-----------------------------------------------------------
928 */
929
930 #define SCR_DATA_OUT 0x00000000
931 #define SCR_DATA_IN 0x01000000
932 #define SCR_COMMAND 0x02000000
933 #define SCR_STATUS 0x03000000
934 #define SCR_DT_DATA_OUT 0x04000000
935 #define SCR_DT_DATA_IN 0x05000000
936 #define SCR_MSG_OUT 0x06000000
937 #define SCR_MSG_IN 0x07000000
938
939 #define SCR_ILG_OUT 0x04000000
940 #define SCR_ILG_IN 0x05000000
941
942 /*-----------------------------------------------------------
943 **
944 ** Data transfer via SCSI.
945 **
946 **-----------------------------------------------------------
947 **
948 ** MOVE_ABS (LEN)
949 ** <<start address>>
950 **
951 ** MOVE_IND (LEN)
952 ** <<dnad_offset>>
953 **
954 ** MOVE_TBL
955 ** <<dnad_offset>>
956 **
957 **-----------------------------------------------------------
958 */
959
960 #define OPC_MOVE 0x08000000
961
962 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
963 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
964 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
965
966 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
967 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
968 #define SCR_CHMOV_TBL (0x10000000)
969
970 struct scr_tblmove {
971 u32 size;
972 u32 addr;
973 };
974
975 /*-----------------------------------------------------------
976 **
977 ** Selection
978 **
979 **-----------------------------------------------------------
980 **
981 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
982 ** <<alternate_address>>
983 **
984 ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
985 ** <<alternate_address>>
986 **
987 **-----------------------------------------------------------
988 */
989
990 #define SCR_SEL_ABS 0x40000000
991 #define SCR_SEL_ABS_ATN 0x41000000
992 #define SCR_SEL_TBL 0x42000000
993 #define SCR_SEL_TBL_ATN 0x43000000
994
995
996 #ifdef SCSI_NCR_BIG_ENDIAN
997 struct scr_tblsel {
998 u8 sel_scntl3;
999 u8 sel_id;
1000 u8 sel_sxfer;
1001 u8 sel_scntl4;
1002 };
1003 #else
1004 struct scr_tblsel {
1005 u8 sel_scntl4;
1006 u8 sel_sxfer;
1007 u8 sel_id;
1008 u8 sel_scntl3;
1009 };
1010 #endif
1011
1012 #define SCR_JMP_REL 0x04000000
1013 #define SCR_ID(id) (((u32)(id)) << 16)
1014
1015 /*-----------------------------------------------------------
1016 **
1017 ** Waiting for Disconnect or Reselect
1018 **
1019 **-----------------------------------------------------------
1020 **
1021 ** WAIT_DISC
1022 ** dummy: <<alternate_address>>
1023 **
1024 ** WAIT_RESEL
1025 ** <<alternate_address>>
1026 **
1027 **-----------------------------------------------------------
1028 */
1029
1030 #define SCR_WAIT_DISC 0x48000000
1031 #define SCR_WAIT_RESEL 0x50000000
1032
1033 /*-----------------------------------------------------------
1034 **
1035 ** Bit Set / Reset
1036 **
1037 **-----------------------------------------------------------
1038 **
1039 ** SET (flags {|.. })
1040 **
1041 ** CLR (flags {|.. })
1042 **
1043 **-----------------------------------------------------------
1044 */
1045
1046 #define SCR_SET(f) (0x58000000 | (f))
1047 #define SCR_CLR(f) (0x60000000 | (f))
1048
1049 #define SCR_CARRY 0x00000400
1050 #define SCR_TRG 0x00000200
1051 #define SCR_ACK 0x00000040
1052 #define SCR_ATN 0x00000008
1053
1054
1055
1056
1057 /*-----------------------------------------------------------
1058 **
1059 ** Memory to memory move
1060 **
1061 **-----------------------------------------------------------
1062 **
1063 ** COPY (bytecount)
1064 ** << source_address >>
1065 ** << destination_address >>
1066 **
1067 ** SCR_COPY sets the NO FLUSH option by default.
1068 ** SCR_COPY_F does not set this option.
1069 **
1070 ** For chips which do not support this option,
1071 ** ncr_copy_and_bind() will remove this bit.
1072 **-----------------------------------------------------------
1073 */
1074
1075 #define SCR_NO_FLUSH 0x01000000
1076
1077 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1078 #define SCR_COPY_F(n) (0xc0000000 | (n))
1079
1080 /*-----------------------------------------------------------
1081 **
1082 ** Register move and binary operations
1083 **
1084 **-----------------------------------------------------------
1085 **
1086 ** SFBR_REG (reg, op, data) reg = SFBR op data
1087 ** << 0 >>
1088 **
1089 ** REG_SFBR (reg, op, data) SFBR = reg op data
1090 ** << 0 >>
1091 **
1092 ** REG_REG (reg, op, data) reg = reg op data
1093 ** << 0 >>
1094 **
1095 **-----------------------------------------------------------
1096 ** On 810A, 860, 825A, 875, 895 and 896 chips the content
1097 ** of SFBR register can be used as data (SCR_SFBR_DATA).
1098 ** The 896 has additionnal IO registers starting at
1099 ** offset 0x80. Bit 7 of register offset is stored in
1100 ** bit 7 of the SCRIPTS instruction first DWORD.
1101 **-----------------------------------------------------------
1102 */
1103
1104 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1105
1106 #define SCR_SFBR_REG(reg,op,data) \
1107 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1108
1109 #define SCR_REG_SFBR(reg,op,data) \
1110 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1111
1112 #define SCR_REG_REG(reg,op,data) \
1113 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1114
1115
1116 #define SCR_LOAD 0x00000000
1117 #define SCR_SHL 0x01000000
1118 #define SCR_OR 0x02000000
1119 #define SCR_XOR 0x03000000
1120 #define SCR_AND 0x04000000
1121 #define SCR_SHR 0x05000000
1122 #define SCR_ADD 0x06000000
1123 #define SCR_ADDC 0x07000000
1124
1125 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1126
1127 /*-----------------------------------------------------------
1128 **
1129 ** FROM_REG (reg) SFBR = reg
1130 ** << 0 >>
1131 **
1132 ** TO_REG (reg) reg = SFBR
1133 ** << 0 >>
1134 **
1135 ** LOAD_REG (reg, data) reg = <data>
1136 ** << 0 >>
1137 **
1138 ** LOAD_SFBR(data) SFBR = <data>
1139 ** << 0 >>
1140 **
1141 **-----------------------------------------------------------
1142 */
1143
1144 #define SCR_FROM_REG(reg) \
1145 SCR_REG_SFBR(reg,SCR_OR,0)
1146
1147 #define SCR_TO_REG(reg) \
1148 SCR_SFBR_REG(reg,SCR_OR,0)
1149
1150 #define SCR_LOAD_REG(reg,data) \
1151 SCR_REG_REG(reg,SCR_LOAD,data)
1152
1153 #define SCR_LOAD_SFBR(data) \
1154 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1155
1156 /*-----------------------------------------------------------
1157 **
1158 ** LOAD from memory to register.
1159 ** STORE from register to memory.
1160 **
1161 ** Only supported by 810A, 860, 825A, 875, 895 and 896.
1162 **
1163 **-----------------------------------------------------------
1164 **
1165 ** LOAD_ABS (LEN)
1166 ** <<start address>>
1167 **
1168 ** LOAD_REL (LEN) (DSA relative)
1169 ** <<dsa_offset>>
1170 **
1171 **-----------------------------------------------------------
1172 */
1173
1174 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1175 #define SCR_NO_FLUSH2 0x02000000
1176 #define SCR_DSA_REL2 0x10000000
1177
1178 #define SCR_LOAD_R(reg, how, n) \
1179 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1180
1181 #define SCR_STORE_R(reg, how, n) \
1182 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1183
1184 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1185 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1186 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1187 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1188
1189 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1190 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1191 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1192 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1193
1194
1195 /*-----------------------------------------------------------
1196 **
1197 ** Waiting for Disconnect or Reselect
1198 **
1199 **-----------------------------------------------------------
1200 **
1201 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1202 ** <<address>>
1203 **
1204 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1205 ** <<distance>>
1206 **
1207 ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1208 ** <<address>>
1209 **
1210 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1211 ** <<distance>>
1212 **
1213 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1214 ** <<dummy>>
1215 **
1216 ** INT [ | IFTRUE/IFFALSE ( ... ) ]
1217 ** <<ident>>
1218 **
1219 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1220 ** <<ident>>
1221 **
1222 ** Conditions:
1223 ** WHEN (phase)
1224 ** IF (phase)
1225 ** CARRYSET
1226 ** DATA (data, mask)
1227 **
1228 **-----------------------------------------------------------
1229 */
1230
1231 #define SCR_NO_OP 0x80000000
1232 #define SCR_JUMP 0x80080000
1233 #define SCR_JUMP64 0x80480000
1234 #define SCR_JUMPR 0x80880000
1235 #define SCR_CALL 0x88080000
1236 #define SCR_CALLR 0x88880000
1237 #define SCR_RETURN 0x90080000
1238 #define SCR_INT 0x98080000
1239 #define SCR_INT_FLY 0x98180000
1240
1241 #define IFFALSE(arg) (0x00080000 | (arg))
1242 #define IFTRUE(arg) (0x00000000 | (arg))
1243
1244 #define WHEN(phase) (0x00030000 | (phase))
1245 #define IF(phase) (0x00020000 | (phase))
1246
1247 #define DATA(D) (0x00040000 | ((D) & 0xff))
1248 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1249
1250 #define CARRYSET (0x00200000)
1251
1252 /*-----------------------------------------------------------
1253 **
1254 ** SCSI constants.
1255 **
1256 **-----------------------------------------------------------
1257 */
1258
1259 /*
1260 ** Status
1261 */
1262
1263 #define S_GOOD (0x00)
1264 #define S_CHECK_COND (0x02)
1265 #define S_COND_MET (0x04)
1266 #define S_BUSY (0x08)
1267 #define S_INT (0x10)
1268 #define S_INT_COND_MET (0x14)
1269 #define S_CONFLICT (0x18)
1270 #define S_TERMINATED (0x20)
1271 #define S_QUEUE_FULL (0x28)
1272 #define S_ILLEGAL (0xff)
1273 #define S_SENSE (0x80)
1274
1275 /*
1276 * End of ncrreg from FreeBSD
1277 */
1278
1279 /*
1280 Build a scatter/gather entry.
1281 see sym53c8xx_2/sym_hipd.h for more detailed sym_build_sge()
1282 implementation ;)
1283 */
1284
1285 #define ncr_build_sge(np, data, badd, len) \
1286 do { \
1287 (data)->addr = cpu_to_scr(badd); \
1288 (data)->size = cpu_to_scr(len); \
1289 } while (0)
1290
1291 /*==========================================================
1292 **
1293 ** Structures used by the detection routine to transmit
1294 ** device configuration to the attach function.
1295 **
1296 **==========================================================
1297 */
1298 struct ncr_slot {
1299 u_long base;
1300 u_long base_2;
1301 u_long base_c;
1302 u_long base_2_c;
1303 void __iomem *base_v;
1304 void __iomem *base_2_v;
1305 int irq;
1306 /* port and reg fields to use INB, OUTB macros */
1307 volatile struct ncr_reg __iomem *reg;
1308 };
1309
1310 /*==========================================================
1311 **
1312 ** Structure used by detection routine to save data on
1313 ** each detected board for attach.
1314 **
1315 **==========================================================
1316 */
1317 struct ncr_device {
1318 struct device *dev;
1319 struct ncr_slot slot;
1320 struct ncr_chip chip;
1321 u_char host_id;
1322 u8 differential;
1323 };
1324
1325 extern struct Scsi_Host *ncr_attach(struct scsi_host_template *tpnt, int unit, struct ncr_device *device);
1326 extern int ncr53c8xx_release(struct Scsi_Host *host);
1327 irqreturn_t ncr53c8xx_intr(int irq, void *dev_id, struct pt_regs * regs);
1328 extern int ncr53c8xx_init(void);
1329 extern void ncr53c8xx_exit(void);
1330
1331 #endif /* NCR53C8XX_H */
SocketAccessConTroL development