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[PATCH] orinoco: bump version to 0.15
[linux-2.6/sactl.git] / drivers / scsi / ahci.c
blobb4f8fb1d628b9d95ec70a28ffb81008eefb8f4d0
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.2"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69 AHCI_CMD_PREFETCH = (1 << 7),
70 AHCI_CMD_RESET = (1 << 8),
71 AHCI_CMD_CLR_BUSY = (1 << 10),
72
73 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
74
75 board_ahci = 0,
76
77 /* global controller registers */
78 HOST_CAP = 0x00, /* host capabilities */
79 HOST_CTL = 0x04, /* global host control */
80 HOST_IRQ_STAT = 0x08, /* interrupt status */
81 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
82 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
83
84 /* HOST_CTL bits */
85 HOST_RESET = (1 << 0), /* reset controller; self-clear */
86 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
87 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
88
89 /* HOST_CAP bits */
90 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
91 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
92
93 /* registers for each SATA port */
94 PORT_LST_ADDR = 0x00, /* command list DMA addr */
95 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
96 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
97 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
98 PORT_IRQ_STAT = 0x10, /* interrupt status */
99 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
100 PORT_CMD = 0x18, /* port command */
101 PORT_TFDATA = 0x20, /* taskfile data */
102 PORT_SIG = 0x24, /* device TF signature */
103 PORT_CMD_ISSUE = 0x38, /* command issue */
104 PORT_SCR = 0x28, /* SATA phy register block */
105 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
106 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
107 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
108 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
109
110 /* PORT_IRQ_{STAT,MASK} bits */
111 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
112 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
113 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
114 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
115 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
116 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
117 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
118 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
119
120 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
121 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
122 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
123 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
124 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
125 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
126 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
127 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
128 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
129
130 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
131 PORT_IRQ_HBUS_ERR |
132 PORT_IRQ_HBUS_DATA_ERR |
133 PORT_IRQ_IF_ERR,
134 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
135 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
136 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
137 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
138 PORT_IRQ_D2H_REG_FIS,
139
140 /* PORT_CMD bits */
141 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
142 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
143 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
144 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
145 PORT_CMD_CLO = (1 << 3), /* Command list override */
146 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
147 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
148 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
149
150 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
151 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
152 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
153
154 /* hpriv->flags bits */
155 AHCI_FLAG_MSI = (1 << 0),
156 };
157
158 struct ahci_cmd_hdr {
159 u32 opts;
160 u32 status;
161 u32 tbl_addr;
162 u32 tbl_addr_hi;
163 u32 reserved[4];
164 };
165
166 struct ahci_sg {
167 u32 addr;
168 u32 addr_hi;
169 u32 reserved;
170 u32 flags_size;
171 };
172
173 struct ahci_host_priv {
174 unsigned long flags;
175 u32 cap; /* cache of HOST_CAP register */
176 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
177 };
178
179 struct ahci_port_priv {
180 struct ahci_cmd_hdr *cmd_slot;
181 dma_addr_t cmd_slot_dma;
182 void *cmd_tbl;
183 dma_addr_t cmd_tbl_dma;
184 struct ahci_sg *cmd_tbl_sg;
185 void *rx_fis;
186 dma_addr_t rx_fis_dma;
187 };
188
189 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
190 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
191 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
192 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
193 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
194 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
195 static void ahci_irq_clear(struct ata_port *ap);
196 static void ahci_eng_timeout(struct ata_port *ap);
197 static int ahci_port_start(struct ata_port *ap);
198 static void ahci_port_stop(struct ata_port *ap);
199 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
200 static void ahci_qc_prep(struct ata_queued_cmd *qc);
201 static u8 ahci_check_status(struct ata_port *ap);
202 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
203 static void ahci_remove_one (struct pci_dev *pdev);
204
205 static struct scsi_host_template ahci_sht = {
206 .module = THIS_MODULE,
207 .name = DRV_NAME,
208 .ioctl = ata_scsi_ioctl,
209 .queuecommand = ata_scsi_queuecmd,
210 .can_queue = ATA_DEF_QUEUE,
211 .this_id = ATA_SHT_THIS_ID,
212 .sg_tablesize = AHCI_MAX_SG,
213 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
214 .emulated = ATA_SHT_EMULATED,
215 .use_clustering = AHCI_USE_CLUSTERING,
216 .proc_name = DRV_NAME,
217 .dma_boundary = AHCI_DMA_BOUNDARY,
218 .slave_configure = ata_scsi_slave_config,
219 .bios_param = ata_std_bios_param,
220 };
221
222 static const struct ata_port_operations ahci_ops = {
223 .port_disable = ata_port_disable,
224
225 .check_status = ahci_check_status,
226 .check_altstatus = ahci_check_status,
227 .dev_select = ata_noop_dev_select,
228
229 .tf_read = ahci_tf_read,
230
231 .probe_reset = ahci_probe_reset,
232
233 .qc_prep = ahci_qc_prep,
234 .qc_issue = ahci_qc_issue,
235
236 .eng_timeout = ahci_eng_timeout,
237
238 .irq_handler = ahci_interrupt,
239 .irq_clear = ahci_irq_clear,
240
241 .scr_read = ahci_scr_read,
242 .scr_write = ahci_scr_write,
243
244 .port_start = ahci_port_start,
245 .port_stop = ahci_port_stop,
246 };
247
248 static const struct ata_port_info ahci_port_info[] = {
249 /* board_ahci */
250 {
251 .sht = &ahci_sht,
252 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
253 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
254 .pio_mask = 0x1f, /* pio0-4 */
255 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
256 .port_ops = &ahci_ops,
257 },
258 };
259
260 static const struct pci_device_id ahci_pci_tbl[] = {
261 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH6 */
263 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ICH6M */
265 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ICH7 */
267 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ICH7M */
269 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ICH7R */
271 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
272 board_ahci }, /* ULi M5288 */
273 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 board_ahci }, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ESB2 */
277 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ESB2 */
279 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
280 board_ahci }, /* ICH7-M DH */
281 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 board_ahci }, /* ICH8 */
283 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 board_ahci }, /* ICH8 */
285 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 board_ahci }, /* ICH8 */
287 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH8M */
289 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 board_ahci }, /* ICH8M */
291 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292 board_ahci }, /* JMicron JMB360 */
293 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
294 board_ahci }, /* JMicron JMB363 */
295 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
296 board_ahci }, /* ATI SB600 non-raid */
297 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
298 board_ahci }, /* ATI SB600 raid */
299 { } /* terminate list */
300 };
301
302
303 static struct pci_driver ahci_pci_driver = {
304 .name = DRV_NAME,
305 .id_table = ahci_pci_tbl,
306 .probe = ahci_init_one,
307 .remove = ahci_remove_one,
308 };
309
310
311 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
312 {
313 return base + 0x100 + (port * 0x80);
314 }
315
316 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
317 {
318 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
319 }
320
321 static int ahci_port_start(struct ata_port *ap)
322 {
323 struct device *dev = ap->host_set->dev;
324 struct ahci_host_priv *hpriv = ap->host_set->private_data;
325 struct ahci_port_priv *pp;
326 void __iomem *mmio = ap->host_set->mmio_base;
327 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
328 void *mem;
329 dma_addr_t mem_dma;
330 int rc;
331
332 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
333 if (!pp)
334 return -ENOMEM;
335 memset(pp, 0, sizeof(*pp));
336
337 rc = ata_pad_alloc(ap, dev);
338 if (rc) {
339 kfree(pp);
340 return rc;
341 }
342
343 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
344 if (!mem) {
345 ata_pad_free(ap, dev);
346 kfree(pp);
347 return -ENOMEM;
348 }
349 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
350
351 /*
352 * First item in chunk of DMA memory: 32-slot command table,
353 * 32 bytes each in size
354 */
355 pp->cmd_slot = mem;
356 pp->cmd_slot_dma = mem_dma;
357
358 mem += AHCI_CMD_SLOT_SZ;
359 mem_dma += AHCI_CMD_SLOT_SZ;
360
361 /*
362 * Second item: Received-FIS area
363 */
364 pp->rx_fis = mem;
365 pp->rx_fis_dma = mem_dma;
366
367 mem += AHCI_RX_FIS_SZ;
368 mem_dma += AHCI_RX_FIS_SZ;
369
370 /*
371 * Third item: data area for storing a single command
372 * and its scatter-gather table
373 */
374 pp->cmd_tbl = mem;
375 pp->cmd_tbl_dma = mem_dma;
376
377 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
378
379 ap->private_data = pp;
380
381 if (hpriv->cap & HOST_CAP_64)
382 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
383 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
384 readl(port_mmio + PORT_LST_ADDR); /* flush */
385
386 if (hpriv->cap & HOST_CAP_64)
387 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
388 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
389 readl(port_mmio + PORT_FIS_ADDR); /* flush */
390
391 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
392 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
393 PORT_CMD_START, port_mmio + PORT_CMD);
394 readl(port_mmio + PORT_CMD); /* flush */
395
396 return 0;
397 }
398
399
400 static void ahci_port_stop(struct ata_port *ap)
401 {
402 struct device *dev = ap->host_set->dev;
403 struct ahci_port_priv *pp = ap->private_data;
404 void __iomem *mmio = ap->host_set->mmio_base;
405 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
406 u32 tmp;
407
408 tmp = readl(port_mmio + PORT_CMD);
409 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
410 writel(tmp, port_mmio + PORT_CMD);
411 readl(port_mmio + PORT_CMD); /* flush */
412
413 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
414 * this is slightly incorrect.
415 */
416 msleep(500);
417
418 ap->private_data = NULL;
419 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
420 pp->cmd_slot, pp->cmd_slot_dma);
421 ata_pad_free(ap, dev);
422 kfree(pp);
423 }
424
425 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
426 {
427 unsigned int sc_reg;
428
429 switch (sc_reg_in) {
430 case SCR_STATUS: sc_reg = 0; break;
431 case SCR_CONTROL: sc_reg = 1; break;
432 case SCR_ERROR: sc_reg = 2; break;
433 case SCR_ACTIVE: sc_reg = 3; break;
434 default:
435 return 0xffffffffU;
436 }
437
438 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
439 }
440
441
442 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
443 u32 val)
444 {
445 unsigned int sc_reg;
446
447 switch (sc_reg_in) {
448 case SCR_STATUS: sc_reg = 0; break;
449 case SCR_CONTROL: sc_reg = 1; break;
450 case SCR_ERROR: sc_reg = 2; break;
451 case SCR_ACTIVE: sc_reg = 3; break;
452 default:
453 return;
454 }
455
456 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
457 }
458
459 static int ahci_stop_engine(struct ata_port *ap)
460 {
461 void __iomem *mmio = ap->host_set->mmio_base;
462 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
463 int work;
464 u32 tmp;
465
466 tmp = readl(port_mmio + PORT_CMD);
467 tmp &= ~PORT_CMD_START;
468 writel(tmp, port_mmio + PORT_CMD);
469
470 /* wait for engine to stop. TODO: this could be
471 * as long as 500 msec
472 */
473 work = 1000;
474 while (work-- > 0) {
475 tmp = readl(port_mmio + PORT_CMD);
476 if ((tmp & PORT_CMD_LIST_ON) == 0)
477 return 0;
478 udelay(10);
479 }
480
481 return -EIO;
482 }
483
484 static void ahci_start_engine(struct ata_port *ap)
485 {
486 void __iomem *mmio = ap->host_set->mmio_base;
487 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
488 u32 tmp;
489
490 tmp = readl(port_mmio + PORT_CMD);
491 tmp |= PORT_CMD_START;
492 writel(tmp, port_mmio + PORT_CMD);
493 readl(port_mmio + PORT_CMD); /* flush */
494 }
495
496 static unsigned int ahci_dev_classify(struct ata_port *ap)
497 {
498 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
499 struct ata_taskfile tf;
500 u32 tmp;
501
502 tmp = readl(port_mmio + PORT_SIG);
503 tf.lbah = (tmp >> 24) & 0xff;
504 tf.lbam = (tmp >> 16) & 0xff;
505 tf.lbal = (tmp >> 8) & 0xff;
506 tf.nsect = (tmp) & 0xff;
507
508 return ata_dev_classify(&tf);
509 }
510
511 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
512 {
513 pp->cmd_slot[0].opts = cpu_to_le32(opts);
514 pp->cmd_slot[0].status = 0;
515 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
516 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
517 }
518
519 static int ahci_poll_register(void __iomem *reg, u32 mask, u32 val,
520 unsigned long interval_msec,
521 unsigned long timeout_msec)
522 {
523 unsigned long timeout;
524 u32 tmp;
525
526 timeout = jiffies + (timeout_msec * HZ) / 1000;
527 do {
528 tmp = readl(reg);
529 if ((tmp & mask) == val)
530 return 0;
531 msleep(interval_msec);
532 } while (time_before(jiffies, timeout));
533
534 return -1;
535 }
536
537 static int ahci_softreset(struct ata_port *ap, int verbose, unsigned int *class)
538 {
539 struct ahci_host_priv *hpriv = ap->host_set->private_data;
540 struct ahci_port_priv *pp = ap->private_data;
541 void __iomem *mmio = ap->host_set->mmio_base;
542 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
543 const u32 cmd_fis_len = 5; /* five dwords */
544 const char *reason = NULL;
545 struct ata_taskfile tf;
546 u8 *fis;
547 int rc;
548
549 DPRINTK("ENTER\n");
550
551 /* prepare for SRST (AHCI-1.1 10.4.1) */
552 rc = ahci_stop_engine(ap);
553 if (rc) {
554 reason = "failed to stop engine";
555 goto fail_restart;
556 }
557
558 /* check BUSY/DRQ, perform Command List Override if necessary */
559 ahci_tf_read(ap, &tf);
560 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
561 u32 tmp;
562
563 if (!(hpriv->cap & HOST_CAP_CLO)) {
564 rc = -EIO;
565 reason = "port busy but no CLO";
566 goto fail_restart;
567 }
568
569 tmp = readl(port_mmio + PORT_CMD);
570 tmp |= PORT_CMD_CLO;
571 writel(tmp, port_mmio + PORT_CMD);
572 readl(port_mmio + PORT_CMD); /* flush */
573
574 if (ahci_poll_register(port_mmio + PORT_CMD, PORT_CMD_CLO, 0x0,
575 1, 500)) {
576 rc = -EIO;
577 reason = "CLO failed";
578 goto fail_restart;
579 }
580 }
581
582 /* restart engine */
583 ahci_start_engine(ap);
584
585 ata_tf_init(ap, &tf, 0);
586 fis = pp->cmd_tbl;
587
588 /* issue the first D2H Register FIS */
589 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
590
591 tf.ctl |= ATA_SRST;
592 ata_tf_to_fis(&tf, fis, 0);
593 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
594
595 writel(1, port_mmio + PORT_CMD_ISSUE);
596 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
597
598 if (ahci_poll_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x0, 1, 500)) {
599 rc = -EIO;
600 reason = "1st FIS failed";
601 goto fail;
602 }
603
604 /* spec says at least 5us, but be generous and sleep for 1ms */
605 msleep(1);
606
607 /* issue the second D2H Register FIS */
608 ahci_fill_cmd_slot(pp, cmd_fis_len);
609
610 tf.ctl &= ~ATA_SRST;
611 ata_tf_to_fis(&tf, fis, 0);
612 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
613
614 writel(1, port_mmio + PORT_CMD_ISSUE);
615 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
616
617 /* spec mandates ">= 2ms" before checking status.
618 * We wait 150ms, because that was the magic delay used for
619 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
620 * between when the ATA command register is written, and then
621 * status is checked. Because waiting for "a while" before
622 * checking status is fine, post SRST, we perform this magic
623 * delay here as well.
624 */
625 msleep(150);
626
627 *class = ATA_DEV_NONE;
628 if (sata_dev_present(ap)) {
629 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
630 rc = -EIO;
631 reason = "device not ready";
632 goto fail;
633 }
634 *class = ahci_dev_classify(ap);
635 }
636
637 DPRINTK("EXIT, class=%u\n", *class);
638 return 0;
639
640 fail_restart:
641 ahci_start_engine(ap);
642 fail:
643 if (verbose)
644 printk(KERN_ERR "ata%u: softreset failed (%s)\n",
645 ap->id, reason);
646 else
647 DPRINTK("EXIT, rc=%d reason=\"%s\"\n", rc, reason);
648 return rc;
649 }
650
651 static int ahci_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
652 {
653 int rc;
654
655 DPRINTK("ENTER\n");
656
657 ahci_stop_engine(ap);
658 rc = sata_std_hardreset(ap, verbose, class);
659 ahci_start_engine(ap);
660
661 if (rc == 0)
662 *class = ahci_dev_classify(ap);
663 if (*class == ATA_DEV_UNKNOWN)
664 *class = ATA_DEV_NONE;
665
666 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
667 return rc;
668 }
669
670 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
671 {
672 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
673 u32 new_tmp, tmp;
674
675 ata_std_postreset(ap, class);
676
677 /* Make sure port's ATAPI bit is set appropriately */
678 new_tmp = tmp = readl(port_mmio + PORT_CMD);
679 if (*class == ATA_DEV_ATAPI)
680 new_tmp |= PORT_CMD_ATAPI;
681 else
682 new_tmp &= ~PORT_CMD_ATAPI;
683 if (new_tmp != tmp) {
684 writel(new_tmp, port_mmio + PORT_CMD);
685 readl(port_mmio + PORT_CMD); /* flush */
686 }
687 }
688
689 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
690 {
691 return ata_drive_probe_reset(ap, ata_std_probeinit,
692 ahci_softreset, ahci_hardreset,
693 ahci_postreset, classes);
694 }
695
696 static u8 ahci_check_status(struct ata_port *ap)
697 {
698 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
699
700 return readl(mmio + PORT_TFDATA) & 0xFF;
701 }
702
703 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
704 {
705 struct ahci_port_priv *pp = ap->private_data;
706 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
707
708 ata_tf_from_fis(d2h_fis, tf);
709 }
710
711 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
712 {
713 struct ahci_port_priv *pp = qc->ap->private_data;
714 struct scatterlist *sg;
715 struct ahci_sg *ahci_sg;
716 unsigned int n_sg = 0;
717
718 VPRINTK("ENTER\n");
719
720 /*
721 * Next, the S/G list.
722 */
723 ahci_sg = pp->cmd_tbl_sg;
724 ata_for_each_sg(sg, qc) {
725 dma_addr_t addr = sg_dma_address(sg);
726 u32 sg_len = sg_dma_len(sg);
727
728 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
729 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
730 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
731
732 ahci_sg++;
733 n_sg++;
734 }
735
736 return n_sg;
737 }
738
739 static void ahci_qc_prep(struct ata_queued_cmd *qc)
740 {
741 struct ata_port *ap = qc->ap;
742 struct ahci_port_priv *pp = ap->private_data;
743 int is_atapi = is_atapi_taskfile(&qc->tf);
744 u32 opts;
745 const u32 cmd_fis_len = 5; /* five dwords */
746 unsigned int n_elem;
747
748 /*
749 * Fill in command table information. First, the header,
750 * a SATA Register - Host to Device command FIS.
751 */
752 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
753 if (is_atapi) {
754 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
755 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
756 qc->dev->cdb_len);
757 }
758
759 n_elem = 0;
760 if (qc->flags & ATA_QCFLAG_DMAMAP)
761 n_elem = ahci_fill_sg(qc);
762
763 /*
764 * Fill in command slot information.
765 */
766 opts = cmd_fis_len | n_elem << 16;
767 if (qc->tf.flags & ATA_TFLAG_WRITE)
768 opts |= AHCI_CMD_WRITE;
769 if (is_atapi)
770 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
771
772 ahci_fill_cmd_slot(pp, opts);
773 }
774
775 static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
776 {
777 void __iomem *mmio = ap->host_set->mmio_base;
778 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
779 u32 tmp;
780
781 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
782 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
783 printk(KERN_WARNING "ata%u: port reset, "
784 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
785 ap->id,
786 irq_stat,
787 readl(mmio + HOST_IRQ_STAT),
788 readl(port_mmio + PORT_IRQ_STAT),
789 readl(port_mmio + PORT_CMD),
790 readl(port_mmio + PORT_TFDATA),
791 readl(port_mmio + PORT_SCR_STAT),
792 readl(port_mmio + PORT_SCR_ERR));
793
794 /* stop DMA */
795 ahci_stop_engine(ap);
796
797 /* clear SATA phy error, if any */
798 tmp = readl(port_mmio + PORT_SCR_ERR);
799 writel(tmp, port_mmio + PORT_SCR_ERR);
800
801 /* if DRQ/BSY is set, device needs to be reset.
802 * if so, issue COMRESET
803 */
804 tmp = readl(port_mmio + PORT_TFDATA);
805 if (tmp & (ATA_BUSY | ATA_DRQ)) {
806 writel(0x301, port_mmio + PORT_SCR_CTL);
807 readl(port_mmio + PORT_SCR_CTL); /* flush */
808 udelay(10);
809 writel(0x300, port_mmio + PORT_SCR_CTL);
810 readl(port_mmio + PORT_SCR_CTL); /* flush */
811 }
812
813 /* re-start DMA */
814 ahci_start_engine(ap);
815 }
816
817 static void ahci_eng_timeout(struct ata_port *ap)
818 {
819 struct ata_host_set *host_set = ap->host_set;
820 void __iomem *mmio = host_set->mmio_base;
821 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
822 struct ata_queued_cmd *qc;
823 unsigned long flags;
824
825 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
826
827 spin_lock_irqsave(&host_set->lock, flags);
828
829 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
830 qc = ata_qc_from_tag(ap, ap->active_tag);
831 qc->err_mask |= AC_ERR_TIMEOUT;
832
833 spin_unlock_irqrestore(&host_set->lock, flags);
834
835 ata_eh_qc_complete(qc);
836 }
837
838 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
839 {
840 void __iomem *mmio = ap->host_set->mmio_base;
841 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
842 u32 status, serr, ci;
843
844 serr = readl(port_mmio + PORT_SCR_ERR);
845 writel(serr, port_mmio + PORT_SCR_ERR);
846
847 status = readl(port_mmio + PORT_IRQ_STAT);
848 writel(status, port_mmio + PORT_IRQ_STAT);
849
850 ci = readl(port_mmio + PORT_CMD_ISSUE);
851 if (likely((ci & 0x1) == 0)) {
852 if (qc) {
853 WARN_ON(qc->err_mask);
854 ata_qc_complete(qc);
855 qc = NULL;
856 }
857 }
858
859 if (status & PORT_IRQ_FATAL) {
860 unsigned int err_mask;
861 if (status & PORT_IRQ_TF_ERR)
862 err_mask = AC_ERR_DEV;
863 else if (status & PORT_IRQ_IF_ERR)
864 err_mask = AC_ERR_ATA_BUS;
865 else
866 err_mask = AC_ERR_HOST_BUS;
867
868 /* command processing has stopped due to error; restart */
869 ahci_restart_port(ap, status);
870
871 if (qc) {
872 qc->err_mask |= err_mask;
873 ata_qc_complete(qc);
874 }
875 }
876
877 return 1;
878 }
879
880 static void ahci_irq_clear(struct ata_port *ap)
881 {
882 /* TODO */
883 }
884
885 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
886 {
887 struct ata_host_set *host_set = dev_instance;
888 struct ahci_host_priv *hpriv;
889 unsigned int i, handled = 0;
890 void __iomem *mmio;
891 u32 irq_stat, irq_ack = 0;
892
893 VPRINTK("ENTER\n");
894
895 hpriv = host_set->private_data;
896 mmio = host_set->mmio_base;
897
898 /* sigh. 0xffffffff is a valid return from h/w */
899 irq_stat = readl(mmio + HOST_IRQ_STAT);
900 irq_stat &= hpriv->port_map;
901 if (!irq_stat)
902 return IRQ_NONE;
903
904 spin_lock(&host_set->lock);
905
906 for (i = 0; i < host_set->n_ports; i++) {
907 struct ata_port *ap;
908
909 if (!(irq_stat & (1 << i)))
910 continue;
911
912 ap = host_set->ports[i];
913 if (ap) {
914 struct ata_queued_cmd *qc;
915 qc = ata_qc_from_tag(ap, ap->active_tag);
916 if (!ahci_host_intr(ap, qc))
917 if (ata_ratelimit())
918 dev_printk(KERN_WARNING, host_set->dev,
919 "unhandled interrupt on port %u\n",
920 i);
921
922 VPRINTK("port %u\n", i);
923 } else {
924 VPRINTK("port %u (no irq)\n", i);
925 if (ata_ratelimit())
926 dev_printk(KERN_WARNING, host_set->dev,
927 "interrupt on disabled port %u\n", i);
928 }
929
930 irq_ack |= (1 << i);
931 }
932
933 if (irq_ack) {
934 writel(irq_ack, mmio + HOST_IRQ_STAT);
935 handled = 1;
936 }
937
938 spin_unlock(&host_set->lock);
939
940 VPRINTK("EXIT\n");
941
942 return IRQ_RETVAL(handled);
943 }
944
945 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
946 {
947 struct ata_port *ap = qc->ap;
948 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
949
950 writel(1, port_mmio + PORT_CMD_ISSUE);
951 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
952
953 return 0;
954 }
955
956 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
957 unsigned int port_idx)
958 {
959 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
960 base = ahci_port_base_ul(base, port_idx);
961 VPRINTK("base now==0x%lx\n", base);
962
963 port->cmd_addr = base;
964 port->scr_addr = base + PORT_SCR;
965
966 VPRINTK("EXIT\n");
967 }
968
969 static int ahci_host_init(struct ata_probe_ent *probe_ent)
970 {
971 struct ahci_host_priv *hpriv = probe_ent->private_data;
972 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
973 void __iomem *mmio = probe_ent->mmio_base;
974 u32 tmp, cap_save;
975 unsigned int i, j, using_dac;
976 int rc;
977 void __iomem *port_mmio;
978
979 cap_save = readl(mmio + HOST_CAP);
980 cap_save &= ( (1<<28) | (1<<17) );
981 cap_save |= (1 << 27);
982
983 /* global controller reset */
984 tmp = readl(mmio + HOST_CTL);
985 if ((tmp & HOST_RESET) == 0) {
986 writel(tmp | HOST_RESET, mmio + HOST_CTL);
987 readl(mmio + HOST_CTL); /* flush */
988 }
989
990 /* reset must complete within 1 second, or
991 * the hardware should be considered fried.
992 */
993 ssleep(1);
994
995 tmp = readl(mmio + HOST_CTL);
996 if (tmp & HOST_RESET) {
997 dev_printk(KERN_ERR, &pdev->dev,
998 "controller reset failed (0x%x)\n", tmp);
999 return -EIO;
1000 }
1001
1002 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1003 (void) readl(mmio + HOST_CTL); /* flush */
1004 writel(cap_save, mmio + HOST_CAP);
1005 writel(0xf, mmio + HOST_PORTS_IMPL);
1006 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1007
1008 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1009 u16 tmp16;
1010
1011 pci_read_config_word(pdev, 0x92, &tmp16);
1012 tmp16 |= 0xf;
1013 pci_write_config_word(pdev, 0x92, tmp16);
1014 }
1015
1016 hpriv->cap = readl(mmio + HOST_CAP);
1017 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1018 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1019
1020 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1021 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1022
1023 using_dac = hpriv->cap & HOST_CAP_64;
1024 if (using_dac &&
1025 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1026 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1027 if (rc) {
1028 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1029 if (rc) {
1030 dev_printk(KERN_ERR, &pdev->dev,
1031 "64-bit DMA enable failed\n");
1032 return rc;
1033 }
1034 }
1035 } else {
1036 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1037 if (rc) {
1038 dev_printk(KERN_ERR, &pdev->dev,
1039 "32-bit DMA enable failed\n");
1040 return rc;
1041 }
1042 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1043 if (rc) {
1044 dev_printk(KERN_ERR, &pdev->dev,
1045 "32-bit consistent DMA enable failed\n");
1046 return rc;
1047 }
1048 }
1049
1050 for (i = 0; i < probe_ent->n_ports; i++) {
1051 #if 0 /* BIOSen initialize this incorrectly */
1052 if (!(hpriv->port_map & (1 << i)))
1053 continue;
1054 #endif
1055
1056 port_mmio = ahci_port_base(mmio, i);
1057 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1058
1059 ahci_setup_port(&probe_ent->port[i],
1060 (unsigned long) mmio, i);
1061
1062 /* make sure port is not active */
1063 tmp = readl(port_mmio + PORT_CMD);
1064 VPRINTK("PORT_CMD 0x%x\n", tmp);
1065 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1066 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1067 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1068 PORT_CMD_FIS_RX | PORT_CMD_START);
1069 writel(tmp, port_mmio + PORT_CMD);
1070 readl(port_mmio + PORT_CMD); /* flush */
1071
1072 /* spec says 500 msecs for each bit, so
1073 * this is slightly incorrect.
1074 */
1075 msleep(500);
1076 }
1077
1078 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1079
1080 j = 0;
1081 while (j < 100) {
1082 msleep(10);
1083 tmp = readl(port_mmio + PORT_SCR_STAT);
1084 if ((tmp & 0xf) == 0x3)
1085 break;
1086 j++;
1087 }
1088
1089 tmp = readl(port_mmio + PORT_SCR_ERR);
1090 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1091 writel(tmp, port_mmio + PORT_SCR_ERR);
1092
1093 /* ack any pending irq events for this port */
1094 tmp = readl(port_mmio + PORT_IRQ_STAT);
1095 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1096 if (tmp)
1097 writel(tmp, port_mmio + PORT_IRQ_STAT);
1098
1099 writel(1 << i, mmio + HOST_IRQ_STAT);
1100
1101 /* set irq mask (enables interrupts) */
1102 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1103 }
1104
1105 tmp = readl(mmio + HOST_CTL);
1106 VPRINTK("HOST_CTL 0x%x\n", tmp);
1107 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1108 tmp = readl(mmio + HOST_CTL);
1109 VPRINTK("HOST_CTL 0x%x\n", tmp);
1110
1111 pci_set_master(pdev);
1112
1113 return 0;
1114 }
1115
1116 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1117 {
1118 struct ahci_host_priv *hpriv = probe_ent->private_data;
1119 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1120 void __iomem *mmio = probe_ent->mmio_base;
1121 u32 vers, cap, impl, speed;
1122 const char *speed_s;
1123 u16 cc;
1124 const char *scc_s;
1125
1126 vers = readl(mmio + HOST_VERSION);
1127 cap = hpriv->cap;
1128 impl = hpriv->port_map;
1129
1130 speed = (cap >> 20) & 0xf;
1131 if (speed == 1)
1132 speed_s = "1.5";
1133 else if (speed == 2)
1134 speed_s = "3";
1135 else
1136 speed_s = "?";
1137
1138 pci_read_config_word(pdev, 0x0a, &cc);
1139 if (cc == 0x0101)
1140 scc_s = "IDE";
1141 else if (cc == 0x0106)
1142 scc_s = "SATA";
1143 else if (cc == 0x0104)
1144 scc_s = "RAID";
1145 else
1146 scc_s = "unknown";
1147
1148 dev_printk(KERN_INFO, &pdev->dev,
1149 "AHCI %02x%02x.%02x%02x "
1150 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1151 ,
1152
1153 (vers >> 24) & 0xff,
1154 (vers >> 16) & 0xff,
1155 (vers >> 8) & 0xff,
1156 vers & 0xff,
1157
1158 ((cap >> 8) & 0x1f) + 1,
1159 (cap & 0x1f) + 1,
1160 speed_s,
1161 impl,
1162 scc_s);
1163
1164 dev_printk(KERN_INFO, &pdev->dev,
1165 "flags: "
1166 "%s%s%s%s%s%s"
1167 "%s%s%s%s%s%s%s\n"
1168 ,
1169
1170 cap & (1 << 31) ? "64bit " : "",
1171 cap & (1 << 30) ? "ncq " : "",
1172 cap & (1 << 28) ? "ilck " : "",
1173 cap & (1 << 27) ? "stag " : "",
1174 cap & (1 << 26) ? "pm " : "",
1175 cap & (1 << 25) ? "led " : "",
1176
1177 cap & (1 << 24) ? "clo " : "",
1178 cap & (1 << 19) ? "nz " : "",
1179 cap & (1 << 18) ? "only " : "",
1180 cap & (1 << 17) ? "pmp " : "",
1181 cap & (1 << 15) ? "pio " : "",
1182 cap & (1 << 14) ? "slum " : "",
1183 cap & (1 << 13) ? "part " : ""
1184 );
1185 }
1186
1187 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1188 {
1189 static int printed_version;
1190 struct ata_probe_ent *probe_ent = NULL;
1191 struct ahci_host_priv *hpriv;
1192 unsigned long base;
1193 void __iomem *mmio_base;
1194 unsigned int board_idx = (unsigned int) ent->driver_data;
1195 int have_msi, pci_dev_busy = 0;
1196 int rc;
1197
1198 VPRINTK("ENTER\n");
1199
1200 if (!printed_version++)
1201 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1202
1203 rc = pci_enable_device(pdev);
1204 if (rc)
1205 return rc;
1206
1207 rc = pci_request_regions(pdev, DRV_NAME);
1208 if (rc) {
1209 pci_dev_busy = 1;
1210 goto err_out;
1211 }
1212
1213 if (pci_enable_msi(pdev) == 0)
1214 have_msi = 1;
1215 else {
1216 pci_intx(pdev, 1);
1217 have_msi = 0;
1218 }
1219
1220 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1221 if (probe_ent == NULL) {
1222 rc = -ENOMEM;
1223 goto err_out_msi;
1224 }
1225
1226 memset(probe_ent, 0, sizeof(*probe_ent));
1227 probe_ent->dev = pci_dev_to_dev(pdev);
1228 INIT_LIST_HEAD(&probe_ent->node);
1229
1230 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1231 if (mmio_base == NULL) {
1232 rc = -ENOMEM;
1233 goto err_out_free_ent;
1234 }
1235 base = (unsigned long) mmio_base;
1236
1237 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1238 if (!hpriv) {
1239 rc = -ENOMEM;
1240 goto err_out_iounmap;
1241 }
1242 memset(hpriv, 0, sizeof(*hpriv));
1243
1244 probe_ent->sht = ahci_port_info[board_idx].sht;
1245 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1246 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1247 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1248 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1249
1250 probe_ent->irq = pdev->irq;
1251 probe_ent->irq_flags = SA_SHIRQ;
1252 probe_ent->mmio_base = mmio_base;
1253 probe_ent->private_data = hpriv;
1254
1255 if (have_msi)
1256 hpriv->flags |= AHCI_FLAG_MSI;
1257
1258 /* JMicron-specific fixup: make sure we're in AHCI mode */
1259 if (pdev->vendor == 0x197b)
1260 pci_write_config_byte(pdev, 0x41, 0xa1);
1261
1262 /* initialize adapter */
1263 rc = ahci_host_init(probe_ent);
1264 if (rc)
1265 goto err_out_hpriv;
1266
1267 ahci_print_info(probe_ent);
1268
1269 /* FIXME: check ata_device_add return value */
1270 ata_device_add(probe_ent);
1271 kfree(probe_ent);
1272
1273 return 0;
1274
1275 err_out_hpriv:
1276 kfree(hpriv);
1277 err_out_iounmap:
1278 pci_iounmap(pdev, mmio_base);
1279 err_out_free_ent:
1280 kfree(probe_ent);
1281 err_out_msi:
1282 if (have_msi)
1283 pci_disable_msi(pdev);
1284 else
1285 pci_intx(pdev, 0);
1286 pci_release_regions(pdev);
1287 err_out:
1288 if (!pci_dev_busy)
1289 pci_disable_device(pdev);
1290 return rc;
1291 }
1292
1293 static void ahci_remove_one (struct pci_dev *pdev)
1294 {
1295 struct device *dev = pci_dev_to_dev(pdev);
1296 struct ata_host_set *host_set = dev_get_drvdata(dev);
1297 struct ahci_host_priv *hpriv = host_set->private_data;
1298 struct ata_port *ap;
1299 unsigned int i;
1300 int have_msi;
1301
1302 for (i = 0; i < host_set->n_ports; i++) {
1303 ap = host_set->ports[i];
1304
1305 scsi_remove_host(ap->host);
1306 }
1307
1308 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1309 free_irq(host_set->irq, host_set);
1310
1311 for (i = 0; i < host_set->n_ports; i++) {
1312 ap = host_set->ports[i];
1313
1314 ata_scsi_release(ap->host);
1315 scsi_host_put(ap->host);
1316 }
1317
1318 kfree(hpriv);
1319 pci_iounmap(pdev, host_set->mmio_base);
1320 kfree(host_set);
1321
1322 if (have_msi)
1323 pci_disable_msi(pdev);
1324 else
1325 pci_intx(pdev, 0);
1326 pci_release_regions(pdev);
1327 pci_disable_device(pdev);
1328 dev_set_drvdata(dev, NULL);
1329 }
1330
1331 static int __init ahci_init(void)
1332 {
1333 return pci_module_init(&ahci_pci_driver);
1334 }
1335
1336 static void __exit ahci_exit(void)
1337 {
1338 pci_unregister_driver(&ahci_pci_driver);
1339 }
1340
1341
1342 MODULE_AUTHOR("Jeff Garzik");
1343 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1344 MODULE_LICENSE("GPL");
1345 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1346 MODULE_VERSION(DRV_VERSION);
1347
1348 module_init(ahci_init);
1349 module_exit(ahci_exit);
SocketAccessConTroL development