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PCI ACPI: Rework PCI handling of wake-up
[linux-2.6/sactl.git] / drivers / pci / probe.c
blobb1724cf31b669ef459d3250aa8fae48b38e4c7fa
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
19
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
23
24
25 static int find_anything(struct device *dev, void *data)
26 {
27 return 1;
28 }
29
30 /*
31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type.
34 */
35 int no_pci_devices(void)
36 {
37 struct device *dev;
38 int no_devices;
39
40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
41 no_devices = (dev == NULL);
42 put_device(dev);
43 return no_devices;
44 }
45 EXPORT_SYMBOL(no_pci_devices);
46
47 #ifdef HAVE_PCI_LEGACY
48 /**
49 * pci_create_legacy_files - create legacy I/O port and memory files
50 * @b: bus to create files under
51 *
52 * Some platforms allow access to legacy I/O port and ISA memory space on
53 * a per-bus basis. This routine creates the files and ties them into
54 * their associated read, write and mmap files from pci-sysfs.c
55 */
56 static void pci_create_legacy_files(struct pci_bus *b)
57 {
58 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
59 GFP_ATOMIC);
60 if (b->legacy_io) {
61 b->legacy_io->attr.name = "legacy_io";
62 b->legacy_io->size = 0xffff;
63 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
64 b->legacy_io->read = pci_read_legacy_io;
65 b->legacy_io->write = pci_write_legacy_io;
66 device_create_bin_file(&b->dev, b->legacy_io);
67
68 /* Allocated above after the legacy_io struct */
69 b->legacy_mem = b->legacy_io + 1;
70 b->legacy_mem->attr.name = "legacy_mem";
71 b->legacy_mem->size = 1024*1024;
72 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
73 b->legacy_mem->mmap = pci_mmap_legacy_mem;
74 device_create_bin_file(&b->dev, b->legacy_mem);
75 }
76 }
77
78 void pci_remove_legacy_files(struct pci_bus *b)
79 {
80 if (b->legacy_io) {
81 device_remove_bin_file(&b->dev, b->legacy_io);
82 device_remove_bin_file(&b->dev, b->legacy_mem);
83 kfree(b->legacy_io); /* both are allocated here */
84 }
85 }
86 #else /* !HAVE_PCI_LEGACY */
87 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
88 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
89 #endif /* HAVE_PCI_LEGACY */
90
91 /*
92 * PCI Bus Class Devices
93 */
94 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
95 int type,
96 struct device_attribute *attr,
97 char *buf)
98 {
99 int ret;
100 cpumask_t cpumask;
101
102 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
103 ret = type?
104 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask):
105 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
106 buf[ret++] = '\n';
107 buf[ret] = '\0';
108 return ret;
109 }
110
111 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
112 struct device_attribute *attr,
113 char *buf)
114 {
115 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
116 }
117
118 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
119 struct device_attribute *attr,
120 char *buf)
121 {
122 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
123 }
124
125 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
126 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
127
128 /*
129 * PCI Bus Class
130 */
131 static void release_pcibus_dev(struct device *dev)
132 {
133 struct pci_bus *pci_bus = to_pci_bus(dev);
134
135 if (pci_bus->bridge)
136 put_device(pci_bus->bridge);
137 kfree(pci_bus);
138 }
139
140 static struct class pcibus_class = {
141 .name = "pci_bus",
142 .dev_release = &release_pcibus_dev,
143 };
144
145 static int __init pcibus_class_init(void)
146 {
147 return class_register(&pcibus_class);
148 }
149 postcore_initcall(pcibus_class_init);
150
151 /*
152 * Translate the low bits of the PCI base
153 * to the resource type
154 */
155 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
156 {
157 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
158 return IORESOURCE_IO;
159
160 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
161 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
162
163 return IORESOURCE_MEM;
164 }
165
166 /*
167 * Find the extent of a PCI decode..
168 */
169 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
170 {
171 u32 size = mask & maxbase; /* Find the significant bits */
172 if (!size)
173 return 0;
174
175 /* Get the lowest of them to find the decode size, and
176 from that the extent. */
177 size = (size & ~(size-1)) - 1;
178
179 /* base == maxbase can be valid only if the BAR has
180 already been programmed with all 1s. */
181 if (base == maxbase && ((base | size) & mask) != mask)
182 return 0;
183
184 return size;
185 }
186
187 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
188 {
189 u64 size = mask & maxbase; /* Find the significant bits */
190 if (!size)
191 return 0;
192
193 /* Get the lowest of them to find the decode size, and
194 from that the extent. */
195 size = (size & ~(size-1)) - 1;
196
197 /* base == maxbase can be valid only if the BAR has
198 already been programmed with all 1s. */
199 if (base == maxbase && ((base | size) & mask) != mask)
200 return 0;
201
202 return size;
203 }
204
205 static inline int is_64bit_memory(u32 mask)
206 {
207 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
208 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
209 return 1;
210 return 0;
211 }
212
213 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
214 {
215 unsigned int pos, reg, next;
216 u32 l, sz;
217 struct resource *res;
218
219 for(pos=0; pos<howmany; pos = next) {
220 u64 l64;
221 u64 sz64;
222 u32 raw_sz;
223
224 next = pos+1;
225 res = &dev->resource[pos];
226 res->name = pci_name(dev);
227 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
228 pci_read_config_dword(dev, reg, &l);
229 pci_write_config_dword(dev, reg, ~0);
230 pci_read_config_dword(dev, reg, &sz);
231 pci_write_config_dword(dev, reg, l);
232 if (!sz || sz == 0xffffffff)
233 continue;
234 if (l == 0xffffffff)
235 l = 0;
236 raw_sz = sz;
237 if ((l & PCI_BASE_ADDRESS_SPACE) ==
238 PCI_BASE_ADDRESS_SPACE_MEMORY) {
239 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
240 /*
241 * For 64bit prefetchable memory sz could be 0, if the
242 * real size is bigger than 4G, so we need to check
243 * szhi for that.
244 */
245 if (!is_64bit_memory(l) && !sz)
246 continue;
247 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
248 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
249 } else {
250 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
251 if (!sz)
252 continue;
253 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
254 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
255 }
256 res->end = res->start + (unsigned long) sz;
257 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
258 if (is_64bit_memory(l)) {
259 u32 szhi, lhi;
260
261 pci_read_config_dword(dev, reg+4, &lhi);
262 pci_write_config_dword(dev, reg+4, ~0);
263 pci_read_config_dword(dev, reg+4, &szhi);
264 pci_write_config_dword(dev, reg+4, lhi);
265 sz64 = ((u64)szhi << 32) | raw_sz;
266 l64 = ((u64)lhi << 32) | l;
267 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
268 next++;
269 #if BITS_PER_LONG == 64
270 if (!sz64) {
271 res->start = 0;
272 res->end = 0;
273 res->flags = 0;
274 continue;
275 }
276 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
277 res->end = res->start + sz64;
278 #else
279 if (sz64 > 0x100000000ULL) {
280 dev_err(&dev->dev, "BAR %d: can't handle 64-bit"
281 " BAR\n", pos);
282 res->start = 0;
283 res->flags = 0;
284 } else if (lhi) {
285 /* 64-bit wide address, treat as disabled */
286 pci_write_config_dword(dev, reg,
287 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
288 pci_write_config_dword(dev, reg+4, 0);
289 res->start = 0;
290 res->end = sz;
291 }
292 #endif
293 }
294 }
295 if (rom) {
296 dev->rom_base_reg = rom;
297 res = &dev->resource[PCI_ROM_RESOURCE];
298 res->name = pci_name(dev);
299 pci_read_config_dword(dev, rom, &l);
300 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
301 pci_read_config_dword(dev, rom, &sz);
302 pci_write_config_dword(dev, rom, l);
303 if (l == 0xffffffff)
304 l = 0;
305 if (sz && sz != 0xffffffff) {
306 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
307 if (sz) {
308 res->flags = (l & IORESOURCE_ROM_ENABLE) |
309 IORESOURCE_MEM | IORESOURCE_PREFETCH |
310 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
311 IORESOURCE_SIZEALIGN;
312 res->start = l & PCI_ROM_ADDRESS_MASK;
313 res->end = res->start + (unsigned long) sz;
314 }
315 }
316 }
317 }
318
319 void __devinit pci_read_bridge_bases(struct pci_bus *child)
320 {
321 struct pci_dev *dev = child->self;
322 u8 io_base_lo, io_limit_lo;
323 u16 mem_base_lo, mem_limit_lo;
324 unsigned long base, limit;
325 struct resource *res;
326 int i;
327
328 if (!dev) /* It's a host bus, nothing to read */
329 return;
330
331 if (dev->transparent) {
332 dev_info(&dev->dev, "transparent bridge\n");
333 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
334 child->resource[i] = child->parent->resource[i - 3];
335 }
336
337 for(i=0; i<3; i++)
338 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
339
340 res = child->resource[0];
341 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
342 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
343 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
344 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
345
346 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
347 u16 io_base_hi, io_limit_hi;
348 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
349 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
350 base |= (io_base_hi << 16);
351 limit |= (io_limit_hi << 16);
352 }
353
354 if (base <= limit) {
355 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
356 if (!res->start)
357 res->start = base;
358 if (!res->end)
359 res->end = limit + 0xfff;
360 }
361
362 res = child->resource[1];
363 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
364 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
365 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
366 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
367 if (base <= limit) {
368 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
369 res->start = base;
370 res->end = limit + 0xfffff;
371 }
372
373 res = child->resource[2];
374 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
375 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
376 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
377 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
378
379 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
380 u32 mem_base_hi, mem_limit_hi;
381 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
382 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
383
384 /*
385 * Some bridges set the base > limit by default, and some
386 * (broken) BIOSes do not initialize them. If we find
387 * this, just assume they are not being used.
388 */
389 if (mem_base_hi <= mem_limit_hi) {
390 #if BITS_PER_LONG == 64
391 base |= ((long) mem_base_hi) << 32;
392 limit |= ((long) mem_limit_hi) << 32;
393 #else
394 if (mem_base_hi || mem_limit_hi) {
395 dev_err(&dev->dev, "can't handle 64-bit "
396 "address space for bridge\n");
397 return;
398 }
399 #endif
400 }
401 }
402 if (base <= limit) {
403 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
404 res->start = base;
405 res->end = limit + 0xfffff;
406 }
407 }
408
409 static struct pci_bus * pci_alloc_bus(void)
410 {
411 struct pci_bus *b;
412
413 b = kzalloc(sizeof(*b), GFP_KERNEL);
414 if (b) {
415 INIT_LIST_HEAD(&b->node);
416 INIT_LIST_HEAD(&b->children);
417 INIT_LIST_HEAD(&b->devices);
418 INIT_LIST_HEAD(&b->slots);
419 }
420 return b;
421 }
422
423 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
424 struct pci_dev *bridge, int busnr)
425 {
426 struct pci_bus *child;
427 int i;
428
429 /*
430 * Allocate a new bus, and inherit stuff from the parent..
431 */
432 child = pci_alloc_bus();
433 if (!child)
434 return NULL;
435
436 child->self = bridge;
437 child->parent = parent;
438 child->ops = parent->ops;
439 child->sysdata = parent->sysdata;
440 child->bus_flags = parent->bus_flags;
441 child->bridge = get_device(&bridge->dev);
442
443 /* initialize some portions of the bus device, but don't register it
444 * now as the parent is not properly set up yet. This device will get
445 * registered later in pci_bus_add_devices()
446 */
447 child->dev.class = &pcibus_class;
448 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
449
450 /*
451 * Set up the primary, secondary and subordinate
452 * bus numbers.
453 */
454 child->number = child->secondary = busnr;
455 child->primary = parent->secondary;
456 child->subordinate = 0xff;
457
458 /* Set up default resource pointers and names.. */
459 for (i = 0; i < 4; i++) {
460 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
461 child->resource[i]->name = child->name;
462 }
463 bridge->subordinate = child;
464
465 return child;
466 }
467
468 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
469 {
470 struct pci_bus *child;
471
472 child = pci_alloc_child_bus(parent, dev, busnr);
473 if (child) {
474 down_write(&pci_bus_sem);
475 list_add_tail(&child->node, &parent->children);
476 up_write(&pci_bus_sem);
477 }
478 return child;
479 }
480
481 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
482 {
483 struct pci_bus *parent = child->parent;
484
485 /* Attempts to fix that up are really dangerous unless
486 we're going to re-assign all bus numbers. */
487 if (!pcibios_assign_all_busses())
488 return;
489
490 while (parent->parent && parent->subordinate < max) {
491 parent->subordinate = max;
492 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
493 parent = parent->parent;
494 }
495 }
496
497 /*
498 * If it's a bridge, configure it and scan the bus behind it.
499 * For CardBus bridges, we don't scan behind as the devices will
500 * be handled by the bridge driver itself.
501 *
502 * We need to process bridges in two passes -- first we scan those
503 * already configured by the BIOS and after we are done with all of
504 * them, we proceed to assigning numbers to the remaining buses in
505 * order to avoid overlaps between old and new bus numbers.
506 */
507 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
508 {
509 struct pci_bus *child;
510 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
511 u32 buses, i, j = 0;
512 u16 bctl;
513
514 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
515
516 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
517 buses & 0xffffff, pass);
518
519 /* Disable MasterAbortMode during probing to avoid reporting
520 of bus errors (in some architectures) */
521 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
522 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
523 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
524
525 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
526 unsigned int cmax, busnr;
527 /*
528 * Bus already configured by firmware, process it in the first
529 * pass and just note the configuration.
530 */
531 if (pass)
532 goto out;
533 busnr = (buses >> 8) & 0xFF;
534
535 /*
536 * If we already got to this bus through a different bridge,
537 * ignore it. This can happen with the i450NX chipset.
538 */
539 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
540 dev_info(&dev->dev, "bus %04x:%02x already known\n",
541 pci_domain_nr(bus), busnr);
542 goto out;
543 }
544
545 child = pci_add_new_bus(bus, dev, busnr);
546 if (!child)
547 goto out;
548 child->primary = buses & 0xFF;
549 child->subordinate = (buses >> 16) & 0xFF;
550 child->bridge_ctl = bctl;
551
552 cmax = pci_scan_child_bus(child);
553 if (cmax > max)
554 max = cmax;
555 if (child->subordinate > max)
556 max = child->subordinate;
557 } else {
558 /*
559 * We need to assign a number to this bus which we always
560 * do in the second pass.
561 */
562 if (!pass) {
563 if (pcibios_assign_all_busses())
564 /* Temporarily disable forwarding of the
565 configuration cycles on all bridges in
566 this bus segment to avoid possible
567 conflicts in the second pass between two
568 bridges programmed with overlapping
569 bus ranges. */
570 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
571 buses & ~0xffffff);
572 goto out;
573 }
574
575 /* Clear errors */
576 pci_write_config_word(dev, PCI_STATUS, 0xffff);
577
578 /* Prevent assigning a bus number that already exists.
579 * This can happen when a bridge is hot-plugged */
580 if (pci_find_bus(pci_domain_nr(bus), max+1))
581 goto out;
582 child = pci_add_new_bus(bus, dev, ++max);
583 buses = (buses & 0xff000000)
584 | ((unsigned int)(child->primary) << 0)
585 | ((unsigned int)(child->secondary) << 8)
586 | ((unsigned int)(child->subordinate) << 16);
587
588 /*
589 * yenta.c forces a secondary latency timer of 176.
590 * Copy that behaviour here.
591 */
592 if (is_cardbus) {
593 buses &= ~0xff000000;
594 buses |= CARDBUS_LATENCY_TIMER << 24;
595 }
596
597 /*
598 * We need to blast all three values with a single write.
599 */
600 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
601
602 if (!is_cardbus) {
603 child->bridge_ctl = bctl;
604 /*
605 * Adjust subordinate busnr in parent buses.
606 * We do this before scanning for children because
607 * some devices may not be detected if the bios
608 * was lazy.
609 */
610 pci_fixup_parent_subordinate_busnr(child, max);
611 /* Now we can scan all subordinate buses... */
612 max = pci_scan_child_bus(child);
613 /*
614 * now fix it up again since we have found
615 * the real value of max.
616 */
617 pci_fixup_parent_subordinate_busnr(child, max);
618 } else {
619 /*
620 * For CardBus bridges, we leave 4 bus numbers
621 * as cards with a PCI-to-PCI bridge can be
622 * inserted later.
623 */
624 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
625 struct pci_bus *parent = bus;
626 if (pci_find_bus(pci_domain_nr(bus),
627 max+i+1))
628 break;
629 while (parent->parent) {
630 if ((!pcibios_assign_all_busses()) &&
631 (parent->subordinate > max) &&
632 (parent->subordinate <= max+i)) {
633 j = 1;
634 }
635 parent = parent->parent;
636 }
637 if (j) {
638 /*
639 * Often, there are two cardbus bridges
640 * -- try to leave one valid bus number
641 * for each one.
642 */
643 i /= 2;
644 break;
645 }
646 }
647 max += i;
648 pci_fixup_parent_subordinate_busnr(child, max);
649 }
650 /*
651 * Set the subordinate bus number to its real value.
652 */
653 child->subordinate = max;
654 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
655 }
656
657 sprintf(child->name,
658 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
659 pci_domain_nr(bus), child->number);
660
661 /* Has only triggered on CardBus, fixup is in yenta_socket */
662 while (bus->parent) {
663 if ((child->subordinate > bus->subordinate) ||
664 (child->number > bus->subordinate) ||
665 (child->number < bus->number) ||
666 (child->subordinate < bus->number)) {
667 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
668 "hidden behind%s bridge #%02x (-#%02x)\n",
669 child->number, child->subordinate,
670 (bus->number > child->subordinate &&
671 bus->subordinate < child->number) ?
672 "wholly" : "partially",
673 bus->self->transparent ? " transparent" : "",
674 bus->number, bus->subordinate);
675 }
676 bus = bus->parent;
677 }
678
679 out:
680 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
681
682 return max;
683 }
684
685 /*
686 * Read interrupt line and base address registers.
687 * The architecture-dependent code can tweak these, of course.
688 */
689 static void pci_read_irq(struct pci_dev *dev)
690 {
691 unsigned char irq;
692
693 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
694 dev->pin = irq;
695 if (irq)
696 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
697 dev->irq = irq;
698 }
699
700 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
701
702 /**
703 * pci_setup_device - fill in class and map information of a device
704 * @dev: the device structure to fill
705 *
706 * Initialize the device structure with information about the device's
707 * vendor,class,memory and IO-space addresses,IRQ lines etc.
708 * Called at initialisation of the PCI subsystem and by CardBus services.
709 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
710 * or CardBus).
711 */
712 static int pci_setup_device(struct pci_dev * dev)
713 {
714 u32 class;
715
716 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
717 dev->bus->number, PCI_SLOT(dev->devfn),
718 PCI_FUNC(dev->devfn));
719
720 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
721 dev->revision = class & 0xff;
722 class >>= 8; /* upper 3 bytes */
723 dev->class = class;
724 class >>= 8;
725
726 dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n",
727 dev->vendor, dev->device, class, dev->hdr_type);
728
729 /* "Unknown power state" */
730 dev->current_state = PCI_UNKNOWN;
731
732 /* Early fixups, before probing the BARs */
733 pci_fixup_device(pci_fixup_early, dev);
734 class = dev->class >> 8;
735
736 switch (dev->hdr_type) { /* header type */
737 case PCI_HEADER_TYPE_NORMAL: /* standard header */
738 if (class == PCI_CLASS_BRIDGE_PCI)
739 goto bad;
740 pci_read_irq(dev);
741 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
742 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
743 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
744
745 /*
746 * Do the ugly legacy mode stuff here rather than broken chip
747 * quirk code. Legacy mode ATA controllers have fixed
748 * addresses. These are not always echoed in BAR0-3, and
749 * BAR0-3 in a few cases contain junk!
750 */
751 if (class == PCI_CLASS_STORAGE_IDE) {
752 u8 progif;
753 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
754 if ((progif & 1) == 0) {
755 dev->resource[0].start = 0x1F0;
756 dev->resource[0].end = 0x1F7;
757 dev->resource[0].flags = LEGACY_IO_RESOURCE;
758 dev->resource[1].start = 0x3F6;
759 dev->resource[1].end = 0x3F6;
760 dev->resource[1].flags = LEGACY_IO_RESOURCE;
761 }
762 if ((progif & 4) == 0) {
763 dev->resource[2].start = 0x170;
764 dev->resource[2].end = 0x177;
765 dev->resource[2].flags = LEGACY_IO_RESOURCE;
766 dev->resource[3].start = 0x376;
767 dev->resource[3].end = 0x376;
768 dev->resource[3].flags = LEGACY_IO_RESOURCE;
769 }
770 }
771 break;
772
773 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
774 if (class != PCI_CLASS_BRIDGE_PCI)
775 goto bad;
776 /* The PCI-to-PCI bridge spec requires that subtractive
777 decoding (i.e. transparent) bridge must have programming
778 interface code of 0x01. */
779 pci_read_irq(dev);
780 dev->transparent = ((dev->class & 0xff) == 1);
781 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
782 break;
783
784 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
785 if (class != PCI_CLASS_BRIDGE_CARDBUS)
786 goto bad;
787 pci_read_irq(dev);
788 pci_read_bases(dev, 1, 0);
789 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
790 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
791 break;
792
793 default: /* unknown header */
794 dev_err(&dev->dev, "unknown header type %02x, "
795 "ignoring device\n", dev->hdr_type);
796 return -1;
797
798 bad:
799 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
800 "type %02x)\n", class, dev->hdr_type);
801 dev->class = PCI_CLASS_NOT_DEFINED;
802 }
803
804 /* We found a fine healthy device, go go go... */
805 return 0;
806 }
807
808 /**
809 * pci_release_dev - free a pci device structure when all users of it are finished.
810 * @dev: device that's been disconnected
811 *
812 * Will be called only by the device core when all users of this pci device are
813 * done.
814 */
815 static void pci_release_dev(struct device *dev)
816 {
817 struct pci_dev *pci_dev;
818
819 pci_dev = to_pci_dev(dev);
820 pci_vpd_release(pci_dev);
821 kfree(pci_dev);
822 }
823
824 static void set_pcie_port_type(struct pci_dev *pdev)
825 {
826 int pos;
827 u16 reg16;
828
829 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
830 if (!pos)
831 return;
832 pdev->is_pcie = 1;
833 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
834 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
835 }
836
837 /**
838 * pci_cfg_space_size - get the configuration space size of the PCI device.
839 * @dev: PCI device
840 *
841 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
842 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
843 * access it. Maybe we don't have a way to generate extended config space
844 * accesses, or the device is behind a reverse Express bridge. So we try
845 * reading the dword at 0x100 which must either be 0 or a valid extended
846 * capability header.
847 */
848 int pci_cfg_space_size_ext(struct pci_dev *dev)
849 {
850 u32 status;
851
852 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
853 goto fail;
854 if (status == 0xffffffff)
855 goto fail;
856
857 return PCI_CFG_SPACE_EXP_SIZE;
858
859 fail:
860 return PCI_CFG_SPACE_SIZE;
861 }
862
863 int pci_cfg_space_size(struct pci_dev *dev)
864 {
865 int pos;
866 u32 status;
867
868 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
869 if (!pos) {
870 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
871 if (!pos)
872 goto fail;
873
874 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
875 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
876 goto fail;
877 }
878
879 return pci_cfg_space_size_ext(dev);
880
881 fail:
882 return PCI_CFG_SPACE_SIZE;
883 }
884
885 static void pci_release_bus_bridge_dev(struct device *dev)
886 {
887 kfree(dev);
888 }
889
890 struct pci_dev *alloc_pci_dev(void)
891 {
892 struct pci_dev *dev;
893
894 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
895 if (!dev)
896 return NULL;
897
898 INIT_LIST_HEAD(&dev->bus_list);
899
900 pci_msi_init_pci_dev(dev);
901
902 return dev;
903 }
904 EXPORT_SYMBOL(alloc_pci_dev);
905
906 /*
907 * Read the config data for a PCI device, sanity-check it
908 * and fill in the dev structure...
909 */
910 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
911 {
912 struct pci_dev *dev;
913 u32 l;
914 u8 hdr_type;
915 int delay = 1;
916
917 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
918 return NULL;
919
920 /* some broken boards return 0 or ~0 if a slot is empty: */
921 if (l == 0xffffffff || l == 0x00000000 ||
922 l == 0x0000ffff || l == 0xffff0000)
923 return NULL;
924
925 /* Configuration request Retry Status */
926 while (l == 0xffff0001) {
927 msleep(delay);
928 delay *= 2;
929 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
930 return NULL;
931 /* Card hasn't responded in 60 seconds? Must be stuck. */
932 if (delay > 60 * 1000) {
933 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
934 "responding\n", pci_domain_nr(bus),
935 bus->number, PCI_SLOT(devfn),
936 PCI_FUNC(devfn));
937 return NULL;
938 }
939 }
940
941 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
942 return NULL;
943
944 dev = alloc_pci_dev();
945 if (!dev)
946 return NULL;
947
948 dev->bus = bus;
949 dev->sysdata = bus->sysdata;
950 dev->dev.parent = bus->bridge;
951 dev->dev.bus = &pci_bus_type;
952 dev->devfn = devfn;
953 dev->hdr_type = hdr_type & 0x7f;
954 dev->multifunction = !!(hdr_type & 0x80);
955 dev->vendor = l & 0xffff;
956 dev->device = (l >> 16) & 0xffff;
957 dev->cfg_size = pci_cfg_space_size(dev);
958 dev->error_state = pci_channel_io_normal;
959 set_pcie_port_type(dev);
960
961 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
962 set this higher, assuming the system even supports it. */
963 dev->dma_mask = 0xffffffff;
964 if (pci_setup_device(dev) < 0) {
965 kfree(dev);
966 return NULL;
967 }
968
969 pci_vpd_pci22_init(dev);
970
971 return dev;
972 }
973
974 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
975 {
976 device_initialize(&dev->dev);
977 dev->dev.release = pci_release_dev;
978 pci_dev_get(dev);
979
980 dev->dev.dma_mask = &dev->dma_mask;
981 dev->dev.dma_parms = &dev->dma_parms;
982 dev->dev.coherent_dma_mask = 0xffffffffull;
983
984 pci_set_dma_max_seg_size(dev, 65536);
985 pci_set_dma_seg_boundary(dev, 0xffffffff);
986
987 /* Fix up broken headers */
988 pci_fixup_device(pci_fixup_header, dev);
989
990 /* Initialize power management of the device */
991 pci_pm_init(dev);
992
993 /*
994 * Add the device to our list of discovered devices
995 * and the bus list for fixup functions, etc.
996 */
997 down_write(&pci_bus_sem);
998 list_add_tail(&dev->bus_list, &bus->devices);
999 up_write(&pci_bus_sem);
1000 }
1001
1002 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1003 {
1004 struct pci_dev *dev;
1005
1006 dev = pci_scan_device(bus, devfn);
1007 if (!dev)
1008 return NULL;
1009
1010 pci_device_add(dev, bus);
1011
1012 return dev;
1013 }
1014 EXPORT_SYMBOL(pci_scan_single_device);
1015
1016 /**
1017 * pci_scan_slot - scan a PCI slot on a bus for devices.
1018 * @bus: PCI bus to scan
1019 * @devfn: slot number to scan (must have zero function.)
1020 *
1021 * Scan a PCI slot on the specified PCI bus for devices, adding
1022 * discovered devices to the @bus->devices list. New devices
1023 * will not have is_added set.
1024 */
1025 int pci_scan_slot(struct pci_bus *bus, int devfn)
1026 {
1027 int func, nr = 0;
1028 int scan_all_fns;
1029
1030 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
1031
1032 for (func = 0; func < 8; func++, devfn++) {
1033 struct pci_dev *dev;
1034
1035 dev = pci_scan_single_device(bus, devfn);
1036 if (dev) {
1037 nr++;
1038
1039 /*
1040 * If this is a single function device,
1041 * don't scan past the first function.
1042 */
1043 if (!dev->multifunction) {
1044 if (func > 0) {
1045 dev->multifunction = 1;
1046 } else {
1047 break;
1048 }
1049 }
1050 } else {
1051 if (func == 0 && !scan_all_fns)
1052 break;
1053 }
1054 }
1055
1056 if (bus->self)
1057 pcie_aspm_init_link_state(bus->self);
1058
1059 return nr;
1060 }
1061
1062 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1063 {
1064 unsigned int devfn, pass, max = bus->secondary;
1065 struct pci_dev *dev;
1066
1067 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1068
1069 /* Go find them, Rover! */
1070 for (devfn = 0; devfn < 0x100; devfn += 8)
1071 pci_scan_slot(bus, devfn);
1072
1073 /*
1074 * After performing arch-dependent fixup of the bus, look behind
1075 * all PCI-to-PCI bridges on this bus.
1076 */
1077 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1078 pcibios_fixup_bus(bus);
1079 for (pass=0; pass < 2; pass++)
1080 list_for_each_entry(dev, &bus->devices, bus_list) {
1081 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1082 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1083 max = pci_scan_bridge(bus, dev, max, pass);
1084 }
1085
1086 /*
1087 * We've scanned the bus and so we know all about what's on
1088 * the other side of any bridges that may be on this bus plus
1089 * any devices.
1090 *
1091 * Return how far we've got finding sub-buses.
1092 */
1093 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1094 pci_domain_nr(bus), bus->number, max);
1095 return max;
1096 }
1097
1098 void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
1099 {
1100 }
1101
1102 struct pci_bus * pci_create_bus(struct device *parent,
1103 int bus, struct pci_ops *ops, void *sysdata)
1104 {
1105 int error;
1106 struct pci_bus *b;
1107 struct device *dev;
1108
1109 b = pci_alloc_bus();
1110 if (!b)
1111 return NULL;
1112
1113 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1114 if (!dev){
1115 kfree(b);
1116 return NULL;
1117 }
1118
1119 b->sysdata = sysdata;
1120 b->ops = ops;
1121
1122 if (pci_find_bus(pci_domain_nr(b), bus)) {
1123 /* If we already got to this bus through a different bridge, ignore it */
1124 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1125 goto err_out;
1126 }
1127
1128 down_write(&pci_bus_sem);
1129 list_add_tail(&b->node, &pci_root_buses);
1130 up_write(&pci_bus_sem);
1131
1132 memset(dev, 0, sizeof(*dev));
1133 dev->parent = parent;
1134 dev->release = pci_release_bus_bridge_dev;
1135 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1136 error = device_register(dev);
1137 if (error)
1138 goto dev_reg_err;
1139 b->bridge = get_device(dev);
1140
1141 if (!parent)
1142 set_dev_node(b->bridge, pcibus_to_node(b));
1143
1144 b->dev.class = &pcibus_class;
1145 b->dev.parent = b->bridge;
1146 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1147 error = device_register(&b->dev);
1148 if (error)
1149 goto class_dev_reg_err;
1150 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1151 if (error)
1152 goto dev_create_file_err;
1153
1154 /* Create legacy_io and legacy_mem files for this bus */
1155 pci_create_legacy_files(b);
1156
1157 b->number = b->secondary = bus;
1158 b->resource[0] = &ioport_resource;
1159 b->resource[1] = &iomem_resource;
1160
1161 set_pci_bus_resources_arch_default(b);
1162
1163 return b;
1164
1165 dev_create_file_err:
1166 device_unregister(&b->dev);
1167 class_dev_reg_err:
1168 device_unregister(dev);
1169 dev_reg_err:
1170 down_write(&pci_bus_sem);
1171 list_del(&b->node);
1172 up_write(&pci_bus_sem);
1173 err_out:
1174 kfree(dev);
1175 kfree(b);
1176 return NULL;
1177 }
1178
1179 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1180 int bus, struct pci_ops *ops, void *sysdata)
1181 {
1182 struct pci_bus *b;
1183
1184 b = pci_create_bus(parent, bus, ops, sysdata);
1185 if (b)
1186 b->subordinate = pci_scan_child_bus(b);
1187 return b;
1188 }
1189 EXPORT_SYMBOL(pci_scan_bus_parented);
1190
1191 #ifdef CONFIG_HOTPLUG
1192 EXPORT_SYMBOL(pci_add_new_bus);
1193 EXPORT_SYMBOL(pci_scan_slot);
1194 EXPORT_SYMBOL(pci_scan_bridge);
1195 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1196 #endif
1197
1198 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1199 {
1200 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1201 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1202
1203 if (a->bus->number < b->bus->number) return -1;
1204 else if (a->bus->number > b->bus->number) return 1;
1205
1206 if (a->devfn < b->devfn) return -1;
1207 else if (a->devfn > b->devfn) return 1;
1208
1209 return 0;
1210 }
1211
1212 /*
1213 * Yes, this forcably breaks the klist abstraction temporarily. It
1214 * just wants to sort the klist, not change reference counts and
1215 * take/drop locks rapidly in the process. It does all this while
1216 * holding the lock for the list, so objects can't otherwise be
1217 * added/removed while we're swizzling.
1218 */
1219 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1220 {
1221 struct list_head *pos;
1222 struct klist_node *n;
1223 struct device *dev;
1224 struct pci_dev *b;
1225
1226 list_for_each(pos, list) {
1227 n = container_of(pos, struct klist_node, n_node);
1228 dev = container_of(n, struct device, knode_bus);
1229 b = to_pci_dev(dev);
1230 if (pci_sort_bf_cmp(a, b) <= 0) {
1231 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1232 return;
1233 }
1234 }
1235 list_move_tail(&a->dev.knode_bus.n_node, list);
1236 }
1237
1238 void __init pci_sort_breadthfirst(void)
1239 {
1240 LIST_HEAD(sorted_devices);
1241 struct list_head *pos, *tmp;
1242 struct klist_node *n;
1243 struct device *dev;
1244 struct pci_dev *pdev;
1245 struct klist *device_klist;
1246
1247 device_klist = bus_get_device_klist(&pci_bus_type);
1248
1249 spin_lock(&device_klist->k_lock);
1250 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1251 n = container_of(pos, struct klist_node, n_node);
1252 dev = container_of(n, struct device, knode_bus);
1253 pdev = to_pci_dev(dev);
1254 pci_insertion_sort_klist(pdev, &sorted_devices);
1255 }
1256 list_splice(&sorted_devices, &device_klist->k_list);
1257 spin_unlock(&device_klist->k_lock);
1258 }
SocketAccessConTroL development