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mac80211: move TX info into skb->cb
[linux-2.6/sactl.git] / drivers / net / wireless / rtl8187_dev.c
blobb581ef8a63773191e8480b4e5a81aaa203fff066
1 /*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
10 * Magic delays and register offsets below are taken from the original
11 * r8187 driver sources. Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/usb.h>
20 #include <linux/delay.h>
21 #include <linux/etherdevice.h>
22 #include <linux/eeprom_93cx6.h>
23 #include <net/mac80211.h>
24
25 #include "rtl8187.h"
26 #include "rtl8187_rtl8225.h"
27
28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
30 MODULE_DESCRIPTION("RTL8187 USB wireless driver");
31 MODULE_LICENSE("GPL");
32
33 static struct usb_device_id rtl8187_table[] __devinitdata = {
34 /* Realtek */
35 {USB_DEVICE(0x0bda, 0x8187)},
36 /* Netgear */
37 {USB_DEVICE(0x0846, 0x6100)},
38 {USB_DEVICE(0x0846, 0x6a00)},
39 /* HP */
40 {USB_DEVICE(0x03f0, 0xca02)},
41 /* Sitecom */
42 {USB_DEVICE(0x0df6, 0x000d)},
43 {}
44 };
45
46 MODULE_DEVICE_TABLE(usb, rtl8187_table);
47
48 static const struct ieee80211_rate rtl818x_rates[] = {
49 { .bitrate = 10, .hw_value = 0, },
50 { .bitrate = 20, .hw_value = 1, },
51 { .bitrate = 55, .hw_value = 2, },
52 { .bitrate = 110, .hw_value = 3, },
53 { .bitrate = 60, .hw_value = 4, },
54 { .bitrate = 90, .hw_value = 5, },
55 { .bitrate = 120, .hw_value = 6, },
56 { .bitrate = 180, .hw_value = 7, },
57 { .bitrate = 240, .hw_value = 8, },
58 { .bitrate = 360, .hw_value = 9, },
59 { .bitrate = 480, .hw_value = 10, },
60 { .bitrate = 540, .hw_value = 11, },
61 };
62
63 static const struct ieee80211_channel rtl818x_channels[] = {
64 { .center_freq = 2412 },
65 { .center_freq = 2417 },
66 { .center_freq = 2422 },
67 { .center_freq = 2427 },
68 { .center_freq = 2432 },
69 { .center_freq = 2437 },
70 { .center_freq = 2442 },
71 { .center_freq = 2447 },
72 { .center_freq = 2452 },
73 { .center_freq = 2457 },
74 { .center_freq = 2462 },
75 { .center_freq = 2467 },
76 { .center_freq = 2472 },
77 { .center_freq = 2484 },
78 };
79
80 static void rtl8187_iowrite_async_cb(struct urb *urb)
81 {
82 kfree(urb->context);
83 usb_free_urb(urb);
84 }
85
86 static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
87 void *data, u16 len)
88 {
89 struct usb_ctrlrequest *dr;
90 struct urb *urb;
91 struct rtl8187_async_write_data {
92 u8 data[4];
93 struct usb_ctrlrequest dr;
94 } *buf;
95
96 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
97 if (!buf)
98 return;
99
100 urb = usb_alloc_urb(0, GFP_ATOMIC);
101 if (!urb) {
102 kfree(buf);
103 return;
104 }
105
106 dr = &buf->dr;
107
108 dr->bRequestType = RTL8187_REQT_WRITE;
109 dr->bRequest = RTL8187_REQ_SET_REG;
110 dr->wValue = addr;
111 dr->wIndex = 0;
112 dr->wLength = cpu_to_le16(len);
113
114 memcpy(buf, data, len);
115
116 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
117 (unsigned char *)dr, buf, len,
118 rtl8187_iowrite_async_cb, buf);
119 usb_submit_urb(urb, GFP_ATOMIC);
120 }
121
122 static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
123 __le32 *addr, u32 val)
124 {
125 __le32 buf = cpu_to_le32(val);
126
127 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
128 &buf, sizeof(buf));
129 }
130
131 void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
132 {
133 struct rtl8187_priv *priv = dev->priv;
134
135 data <<= 8;
136 data |= addr | 0x80;
137
138 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
139 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
140 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
141 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
142
143 msleep(1);
144 }
145
146 static void rtl8187_tx_cb(struct urb *urb)
147 {
148 struct sk_buff *skb = (struct sk_buff *)urb->context;
149 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
150 struct ieee80211_hw *hw = info->driver_data[0];
151
152 usb_free_urb(info->driver_data[1]);
153 skb_pull(skb, sizeof(struct rtl8187_tx_hdr));
154 memset(&info->status, 0, sizeof(info->status));
155 info->flags |= IEEE80211_TX_STAT_ACK;
156 ieee80211_tx_status_irqsafe(hw, skb);
157 }
158
159 static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
160 {
161 struct rtl8187_priv *priv = dev->priv;
162 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
163 struct rtl8187_tx_hdr *hdr;
164 struct urb *urb;
165 __le16 rts_dur = 0;
166 u32 flags;
167
168 urb = usb_alloc_urb(0, GFP_ATOMIC);
169 if (!urb) {
170 kfree_skb(skb);
171 return 0;
172 }
173
174 flags = skb->len;
175 flags |= RTL8187_TX_FLAG_NO_ENCRYPT;
176
177 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
178 if (ieee80211_get_morefrag((struct ieee80211_hdr *)skb->data))
179 flags |= RTL8187_TX_FLAG_MORE_FRAG;
180 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
181 flags |= RTL8187_TX_FLAG_RTS;
182 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
183 rts_dur = ieee80211_rts_duration(dev, priv->vif,
184 skb->len, info);
185 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
186 flags |= RTL8187_TX_FLAG_CTS;
187 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
188 }
189
190 hdr = (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
191 hdr->flags = cpu_to_le32(flags);
192 hdr->len = 0;
193 hdr->rts_duration = rts_dur;
194 hdr->retry = cpu_to_le32(info->control.retry_limit << 8);
195
196 info->driver_data[0] = dev;
197 info->driver_data[1] = urb;
198 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, 2),
199 hdr, skb->len, rtl8187_tx_cb, skb);
200 usb_submit_urb(urb, GFP_ATOMIC);
201
202 return 0;
203 }
204
205 static void rtl8187_rx_cb(struct urb *urb)
206 {
207 struct sk_buff *skb = (struct sk_buff *)urb->context;
208 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
209 struct ieee80211_hw *dev = info->dev;
210 struct rtl8187_priv *priv = dev->priv;
211 struct rtl8187_rx_hdr *hdr;
212 struct ieee80211_rx_status rx_status = { 0 };
213 int rate, signal;
214 u32 flags;
215
216 spin_lock(&priv->rx_queue.lock);
217 if (skb->next)
218 __skb_unlink(skb, &priv->rx_queue);
219 else {
220 spin_unlock(&priv->rx_queue.lock);
221 return;
222 }
223 spin_unlock(&priv->rx_queue.lock);
224
225 if (unlikely(urb->status)) {
226 usb_free_urb(urb);
227 dev_kfree_skb_irq(skb);
228 return;
229 }
230
231 skb_put(skb, urb->actual_length);
232 hdr = (struct rtl8187_rx_hdr *)(skb_tail_pointer(skb) - sizeof(*hdr));
233 flags = le32_to_cpu(hdr->flags);
234 skb_trim(skb, flags & 0x0FFF);
235
236 signal = hdr->agc >> 1;
237 rate = (flags >> 20) & 0xF;
238 if (rate > 3) { /* OFDM rate */
239 if (signal > 90)
240 signal = 90;
241 else if (signal < 25)
242 signal = 25;
243 signal = 90 - signal;
244 } else { /* CCK rate */
245 if (signal > 95)
246 signal = 95;
247 else if (signal < 30)
248 signal = 30;
249 signal = 95 - signal;
250 }
251
252 rx_status.antenna = (hdr->signal >> 7) & 1;
253 rx_status.qual = 64 - min(hdr->noise, (u8)64);
254 rx_status.signal = signal;
255 rx_status.rate_idx = rate;
256 rx_status.freq = dev->conf.channel->center_freq;
257 rx_status.band = dev->conf.channel->band;
258 rx_status.mactime = le64_to_cpu(hdr->mac_time);
259 rx_status.flag |= RX_FLAG_TSFT;
260 if (flags & (1 << 13))
261 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
262 ieee80211_rx_irqsafe(dev, skb, &rx_status);
263
264 skb = dev_alloc_skb(RTL8187_MAX_RX);
265 if (unlikely(!skb)) {
266 usb_free_urb(urb);
267 /* TODO check rx queue length and refill *somewhere* */
268 return;
269 }
270
271 info = (struct rtl8187_rx_info *)skb->cb;
272 info->urb = urb;
273 info->dev = dev;
274 urb->transfer_buffer = skb_tail_pointer(skb);
275 urb->context = skb;
276 skb_queue_tail(&priv->rx_queue, skb);
277
278 usb_submit_urb(urb, GFP_ATOMIC);
279 }
280
281 static int rtl8187_init_urbs(struct ieee80211_hw *dev)
282 {
283 struct rtl8187_priv *priv = dev->priv;
284 struct urb *entry;
285 struct sk_buff *skb;
286 struct rtl8187_rx_info *info;
287
288 while (skb_queue_len(&priv->rx_queue) < 8) {
289 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
290 if (!skb)
291 break;
292 entry = usb_alloc_urb(0, GFP_KERNEL);
293 if (!entry) {
294 kfree_skb(skb);
295 break;
296 }
297 usb_fill_bulk_urb(entry, priv->udev,
298 usb_rcvbulkpipe(priv->udev, 1),
299 skb_tail_pointer(skb),
300 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
301 info = (struct rtl8187_rx_info *)skb->cb;
302 info->urb = entry;
303 info->dev = dev;
304 skb_queue_tail(&priv->rx_queue, skb);
305 usb_submit_urb(entry, GFP_KERNEL);
306 }
307
308 return 0;
309 }
310
311 static int rtl8187_init_hw(struct ieee80211_hw *dev)
312 {
313 struct rtl8187_priv *priv = dev->priv;
314 u8 reg;
315 int i;
316
317 /* reset */
318 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
319 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
320 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
321 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON);
322 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
323 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
324 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
325
326 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
327
328 msleep(200);
329 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
330 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
331 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
332 msleep(200);
333
334 reg = rtl818x_ioread8(priv, &priv->map->CMD);
335 reg &= (1 << 1);
336 reg |= RTL818X_CMD_RESET;
337 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
338
339 i = 10;
340 do {
341 msleep(2);
342 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
343 RTL818X_CMD_RESET))
344 break;
345 } while (--i);
346
347 if (!i) {
348 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
349 return -ETIMEDOUT;
350 }
351
352 /* reload registers from eeprom */
353 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
354
355 i = 10;
356 do {
357 msleep(4);
358 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
359 RTL818X_EEPROM_CMD_CONFIG))
360 break;
361 } while (--i);
362
363 if (!i) {
364 printk(KERN_ERR "%s: eeprom reset timeout!\n",
365 wiphy_name(dev->wiphy));
366 return -ETIMEDOUT;
367 }
368
369 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
370 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
371 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
372 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON);
373 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
374 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
375 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
376
377 /* setup card */
378 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
379 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
380
381 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
382 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
383 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
384
385 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
386
387 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
388 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
389 reg &= 0x3F;
390 reg |= 0x80;
391 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
392
393 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
394
395 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
396 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
397 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
398
399 // TODO: set RESP_RATE and BRSR properly
400 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
401 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
402
403 /* host_usb_init */
404 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
405 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
406 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
407 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
408 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
409 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
410 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
411 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
412 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
413 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
414 msleep(100);
415
416 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
417 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
418 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
419 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
420 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
421 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
422 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
423 msleep(100);
424
425 priv->rf->init(dev);
426
427 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
428 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
429 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
430 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
431 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
432 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
433 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
434
435 return 0;
436 }
437
438 static int rtl8187_start(struct ieee80211_hw *dev)
439 {
440 struct rtl8187_priv *priv = dev->priv;
441 u32 reg;
442 int ret;
443
444 ret = rtl8187_init_hw(dev);
445 if (ret)
446 return ret;
447
448 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
449
450 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
451 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
452
453 rtl8187_init_urbs(dev);
454
455 reg = RTL818X_RX_CONF_ONLYERLPKT |
456 RTL818X_RX_CONF_RX_AUTORESETPHY |
457 RTL818X_RX_CONF_BSSID |
458 RTL818X_RX_CONF_MGMT |
459 RTL818X_RX_CONF_DATA |
460 (7 << 13 /* RX FIFO threshold NONE */) |
461 (7 << 10 /* MAX RX DMA */) |
462 RTL818X_RX_CONF_BROADCAST |
463 RTL818X_RX_CONF_NICMAC;
464
465 priv->rx_conf = reg;
466 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
467
468 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
469 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
470 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
471 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
472
473 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
474 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
475 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
476 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
477 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
478
479 reg = RTL818X_TX_CONF_CW_MIN |
480 (7 << 21 /* MAX TX DMA */) |
481 RTL818X_TX_CONF_NO_ICV;
482 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
483
484 reg = rtl818x_ioread8(priv, &priv->map->CMD);
485 reg |= RTL818X_CMD_TX_ENABLE;
486 reg |= RTL818X_CMD_RX_ENABLE;
487 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
488
489 return 0;
490 }
491
492 static void rtl8187_stop(struct ieee80211_hw *dev)
493 {
494 struct rtl8187_priv *priv = dev->priv;
495 struct rtl8187_rx_info *info;
496 struct sk_buff *skb;
497 u32 reg;
498
499 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
500
501 reg = rtl818x_ioread8(priv, &priv->map->CMD);
502 reg &= ~RTL818X_CMD_TX_ENABLE;
503 reg &= ~RTL818X_CMD_RX_ENABLE;
504 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
505
506 priv->rf->stop(dev);
507
508 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
509 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
510 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
511 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
512
513 while ((skb = skb_dequeue(&priv->rx_queue))) {
514 info = (struct rtl8187_rx_info *)skb->cb;
515 usb_kill_urb(info->urb);
516 kfree_skb(skb);
517 }
518 return;
519 }
520
521 static int rtl8187_add_interface(struct ieee80211_hw *dev,
522 struct ieee80211_if_init_conf *conf)
523 {
524 struct rtl8187_priv *priv = dev->priv;
525 int i;
526
527 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
528 return -EOPNOTSUPP;
529
530 switch (conf->type) {
531 case IEEE80211_IF_TYPE_STA:
532 priv->mode = conf->type;
533 break;
534 default:
535 return -EOPNOTSUPP;
536 }
537
538 priv->vif = conf->vif;
539
540 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
541 for (i = 0; i < ETH_ALEN; i++)
542 rtl818x_iowrite8(priv, &priv->map->MAC[i],
543 ((u8 *)conf->mac_addr)[i]);
544 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
545
546 return 0;
547 }
548
549 static void rtl8187_remove_interface(struct ieee80211_hw *dev,
550 struct ieee80211_if_init_conf *conf)
551 {
552 struct rtl8187_priv *priv = dev->priv;
553 priv->mode = IEEE80211_IF_TYPE_MNTR;
554 priv->vif = NULL;
555 }
556
557 static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
558 {
559 struct rtl8187_priv *priv = dev->priv;
560 u32 reg;
561
562 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
563 /* Enable TX loopback on MAC level to avoid TX during channel
564 * changes, as this has be seen to causes problems and the
565 * card will stop work until next reset
566 */
567 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
568 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
569 msleep(10);
570 priv->rf->set_chan(dev, conf);
571 msleep(10);
572 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
573
574 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
575
576 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
577 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
578 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
579 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
580 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73);
581 } else {
582 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
583 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
584 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
585 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5);
586 }
587
588 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
589 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
590 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
591 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
592 return 0;
593 }
594
595 static int rtl8187_config_interface(struct ieee80211_hw *dev,
596 struct ieee80211_vif *vif,
597 struct ieee80211_if_conf *conf)
598 {
599 struct rtl8187_priv *priv = dev->priv;
600 int i;
601
602 for (i = 0; i < ETH_ALEN; i++)
603 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
604
605 if (is_valid_ether_addr(conf->bssid))
606 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_INFRA);
607 else
608 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_NO_LINK);
609
610 return 0;
611 }
612
613 static void rtl8187_configure_filter(struct ieee80211_hw *dev,
614 unsigned int changed_flags,
615 unsigned int *total_flags,
616 int mc_count, struct dev_addr_list *mclist)
617 {
618 struct rtl8187_priv *priv = dev->priv;
619
620 if (changed_flags & FIF_FCSFAIL)
621 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
622 if (changed_flags & FIF_CONTROL)
623 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
624 if (changed_flags & FIF_OTHER_BSS)
625 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
626 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
627 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
628 else
629 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
630
631 *total_flags = 0;
632
633 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
634 *total_flags |= FIF_FCSFAIL;
635 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
636 *total_flags |= FIF_CONTROL;
637 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
638 *total_flags |= FIF_OTHER_BSS;
639 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
640 *total_flags |= FIF_ALLMULTI;
641
642 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
643 }
644
645 static const struct ieee80211_ops rtl8187_ops = {
646 .tx = rtl8187_tx,
647 .start = rtl8187_start,
648 .stop = rtl8187_stop,
649 .add_interface = rtl8187_add_interface,
650 .remove_interface = rtl8187_remove_interface,
651 .config = rtl8187_config,
652 .config_interface = rtl8187_config_interface,
653 .configure_filter = rtl8187_configure_filter,
654 };
655
656 static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
657 {
658 struct ieee80211_hw *dev = eeprom->data;
659 struct rtl8187_priv *priv = dev->priv;
660 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
661
662 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
663 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
664 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
665 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
666 }
667
668 static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
669 {
670 struct ieee80211_hw *dev = eeprom->data;
671 struct rtl8187_priv *priv = dev->priv;
672 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
673
674 if (eeprom->reg_data_in)
675 reg |= RTL818X_EEPROM_CMD_WRITE;
676 if (eeprom->reg_data_out)
677 reg |= RTL818X_EEPROM_CMD_READ;
678 if (eeprom->reg_data_clock)
679 reg |= RTL818X_EEPROM_CMD_CK;
680 if (eeprom->reg_chip_select)
681 reg |= RTL818X_EEPROM_CMD_CS;
682
683 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
684 udelay(10);
685 }
686
687 static int __devinit rtl8187_probe(struct usb_interface *intf,
688 const struct usb_device_id *id)
689 {
690 struct usb_device *udev = interface_to_usbdev(intf);
691 struct ieee80211_hw *dev;
692 struct rtl8187_priv *priv;
693 struct eeprom_93cx6 eeprom;
694 struct ieee80211_channel *channel;
695 u16 txpwr, reg;
696 int err, i;
697 DECLARE_MAC_BUF(mac);
698
699 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
700 if (!dev) {
701 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
702 return -ENOMEM;
703 }
704
705 priv = dev->priv;
706
707 SET_IEEE80211_DEV(dev, &intf->dev);
708 usb_set_intfdata(intf, dev);
709 priv->udev = udev;
710
711 usb_get_dev(udev);
712
713 skb_queue_head_init(&priv->rx_queue);
714
715 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
716 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
717
718 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
719 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
720 priv->map = (struct rtl818x_csr *)0xFF00;
721
722 priv->band.band = IEEE80211_BAND_2GHZ;
723 priv->band.channels = priv->channels;
724 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
725 priv->band.bitrates = priv->rates;
726 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
727 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
728
729
730 priv->mode = IEEE80211_IF_TYPE_MNTR;
731 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
732 IEEE80211_HW_RX_INCLUDES_FCS |
733 IEEE80211_HW_SIGNAL_UNSPEC;
734 dev->extra_tx_headroom = sizeof(struct rtl8187_tx_hdr);
735 dev->queues = 1;
736 dev->max_signal = 65;
737
738 eeprom.data = dev;
739 eeprom.register_read = rtl8187_eeprom_register_read;
740 eeprom.register_write = rtl8187_eeprom_register_write;
741 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
742 eeprom.width = PCI_EEPROM_WIDTH_93C66;
743 else
744 eeprom.width = PCI_EEPROM_WIDTH_93C46;
745
746 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
747 udelay(10);
748
749 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
750 (__le16 __force *)dev->wiphy->perm_addr, 3);
751 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
752 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
753 "generated MAC address\n");
754 random_ether_addr(dev->wiphy->perm_addr);
755 }
756
757 channel = priv->channels;
758 for (i = 0; i < 3; i++) {
759 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
760 &txpwr);
761 (*channel++).hw_value = txpwr & 0xFF;
762 (*channel++).hw_value = txpwr >> 8;
763 }
764 for (i = 0; i < 2; i++) {
765 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
766 &txpwr);
767 (*channel++).hw_value = txpwr & 0xFF;
768 (*channel++).hw_value = txpwr >> 8;
769 }
770 for (i = 0; i < 2; i++) {
771 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6 + i,
772 &txpwr);
773 (*channel++).hw_value = txpwr & 0xFF;
774 (*channel++).hw_value = txpwr >> 8;
775 }
776
777 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
778 &priv->txpwr_base);
779
780 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
781 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
782 /* 0 means asic B-cut, we should use SW 3 wire
783 * bit-by-bit banging for radio. 1 means we can use
784 * USB specific request to write radio registers */
785 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
786 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
787 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
788
789 priv->rf = rtl8187_detect_rf(dev);
790
791 err = ieee80211_register_hw(dev);
792 if (err) {
793 printk(KERN_ERR "rtl8187: Cannot register device\n");
794 goto err_free_dev;
795 }
796
797 printk(KERN_INFO "%s: hwaddr %s, rtl8187 V%d + %s\n",
798 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
799 priv->asic_rev, priv->rf->name);
800
801 return 0;
802
803 err_free_dev:
804 ieee80211_free_hw(dev);
805 usb_set_intfdata(intf, NULL);
806 usb_put_dev(udev);
807 return err;
808 }
809
810 static void __devexit rtl8187_disconnect(struct usb_interface *intf)
811 {
812 struct ieee80211_hw *dev = usb_get_intfdata(intf);
813 struct rtl8187_priv *priv;
814
815 if (!dev)
816 return;
817
818 ieee80211_unregister_hw(dev);
819
820 priv = dev->priv;
821 usb_put_dev(interface_to_usbdev(intf));
822 ieee80211_free_hw(dev);
823 }
824
825 static struct usb_driver rtl8187_driver = {
826 .name = KBUILD_MODNAME,
827 .id_table = rtl8187_table,
828 .probe = rtl8187_probe,
829 .disconnect = rtl8187_disconnect,
830 };
831
832 static int __init rtl8187_init(void)
833 {
834 return usb_register(&rtl8187_driver);
835 }
836
837 static void __exit rtl8187_exit(void)
838 {
839 usb_deregister(&rtl8187_driver);
840 }
841
842 module_init(rtl8187_init);
843 module_exit(rtl8187_exit);
SocketAccessConTroL development