2 * arch/sh/kernel/cpu/clock.c - SuperH clock framework
4 * Copyright (C) 2005, 2006, 2007 Paul Mundt
6 * This clock framework is derived from the OMAP version by:
8 * Copyright (C) 2004 - 2005 Nokia Corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/list.h>
22 #include <linux/kref.h>
23 #include <linux/seq_file.h>
24 #include <linux/err.h>
25 #include <linux/platform_device.h>
26 #include <linux/proc_fs.h>
27 #include <asm/clock.h>
28 #include <asm/timer.h>
30 static LIST_HEAD(clock_list
);
31 static DEFINE_SPINLOCK(clock_lock
);
32 static DEFINE_MUTEX(clock_list_sem
);
35 * Each subtype is expected to define the init routines for these clocks,
36 * as each subtype (or processor family) will have these clocks at the
37 * very least. These are all provided through the CPG, which even some of
38 * the more quirky parts (such as ST40, SH4-202, etc.) still have.
40 * The processor-specific code is expected to register any additional
41 * clock sources that are of interest.
43 static struct clk master_clk
= {
45 .flags
= CLK_ALWAYS_ENABLED
| CLK_RATE_PROPAGATES
,
46 .rate
= CONFIG_SH_PCLK_FREQ
,
49 static struct clk module_clk
= {
51 .parent
= &master_clk
,
52 .flags
= CLK_ALWAYS_ENABLED
| CLK_RATE_PROPAGATES
,
55 static struct clk bus_clk
= {
57 .parent
= &master_clk
,
58 .flags
= CLK_ALWAYS_ENABLED
| CLK_RATE_PROPAGATES
,
61 static struct clk cpu_clk
= {
63 .parent
= &master_clk
,
64 .flags
= CLK_ALWAYS_ENABLED
,
68 * The ordering of these clocks matters, do not change it.
70 static struct clk
*onchip_clocks
[] = {
77 static void propagate_rate(struct clk
*clk
)
81 list_for_each_entry(clkp
, &clock_list
, node
) {
82 if (likely(clkp
->parent
!= clk
))
84 if (likely(clkp
->ops
&& clkp
->ops
->recalc
))
85 clkp
->ops
->recalc(clkp
);
89 int __clk_enable(struct clk
*clk
)
92 * See if this is the first time we're enabling the clock, some
93 * clocks that are always enabled still require "special"
94 * initialization. This is especially true if the clock mode
95 * changes and the clock needs to hunt for the proper set of
96 * divisors to use before it can effectively recalc.
98 if (unlikely(atomic_read(&clk
->kref
.refcount
) == 1))
99 if (clk
->ops
&& clk
->ops
->init
)
102 kref_get(&clk
->kref
);
104 if (clk
->flags
& CLK_ALWAYS_ENABLED
)
107 if (likely(clk
->ops
&& clk
->ops
->enable
))
108 clk
->ops
->enable(clk
);
112 EXPORT_SYMBOL_GPL(__clk_enable
);
114 int clk_enable(struct clk
*clk
)
119 spin_lock_irqsave(&clock_lock
, flags
);
120 ret
= __clk_enable(clk
);
121 spin_unlock_irqrestore(&clock_lock
, flags
);
125 EXPORT_SYMBOL_GPL(clk_enable
);
127 static void clk_kref_release(struct kref
*kref
)
132 void __clk_disable(struct clk
*clk
)
134 int count
= kref_put(&clk
->kref
, clk_kref_release
);
136 if (clk
->flags
& CLK_ALWAYS_ENABLED
)
139 if (!count
) { /* count reaches zero, disable the clock */
140 if (likely(clk
->ops
&& clk
->ops
->disable
))
141 clk
->ops
->disable(clk
);
144 EXPORT_SYMBOL_GPL(__clk_disable
);
146 void clk_disable(struct clk
*clk
)
150 spin_lock_irqsave(&clock_lock
, flags
);
152 spin_unlock_irqrestore(&clock_lock
, flags
);
154 EXPORT_SYMBOL_GPL(clk_disable
);
156 int clk_register(struct clk
*clk
)
158 mutex_lock(&clock_list_sem
);
160 list_add(&clk
->node
, &clock_list
);
161 kref_init(&clk
->kref
);
163 mutex_unlock(&clock_list_sem
);
165 if (clk
->flags
& CLK_ALWAYS_ENABLED
) {
166 pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk
->name
);
167 if (clk
->ops
&& clk
->ops
->init
)
169 if (clk
->ops
&& clk
->ops
->enable
)
170 clk
->ops
->enable(clk
);
171 pr_debug( "Enabled.");
176 EXPORT_SYMBOL_GPL(clk_register
);
178 void clk_unregister(struct clk
*clk
)
180 mutex_lock(&clock_list_sem
);
181 list_del(&clk
->node
);
182 mutex_unlock(&clock_list_sem
);
184 EXPORT_SYMBOL_GPL(clk_unregister
);
186 unsigned long clk_get_rate(struct clk
*clk
)
190 EXPORT_SYMBOL_GPL(clk_get_rate
);
192 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
194 return clk_set_rate_ex(clk
, rate
, 0);
196 EXPORT_SYMBOL_GPL(clk_set_rate
);
198 int clk_set_rate_ex(struct clk
*clk
, unsigned long rate
, int algo_id
)
200 int ret
= -EOPNOTSUPP
;
202 if (likely(clk
->ops
&& clk
->ops
->set_rate
)) {
205 spin_lock_irqsave(&clock_lock
, flags
);
206 ret
= clk
->ops
->set_rate(clk
, rate
, algo_id
);
207 spin_unlock_irqrestore(&clock_lock
, flags
);
210 if (unlikely(clk
->flags
& CLK_RATE_PROPAGATES
))
215 EXPORT_SYMBOL_GPL(clk_set_rate_ex
);
217 void clk_recalc_rate(struct clk
*clk
)
219 if (likely(clk
->ops
&& clk
->ops
->recalc
)) {
222 spin_lock_irqsave(&clock_lock
, flags
);
223 clk
->ops
->recalc(clk
);
224 spin_unlock_irqrestore(&clock_lock
, flags
);
227 if (unlikely(clk
->flags
& CLK_RATE_PROPAGATES
))
230 EXPORT_SYMBOL_GPL(clk_recalc_rate
);
233 * Returns a clock. Note that we first try to use device id on the bus
234 * and clock name. If this fails, we try to use clock name only.
236 struct clk
*clk_get(struct device
*dev
, const char *id
)
238 struct clk
*p
, *clk
= ERR_PTR(-ENOENT
);
241 if (dev
== NULL
|| dev
->bus
!= &platform_bus_type
)
244 idno
= to_platform_device(dev
)->id
;
246 mutex_lock(&clock_list_sem
);
247 list_for_each_entry(p
, &clock_list
, node
) {
249 strcmp(id
, p
->name
) == 0 && try_module_get(p
->owner
)) {
255 list_for_each_entry(p
, &clock_list
, node
) {
256 if (strcmp(id
, p
->name
) == 0 && try_module_get(p
->owner
)) {
263 mutex_unlock(&clock_list_sem
);
267 EXPORT_SYMBOL_GPL(clk_get
);
269 void clk_put(struct clk
*clk
)
271 if (clk
&& !IS_ERR(clk
))
272 module_put(clk
->owner
);
274 EXPORT_SYMBOL_GPL(clk_put
);
276 void __init
__attribute__ ((weak
))
277 arch_init_clk_ops(struct clk_ops
**ops
, int type
)
281 void __init
__attribute__ ((weak
))
286 static int show_clocks(char *buf
, char **start
, off_t off
,
287 int len
, int *eof
, void *data
)
292 list_for_each_entry_reverse(clk
, &clock_list
, node
) {
293 unsigned long rate
= clk_get_rate(clk
);
296 * Don't bother listing dummy clocks with no ancestry
297 * that only support enable and disable ops.
299 if (unlikely(!rate
&& !clk
->parent
))
302 p
+= sprintf(p
, "%-12s\t: %ld.%02ldMHz\n", clk
->name
,
303 rate
/ 1000000, (rate
% 1000000) / 10000);
309 int __init
clk_init(void)
313 BUG_ON(!master_clk
.rate
);
315 for (i
= 0; i
< ARRAY_SIZE(onchip_clocks
); i
++) {
316 struct clk
*clk
= onchip_clocks
[i
];
318 arch_init_clk_ops(&clk
->ops
, i
);
319 ret
|= clk_register(clk
);
324 /* Kick the child clocks.. */
325 propagate_rate(&master_clk
);
326 propagate_rate(&bus_clk
);
331 static int __init
clk_proc_init(void)
333 struct proc_dir_entry
*p
;
334 p
= create_proc_read_entry("clocks", S_IRUSR
, NULL
,
341 subsys_initcall(clk_proc_init
);