drivers/net/igb/e1000_defines.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_DEFINES_H_
  29 #define _E1000_DEFINES_H_
  30
  31 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
  32 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
  33 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
  34
  35 /* Definitions for power management and wakeup registers */
  36 /* Wake Up Control */
  37 #define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
  38
  39 /* Wake Up Filter Control */
  40 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  41 #define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  42 #define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  43 #define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
  44 #define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  45 #define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
  46 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
  47 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
  48 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
  49 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
  50 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
  51 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
  52 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
  53
  54 /* Wake Up Status */
  55
  56 /* Wake Up Packet Length */
  57
  58 /* Four Flexible Filters are supported */
  59 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
  60
  61 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
  62 #define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
  63
  64
  65 /* Extended Device Control */
  66 #define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
  67 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
  68 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
  69 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
  70 #define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
  71 #define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
  72 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
  73 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
  74 #define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
  75 #define E1000_CTRL_EXT_EIAME          0x01000000
  76 #define E1000_CTRL_EXT_IRCA           0x00000001
  77 /* Interrupt delay cancellation */
  78 /* Driver loaded bit for FW */
  79 #define E1000_CTRL_EXT_DRV_LOAD       0x10000000
  80 /* Interrupt acknowledge Auto-mask */
  81 /* Clear Interrupt timers after IMS clear */
  82 /* packet buffer parity error detection enabled */
  83 /* descriptor FIFO parity error detection enable */
  84 #define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
  85 #define E1000_I2CCMD_REG_ADDR_SHIFT   16
  86 #define E1000_I2CCMD_PHY_ADDR_SHIFT   24
  87 #define E1000_I2CCMD_OPCODE_READ      0x08000000
  88 #define E1000_I2CCMD_OPCODE_WRITE     0x00000000
  89 #define E1000_I2CCMD_READY            0x20000000
  90 #define E1000_I2CCMD_ERROR            0x80000000
  91 #define E1000_MAX_SGMII_PHY_REG_ADDR  255
  92 #define E1000_I2CCMD_PHY_TIMEOUT      200
  93 #define E1000_IVAR_VALID              0x80
  94 #define E1000_GPIE_NSICR              0x00000001
  95 #define E1000_GPIE_MSIX_MODE          0x00000010
  96 #define E1000_GPIE_EIAME              0x40000000
  97 #define E1000_GPIE_PBA                0x80000000
  98
  99 /* Receive Descriptor bit definitions */
 100 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
 101 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
 102 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
 103 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 104 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
 105 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
 106 #define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
 107 #define E1000_RXD_ERR_CE        0x01    /* CRC Error */
 108 #define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
 109 #define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
 110 #define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
 111 #define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
 112 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
 113
 114 #define E1000_RXDEXT_STATERR_CE    0x01000000
 115 #define E1000_RXDEXT_STATERR_SE    0x02000000
 116 #define E1000_RXDEXT_STATERR_SEQ   0x04000000
 117 #define E1000_RXDEXT_STATERR_CXE   0x10000000
 118 #define E1000_RXDEXT_STATERR_TCPE  0x20000000
 119 #define E1000_RXDEXT_STATERR_IPE   0x40000000
 120 #define E1000_RXDEXT_STATERR_RXE   0x80000000
 121
 122 /* mask to determine if packets should be dropped due to frame errors */
 123 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
 124     E1000_RXD_ERR_CE  |                \
 125     E1000_RXD_ERR_SE  |                \
 126     E1000_RXD_ERR_SEQ |                \
 127     E1000_RXD_ERR_CXE |                \
 128     E1000_RXD_ERR_RXE)
 129
 130 /* Same mask, but for extended and packet split descriptors */
 131 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
 132     E1000_RXDEXT_STATERR_CE  |            \
 133     E1000_RXDEXT_STATERR_SE  |            \
 134     E1000_RXDEXT_STATERR_SEQ |            \
 135     E1000_RXDEXT_STATERR_CXE |            \
 136     E1000_RXDEXT_STATERR_RXE)
 137
 138 #define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
 139 #define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
 140 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
 141 #define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
 142 #define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
 143
 144
 145 /* Management Control */
 146 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
 147 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
 148 #define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
 149 /* Enable Neighbor Discovery Filtering */
 150 #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
 151 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
 152 /* Enable MAC address filtering */
 153 #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
 154 /* Enable MNG packets to host memory */
 155 #define E1000_MANC_EN_MNG2HOST   0x00200000
 156 /* Enable IP address filtering */
 157
 158
 159 /* Receive Control */
 160 #define E1000_RCTL_EN             0x00000002    /* enable */
 161 #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
 162 #define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
 163 #define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
 164 #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
 165 #define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
 166 #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
 167 #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
 168 #define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
 169 #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
 170 #define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
 171 #define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
 172 #define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
 173 #define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
 174 #define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
 175 #define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
 176 #define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
 177 #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
 178
 179 /*
 180  * Use byte values for the following shift parameters
 181  * Usage:
 182  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
 183  *                  E1000_PSRCTL_BSIZE0_MASK) |
 184  *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
 185  *                  E1000_PSRCTL_BSIZE1_MASK) |
 186  *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
 187  *                  E1000_PSRCTL_BSIZE2_MASK) |
 188  *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
 189  *                  E1000_PSRCTL_BSIZE3_MASK))
 190  * where value0 = [128..16256],  default=256
 191  *       value1 = [1024..64512], default=4096
 192  *       value2 = [0..64512],    default=4096
 193  *       value3 = [0..64512],    default=0
 194  */
 195
 196 #define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
 197 #define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
 198 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
 199 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
 200
 201 #define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
 202 #define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
 203 #define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
 204 #define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
 205
 206 /* SWFW_SYNC Definitions */
 207 #define E1000_SWFW_EEP_SM   0x1
 208 #define E1000_SWFW_PHY0_SM  0x2
 209 #define E1000_SWFW_PHY1_SM  0x4
 210
 211 /* FACTPS Definitions */
 212 /* Device Control */
 213 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 214 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
 215 #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
 216 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
 217 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
 218 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
 219 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
 220 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
 221 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
 222 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
 223 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
 224 /* Defined polarity of Dock/Undock indication in SDP[0] */
 225 /* Reset both PHY ports, through PHYRST_N pin */
 226 /* enable link status from external LINK_0 and LINK_1 pins */
 227 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 228 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 229 #define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
 230 #define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
 231 #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
 232 #define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
 233 #define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
 234 #define E1000_CTRL_RST      0x04000000  /* Global reset */
 235 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 236 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
 237 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 238 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
 239 /* Initiate an interrupt to manageability engine */
 240 #define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
 241
 242 /* Bit definitions for the Management Data IO (MDIO) and Management Data
 243  * Clock (MDC) pins in the Device Control Register.
 244  */
 245
 246 #define E1000_CONNSW_ENRGSRC             0x4
 247 #define E1000_PCS_CFG_PCS_EN             8
 248 #define E1000_PCS_LCTL_FLV_LINK_UP       1
 249 #define E1000_PCS_LCTL_FSV_100           2
 250 #define E1000_PCS_LCTL_FSV_1000          4
 251 #define E1000_PCS_LCTL_FDV_FULL          8
 252 #define E1000_PCS_LCTL_FSD               0x10
 253 #define E1000_PCS_LCTL_FORCE_LINK        0x20
 254 #define E1000_PCS_LCTL_FORCE_FCTRL       0x80
 255 #define E1000_PCS_LCTL_AN_ENABLE         0x10000
 256 #define E1000_PCS_LCTL_AN_RESTART        0x20000
 257 #define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
 258 #define E1000_ENABLE_SERDES_LOOPBACK     0x0410
 259
 260 #define E1000_PCS_LSTS_LINK_OK           1
 261 #define E1000_PCS_LSTS_SPEED_100         2
 262 #define E1000_PCS_LSTS_SPEED_1000        4
 263 #define E1000_PCS_LSTS_DUPLEX_FULL       8
 264 #define E1000_PCS_LSTS_SYNK_OK           0x10
 265
 266 /* Device Status */
 267 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 268 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 269 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 270 #define E1000_STATUS_FUNC_SHIFT 2
 271 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 272 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 273 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 274 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 275 /* Change in Dock/Undock state. Clear on write '0'. */
 276 /* Status of Master requests. */
 277 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
 278 /* BMC external code execution disabled */
 279
 280 /* Constants used to intrepret the masked PCI-X bus speed. */
 281
 282 #define SPEED_10    10
 283 #define SPEED_100   100
 284 #define SPEED_1000  1000
 285 #define HALF_DUPLEX 1
 286 #define FULL_DUPLEX 2
 287
 288
 289 #define ADVERTISE_10_HALF                 0x0001
 290 #define ADVERTISE_10_FULL                 0x0002
 291 #define ADVERTISE_100_HALF                0x0004
 292 #define ADVERTISE_100_FULL                0x0008
 293 #define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
 294 #define ADVERTISE_1000_FULL               0x0020
 295
 296 /* 1000/H is not supported, nor spec-compliant. */
 297 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
 298                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
 299                                                       ADVERTISE_1000_FULL)
 300 #define E1000_ALL_NOT_GIG      (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
 301                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 302 #define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 303 #define E1000_ALL_10_SPEED     (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL)
 304 #define E1000_ALL_FULL_DUPLEX  (ADVERTISE_10_FULL  |  ADVERTISE_100_FULL | \
 305                                                       ADVERTISE_1000_FULL)
 306 #define E1000_ALL_HALF_DUPLEX  (ADVERTISE_10_HALF  |  ADVERTISE_100_HALF)
 307
 308 #define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
 309
 310 /* LED Control */
 311 #define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
 312 #define E1000_LEDCTL_LED0_MODE_SHIFT      0
 313 #define E1000_LEDCTL_LED0_IVRT            0x00000040
 314 #define E1000_LEDCTL_LED0_BLINK           0x00000080
 315
 316 #define E1000_LEDCTL_MODE_LED_ON        0xE
 317 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 318
 319 /* Transmit Descriptor bit definitions */
 320 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 321 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 322 #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 323 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 324 #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 325 #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 326 #define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 327 /* Extended desc bits for Linksec and timesync */
 328
 329 /* Transmit Control */
 330 #define E1000_TCTL_EN     0x00000002    /* enable tx */
 331 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
 332 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
 333 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
 334 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
 335
 336 /* Transmit Arbitration Count */
 337
 338 /* SerDes Control */
 339 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
 340
 341 /* Receive Checksum Control */
 342 #define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
 343 #define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
 344 #define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
 345
 346 /* Header split receive */
 347 #define E1000_RFCTL_LEF        0x00040000
 348
 349 /* Collision related configuration parameters */
 350 #define E1000_COLLISION_THRESHOLD       15
 351 #define E1000_CT_SHIFT                  4
 352 #define E1000_COLLISION_DISTANCE        63
 353 #define E1000_COLD_SHIFT                12
 354
 355 /* Ethertype field values */
 356 #define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 357
 358 #define MAX_JUMBO_FRAME_SIZE    0x3F00
 359
 360 /* Extended Configuration Control and Size */
 361 #define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
 362
 363 /* PBA constants */
 364 #define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
 365 #define E1000_PBA_24K 0x0018
 366 #define E1000_PBA_34K 0x0022
 367 #define E1000_PBA_64K 0x0040    /* 64KB */
 368
 369 #define IFS_MAX       80
 370 #define IFS_MIN       40
 371 #define IFS_RATIO     4
 372 #define IFS_STEP      10
 373 #define MIN_NUM_XMITS 1000
 374
 375 /* SW Semaphore Register */
 376 #define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
 377 #define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
 378
 379 /* Interrupt Cause Read */
 380 #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
 381 #define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
 382 #define E1000_ICR_LSC           0x00000004 /* Link Status Change */
 383 #define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
 384 #define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
 385 #define E1000_ICR_RXO           0x00000040 /* rx overrun */
 386 #define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
 387 #define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
 388 #define E1000_ICR_RXCFG         0x00000400 /* Rx /c/ ordered set */
 389 #define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
 390 #define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
 391 #define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
 392 #define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
 393 #define E1000_ICR_TXD_LOW       0x00008000
 394 #define E1000_ICR_SRPD          0x00010000
 395 #define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
 396 #define E1000_ICR_MNG           0x00040000 /* Manageability event */
 397 #define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
 398 /* If this bit asserted, the driver should claim the interrupt */
 399 #define E1000_ICR_INT_ASSERTED  0x80000000
 400 /* queue 0 Rx descriptor FIFO parity error */
 401 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000
 402 /* queue 0 Tx descriptor FIFO parity error */
 403 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000
 404 /* host arb read buffer parity error */
 405 #define E1000_ICR_HOST_ARB_PAR  0x00400000
 406 #define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
 407 /* queue 1 Rx descriptor FIFO parity error */
 408 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000
 409 /* queue 1 Tx descriptor FIFO parity error */
 410 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000
 411 /* FW changed the status of DISSW bit in the FWSM */
 412 #define E1000_ICR_DSW           0x00000020
 413 /* LAN connected device generates an interrupt */
 414 #define E1000_ICR_PHYINT        0x00001000
 415 #define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */
 416
 417 /* Extended Interrupt Cause Read */
 418 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
 419 #define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
 420 #define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
 421 #define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
 422 #define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
 423 #define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
 424 #define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
 425 #define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
 426 #define E1000_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
 427 #define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
 428 /* TCP Timer */
 429
 430 /*
 431  * This defines the bits that are set in the Interrupt Mask
 432  * Set/Read Register.  Each bit is documented below:
 433  *   o RXT0   = Receiver Timer Interrupt (ring 0)
 434  *   o TXDW   = Transmit Descriptor Written Back
 435  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 436  *   o RXSEQ  = Receive Sequence Error
 437  *   o LSC    = Link Status Change
 438  */
 439 #define IMS_ENABLE_MASK ( \
 440     E1000_IMS_RXT0   |    \
 441     E1000_IMS_TXDW   |    \
 442     E1000_IMS_RXDMT0 |    \
 443     E1000_IMS_RXSEQ  |    \
 444     E1000_IMS_LSC)
 445
 446 /* Interrupt Mask Set */
 447 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
 448 #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
 449 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 450 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 451 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
 452
 453 /* Extended Interrupt Mask Set */
 454 #define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
 455 #define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 456
 457 /* Interrupt Cause Set */
 458 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 459 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 460
 461 /* Extended Interrupt Cause Set */
 462
 463 /* Transmit Descriptor Control */
 464 /* Enable the counting of descriptors still to be processed. */
 465
 466 /* Flow Control Constants */
 467 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
 468 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
 469 #define FLOW_CONTROL_TYPE         0x8808
 470
 471 /* 802.1q VLAN Packet Size */
 472 #define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
 473 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 474
 475 /* Receive Address */
 476 /*
 477  * Number of high/low register pairs in the RAR. The RAR (Receive Address
 478  * Registers) holds the directed and multicast addresses that we monitor.
 479  * Technically, we have 16 spots.  However, we reserve one of these spots
 480  * (RAR[15]) for our directed address used by controllers with
 481  * manageability enabled, allowing us room for 15 multicast addresses.
 482  */
 483 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
 484
 485 /* Error Codes */
 486 #define E1000_ERR_NVM      1
 487 #define E1000_ERR_PHY      2
 488 #define E1000_ERR_CONFIG   3
 489 #define E1000_ERR_PARAM    4
 490 #define E1000_ERR_MAC_INIT 5
 491 #define E1000_ERR_RESET   9
 492 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
 493 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
 494 #define E1000_BLK_PHY_RESET   12
 495 #define E1000_ERR_SWFW_SYNC 13
 496 #define E1000_NOT_IMPLEMENTED 14
 497
 498 /* Loop limit on how long we wait for auto-negotiation to complete */
 499 #define COPPER_LINK_UP_LIMIT              10
 500 #define PHY_AUTO_NEG_LIMIT                45
 501 #define PHY_FORCE_LIMIT                   20
 502 /* Number of 100 microseconds we wait for PCI Express master disable */
 503 #define MASTER_DISABLE_TIMEOUT      800
 504 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
 505 #define PHY_CFG_TIMEOUT             100
 506 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
 507 /* Number of milliseconds for NVM auto read done after MAC reset. */
 508 #define AUTO_READ_DONE_TIMEOUT      10
 509
 510 /* Flow Control */
 511 #define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
 512
 513 /* Transmit Configuration Word */
 514 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
 515
 516 /* Receive Configuration Word */
 517
 518 /* PCI Express Control */
 519 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
 520 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
 521 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
 522 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
 523 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
 524 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
 525
 526 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
 527                            E1000_GCR_RXDSCW_NO_SNOOP      | \
 528                            E1000_GCR_RXDSCR_NO_SNOOP      | \
 529                            E1000_GCR_TXD_NO_SNOOP         | \
 530                            E1000_GCR_TXDSCW_NO_SNOOP      | \
 531                            E1000_GCR_TXDSCR_NO_SNOOP)
 532
 533 /* PHY Control Register */
 534 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 535 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 536 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
 537 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 538 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
 539 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
 540 #define MII_CR_SPEED_1000       0x0040
 541 #define MII_CR_SPEED_100        0x2000
 542 #define MII_CR_SPEED_10         0x0000
 543
 544 /* PHY Status Register */
 545 #define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
 546 #define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
 547
 548 /* Autoneg Advertisement Register */
 549 #define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
 550 #define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
 551 #define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
 552 #define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
 553 #define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
 554 #define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
 555
 556 /* Link Partner Ability Register (Base Page) */
 557 #define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
 558 #define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
 559
 560 /* Autoneg Expansion Register */
 561
 562 /* 1000BASE-T Control Register */
 563 #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
 564 #define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
 565 #define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
 566                                         /* 0=Configure PHY as Slave */
 567 #define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
 568                                         /* 0=Automatic Master/Slave config */
 569
 570 /* 1000BASE-T Status Register */
 571 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
 572 #define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
 573
 574
 575 /* PHY 1000 MII Register/Bit Definitions */
 576 /* PHY Registers defined by IEEE */
 577 #define PHY_CONTROL      0x00 /* Control Register */
 578 #define PHY_STATUS       0x01 /* Status Register */
 579 #define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
 580 #define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
 581 #define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
 582 #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
 583 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
 584 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
 585
 586 /* NVM Control */
 587 #define E1000_EECD_SK        0x00000001 /* NVM Clock */
 588 #define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
 589 #define E1000_EECD_DI        0x00000004 /* NVM Data In */
 590 #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
 591 #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
 592 #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
 593 #define E1000_EECD_PRES      0x00000100 /* NVM Present */
 594 /* NVM Addressing bits based on type 0=small, 1=large */
 595 #define E1000_EECD_ADDR_BITS 0x00000400
 596 #define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
 597 #define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
 598 #define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
 599 #define E1000_EECD_SIZE_EX_SHIFT     11
 600
 601 /* Offset to data in NVM read/write registers */
 602 #define E1000_NVM_RW_REG_DATA   16
 603 #define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
 604 #define E1000_NVM_RW_REG_START  1    /* Start operation */
 605 #define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
 606 #define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
 607
 608 /* NVM Word Offsets */
 609 #define NVM_ID_LED_SETTINGS        0x0004
 610 /* For SERDES output amplitude adjustment. */
 611 #define NVM_INIT_CONTROL2_REG      0x000F
 612 #define NVM_INIT_CONTROL3_PORT_A   0x0024
 613 #define NVM_ALT_MAC_ADDR_PTR       0x0037
 614 #define NVM_CHECKSUM_REG           0x003F
 615
 616 #define E1000_NVM_CFG_DONE_PORT_0  0x40000 /* MNG config cycle done */
 617 #define E1000_NVM_CFG_DONE_PORT_1  0x80000 /* ...for second port */
 618
 619 /* Mask bits for fields in Word 0x0f of the NVM */
 620 #define NVM_WORD0F_PAUSE_MASK       0x3000
 621 #define NVM_WORD0F_ASM_DIR          0x2000
 622
 623 /* Mask bits for fields in Word 0x1a of the NVM */
 624
 625 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 626 #define NVM_SUM                    0xBABA
 627
 628 #define NVM_PBA_OFFSET_0           8
 629 #define NVM_PBA_OFFSET_1           9
 630 #define NVM_WORD_SIZE_BASE_SHIFT   6
 631
 632 /* NVM Commands - Microwire */
 633
 634 /* NVM Commands - SPI */
 635 #define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
 636 #define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
 637 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
 638 #define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
 639 #define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
 640
 641 /* SPI NVM Status Register */
 642 #define NVM_STATUS_RDY_SPI         0x01
 643
 644 /* Word definitions for ID LED Settings */
 645 #define ID_LED_RESERVED_0000 0x0000
 646 #define ID_LED_RESERVED_FFFF 0xFFFF
 647 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
 648                               (ID_LED_OFF1_OFF2 <<  8) | \
 649                               (ID_LED_DEF1_DEF2 <<  4) | \
 650                               (ID_LED_DEF1_DEF2))
 651 #define ID_LED_DEF1_DEF2     0x1
 652 #define ID_LED_DEF1_ON2      0x2
 653 #define ID_LED_DEF1_OFF2     0x3
 654 #define ID_LED_ON1_DEF2      0x4
 655 #define ID_LED_ON1_ON2       0x5
 656 #define ID_LED_ON1_OFF2      0x6
 657 #define ID_LED_OFF1_DEF2     0x7
 658 #define ID_LED_OFF1_ON2      0x8
 659 #define ID_LED_OFF1_OFF2     0x9
 660
 661 #define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
 662 #define IGP_ACTIVITY_LED_ENABLE 0x0300
 663 #define IGP_LED3_MODE           0x07000000
 664
 665 /* PCI/PCI-X/PCI-EX Config space */
 666 #define PCI_HEADER_TYPE_REGISTER     0x0E
 667 #define PCIE_LINK_STATUS             0x12
 668
 669 #define PCI_HEADER_TYPE_MULTIFUNC    0x80
 670 #define PCIE_LINK_WIDTH_MASK         0x3F0
 671 #define PCIE_LINK_WIDTH_SHIFT        4
 672
 673 #define PHY_REVISION_MASK      0xFFFFFFF0
 674 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
 675 #define MAX_PHY_MULTI_PAGE_REG 0xF
 676
 677 /* Bit definitions for valid PHY IDs. */
 678 /*
 679  * I = Integrated
 680  * E = External
 681  */
 682 #define M88E1111_I_PHY_ID    0x01410CC0
 683 #define IGP03E1000_E_PHY_ID  0x02A80390
 684 #define M88_VENDOR           0x0141
 685
 686 /* M88E1000 Specific Registers */
 687 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
 688 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
 689 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
 690
 691 #define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
 692 #define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
 693
 694 /* M88E1000 PHY Specific Control Register */
 695 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
 696 /* 1=CLK125 low, 0=CLK125 toggling */
 697 #define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
 698                                                /* Manual MDI configuration */
 699 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
 700 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
 701 #define M88E1000_PSCR_AUTO_X_1000T     0x0040
 702 /* Auto crossover enabled all speeds */
 703 #define M88E1000_PSCR_AUTO_X_MODE      0x0060
 704 /*
 705  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
 706  * 0=Normal 10BASE-T Rx Threshold
 707  */
 708 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
 709 #define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
 710
 711 /* M88E1000 PHY Specific Status Register */
 712 #define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
 713 #define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
 714 #define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
 715 /*
 716  * 0 = <50M
 717  * 1 = 50-80M
 718  * 2 = 80-110M
 719  * 3 = 110-140M
 720  * 4 = >140M
 721  */
 722 #define M88E1000_PSSR_CABLE_LENGTH       0x0380
 723 #define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
 724 #define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
 725
 726 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 727
 728 /* M88E1000 Extended PHY Specific Control Register */
 729 /*
 730  * 1 = Lost lock detect enabled.
 731  * Will assert lost lock and bring
 732  * link down if idle not seen
 733  * within 1ms in 1000BASE-T
 734  */
 735 /*
 736  * Number of times we will attempt to autonegotiate before downshifting if we
 737  * are the master
 738  */
 739 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
 740 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
 741 /*
 742  * Number of times we will attempt to autonegotiate before downshifting if we
 743  * are the slave
 744  */
 745 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
 746 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 747 #define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
 748
 749 /* M88EC018 Rev 2 specific DownShift settings */
 750 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
 751 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
 752
 753 /* MDI Control */
 754 #define E1000_MDIC_REG_SHIFT 16
 755 #define E1000_MDIC_PHY_SHIFT 21
 756 #define E1000_MDIC_OP_WRITE  0x04000000
 757 #define E1000_MDIC_OP_READ   0x08000000
 758 #define E1000_MDIC_READY     0x10000000
 759 #define E1000_MDIC_ERROR     0x40000000
 760
 761 /* SerDes Control */
 762 #define E1000_GEN_CTL_READY             0x80000000
 763 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
 764 #define E1000_GEN_POLL_TIMEOUT          640
 765
 766 #endif