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[NET]: Fix drivers to handle napi_disable() disabling interrupts.
[linux-2.6/sactl.git] / drivers / net / sky2.c
blob52ec89b82f64576c239cf807ac82d1fcdc354ccf
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.20"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
138 { 0 }
139 };
140
141 MODULE_DEVICE_TABLE(pci, sky2_id_table);
142
143 /* Avoid conditionals by using array */
144 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
145 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
146 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
147
148 /* This driver supports yukon2 chipset only */
149 static const char *yukon2_name[] = {
150 "XL", /* 0xb3 */
151 "EC Ultra", /* 0xb4 */
152 "Extreme", /* 0xb5 */
153 "EC", /* 0xb6 */
154 "FE", /* 0xb7 */
155 "FE+", /* 0xb8 */
156 };
157
158 static void sky2_set_multicast(struct net_device *dev);
159
160 /* Access to PHY via serial interconnect */
161 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
162 {
163 int i;
164
165 gma_write16(hw, port, GM_SMI_DATA, val);
166 gma_write16(hw, port, GM_SMI_CTRL,
167 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
168
169 for (i = 0; i < PHY_RETRIES; i++) {
170 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
171 if (ctrl == 0xffff)
172 goto io_error;
173
174 if (!(ctrl & GM_SMI_CT_BUSY))
175 return 0;
176
177 udelay(10);
178 }
179
180 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
181 return -ETIMEDOUT;
182
183 io_error:
184 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
185 return -EIO;
186 }
187
188 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
189 {
190 int i;
191
192 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
193 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
194
195 for (i = 0; i < PHY_RETRIES; i++) {
196 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
197 if (ctrl == 0xffff)
198 goto io_error;
199
200 if (ctrl & GM_SMI_CT_RD_VAL) {
201 *val = gma_read16(hw, port, GM_SMI_DATA);
202 return 0;
203 }
204
205 udelay(10);
206 }
207
208 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
209 return -ETIMEDOUT;
210 io_error:
211 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
212 return -EIO;
213 }
214
215 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
216 {
217 u16 v;
218 __gm_phy_read(hw, port, reg, &v);
219 return v;
220 }
221
222
223 static void sky2_power_on(struct sky2_hw *hw)
224 {
225 /* switch power to VCC (WA for VAUX problem) */
226 sky2_write8(hw, B0_POWER_CTRL,
227 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
228
229 /* disable Core Clock Division, */
230 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
231
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 /* enable bits are inverted */
234 sky2_write8(hw, B2_Y2_CLK_GATE,
235 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
236 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
237 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
238 else
239 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
240
241 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
242 u32 reg;
243
244 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
245
246 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
247 /* set all bits to 0 except bits 15..12 and 8 */
248 reg &= P_ASPM_CONTROL_MSK;
249 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
250
251 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
252 /* set all bits to 0 except bits 28 & 27 */
253 reg &= P_CTL_TIM_VMAIN_AV_MSK;
254 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
255
256 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
257
258 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
259 reg = sky2_read32(hw, B2_GP_IO);
260 reg |= GLB_GPIO_STAT_RACE_DIS;
261 sky2_write32(hw, B2_GP_IO, reg);
262
263 sky2_read32(hw, B2_GP_IO);
264 }
265 }
266
267 static void sky2_power_aux(struct sky2_hw *hw)
268 {
269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
278 /* switch power to VAUX */
279 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
283 }
284
285 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
286 {
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
291
292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300 }
301
302 /* flow control to advertise bits */
303 static const u16 copper_fc_adv[] = {
304 [FC_NONE] = 0,
305 [FC_TX] = PHY_M_AN_ASP,
306 [FC_RX] = PHY_M_AN_PC,
307 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
308 };
309
310 /* flow control to advertise bits when using 1000BaseX */
311 static const u16 fiber_fc_adv[] = {
312 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
313 [FC_TX] = PHY_M_P_ASYM_MD_X,
314 [FC_RX] = PHY_M_P_SYM_MD_X,
315 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
316 };
317
318 /* flow control to GMA disable bits */
319 static const u16 gm_fc_disable[] = {
320 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
321 [FC_TX] = GM_GPCR_FC_RX_DIS,
322 [FC_RX] = GM_GPCR_FC_TX_DIS,
323 [FC_BOTH] = 0,
324 };
325
326
327 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
328 {
329 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
330 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
331
332 if (sky2->autoneg == AUTONEG_ENABLE &&
333 !(hw->flags & SKY2_HW_NEWER_PHY)) {
334 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
335
336 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
337 PHY_M_EC_MAC_S_MSK);
338 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
339
340 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
341 if (hw->chip_id == CHIP_ID_YUKON_EC)
342 /* set downshift counter to 3x and enable downshift */
343 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
344 else
345 /* set master & slave downshift counter to 1x */
346 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
347
348 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 if (sky2_is_copper(hw)) {
353 if (!(hw->flags & SKY2_HW_GIGABIT)) {
354 /* enable automatic crossover */
355 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
356
357 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
358 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
359 u16 spec;
360
361 /* Enable Class A driver for FE+ A0 */
362 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 spec |= PHY_M_FESC_SEL_CL_A;
364 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
365 }
366 } else {
367 /* disable energy detect */
368 ctrl &= ~PHY_M_PC_EN_DET_MSK;
369
370 /* enable automatic crossover */
371 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
372
373 /* downshift on PHY 88E1112 and 88E1149 is changed */
374 if (sky2->autoneg == AUTONEG_ENABLE
375 && (hw->flags & SKY2_HW_NEWER_PHY)) {
376 /* set downshift counter to 3x and enable downshift */
377 ctrl &= ~PHY_M_PC_DSC_MSK;
378 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
379 }
380 }
381 } else {
382 /* workaround for deviation #4.88 (CRC errors) */
383 /* disable Automatic Crossover */
384
385 ctrl &= ~PHY_M_PC_MDIX_MSK;
386 }
387
388 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
389
390 /* special setup for PHY 88E1112 Fiber */
391 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
392 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
393
394 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
396 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
397 ctrl &= ~PHY_M_MAC_MD_MSK;
398 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
399 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400
401 if (hw->pmd_type == 'P') {
402 /* select page 1 to access Fiber registers */
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
404
405 /* for SFP-module set SIGDET polarity to low */
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl |= PHY_M_FIB_SIGD_POL;
408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
409 }
410
411 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
412 }
413
414 ctrl = PHY_CT_RESET;
415 ct1000 = 0;
416 adv = PHY_AN_CSMA;
417 reg = 0;
418
419 if (sky2->autoneg == AUTONEG_ENABLE) {
420 if (sky2_is_copper(hw)) {
421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 ct1000 |= PHY_M_1000C_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 ct1000 |= PHY_M_1000C_AHD;
425 if (sky2->advertising & ADVERTISED_100baseT_Full)
426 adv |= PHY_M_AN_100_FD;
427 if (sky2->advertising & ADVERTISED_100baseT_Half)
428 adv |= PHY_M_AN_100_HD;
429 if (sky2->advertising & ADVERTISED_10baseT_Full)
430 adv |= PHY_M_AN_10_FD;
431 if (sky2->advertising & ADVERTISED_10baseT_Half)
432 adv |= PHY_M_AN_10_HD;
433
434 adv |= copper_fc_adv[sky2->flow_mode];
435 } else { /* special defines for FIBER (88E1040S only) */
436 if (sky2->advertising & ADVERTISED_1000baseT_Full)
437 adv |= PHY_M_AN_1000X_AFD;
438 if (sky2->advertising & ADVERTISED_1000baseT_Half)
439 adv |= PHY_M_AN_1000X_AHD;
440
441 adv |= fiber_fc_adv[sky2->flow_mode];
442 }
443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
450 /* Disable auto update for duplex flow control and speed */
451 reg |= GM_GPCR_AU_ALL_DIS;
452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
456 reg |= GM_GPCR_SPEED_1000;
457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
460 reg |= GM_GPCR_SPEED_100;
461 break;
462 }
463
464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
469
470
471 reg |= gm_fc_disable[sky2->flow_mode];
472
473 /* Forward pause packets to GMAC? */
474 if (sky2->flow_mode & FC_RX)
475 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
476 else
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
478 }
479
480 gma_write16(hw, port, GM_GP_CTRL, reg);
481
482 if (hw->flags & SKY2_HW_GIGABIT)
483 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
484
485 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
486 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
487
488 /* Setup Phy LED's */
489 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
490 ledover = 0;
491
492 switch (hw->chip_id) {
493 case CHIP_ID_YUKON_FE:
494 /* on 88E3082 these bits are at 11..9 (shifted left) */
495 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
496
497 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
498
499 /* delete ACT LED control bits */
500 ctrl &= ~PHY_M_FELP_LED1_MSK;
501 /* change ACT LED control to blink mode */
502 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
503 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
504 break;
505
506 case CHIP_ID_YUKON_FE_P:
507 /* Enable Link Partner Next Page */
508 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
509 ctrl |= PHY_M_PC_ENA_LIP_NP;
510
511 /* disable Energy Detect and enable scrambler */
512 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
514
515 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
516 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
517 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
518 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
519
520 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
521 break;
522
523 case CHIP_ID_YUKON_XL:
524 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
525
526 /* select page 3 to access LED control register */
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
528
529 /* set LED Function Control register */
530 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
531 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
532 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
533 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
534 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
535
536 /* set Polarity Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
538 (PHY_M_POLC_LS1_P_MIX(4) |
539 PHY_M_POLC_IS0_P_MIX(4) |
540 PHY_M_POLC_LOS_CTRL(2) |
541 PHY_M_POLC_INIT_CTRL(2) |
542 PHY_M_POLC_STA1_CTRL(2) |
543 PHY_M_POLC_STA0_CTRL(2)));
544
545 /* restore page register */
546 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
547 break;
548
549 case CHIP_ID_YUKON_EC_U:
550 case CHIP_ID_YUKON_EX:
551 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
552
553 /* select page 3 to access LED control register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
555
556 /* set LED Function Control register */
557 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
558 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
559 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
560 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
561 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
562
563 /* set Blink Rate in LED Timer Control Register */
564 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
565 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
566 /* restore page register */
567 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
568 break;
569
570 default:
571 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
572 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
573 /* turn off the Rx LED (LED_RX) */
574 ledover &= ~PHY_M_LED_MO_RX;
575 }
576
577 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
578 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
579 /* apply fixes in PHY AFE */
580 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
581
582 /* increase differential signal amplitude in 10BASE-T */
583 gm_phy_write(hw, port, 0x18, 0xaa99);
584 gm_phy_write(hw, port, 0x17, 0x2011);
585
586 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
587 gm_phy_write(hw, port, 0x18, 0xa204);
588 gm_phy_write(hw, port, 0x17, 0x2002);
589
590 /* set page register to 0 */
591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
592 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
593 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
594 /* apply workaround for integrated resistors calibration */
595 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
596 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
597 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
598 /* no effect on Yukon-XL */
599 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
600
601 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
602 /* turn on 100 Mbps LED (LED_LINK100) */
603 ledover |= PHY_M_LED_MO_100;
604 }
605
606 if (ledover)
607 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
608
609 }
610
611 /* Enable phy interrupt on auto-negotiation complete (or link up) */
612 if (sky2->autoneg == AUTONEG_ENABLE)
613 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
614 else
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
616 }
617
618 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
619 {
620 u32 reg1;
621 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
622 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
623
624 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
625 /* Turn on/off phy power saving */
626 if (onoff)
627 reg1 &= ~phy_power[port];
628 else
629 reg1 |= phy_power[port];
630
631 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
632 reg1 |= coma_mode[port];
633
634 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
635 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
636
637 udelay(100);
638 }
639
640 /* Force a renegotiation */
641 static void sky2_phy_reinit(struct sky2_port *sky2)
642 {
643 spin_lock_bh(&sky2->phy_lock);
644 sky2_phy_init(sky2->hw, sky2->port);
645 spin_unlock_bh(&sky2->phy_lock);
646 }
647
648 /* Put device in state to listen for Wake On Lan */
649 static void sky2_wol_init(struct sky2_port *sky2)
650 {
651 struct sky2_hw *hw = sky2->hw;
652 unsigned port = sky2->port;
653 enum flow_control save_mode;
654 u16 ctrl;
655 u32 reg1;
656
657 /* Bring hardware out of reset */
658 sky2_write16(hw, B0_CTST, CS_RST_CLR);
659 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
660
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
663
664 /* Force to 10/100
665 * sky2_reset will re-enable on resume
666 */
667 save_mode = sky2->flow_mode;
668 ctrl = sky2->advertising;
669
670 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
671 sky2->flow_mode = FC_NONE;
672 sky2_phy_power(hw, port, 1);
673 sky2_phy_reinit(sky2);
674
675 sky2->flow_mode = save_mode;
676 sky2->advertising = ctrl;
677
678 /* Set GMAC to no flow control and auto update for speed/duplex */
679 gma_write16(hw, port, GM_GP_CTRL,
680 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
681 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
682
683 /* Set WOL address */
684 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
685 sky2->netdev->dev_addr, ETH_ALEN);
686
687 /* Turn on appropriate WOL control bits */
688 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
689 ctrl = 0;
690 if (sky2->wol & WAKE_PHY)
691 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
692 else
693 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
694
695 if (sky2->wol & WAKE_MAGIC)
696 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
697 else
698 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
699
700 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
701 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
702
703 /* Turn on legacy PCI-Express PME mode */
704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
705 reg1 |= PCI_Y2_PME_LEGACY;
706 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
707
708 /* block receiver */
709 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
710
711 }
712
713 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
714 {
715 struct net_device *dev = hw->dev[port];
716
717 if (dev->mtu <= ETH_DATA_LEN)
718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
719 TX_JUMBO_DIS | TX_STFW_ENA);
720
721 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
722 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
723 TX_STFW_ENA | TX_JUMBO_ENA);
724 else {
725 /* set Tx GMAC FIFO Almost Empty Threshold */
726 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
727 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
728
729 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
730 TX_JUMBO_ENA | TX_STFW_DIS);
731
732 /* Can't do offload because of lack of store/forward */
733 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
734 }
735 }
736
737 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
738 {
739 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
740 u16 reg;
741 u32 rx_reg;
742 int i;
743 const u8 *addr = hw->dev[port]->dev_addr;
744
745 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
746 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
747
748 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
749
750 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
751 /* WA DEV_472 -- looks like crossed wires on port 2 */
752 /* clear GMAC 1 Control reset */
753 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
754 do {
755 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
756 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
757 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
758 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
759 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
760 }
761
762 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
763
764 /* Enable Transmit FIFO Underrun */
765 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
766
767 spin_lock_bh(&sky2->phy_lock);
768 sky2_phy_init(hw, port);
769 spin_unlock_bh(&sky2->phy_lock);
770
771 /* MIB clear */
772 reg = gma_read16(hw, port, GM_PHY_ADDR);
773 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
774
775 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
776 gma_read16(hw, port, i);
777 gma_write16(hw, port, GM_PHY_ADDR, reg);
778
779 /* transmit control */
780 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
781
782 /* receive control reg: unicast + multicast + no FCS */
783 gma_write16(hw, port, GM_RX_CTRL,
784 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
785
786 /* transmit flow control */
787 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
788
789 /* transmit parameter */
790 gma_write16(hw, port, GM_TX_PARAM,
791 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
792 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
793 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
794 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
795
796 /* serial mode register */
797 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
798 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
799
800 if (hw->dev[port]->mtu > ETH_DATA_LEN)
801 reg |= GM_SMOD_JUMBO_ENA;
802
803 gma_write16(hw, port, GM_SERIAL_MODE, reg);
804
805 /* virtual address for data */
806 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
807
808 /* physical address: used for pause frames */
809 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
810
811 /* ignore counter overflows */
812 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
813 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
814 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
815
816 /* Configure Rx MAC FIFO */
817 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
818 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
819 if (hw->chip_id == CHIP_ID_YUKON_EX ||
820 hw->chip_id == CHIP_ID_YUKON_FE_P)
821 rx_reg |= GMF_RX_OVER_ON;
822
823 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
824
825 if (hw->chip_id == CHIP_ID_YUKON_XL) {
826 /* Hardware errata - clear flush mask */
827 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
828 } else {
829 /* Flush Rx MAC FIFO on any flow control or error */
830 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
831 }
832
833 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
834 reg = RX_GMF_FL_THR_DEF + 1;
835 /* Another magic mystery workaround from sk98lin */
836 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
837 hw->chip_rev == CHIP_REV_YU_FE2_A0)
838 reg = 0x178;
839 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
840
841 /* Configure Tx MAC FIFO */
842 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
843 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
844
845 /* On chips without ram buffer, pause is controled by MAC level */
846 if (sky2_read8(hw, B2_E_0) == 0) {
847 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
848 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
849
850 sky2_set_tx_stfwd(hw, port);
851 }
852
853 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
854 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
855 /* disable dynamic watermark */
856 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
857 reg &= ~TX_DYN_WM_ENA;
858 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
859 }
860 }
861
862 /* Assign Ram Buffer allocation to queue */
863 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
864 {
865 u32 end;
866
867 /* convert from K bytes to qwords used for hw register */
868 start *= 1024/8;
869 space *= 1024/8;
870 end = start + space - 1;
871
872 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
873 sky2_write32(hw, RB_ADDR(q, RB_START), start);
874 sky2_write32(hw, RB_ADDR(q, RB_END), end);
875 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
876 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
877
878 if (q == Q_R1 || q == Q_R2) {
879 u32 tp = space - space/4;
880
881 /* On receive queue's set the thresholds
882 * give receiver priority when > 3/4 full
883 * send pause when down to 2K
884 */
885 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
886 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
887
888 tp = space - 2048/8;
889 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
890 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
891 } else {
892 /* Enable store & forward on Tx queue's because
893 * Tx FIFO is only 1K on Yukon
894 */
895 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
896 }
897
898 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
899 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
900 }
901
902 /* Setup Bus Memory Interface */
903 static void sky2_qset(struct sky2_hw *hw, u16 q)
904 {
905 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
906 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
907 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
908 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
909 }
910
911 /* Setup prefetch unit registers. This is the interface between
912 * hardware and driver list elements
913 */
914 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
915 u64 addr, u32 last)
916 {
917 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
918 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
919 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
920 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
921 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
922 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
923
924 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
925 }
926
927 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
928 {
929 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
930
931 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
932 le->ctrl = 0;
933 return le;
934 }
935
936 static void tx_init(struct sky2_port *sky2)
937 {
938 struct sky2_tx_le *le;
939
940 sky2->tx_prod = sky2->tx_cons = 0;
941 sky2->tx_tcpsum = 0;
942 sky2->tx_last_mss = 0;
943
944 le = get_tx_le(sky2);
945 le->addr = 0;
946 le->opcode = OP_ADDR64 | HW_OWNER;
947 sky2->tx_addr64 = 0;
948 }
949
950 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
951 struct sky2_tx_le *le)
952 {
953 return sky2->tx_ring + (le - sky2->tx_le);
954 }
955
956 /* Update chip's next pointer */
957 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
958 {
959 /* Make sure write' to descriptors are complete before we tell hardware */
960 wmb();
961 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
962
963 /* Synchronize I/O on since next processor may write to tail */
964 mmiowb();
965 }
966
967
968 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
969 {
970 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
971 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
972 le->ctrl = 0;
973 return le;
974 }
975
976 /* Build description to hardware for one receive segment */
977 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
978 dma_addr_t map, unsigned len)
979 {
980 struct sky2_rx_le *le;
981 u32 hi = upper_32_bits(map);
982
983 if (sky2->rx_addr64 != hi) {
984 le = sky2_next_rx(sky2);
985 le->addr = cpu_to_le32(hi);
986 le->opcode = OP_ADDR64 | HW_OWNER;
987 sky2->rx_addr64 = upper_32_bits(map + len);
988 }
989
990 le = sky2_next_rx(sky2);
991 le->addr = cpu_to_le32((u32) map);
992 le->length = cpu_to_le16(len);
993 le->opcode = op | HW_OWNER;
994 }
995
996 /* Build description to hardware for one possibly fragmented skb */
997 static void sky2_rx_submit(struct sky2_port *sky2,
998 const struct rx_ring_info *re)
999 {
1000 int i;
1001
1002 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1003
1004 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1005 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1006 }
1007
1008
1009 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1010 unsigned size)
1011 {
1012 struct sk_buff *skb = re->skb;
1013 int i;
1014
1015 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1016 pci_unmap_len_set(re, data_size, size);
1017
1018 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1019 re->frag_addr[i] = pci_map_page(pdev,
1020 skb_shinfo(skb)->frags[i].page,
1021 skb_shinfo(skb)->frags[i].page_offset,
1022 skb_shinfo(skb)->frags[i].size,
1023 PCI_DMA_FROMDEVICE);
1024 }
1025
1026 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1027 {
1028 struct sk_buff *skb = re->skb;
1029 int i;
1030
1031 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1032 PCI_DMA_FROMDEVICE);
1033
1034 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1035 pci_unmap_page(pdev, re->frag_addr[i],
1036 skb_shinfo(skb)->frags[i].size,
1037 PCI_DMA_FROMDEVICE);
1038 }
1039
1040 /* Tell chip where to start receive checksum.
1041 * Actually has two checksums, but set both same to avoid possible byte
1042 * order problems.
1043 */
1044 static void rx_set_checksum(struct sky2_port *sky2)
1045 {
1046 struct sky2_rx_le *le = sky2_next_rx(sky2);
1047
1048 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1049 le->ctrl = 0;
1050 le->opcode = OP_TCPSTART | HW_OWNER;
1051
1052 sky2_write32(sky2->hw,
1053 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1054 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1055 }
1056
1057 /*
1058 * The RX Stop command will not work for Yukon-2 if the BMU does not
1059 * reach the end of packet and since we can't make sure that we have
1060 * incoming data, we must reset the BMU while it is not doing a DMA
1061 * transfer. Since it is possible that the RX path is still active,
1062 * the RX RAM buffer will be stopped first, so any possible incoming
1063 * data will not trigger a DMA. After the RAM buffer is stopped, the
1064 * BMU is polled until any DMA in progress is ended and only then it
1065 * will be reset.
1066 */
1067 static void sky2_rx_stop(struct sky2_port *sky2)
1068 {
1069 struct sky2_hw *hw = sky2->hw;
1070 unsigned rxq = rxqaddr[sky2->port];
1071 int i;
1072
1073 /* disable the RAM Buffer receive queue */
1074 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1075
1076 for (i = 0; i < 0xffff; i++)
1077 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1078 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1079 goto stopped;
1080
1081 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1082 sky2->netdev->name);
1083 stopped:
1084 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1085
1086 /* reset the Rx prefetch unit */
1087 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1088 mmiowb();
1089 }
1090
1091 /* Clean out receive buffer area, assumes receiver hardware stopped */
1092 static void sky2_rx_clean(struct sky2_port *sky2)
1093 {
1094 unsigned i;
1095
1096 memset(sky2->rx_le, 0, RX_LE_BYTES);
1097 for (i = 0; i < sky2->rx_pending; i++) {
1098 struct rx_ring_info *re = sky2->rx_ring + i;
1099
1100 if (re->skb) {
1101 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1102 kfree_skb(re->skb);
1103 re->skb = NULL;
1104 }
1105 }
1106 }
1107
1108 /* Basic MII support */
1109 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1110 {
1111 struct mii_ioctl_data *data = if_mii(ifr);
1112 struct sky2_port *sky2 = netdev_priv(dev);
1113 struct sky2_hw *hw = sky2->hw;
1114 int err = -EOPNOTSUPP;
1115
1116 if (!netif_running(dev))
1117 return -ENODEV; /* Phy still in reset */
1118
1119 switch (cmd) {
1120 case SIOCGMIIPHY:
1121 data->phy_id = PHY_ADDR_MARV;
1122
1123 /* fallthru */
1124 case SIOCGMIIREG: {
1125 u16 val = 0;
1126
1127 spin_lock_bh(&sky2->phy_lock);
1128 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1129 spin_unlock_bh(&sky2->phy_lock);
1130
1131 data->val_out = val;
1132 break;
1133 }
1134
1135 case SIOCSMIIREG:
1136 if (!capable(CAP_NET_ADMIN))
1137 return -EPERM;
1138
1139 spin_lock_bh(&sky2->phy_lock);
1140 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1141 data->val_in);
1142 spin_unlock_bh(&sky2->phy_lock);
1143 break;
1144 }
1145 return err;
1146 }
1147
1148 #ifdef SKY2_VLAN_TAG_USED
1149 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1150 {
1151 struct sky2_port *sky2 = netdev_priv(dev);
1152 struct sky2_hw *hw = sky2->hw;
1153 u16 port = sky2->port;
1154
1155 netif_tx_lock_bh(dev);
1156 napi_disable(&hw->napi);
1157
1158 sky2->vlgrp = grp;
1159 if (grp) {
1160 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1161 RX_VLAN_STRIP_ON);
1162 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1163 TX_VLAN_TAG_ON);
1164 } else {
1165 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1166 RX_VLAN_STRIP_OFF);
1167 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1168 TX_VLAN_TAG_OFF);
1169 }
1170
1171 sky2_read32(hw, B0_Y2_SP_LISR);
1172 napi_enable(&hw->napi);
1173 netif_tx_unlock_bh(dev);
1174 }
1175 #endif
1176
1177 /*
1178 * Allocate an skb for receiving. If the MTU is large enough
1179 * make the skb non-linear with a fragment list of pages.
1180 *
1181 * It appears the hardware has a bug in the FIFO logic that
1182 * cause it to hang if the FIFO gets overrun and the receive buffer
1183 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1184 * aligned except if slab debugging is enabled.
1185 */
1186 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1187 {
1188 struct sk_buff *skb;
1189 unsigned long p;
1190 int i;
1191
1192 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1193 if (!skb)
1194 goto nomem;
1195
1196 p = (unsigned long) skb->data;
1197 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1198
1199 for (i = 0; i < sky2->rx_nfrags; i++) {
1200 struct page *page = alloc_page(GFP_ATOMIC);
1201
1202 if (!page)
1203 goto free_partial;
1204 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1205 }
1206
1207 return skb;
1208 free_partial:
1209 kfree_skb(skb);
1210 nomem:
1211 return NULL;
1212 }
1213
1214 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1215 {
1216 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1217 }
1218
1219 /*
1220 * Allocate and setup receiver buffer pool.
1221 * Normal case this ends up creating one list element for skb
1222 * in the receive ring. Worst case if using large MTU and each
1223 * allocation falls on a different 64 bit region, that results
1224 * in 6 list elements per ring entry.
1225 * One element is used for checksum enable/disable, and one
1226 * extra to avoid wrap.
1227 */
1228 static int sky2_rx_start(struct sky2_port *sky2)
1229 {
1230 struct sky2_hw *hw = sky2->hw;
1231 struct rx_ring_info *re;
1232 unsigned rxq = rxqaddr[sky2->port];
1233 unsigned i, size, space, thresh;
1234
1235 sky2->rx_put = sky2->rx_next = 0;
1236 sky2_qset(hw, rxq);
1237
1238 /* On PCI express lowering the watermark gives better performance */
1239 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1240 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1241
1242 /* These chips have no ram buffer?
1243 * MAC Rx RAM Read is controlled by hardware */
1244 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1245 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1246 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1247 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1248
1249 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1250
1251 if (!(hw->flags & SKY2_HW_NEW_LE))
1252 rx_set_checksum(sky2);
1253
1254 /* Space needed for frame data + headers rounded up */
1255 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1256
1257 /* Stopping point for hardware truncation */
1258 thresh = (size - 8) / sizeof(u32);
1259
1260 /* Account for overhead of skb - to avoid order > 0 allocation */
1261 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1262 + sizeof(struct skb_shared_info);
1263
1264 sky2->rx_nfrags = space >> PAGE_SHIFT;
1265 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1266
1267 if (sky2->rx_nfrags != 0) {
1268 /* Compute residue after pages */
1269 space = sky2->rx_nfrags << PAGE_SHIFT;
1270
1271 if (space < size)
1272 size -= space;
1273 else
1274 size = 0;
1275
1276 /* Optimize to handle small packets and headers */
1277 if (size < copybreak)
1278 size = copybreak;
1279 if (size < ETH_HLEN)
1280 size = ETH_HLEN;
1281 }
1282 sky2->rx_data_size = size;
1283
1284 /* Fill Rx ring */
1285 for (i = 0; i < sky2->rx_pending; i++) {
1286 re = sky2->rx_ring + i;
1287
1288 re->skb = sky2_rx_alloc(sky2);
1289 if (!re->skb)
1290 goto nomem;
1291
1292 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1293 sky2_rx_submit(sky2, re);
1294 }
1295
1296 /*
1297 * The receiver hangs if it receives frames larger than the
1298 * packet buffer. As a workaround, truncate oversize frames, but
1299 * the register is limited to 9 bits, so if you do frames > 2052
1300 * you better get the MTU right!
1301 */
1302 if (thresh > 0x1ff)
1303 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1304 else {
1305 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1306 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1307 }
1308
1309 /* Tell chip about available buffers */
1310 sky2_rx_update(sky2, rxq);
1311 return 0;
1312 nomem:
1313 sky2_rx_clean(sky2);
1314 return -ENOMEM;
1315 }
1316
1317 /* Bring up network interface. */
1318 static int sky2_up(struct net_device *dev)
1319 {
1320 struct sky2_port *sky2 = netdev_priv(dev);
1321 struct sky2_hw *hw = sky2->hw;
1322 unsigned port = sky2->port;
1323 u32 imask, ramsize;
1324 int cap, err = -ENOMEM;
1325 struct net_device *otherdev = hw->dev[sky2->port^1];
1326
1327 /*
1328 * On dual port PCI-X card, there is an problem where status
1329 * can be received out of order due to split transactions
1330 */
1331 if (otherdev && netif_running(otherdev) &&
1332 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1333 u16 cmd;
1334
1335 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1336 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1337 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1338
1339 }
1340
1341 if (netif_msg_ifup(sky2))
1342 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1343
1344 netif_carrier_off(dev);
1345
1346 /* must be power of 2 */
1347 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1348 TX_RING_SIZE *
1349 sizeof(struct sky2_tx_le),
1350 &sky2->tx_le_map);
1351 if (!sky2->tx_le)
1352 goto err_out;
1353
1354 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1355 GFP_KERNEL);
1356 if (!sky2->tx_ring)
1357 goto err_out;
1358
1359 tx_init(sky2);
1360
1361 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1362 &sky2->rx_le_map);
1363 if (!sky2->rx_le)
1364 goto err_out;
1365 memset(sky2->rx_le, 0, RX_LE_BYTES);
1366
1367 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1368 GFP_KERNEL);
1369 if (!sky2->rx_ring)
1370 goto err_out;
1371
1372 sky2_phy_power(hw, port, 1);
1373
1374 sky2_mac_init(hw, port);
1375
1376 /* Register is number of 4K blocks on internal RAM buffer. */
1377 ramsize = sky2_read8(hw, B2_E_0) * 4;
1378 if (ramsize > 0) {
1379 u32 rxspace;
1380
1381 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1382 if (ramsize < 16)
1383 rxspace = ramsize / 2;
1384 else
1385 rxspace = 8 + (2*(ramsize - 16))/3;
1386
1387 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1388 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1389
1390 /* Make sure SyncQ is disabled */
1391 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1392 RB_RST_SET);
1393 }
1394
1395 sky2_qset(hw, txqaddr[port]);
1396
1397 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1398 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1399 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1400
1401 /* Set almost empty threshold */
1402 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1403 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1404 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1405
1406 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1407 TX_RING_SIZE - 1);
1408
1409 err = sky2_rx_start(sky2);
1410 if (err)
1411 goto err_out;
1412
1413 /* Enable interrupts from phy/mac for port */
1414 imask = sky2_read32(hw, B0_IMSK);
1415 imask |= portirq_msk[port];
1416 sky2_write32(hw, B0_IMSK, imask);
1417
1418 return 0;
1419
1420 err_out:
1421 if (sky2->rx_le) {
1422 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1423 sky2->rx_le, sky2->rx_le_map);
1424 sky2->rx_le = NULL;
1425 }
1426 if (sky2->tx_le) {
1427 pci_free_consistent(hw->pdev,
1428 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1429 sky2->tx_le, sky2->tx_le_map);
1430 sky2->tx_le = NULL;
1431 }
1432 kfree(sky2->tx_ring);
1433 kfree(sky2->rx_ring);
1434
1435 sky2->tx_ring = NULL;
1436 sky2->rx_ring = NULL;
1437 return err;
1438 }
1439
1440 /* Modular subtraction in ring */
1441 static inline int tx_dist(unsigned tail, unsigned head)
1442 {
1443 return (head - tail) & (TX_RING_SIZE - 1);
1444 }
1445
1446 /* Number of list elements available for next tx */
1447 static inline int tx_avail(const struct sky2_port *sky2)
1448 {
1449 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1450 }
1451
1452 /* Estimate of number of transmit list elements required */
1453 static unsigned tx_le_req(const struct sk_buff *skb)
1454 {
1455 unsigned count;
1456
1457 count = sizeof(dma_addr_t) / sizeof(u32);
1458 count += skb_shinfo(skb)->nr_frags * count;
1459
1460 if (skb_is_gso(skb))
1461 ++count;
1462
1463 if (skb->ip_summed == CHECKSUM_PARTIAL)
1464 ++count;
1465
1466 return count;
1467 }
1468
1469 /*
1470 * Put one packet in ring for transmit.
1471 * A single packet can generate multiple list elements, and
1472 * the number of ring elements will probably be less than the number
1473 * of list elements used.
1474 */
1475 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1476 {
1477 struct sky2_port *sky2 = netdev_priv(dev);
1478 struct sky2_hw *hw = sky2->hw;
1479 struct sky2_tx_le *le = NULL;
1480 struct tx_ring_info *re;
1481 unsigned i, len;
1482 dma_addr_t mapping;
1483 u32 addr64;
1484 u16 mss;
1485 u8 ctrl;
1486
1487 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1488 return NETDEV_TX_BUSY;
1489
1490 if (unlikely(netif_msg_tx_queued(sky2)))
1491 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1492 dev->name, sky2->tx_prod, skb->len);
1493
1494 len = skb_headlen(skb);
1495 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1496 addr64 = upper_32_bits(mapping);
1497
1498 /* Send high bits if changed or crosses boundary */
1499 if (addr64 != sky2->tx_addr64 ||
1500 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1501 le = get_tx_le(sky2);
1502 le->addr = cpu_to_le32(addr64);
1503 le->opcode = OP_ADDR64 | HW_OWNER;
1504 sky2->tx_addr64 = upper_32_bits(mapping + len);
1505 }
1506
1507 /* Check for TCP Segmentation Offload */
1508 mss = skb_shinfo(skb)->gso_size;
1509 if (mss != 0) {
1510
1511 if (!(hw->flags & SKY2_HW_NEW_LE))
1512 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1513
1514 if (mss != sky2->tx_last_mss) {
1515 le = get_tx_le(sky2);
1516 le->addr = cpu_to_le32(mss);
1517
1518 if (hw->flags & SKY2_HW_NEW_LE)
1519 le->opcode = OP_MSS | HW_OWNER;
1520 else
1521 le->opcode = OP_LRGLEN | HW_OWNER;
1522 sky2->tx_last_mss = mss;
1523 }
1524 }
1525
1526 ctrl = 0;
1527 #ifdef SKY2_VLAN_TAG_USED
1528 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1529 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1530 if (!le) {
1531 le = get_tx_le(sky2);
1532 le->addr = 0;
1533 le->opcode = OP_VLAN|HW_OWNER;
1534 } else
1535 le->opcode |= OP_VLAN;
1536 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1537 ctrl |= INS_VLAN;
1538 }
1539 #endif
1540
1541 /* Handle TCP checksum offload */
1542 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1543 /* On Yukon EX (some versions) encoding change. */
1544 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1545 ctrl |= CALSUM; /* auto checksum */
1546 else {
1547 const unsigned offset = skb_transport_offset(skb);
1548 u32 tcpsum;
1549
1550 tcpsum = offset << 16; /* sum start */
1551 tcpsum |= offset + skb->csum_offset; /* sum write */
1552
1553 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1554 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1555 ctrl |= UDPTCP;
1556
1557 if (tcpsum != sky2->tx_tcpsum) {
1558 sky2->tx_tcpsum = tcpsum;
1559
1560 le = get_tx_le(sky2);
1561 le->addr = cpu_to_le32(tcpsum);
1562 le->length = 0; /* initial checksum value */
1563 le->ctrl = 1; /* one packet */
1564 le->opcode = OP_TCPLISW | HW_OWNER;
1565 }
1566 }
1567 }
1568
1569 le = get_tx_le(sky2);
1570 le->addr = cpu_to_le32((u32) mapping);
1571 le->length = cpu_to_le16(len);
1572 le->ctrl = ctrl;
1573 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1574
1575 re = tx_le_re(sky2, le);
1576 re->skb = skb;
1577 pci_unmap_addr_set(re, mapaddr, mapping);
1578 pci_unmap_len_set(re, maplen, len);
1579
1580 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1581 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1582
1583 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1584 frag->size, PCI_DMA_TODEVICE);
1585 addr64 = upper_32_bits(mapping);
1586 if (addr64 != sky2->tx_addr64) {
1587 le = get_tx_le(sky2);
1588 le->addr = cpu_to_le32(addr64);
1589 le->ctrl = 0;
1590 le->opcode = OP_ADDR64 | HW_OWNER;
1591 sky2->tx_addr64 = addr64;
1592 }
1593
1594 le = get_tx_le(sky2);
1595 le->addr = cpu_to_le32((u32) mapping);
1596 le->length = cpu_to_le16(frag->size);
1597 le->ctrl = ctrl;
1598 le->opcode = OP_BUFFER | HW_OWNER;
1599
1600 re = tx_le_re(sky2, le);
1601 re->skb = skb;
1602 pci_unmap_addr_set(re, mapaddr, mapping);
1603 pci_unmap_len_set(re, maplen, frag->size);
1604 }
1605
1606 le->ctrl |= EOP;
1607
1608 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1609 netif_stop_queue(dev);
1610
1611 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1612
1613 dev->trans_start = jiffies;
1614 return NETDEV_TX_OK;
1615 }
1616
1617 /*
1618 * Free ring elements from starting at tx_cons until "done"
1619 *
1620 * NB: the hardware will tell us about partial completion of multi-part
1621 * buffers so make sure not to free skb to early.
1622 */
1623 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1624 {
1625 struct net_device *dev = sky2->netdev;
1626 struct pci_dev *pdev = sky2->hw->pdev;
1627 unsigned idx;
1628
1629 BUG_ON(done >= TX_RING_SIZE);
1630
1631 for (idx = sky2->tx_cons; idx != done;
1632 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1633 struct sky2_tx_le *le = sky2->tx_le + idx;
1634 struct tx_ring_info *re = sky2->tx_ring + idx;
1635
1636 switch(le->opcode & ~HW_OWNER) {
1637 case OP_LARGESEND:
1638 case OP_PACKET:
1639 pci_unmap_single(pdev,
1640 pci_unmap_addr(re, mapaddr),
1641 pci_unmap_len(re, maplen),
1642 PCI_DMA_TODEVICE);
1643 break;
1644 case OP_BUFFER:
1645 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1646 pci_unmap_len(re, maplen),
1647 PCI_DMA_TODEVICE);
1648 break;
1649 }
1650
1651 if (le->ctrl & EOP) {
1652 if (unlikely(netif_msg_tx_done(sky2)))
1653 printk(KERN_DEBUG "%s: tx done %u\n",
1654 dev->name, idx);
1655
1656 dev->stats.tx_packets++;
1657 dev->stats.tx_bytes += re->skb->len;
1658
1659 dev_kfree_skb_any(re->skb);
1660 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1661 }
1662 }
1663
1664 sky2->tx_cons = idx;
1665 smp_mb();
1666
1667 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1668 netif_wake_queue(dev);
1669 }
1670
1671 /* Cleanup all untransmitted buffers, assume transmitter not running */
1672 static void sky2_tx_clean(struct net_device *dev)
1673 {
1674 struct sky2_port *sky2 = netdev_priv(dev);
1675
1676 netif_tx_lock_bh(dev);
1677 sky2_tx_complete(sky2, sky2->tx_prod);
1678 netif_tx_unlock_bh(dev);
1679 }
1680
1681 /* Network shutdown */
1682 static int sky2_down(struct net_device *dev)
1683 {
1684 struct sky2_port *sky2 = netdev_priv(dev);
1685 struct sky2_hw *hw = sky2->hw;
1686 unsigned port = sky2->port;
1687 u16 ctrl;
1688 u32 imask;
1689
1690 /* Never really got started! */
1691 if (!sky2->tx_le)
1692 return 0;
1693
1694 if (netif_msg_ifdown(sky2))
1695 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1696
1697 /* Stop more packets from being queued */
1698 netif_stop_queue(dev);
1699
1700 /* Disable port IRQ */
1701 imask = sky2_read32(hw, B0_IMSK);
1702 imask &= ~portirq_msk[port];
1703 sky2_write32(hw, B0_IMSK, imask);
1704
1705 synchronize_irq(hw->pdev->irq);
1706
1707 sky2_gmac_reset(hw, port);
1708
1709 /* Stop transmitter */
1710 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1711 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1712
1713 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1714 RB_RST_SET | RB_DIS_OP_MD);
1715
1716 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1717 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1718 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1719
1720 /* Make sure no packets are pending */
1721 napi_synchronize(&hw->napi);
1722
1723 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1724
1725 /* Workaround shared GMAC reset */
1726 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1727 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1728 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1729
1730 /* Disable Force Sync bit and Enable Alloc bit */
1731 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1732 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1733
1734 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1735 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1736 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1737
1738 /* Reset the PCI FIFO of the async Tx queue */
1739 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1740 BMU_RST_SET | BMU_FIFO_RST);
1741
1742 /* Reset the Tx prefetch units */
1743 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1744 PREF_UNIT_RST_SET);
1745
1746 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1747
1748 sky2_rx_stop(sky2);
1749
1750 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1751 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1752
1753 sky2_phy_power(hw, port, 0);
1754
1755 netif_carrier_off(dev);
1756
1757 /* turn off LED's */
1758 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1759
1760 sky2_tx_clean(dev);
1761 sky2_rx_clean(sky2);
1762
1763 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1764 sky2->rx_le, sky2->rx_le_map);
1765 kfree(sky2->rx_ring);
1766
1767 pci_free_consistent(hw->pdev,
1768 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1769 sky2->tx_le, sky2->tx_le_map);
1770 kfree(sky2->tx_ring);
1771
1772 sky2->tx_le = NULL;
1773 sky2->rx_le = NULL;
1774
1775 sky2->rx_ring = NULL;
1776 sky2->tx_ring = NULL;
1777
1778 return 0;
1779 }
1780
1781 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1782 {
1783 if (hw->flags & SKY2_HW_FIBRE_PHY)
1784 return SPEED_1000;
1785
1786 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1787 if (aux & PHY_M_PS_SPEED_100)
1788 return SPEED_100;
1789 else
1790 return SPEED_10;
1791 }
1792
1793 switch (aux & PHY_M_PS_SPEED_MSK) {
1794 case PHY_M_PS_SPEED_1000:
1795 return SPEED_1000;
1796 case PHY_M_PS_SPEED_100:
1797 return SPEED_100;
1798 default:
1799 return SPEED_10;
1800 }
1801 }
1802
1803 static void sky2_link_up(struct sky2_port *sky2)
1804 {
1805 struct sky2_hw *hw = sky2->hw;
1806 unsigned port = sky2->port;
1807 u16 reg;
1808 static const char *fc_name[] = {
1809 [FC_NONE] = "none",
1810 [FC_TX] = "tx",
1811 [FC_RX] = "rx",
1812 [FC_BOTH] = "both",
1813 };
1814
1815 /* enable Rx/Tx */
1816 reg = gma_read16(hw, port, GM_GP_CTRL);
1817 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1818 gma_write16(hw, port, GM_GP_CTRL, reg);
1819
1820 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1821
1822 netif_carrier_on(sky2->netdev);
1823
1824 mod_timer(&hw->watchdog_timer, jiffies + 1);
1825
1826 /* Turn on link LED */
1827 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1828 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1829
1830 if (netif_msg_link(sky2))
1831 printk(KERN_INFO PFX
1832 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1833 sky2->netdev->name, sky2->speed,
1834 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1835 fc_name[sky2->flow_status]);
1836 }
1837
1838 static void sky2_link_down(struct sky2_port *sky2)
1839 {
1840 struct sky2_hw *hw = sky2->hw;
1841 unsigned port = sky2->port;
1842 u16 reg;
1843
1844 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1845
1846 reg = gma_read16(hw, port, GM_GP_CTRL);
1847 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1848 gma_write16(hw, port, GM_GP_CTRL, reg);
1849
1850 netif_carrier_off(sky2->netdev);
1851
1852 /* Turn on link LED */
1853 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1854
1855 if (netif_msg_link(sky2))
1856 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1857
1858 sky2_phy_init(hw, port);
1859 }
1860
1861 static enum flow_control sky2_flow(int rx, int tx)
1862 {
1863 if (rx)
1864 return tx ? FC_BOTH : FC_RX;
1865 else
1866 return tx ? FC_TX : FC_NONE;
1867 }
1868
1869 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1870 {
1871 struct sky2_hw *hw = sky2->hw;
1872 unsigned port = sky2->port;
1873 u16 advert, lpa;
1874
1875 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1876 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1877 if (lpa & PHY_M_AN_RF) {
1878 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1879 return -1;
1880 }
1881
1882 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1883 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1884 sky2->netdev->name);
1885 return -1;
1886 }
1887
1888 sky2->speed = sky2_phy_speed(hw, aux);
1889 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1890
1891 /* Since the pause result bits seem to in different positions on
1892 * different chips. look at registers.
1893 */
1894 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1895 /* Shift for bits in fiber PHY */
1896 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1897 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1898
1899 if (advert & ADVERTISE_1000XPAUSE)
1900 advert |= ADVERTISE_PAUSE_CAP;
1901 if (advert & ADVERTISE_1000XPSE_ASYM)
1902 advert |= ADVERTISE_PAUSE_ASYM;
1903 if (lpa & LPA_1000XPAUSE)
1904 lpa |= LPA_PAUSE_CAP;
1905 if (lpa & LPA_1000XPAUSE_ASYM)
1906 lpa |= LPA_PAUSE_ASYM;
1907 }
1908
1909 sky2->flow_status = FC_NONE;
1910 if (advert & ADVERTISE_PAUSE_CAP) {
1911 if (lpa & LPA_PAUSE_CAP)
1912 sky2->flow_status = FC_BOTH;
1913 else if (advert & ADVERTISE_PAUSE_ASYM)
1914 sky2->flow_status = FC_RX;
1915 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1916 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1917 sky2->flow_status = FC_TX;
1918 }
1919
1920 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1921 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1922 sky2->flow_status = FC_NONE;
1923
1924 if (sky2->flow_status & FC_TX)
1925 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1926 else
1927 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1928
1929 return 0;
1930 }
1931
1932 /* Interrupt from PHY */
1933 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1934 {
1935 struct net_device *dev = hw->dev[port];
1936 struct sky2_port *sky2 = netdev_priv(dev);
1937 u16 istatus, phystat;
1938
1939 if (!netif_running(dev))
1940 return;
1941
1942 spin_lock(&sky2->phy_lock);
1943 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1944 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1945
1946 if (netif_msg_intr(sky2))
1947 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1948 sky2->netdev->name, istatus, phystat);
1949
1950 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1951 if (sky2_autoneg_done(sky2, phystat) == 0)
1952 sky2_link_up(sky2);
1953 goto out;
1954 }
1955
1956 if (istatus & PHY_M_IS_LSP_CHANGE)
1957 sky2->speed = sky2_phy_speed(hw, phystat);
1958
1959 if (istatus & PHY_M_IS_DUP_CHANGE)
1960 sky2->duplex =
1961 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1962
1963 if (istatus & PHY_M_IS_LST_CHANGE) {
1964 if (phystat & PHY_M_PS_LINK_UP)
1965 sky2_link_up(sky2);
1966 else
1967 sky2_link_down(sky2);
1968 }
1969 out:
1970 spin_unlock(&sky2->phy_lock);
1971 }
1972
1973 /* Transmit timeout is only called if we are running, carrier is up
1974 * and tx queue is full (stopped).
1975 */
1976 static void sky2_tx_timeout(struct net_device *dev)
1977 {
1978 struct sky2_port *sky2 = netdev_priv(dev);
1979 struct sky2_hw *hw = sky2->hw;
1980
1981 if (netif_msg_timer(sky2))
1982 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1983
1984 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1985 dev->name, sky2->tx_cons, sky2->tx_prod,
1986 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1987 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1988
1989 /* can't restart safely under softirq */
1990 schedule_work(&hw->restart_work);
1991 }
1992
1993 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1994 {
1995 struct sky2_port *sky2 = netdev_priv(dev);
1996 struct sky2_hw *hw = sky2->hw;
1997 unsigned port = sky2->port;
1998 int err;
1999 u16 ctl, mode;
2000 u32 imask;
2001
2002 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2003 return -EINVAL;
2004
2005 if (new_mtu > ETH_DATA_LEN &&
2006 (hw->chip_id == CHIP_ID_YUKON_FE ||
2007 hw->chip_id == CHIP_ID_YUKON_FE_P))
2008 return -EINVAL;
2009
2010 if (!netif_running(dev)) {
2011 dev->mtu = new_mtu;
2012 return 0;
2013 }
2014
2015 imask = sky2_read32(hw, B0_IMSK);
2016 sky2_write32(hw, B0_IMSK, 0);
2017
2018 dev->trans_start = jiffies; /* prevent tx timeout */
2019 netif_stop_queue(dev);
2020 napi_disable(&hw->napi);
2021
2022 synchronize_irq(hw->pdev->irq);
2023
2024 if (sky2_read8(hw, B2_E_0) == 0)
2025 sky2_set_tx_stfwd(hw, port);
2026
2027 ctl = gma_read16(hw, port, GM_GP_CTRL);
2028 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2029 sky2_rx_stop(sky2);
2030 sky2_rx_clean(sky2);
2031
2032 dev->mtu = new_mtu;
2033
2034 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2035 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2036
2037 if (dev->mtu > ETH_DATA_LEN)
2038 mode |= GM_SMOD_JUMBO_ENA;
2039
2040 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2041
2042 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2043
2044 err = sky2_rx_start(sky2);
2045 sky2_write32(hw, B0_IMSK, imask);
2046
2047 sky2_read32(hw, B0_Y2_SP_LISR);
2048 napi_enable(&hw->napi);
2049
2050 if (err)
2051 dev_close(dev);
2052 else {
2053 gma_write16(hw, port, GM_GP_CTRL, ctl);
2054
2055 netif_wake_queue(dev);
2056 }
2057
2058 return err;
2059 }
2060
2061 /* For small just reuse existing skb for next receive */
2062 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2063 const struct rx_ring_info *re,
2064 unsigned length)
2065 {
2066 struct sk_buff *skb;
2067
2068 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2069 if (likely(skb)) {
2070 skb_reserve(skb, 2);
2071 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2072 length, PCI_DMA_FROMDEVICE);
2073 skb_copy_from_linear_data(re->skb, skb->data, length);
2074 skb->ip_summed = re->skb->ip_summed;
2075 skb->csum = re->skb->csum;
2076 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2077 length, PCI_DMA_FROMDEVICE);
2078 re->skb->ip_summed = CHECKSUM_NONE;
2079 skb_put(skb, length);
2080 }
2081 return skb;
2082 }
2083
2084 /* Adjust length of skb with fragments to match received data */
2085 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2086 unsigned int length)
2087 {
2088 int i, num_frags;
2089 unsigned int size;
2090
2091 /* put header into skb */
2092 size = min(length, hdr_space);
2093 skb->tail += size;
2094 skb->len += size;
2095 length -= size;
2096
2097 num_frags = skb_shinfo(skb)->nr_frags;
2098 for (i = 0; i < num_frags; i++) {
2099 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2100
2101 if (length == 0) {
2102 /* don't need this page */
2103 __free_page(frag->page);
2104 --skb_shinfo(skb)->nr_frags;
2105 } else {
2106 size = min(length, (unsigned) PAGE_SIZE);
2107
2108 frag->size = size;
2109 skb->data_len += size;
2110 skb->truesize += size;
2111 skb->len += size;
2112 length -= size;
2113 }
2114 }
2115 }
2116
2117 /* Normal packet - take skb from ring element and put in a new one */
2118 static struct sk_buff *receive_new(struct sky2_port *sky2,
2119 struct rx_ring_info *re,
2120 unsigned int length)
2121 {
2122 struct sk_buff *skb, *nskb;
2123 unsigned hdr_space = sky2->rx_data_size;
2124
2125 /* Don't be tricky about reusing pages (yet) */
2126 nskb = sky2_rx_alloc(sky2);
2127 if (unlikely(!nskb))
2128 return NULL;
2129
2130 skb = re->skb;
2131 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2132
2133 prefetch(skb->data);
2134 re->skb = nskb;
2135 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2136
2137 if (skb_shinfo(skb)->nr_frags)
2138 skb_put_frags(skb, hdr_space, length);
2139 else
2140 skb_put(skb, length);
2141 return skb;
2142 }
2143
2144 /*
2145 * Receive one packet.
2146 * For larger packets, get new buffer.
2147 */
2148 static struct sk_buff *sky2_receive(struct net_device *dev,
2149 u16 length, u32 status)
2150 {
2151 struct sky2_port *sky2 = netdev_priv(dev);
2152 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2153 struct sk_buff *skb = NULL;
2154 u16 count = (status & GMR_FS_LEN) >> 16;
2155
2156 #ifdef SKY2_VLAN_TAG_USED
2157 /* Account for vlan tag */
2158 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2159 count -= VLAN_HLEN;
2160 #endif
2161
2162 if (unlikely(netif_msg_rx_status(sky2)))
2163 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2164 dev->name, sky2->rx_next, status, length);
2165
2166 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2167 prefetch(sky2->rx_ring + sky2->rx_next);
2168
2169 /* This chip has hardware problems that generates bogus status.
2170 * So do only marginal checking and expect higher level protocols
2171 * to handle crap frames.
2172 */
2173 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2174 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2175 length != count)
2176 goto okay;
2177
2178 if (status & GMR_FS_ANY_ERR)
2179 goto error;
2180
2181 if (!(status & GMR_FS_RX_OK))
2182 goto resubmit;
2183
2184 /* if length reported by DMA does not match PHY, packet was truncated */
2185 if (length != count)
2186 goto len_error;
2187
2188 okay:
2189 if (length < copybreak)
2190 skb = receive_copy(sky2, re, length);
2191 else
2192 skb = receive_new(sky2, re, length);
2193 resubmit:
2194 sky2_rx_submit(sky2, re);
2195
2196 return skb;
2197
2198 len_error:
2199 /* Truncation of overlength packets
2200 causes PHY length to not match MAC length */
2201 ++dev->stats.rx_length_errors;
2202 if (netif_msg_rx_err(sky2) && net_ratelimit())
2203 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2204 dev->name, status, length);
2205 goto resubmit;
2206
2207 error:
2208 ++dev->stats.rx_errors;
2209 if (status & GMR_FS_RX_FF_OV) {
2210 dev->stats.rx_over_errors++;
2211 goto resubmit;
2212 }
2213
2214 if (netif_msg_rx_err(sky2) && net_ratelimit())
2215 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2216 dev->name, status, length);
2217
2218 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2219 dev->stats.rx_length_errors++;
2220 if (status & GMR_FS_FRAGMENT)
2221 dev->stats.rx_frame_errors++;
2222 if (status & GMR_FS_CRC_ERR)
2223 dev->stats.rx_crc_errors++;
2224
2225 goto resubmit;
2226 }
2227
2228 /* Transmit complete */
2229 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2230 {
2231 struct sky2_port *sky2 = netdev_priv(dev);
2232
2233 if (netif_running(dev)) {
2234 netif_tx_lock(dev);
2235 sky2_tx_complete(sky2, last);
2236 netif_tx_unlock(dev);
2237 }
2238 }
2239
2240 /* Process status response ring */
2241 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2242 {
2243 int work_done = 0;
2244 unsigned rx[2] = { 0, 0 };
2245
2246 rmb();
2247 do {
2248 struct sky2_port *sky2;
2249 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2250 unsigned port;
2251 struct net_device *dev;
2252 struct sk_buff *skb;
2253 u32 status;
2254 u16 length;
2255 u8 opcode = le->opcode;
2256
2257 if (!(opcode & HW_OWNER))
2258 break;
2259
2260 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2261
2262 port = le->css & CSS_LINK_BIT;
2263 dev = hw->dev[port];
2264 sky2 = netdev_priv(dev);
2265 length = le16_to_cpu(le->length);
2266 status = le32_to_cpu(le->status);
2267
2268 le->opcode = 0;
2269 switch (opcode & ~HW_OWNER) {
2270 case OP_RXSTAT:
2271 ++rx[port];
2272 skb = sky2_receive(dev, length, status);
2273 if (unlikely(!skb)) {
2274 dev->stats.rx_dropped++;
2275 break;
2276 }
2277
2278 /* This chip reports checksum status differently */
2279 if (hw->flags & SKY2_HW_NEW_LE) {
2280 if (sky2->rx_csum &&
2281 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2282 (le->css & CSS_TCPUDPCSOK))
2283 skb->ip_summed = CHECKSUM_UNNECESSARY;
2284 else
2285 skb->ip_summed = CHECKSUM_NONE;
2286 }
2287
2288 skb->protocol = eth_type_trans(skb, dev);
2289 dev->stats.rx_packets++;
2290 dev->stats.rx_bytes += skb->len;
2291 dev->last_rx = jiffies;
2292
2293 #ifdef SKY2_VLAN_TAG_USED
2294 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2295 vlan_hwaccel_receive_skb(skb,
2296 sky2->vlgrp,
2297 be16_to_cpu(sky2->rx_tag));
2298 } else
2299 #endif
2300 netif_receive_skb(skb);
2301
2302 /* Stop after net poll weight */
2303 if (++work_done >= to_do)
2304 goto exit_loop;
2305 break;
2306
2307 #ifdef SKY2_VLAN_TAG_USED
2308 case OP_RXVLAN:
2309 sky2->rx_tag = length;
2310 break;
2311
2312 case OP_RXCHKSVLAN:
2313 sky2->rx_tag = length;
2314 /* fall through */
2315 #endif
2316 case OP_RXCHKS:
2317 if (!sky2->rx_csum)
2318 break;
2319
2320 /* If this happens then driver assuming wrong format */
2321 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2322 if (net_ratelimit())
2323 printk(KERN_NOTICE "%s: unexpected"
2324 " checksum status\n",
2325 dev->name);
2326 break;
2327 }
2328
2329 /* Both checksum counters are programmed to start at
2330 * the same offset, so unless there is a problem they
2331 * should match. This failure is an early indication that
2332 * hardware receive checksumming won't work.
2333 */
2334 if (likely(status >> 16 == (status & 0xffff))) {
2335 skb = sky2->rx_ring[sky2->rx_next].skb;
2336 skb->ip_summed = CHECKSUM_COMPLETE;
2337 skb->csum = status & 0xffff;
2338 } else {
2339 printk(KERN_NOTICE PFX "%s: hardware receive "
2340 "checksum problem (status = %#x)\n",
2341 dev->name, status);
2342 sky2->rx_csum = 0;
2343 sky2_write32(sky2->hw,
2344 Q_ADDR(rxqaddr[port], Q_CSR),
2345 BMU_DIS_RX_CHKSUM);
2346 }
2347 break;
2348
2349 case OP_TXINDEXLE:
2350 /* TX index reports status for both ports */
2351 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2352 sky2_tx_done(hw->dev[0], status & 0xfff);
2353 if (hw->dev[1])
2354 sky2_tx_done(hw->dev[1],
2355 ((status >> 24) & 0xff)
2356 | (u16)(length & 0xf) << 8);
2357 break;
2358
2359 default:
2360 if (net_ratelimit())
2361 printk(KERN_WARNING PFX
2362 "unknown status opcode 0x%x\n", opcode);
2363 }
2364 } while (hw->st_idx != idx);
2365
2366 /* Fully processed status ring so clear irq */
2367 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2368
2369 exit_loop:
2370 if (rx[0])
2371 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2372
2373 if (rx[1])
2374 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2375
2376 return work_done;
2377 }
2378
2379 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2380 {
2381 struct net_device *dev = hw->dev[port];
2382
2383 if (net_ratelimit())
2384 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2385 dev->name, status);
2386
2387 if (status & Y2_IS_PAR_RD1) {
2388 if (net_ratelimit())
2389 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2390 dev->name);
2391 /* Clear IRQ */
2392 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2393 }
2394
2395 if (status & Y2_IS_PAR_WR1) {
2396 if (net_ratelimit())
2397 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2398 dev->name);
2399
2400 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2401 }
2402
2403 if (status & Y2_IS_PAR_MAC1) {
2404 if (net_ratelimit())
2405 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2407 }
2408
2409 if (status & Y2_IS_PAR_RX1) {
2410 if (net_ratelimit())
2411 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2412 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2413 }
2414
2415 if (status & Y2_IS_TCP_TXA1) {
2416 if (net_ratelimit())
2417 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2418 dev->name);
2419 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2420 }
2421 }
2422
2423 static void sky2_hw_intr(struct sky2_hw *hw)
2424 {
2425 struct pci_dev *pdev = hw->pdev;
2426 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2427 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2428
2429 status &= hwmsk;
2430
2431 if (status & Y2_IS_TIST_OV)
2432 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2433
2434 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2435 u16 pci_err;
2436
2437 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2438 if (net_ratelimit())
2439 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2440 pci_err);
2441
2442 sky2_pci_write16(hw, PCI_STATUS,
2443 pci_err | PCI_STATUS_ERROR_BITS);
2444 }
2445
2446 if (status & Y2_IS_PCI_EXP) {
2447 /* PCI-Express uncorrectable Error occurred */
2448 u32 err;
2449
2450 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2451 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2452 0xfffffffful);
2453 if (net_ratelimit())
2454 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2455
2456 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2457 }
2458
2459 if (status & Y2_HWE_L1_MASK)
2460 sky2_hw_error(hw, 0, status);
2461 status >>= 8;
2462 if (status & Y2_HWE_L1_MASK)
2463 sky2_hw_error(hw, 1, status);
2464 }
2465
2466 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2467 {
2468 struct net_device *dev = hw->dev[port];
2469 struct sky2_port *sky2 = netdev_priv(dev);
2470 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2471
2472 if (netif_msg_intr(sky2))
2473 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2474 dev->name, status);
2475
2476 if (status & GM_IS_RX_CO_OV)
2477 gma_read16(hw, port, GM_RX_IRQ_SRC);
2478
2479 if (status & GM_IS_TX_CO_OV)
2480 gma_read16(hw, port, GM_TX_IRQ_SRC);
2481
2482 if (status & GM_IS_RX_FF_OR) {
2483 ++dev->stats.rx_fifo_errors;
2484 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2485 }
2486
2487 if (status & GM_IS_TX_FF_UR) {
2488 ++dev->stats.tx_fifo_errors;
2489 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2490 }
2491 }
2492
2493 /* This should never happen it is a bug. */
2494 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2495 u16 q, unsigned ring_size)
2496 {
2497 struct net_device *dev = hw->dev[port];
2498 struct sky2_port *sky2 = netdev_priv(dev);
2499 unsigned idx;
2500 const u64 *le = (q == Q_R1 || q == Q_R2)
2501 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2502
2503 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2504 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2505 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2506 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2507
2508 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2509 }
2510
2511 static int sky2_rx_hung(struct net_device *dev)
2512 {
2513 struct sky2_port *sky2 = netdev_priv(dev);
2514 struct sky2_hw *hw = sky2->hw;
2515 unsigned port = sky2->port;
2516 unsigned rxq = rxqaddr[port];
2517 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2518 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2519 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2520 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2521
2522 /* If idle and MAC or PCI is stuck */
2523 if (sky2->check.last == dev->last_rx &&
2524 ((mac_rp == sky2->check.mac_rp &&
2525 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2526 /* Check if the PCI RX hang */
2527 (fifo_rp == sky2->check.fifo_rp &&
2528 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2529 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2530 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2531 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2532 return 1;
2533 } else {
2534 sky2->check.last = dev->last_rx;
2535 sky2->check.mac_rp = mac_rp;
2536 sky2->check.mac_lev = mac_lev;
2537 sky2->check.fifo_rp = fifo_rp;
2538 sky2->check.fifo_lev = fifo_lev;
2539 return 0;
2540 }
2541 }
2542
2543 static void sky2_watchdog(unsigned long arg)
2544 {
2545 struct sky2_hw *hw = (struct sky2_hw *) arg;
2546
2547 /* Check for lost IRQ once a second */
2548 if (sky2_read32(hw, B0_ISRC)) {
2549 napi_schedule(&hw->napi);
2550 } else {
2551 int i, active = 0;
2552
2553 for (i = 0; i < hw->ports; i++) {
2554 struct net_device *dev = hw->dev[i];
2555 if (!netif_running(dev))
2556 continue;
2557 ++active;
2558
2559 /* For chips with Rx FIFO, check if stuck */
2560 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2561 sky2_rx_hung(dev)) {
2562 pr_info(PFX "%s: receiver hang detected\n",
2563 dev->name);
2564 schedule_work(&hw->restart_work);
2565 return;
2566 }
2567 }
2568
2569 if (active == 0)
2570 return;
2571 }
2572
2573 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2574 }
2575
2576 /* Hardware/software error handling */
2577 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2578 {
2579 if (net_ratelimit())
2580 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2581
2582 if (status & Y2_IS_HW_ERR)
2583 sky2_hw_intr(hw);
2584
2585 if (status & Y2_IS_IRQ_MAC1)
2586 sky2_mac_intr(hw, 0);
2587
2588 if (status & Y2_IS_IRQ_MAC2)
2589 sky2_mac_intr(hw, 1);
2590
2591 if (status & Y2_IS_CHK_RX1)
2592 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2593
2594 if (status & Y2_IS_CHK_RX2)
2595 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2596
2597 if (status & Y2_IS_CHK_TXA1)
2598 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2599
2600 if (status & Y2_IS_CHK_TXA2)
2601 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2602 }
2603
2604 static int sky2_poll(struct napi_struct *napi, int work_limit)
2605 {
2606 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2607 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2608 int work_done = 0;
2609 u16 idx;
2610
2611 if (unlikely(status & Y2_IS_ERROR))
2612 sky2_err_intr(hw, status);
2613
2614 if (status & Y2_IS_IRQ_PHY1)
2615 sky2_phy_intr(hw, 0);
2616
2617 if (status & Y2_IS_IRQ_PHY2)
2618 sky2_phy_intr(hw, 1);
2619
2620 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2621 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2622
2623 if (work_done >= work_limit)
2624 goto done;
2625 }
2626
2627 /* Bug/Errata workaround?
2628 * Need to kick the TX irq moderation timer.
2629 */
2630 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2631 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2632 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2633 }
2634 napi_complete(napi);
2635 sky2_read32(hw, B0_Y2_SP_LISR);
2636 done:
2637
2638 return work_done;
2639 }
2640
2641 static irqreturn_t sky2_intr(int irq, void *dev_id)
2642 {
2643 struct sky2_hw *hw = dev_id;
2644 u32 status;
2645
2646 /* Reading this mask interrupts as side effect */
2647 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2648 if (status == 0 || status == ~0)
2649 return IRQ_NONE;
2650
2651 prefetch(&hw->st_le[hw->st_idx]);
2652
2653 napi_schedule(&hw->napi);
2654
2655 return IRQ_HANDLED;
2656 }
2657
2658 #ifdef CONFIG_NET_POLL_CONTROLLER
2659 static void sky2_netpoll(struct net_device *dev)
2660 {
2661 struct sky2_port *sky2 = netdev_priv(dev);
2662
2663 napi_schedule(&sky2->hw->napi);
2664 }
2665 #endif
2666
2667 /* Chip internal frequency for clock calculations */
2668 static u32 sky2_mhz(const struct sky2_hw *hw)
2669 {
2670 switch (hw->chip_id) {
2671 case CHIP_ID_YUKON_EC:
2672 case CHIP_ID_YUKON_EC_U:
2673 case CHIP_ID_YUKON_EX:
2674 return 125;
2675
2676 case CHIP_ID_YUKON_FE:
2677 return 100;
2678
2679 case CHIP_ID_YUKON_FE_P:
2680 return 50;
2681
2682 case CHIP_ID_YUKON_XL:
2683 return 156;
2684
2685 default:
2686 BUG();
2687 }
2688 }
2689
2690 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2691 {
2692 return sky2_mhz(hw) * us;
2693 }
2694
2695 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2696 {
2697 return clk / sky2_mhz(hw);
2698 }
2699
2700
2701 static int __devinit sky2_init(struct sky2_hw *hw)
2702 {
2703 u8 t8;
2704
2705 /* Enable all clocks and check for bad PCI access */
2706 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2707
2708 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2709
2710 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2711 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2712
2713 switch(hw->chip_id) {
2714 case CHIP_ID_YUKON_XL:
2715 hw->flags = SKY2_HW_GIGABIT
2716 | SKY2_HW_NEWER_PHY;
2717 if (hw->chip_rev < 3)
2718 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2719
2720 break;
2721
2722 case CHIP_ID_YUKON_EC_U:
2723 hw->flags = SKY2_HW_GIGABIT
2724 | SKY2_HW_NEWER_PHY
2725 | SKY2_HW_ADV_POWER_CTL;
2726 break;
2727
2728 case CHIP_ID_YUKON_EX:
2729 hw->flags = SKY2_HW_GIGABIT
2730 | SKY2_HW_NEWER_PHY
2731 | SKY2_HW_NEW_LE
2732 | SKY2_HW_ADV_POWER_CTL;
2733
2734 /* New transmit checksum */
2735 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2736 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2737 break;
2738
2739 case CHIP_ID_YUKON_EC:
2740 /* This rev is really old, and requires untested workarounds */
2741 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2742 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2743 return -EOPNOTSUPP;
2744 }
2745 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2746 break;
2747
2748 case CHIP_ID_YUKON_FE:
2749 break;
2750
2751 case CHIP_ID_YUKON_FE_P:
2752 hw->flags = SKY2_HW_NEWER_PHY
2753 | SKY2_HW_NEW_LE
2754 | SKY2_HW_AUTO_TX_SUM
2755 | SKY2_HW_ADV_POWER_CTL;
2756 break;
2757 default:
2758 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2759 hw->chip_id);
2760 return -EOPNOTSUPP;
2761 }
2762
2763 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2764 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2765 hw->flags |= SKY2_HW_FIBRE_PHY;
2766
2767
2768 hw->ports = 1;
2769 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2770 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2771 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2772 ++hw->ports;
2773 }
2774
2775 return 0;
2776 }
2777
2778 static void sky2_reset(struct sky2_hw *hw)
2779 {
2780 struct pci_dev *pdev = hw->pdev;
2781 u16 status;
2782 int i, cap;
2783 u32 hwe_mask = Y2_HWE_ALL_MASK;
2784
2785 /* disable ASF */
2786 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2787 status = sky2_read16(hw, HCU_CCSR);
2788 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2789 HCU_CCSR_UC_STATE_MSK);
2790 sky2_write16(hw, HCU_CCSR, status);
2791 } else
2792 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2793 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2794
2795 /* do a SW reset */
2796 sky2_write8(hw, B0_CTST, CS_RST_SET);
2797 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2798
2799 /* allow writes to PCI config */
2800 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2801
2802 /* clear PCI errors, if any */
2803 status = sky2_pci_read16(hw, PCI_STATUS);
2804 status |= PCI_STATUS_ERROR_BITS;
2805 sky2_pci_write16(hw, PCI_STATUS, status);
2806
2807 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2808
2809 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2810 if (cap) {
2811 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2812 0xfffffffful);
2813
2814 /* If error bit is stuck on ignore it */
2815 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2816 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2817 else
2818 hwe_mask |= Y2_IS_PCI_EXP;
2819 }
2820
2821 sky2_power_on(hw);
2822
2823 for (i = 0; i < hw->ports; i++) {
2824 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2825 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2826
2827 if (hw->chip_id == CHIP_ID_YUKON_EX)
2828 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2829 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2830 | GMC_BYP_RETR_ON);
2831 }
2832
2833 /* Clear I2C IRQ noise */
2834 sky2_write32(hw, B2_I2C_IRQ, 1);
2835
2836 /* turn off hardware timer (unused) */
2837 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2838 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2839
2840 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2841
2842 /* Turn off descriptor polling */
2843 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2844
2845 /* Turn off receive timestamp */
2846 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2847 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2848
2849 /* enable the Tx Arbiters */
2850 for (i = 0; i < hw->ports; i++)
2851 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2852
2853 /* Initialize ram interface */
2854 for (i = 0; i < hw->ports; i++) {
2855 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2856
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2862 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2864 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2865 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2867 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2868 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2869 }
2870
2871 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2872
2873 for (i = 0; i < hw->ports; i++)
2874 sky2_gmac_reset(hw, i);
2875
2876 memset(hw->st_le, 0, STATUS_LE_BYTES);
2877 hw->st_idx = 0;
2878
2879 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2880 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2881
2882 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2883 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2884
2885 /* Set the list last index */
2886 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2887
2888 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2889 sky2_write8(hw, STAT_FIFO_WM, 16);
2890
2891 /* set Status-FIFO ISR watermark */
2892 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2893 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2894 else
2895 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2896
2897 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2898 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2899 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2900
2901 /* enable status unit */
2902 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2903
2904 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2905 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2906 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2907 }
2908
2909 static void sky2_restart(struct work_struct *work)
2910 {
2911 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2912 struct net_device *dev;
2913 int i, err;
2914
2915 rtnl_lock();
2916 for (i = 0; i < hw->ports; i++) {
2917 dev = hw->dev[i];
2918 if (netif_running(dev))
2919 sky2_down(dev);
2920 }
2921
2922 napi_disable(&hw->napi);
2923 sky2_write32(hw, B0_IMSK, 0);
2924 sky2_reset(hw);
2925 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2926 napi_enable(&hw->napi);
2927
2928 for (i = 0; i < hw->ports; i++) {
2929 dev = hw->dev[i];
2930 if (netif_running(dev)) {
2931 err = sky2_up(dev);
2932 if (err) {
2933 printk(KERN_INFO PFX "%s: could not restart %d\n",
2934 dev->name, err);
2935 dev_close(dev);
2936 }
2937 }
2938 }
2939
2940 rtnl_unlock();
2941 }
2942
2943 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2944 {
2945 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2946 }
2947
2948 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2949 {
2950 const struct sky2_port *sky2 = netdev_priv(dev);
2951
2952 wol->supported = sky2_wol_supported(sky2->hw);
2953 wol->wolopts = sky2->wol;
2954 }
2955
2956 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2957 {
2958 struct sky2_port *sky2 = netdev_priv(dev);
2959 struct sky2_hw *hw = sky2->hw;
2960
2961 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2962 return -EOPNOTSUPP;
2963
2964 sky2->wol = wol->wolopts;
2965
2966 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2967 hw->chip_id == CHIP_ID_YUKON_EX ||
2968 hw->chip_id == CHIP_ID_YUKON_FE_P)
2969 sky2_write32(hw, B0_CTST, sky2->wol
2970 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2971
2972 if (!netif_running(dev))
2973 sky2_wol_init(sky2);
2974 return 0;
2975 }
2976
2977 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2978 {
2979 if (sky2_is_copper(hw)) {
2980 u32 modes = SUPPORTED_10baseT_Half
2981 | SUPPORTED_10baseT_Full
2982 | SUPPORTED_100baseT_Half
2983 | SUPPORTED_100baseT_Full
2984 | SUPPORTED_Autoneg | SUPPORTED_TP;
2985
2986 if (hw->flags & SKY2_HW_GIGABIT)
2987 modes |= SUPPORTED_1000baseT_Half
2988 | SUPPORTED_1000baseT_Full;
2989 return modes;
2990 } else
2991 return SUPPORTED_1000baseT_Half
2992 | SUPPORTED_1000baseT_Full
2993 | SUPPORTED_Autoneg
2994 | SUPPORTED_FIBRE;
2995 }
2996
2997 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2998 {
2999 struct sky2_port *sky2 = netdev_priv(dev);
3000 struct sky2_hw *hw = sky2->hw;
3001
3002 ecmd->transceiver = XCVR_INTERNAL;
3003 ecmd->supported = sky2_supported_modes(hw);
3004 ecmd->phy_address = PHY_ADDR_MARV;
3005 if (sky2_is_copper(hw)) {
3006 ecmd->port = PORT_TP;
3007 ecmd->speed = sky2->speed;
3008 } else {
3009 ecmd->speed = SPEED_1000;
3010 ecmd->port = PORT_FIBRE;
3011 }
3012
3013 ecmd->advertising = sky2->advertising;
3014 ecmd->autoneg = sky2->autoneg;
3015 ecmd->duplex = sky2->duplex;
3016 return 0;
3017 }
3018
3019 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3020 {
3021 struct sky2_port *sky2 = netdev_priv(dev);
3022 const struct sky2_hw *hw = sky2->hw;
3023 u32 supported = sky2_supported_modes(hw);
3024
3025 if (ecmd->autoneg == AUTONEG_ENABLE) {
3026 ecmd->advertising = supported;
3027 sky2->duplex = -1;
3028 sky2->speed = -1;
3029 } else {
3030 u32 setting;
3031
3032 switch (ecmd->speed) {
3033 case SPEED_1000:
3034 if (ecmd->duplex == DUPLEX_FULL)
3035 setting = SUPPORTED_1000baseT_Full;
3036 else if (ecmd->duplex == DUPLEX_HALF)
3037 setting = SUPPORTED_1000baseT_Half;
3038 else
3039 return -EINVAL;
3040 break;
3041 case SPEED_100:
3042 if (ecmd->duplex == DUPLEX_FULL)
3043 setting = SUPPORTED_100baseT_Full;
3044 else if (ecmd->duplex == DUPLEX_HALF)
3045 setting = SUPPORTED_100baseT_Half;
3046 else
3047 return -EINVAL;
3048 break;
3049
3050 case SPEED_10:
3051 if (ecmd->duplex == DUPLEX_FULL)
3052 setting = SUPPORTED_10baseT_Full;
3053 else if (ecmd->duplex == DUPLEX_HALF)
3054 setting = SUPPORTED_10baseT_Half;
3055 else
3056 return -EINVAL;
3057 break;
3058 default:
3059 return -EINVAL;
3060 }
3061
3062 if ((setting & supported) == 0)
3063 return -EINVAL;
3064
3065 sky2->speed = ecmd->speed;
3066 sky2->duplex = ecmd->duplex;
3067 }
3068
3069 sky2->autoneg = ecmd->autoneg;
3070 sky2->advertising = ecmd->advertising;
3071
3072 if (netif_running(dev)) {
3073 sky2_phy_reinit(sky2);
3074 sky2_set_multicast(dev);
3075 }
3076
3077 return 0;
3078 }
3079
3080 static void sky2_get_drvinfo(struct net_device *dev,
3081 struct ethtool_drvinfo *info)
3082 {
3083 struct sky2_port *sky2 = netdev_priv(dev);
3084
3085 strcpy(info->driver, DRV_NAME);
3086 strcpy(info->version, DRV_VERSION);
3087 strcpy(info->fw_version, "N/A");
3088 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3089 }
3090
3091 static const struct sky2_stat {
3092 char name[ETH_GSTRING_LEN];
3093 u16 offset;
3094 } sky2_stats[] = {
3095 { "tx_bytes", GM_TXO_OK_HI },
3096 { "rx_bytes", GM_RXO_OK_HI },
3097 { "tx_broadcast", GM_TXF_BC_OK },
3098 { "rx_broadcast", GM_RXF_BC_OK },
3099 { "tx_multicast", GM_TXF_MC_OK },
3100 { "rx_multicast", GM_RXF_MC_OK },
3101 { "tx_unicast", GM_TXF_UC_OK },
3102 { "rx_unicast", GM_RXF_UC_OK },
3103 { "tx_mac_pause", GM_TXF_MPAUSE },
3104 { "rx_mac_pause", GM_RXF_MPAUSE },
3105 { "collisions", GM_TXF_COL },
3106 { "late_collision",GM_TXF_LAT_COL },
3107 { "aborted", GM_TXF_ABO_COL },
3108 { "single_collisions", GM_TXF_SNG_COL },
3109 { "multi_collisions", GM_TXF_MUL_COL },
3110
3111 { "rx_short", GM_RXF_SHT },
3112 { "rx_runt", GM_RXE_FRAG },
3113 { "rx_64_byte_packets", GM_RXF_64B },
3114 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3115 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3116 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3117 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3118 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3119 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3120 { "rx_too_long", GM_RXF_LNG_ERR },
3121 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3122 { "rx_jabber", GM_RXF_JAB_PKT },
3123 { "rx_fcs_error", GM_RXF_FCS_ERR },
3124
3125 { "tx_64_byte_packets", GM_TXF_64B },
3126 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3127 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3128 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3129 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3130 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3131 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3132 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3133 };
3134
3135 static u32 sky2_get_rx_csum(struct net_device *dev)
3136 {
3137 struct sky2_port *sky2 = netdev_priv(dev);
3138
3139 return sky2->rx_csum;
3140 }
3141
3142 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3143 {
3144 struct sky2_port *sky2 = netdev_priv(dev);
3145
3146 sky2->rx_csum = data;
3147
3148 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3149 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3150
3151 return 0;
3152 }
3153
3154 static u32 sky2_get_msglevel(struct net_device *netdev)
3155 {
3156 struct sky2_port *sky2 = netdev_priv(netdev);
3157 return sky2->msg_enable;
3158 }
3159
3160 static int sky2_nway_reset(struct net_device *dev)
3161 {
3162 struct sky2_port *sky2 = netdev_priv(dev);
3163
3164 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3165 return -EINVAL;
3166
3167 sky2_phy_reinit(sky2);
3168 sky2_set_multicast(dev);
3169
3170 return 0;
3171 }
3172
3173 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3174 {
3175 struct sky2_hw *hw = sky2->hw;
3176 unsigned port = sky2->port;
3177 int i;
3178
3179 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3180 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3181 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3182 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3183
3184 for (i = 2; i < count; i++)
3185 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3186 }
3187
3188 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3189 {
3190 struct sky2_port *sky2 = netdev_priv(netdev);
3191 sky2->msg_enable = value;
3192 }
3193
3194 static int sky2_get_sset_count(struct net_device *dev, int sset)
3195 {
3196 switch (sset) {
3197 case ETH_SS_STATS:
3198 return ARRAY_SIZE(sky2_stats);
3199 default:
3200 return -EOPNOTSUPP;
3201 }
3202 }
3203
3204 static void sky2_get_ethtool_stats(struct net_device *dev,
3205 struct ethtool_stats *stats, u64 * data)
3206 {
3207 struct sky2_port *sky2 = netdev_priv(dev);
3208
3209 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3210 }
3211
3212 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3213 {
3214 int i;
3215
3216 switch (stringset) {
3217 case ETH_SS_STATS:
3218 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3219 memcpy(data + i * ETH_GSTRING_LEN,
3220 sky2_stats[i].name, ETH_GSTRING_LEN);
3221 break;
3222 }
3223 }
3224
3225 static int sky2_set_mac_address(struct net_device *dev, void *p)
3226 {
3227 struct sky2_port *sky2 = netdev_priv(dev);
3228 struct sky2_hw *hw = sky2->hw;
3229 unsigned port = sky2->port;
3230 const struct sockaddr *addr = p;
3231
3232 if (!is_valid_ether_addr(addr->sa_data))
3233 return -EADDRNOTAVAIL;
3234
3235 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3236 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3237 dev->dev_addr, ETH_ALEN);
3238 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3239 dev->dev_addr, ETH_ALEN);
3240
3241 /* virtual address for data */
3242 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3243
3244 /* physical address: used for pause frames */
3245 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3246
3247 return 0;
3248 }
3249
3250 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3251 {
3252 u32 bit;
3253
3254 bit = ether_crc(ETH_ALEN, addr) & 63;
3255 filter[bit >> 3] |= 1 << (bit & 7);
3256 }
3257
3258 static void sky2_set_multicast(struct net_device *dev)
3259 {
3260 struct sky2_port *sky2 = netdev_priv(dev);
3261 struct sky2_hw *hw = sky2->hw;
3262 unsigned port = sky2->port;
3263 struct dev_mc_list *list = dev->mc_list;
3264 u16 reg;
3265 u8 filter[8];
3266 int rx_pause;
3267 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3268
3269 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3270 memset(filter, 0, sizeof(filter));
3271
3272 reg = gma_read16(hw, port, GM_RX_CTRL);
3273 reg |= GM_RXCR_UCF_ENA;
3274
3275 if (dev->flags & IFF_PROMISC) /* promiscuous */
3276 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3277 else if (dev->flags & IFF_ALLMULTI)
3278 memset(filter, 0xff, sizeof(filter));
3279 else if (dev->mc_count == 0 && !rx_pause)
3280 reg &= ~GM_RXCR_MCF_ENA;
3281 else {
3282 int i;
3283 reg |= GM_RXCR_MCF_ENA;
3284
3285 if (rx_pause)
3286 sky2_add_filter(filter, pause_mc_addr);
3287
3288 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3289 sky2_add_filter(filter, list->dmi_addr);
3290 }
3291
3292 gma_write16(hw, port, GM_MC_ADDR_H1,
3293 (u16) filter[0] | ((u16) filter[1] << 8));
3294 gma_write16(hw, port, GM_MC_ADDR_H2,
3295 (u16) filter[2] | ((u16) filter[3] << 8));
3296 gma_write16(hw, port, GM_MC_ADDR_H3,
3297 (u16) filter[4] | ((u16) filter[5] << 8));
3298 gma_write16(hw, port, GM_MC_ADDR_H4,
3299 (u16) filter[6] | ((u16) filter[7] << 8));
3300
3301 gma_write16(hw, port, GM_RX_CTRL, reg);
3302 }
3303
3304 /* Can have one global because blinking is controlled by
3305 * ethtool and that is always under RTNL mutex
3306 */
3307 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3308 {
3309 u16 pg;
3310
3311 switch (hw->chip_id) {
3312 case CHIP_ID_YUKON_XL:
3313 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3314 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3315 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3316 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3317 PHY_M_LEDC_INIT_CTRL(7) |
3318 PHY_M_LEDC_STA1_CTRL(7) |
3319 PHY_M_LEDC_STA0_CTRL(7))
3320 : 0);
3321
3322 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3323 break;
3324
3325 default:
3326 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3327 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3328 on ? PHY_M_LED_ALL : 0);
3329 }
3330 }
3331
3332 /* blink LED's for finding board */
3333 static int sky2_phys_id(struct net_device *dev, u32 data)
3334 {
3335 struct sky2_port *sky2 = netdev_priv(dev);
3336 struct sky2_hw *hw = sky2->hw;
3337 unsigned port = sky2->port;
3338 u16 ledctrl, ledover = 0;
3339 long ms;
3340 int interrupted;
3341 int onoff = 1;
3342
3343 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3344 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3345 else
3346 ms = data * 1000;
3347
3348 /* save initial values */
3349 spin_lock_bh(&sky2->phy_lock);
3350 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3351 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3353 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3355 } else {
3356 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3357 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3358 }
3359
3360 interrupted = 0;
3361 while (!interrupted && ms > 0) {
3362 sky2_led(hw, port, onoff);
3363 onoff = !onoff;
3364
3365 spin_unlock_bh(&sky2->phy_lock);
3366 interrupted = msleep_interruptible(250);
3367 spin_lock_bh(&sky2->phy_lock);
3368
3369 ms -= 250;
3370 }
3371
3372 /* resume regularly scheduled programming */
3373 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3374 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3375 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3376 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3377 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3378 } else {
3379 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3380 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3381 }
3382 spin_unlock_bh(&sky2->phy_lock);
3383
3384 return 0;
3385 }
3386
3387 static void sky2_get_pauseparam(struct net_device *dev,
3388 struct ethtool_pauseparam *ecmd)
3389 {
3390 struct sky2_port *sky2 = netdev_priv(dev);
3391
3392 switch (sky2->flow_mode) {
3393 case FC_NONE:
3394 ecmd->tx_pause = ecmd->rx_pause = 0;
3395 break;
3396 case FC_TX:
3397 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3398 break;
3399 case FC_RX:
3400 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3401 break;
3402 case FC_BOTH:
3403 ecmd->tx_pause = ecmd->rx_pause = 1;
3404 }
3405
3406 ecmd->autoneg = sky2->autoneg;
3407 }
3408
3409 static int sky2_set_pauseparam(struct net_device *dev,
3410 struct ethtool_pauseparam *ecmd)
3411 {
3412 struct sky2_port *sky2 = netdev_priv(dev);
3413
3414 sky2->autoneg = ecmd->autoneg;
3415 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3416
3417 if (netif_running(dev))
3418 sky2_phy_reinit(sky2);
3419
3420 return 0;
3421 }
3422
3423 static int sky2_get_coalesce(struct net_device *dev,
3424 struct ethtool_coalesce *ecmd)
3425 {
3426 struct sky2_port *sky2 = netdev_priv(dev);
3427 struct sky2_hw *hw = sky2->hw;
3428
3429 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3430 ecmd->tx_coalesce_usecs = 0;
3431 else {
3432 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3433 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3434 }
3435 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3436
3437 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3438 ecmd->rx_coalesce_usecs = 0;
3439 else {
3440 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3441 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3442 }
3443 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3444
3445 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3446 ecmd->rx_coalesce_usecs_irq = 0;
3447 else {
3448 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3449 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3450 }
3451
3452 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3453
3454 return 0;
3455 }
3456
3457 /* Note: this affect both ports */
3458 static int sky2_set_coalesce(struct net_device *dev,
3459 struct ethtool_coalesce *ecmd)
3460 {
3461 struct sky2_port *sky2 = netdev_priv(dev);
3462 struct sky2_hw *hw = sky2->hw;
3463 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3464
3465 if (ecmd->tx_coalesce_usecs > tmax ||
3466 ecmd->rx_coalesce_usecs > tmax ||
3467 ecmd->rx_coalesce_usecs_irq > tmax)
3468 return -EINVAL;
3469
3470 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3471 return -EINVAL;
3472 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3473 return -EINVAL;
3474 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3475 return -EINVAL;
3476
3477 if (ecmd->tx_coalesce_usecs == 0)
3478 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3479 else {
3480 sky2_write32(hw, STAT_TX_TIMER_INI,
3481 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3482 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3483 }
3484 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3485
3486 if (ecmd->rx_coalesce_usecs == 0)
3487 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3488 else {
3489 sky2_write32(hw, STAT_LEV_TIMER_INI,
3490 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3491 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3492 }
3493 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3494
3495 if (ecmd->rx_coalesce_usecs_irq == 0)
3496 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3497 else {
3498 sky2_write32(hw, STAT_ISR_TIMER_INI,
3499 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3500 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3501 }
3502 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3503 return 0;
3504 }
3505
3506 static void sky2_get_ringparam(struct net_device *dev,
3507 struct ethtool_ringparam *ering)
3508 {
3509 struct sky2_port *sky2 = netdev_priv(dev);
3510
3511 ering->rx_max_pending = RX_MAX_PENDING;
3512 ering->rx_mini_max_pending = 0;
3513 ering->rx_jumbo_max_pending = 0;
3514 ering->tx_max_pending = TX_RING_SIZE - 1;
3515
3516 ering->rx_pending = sky2->rx_pending;
3517 ering->rx_mini_pending = 0;
3518 ering->rx_jumbo_pending = 0;
3519 ering->tx_pending = sky2->tx_pending;
3520 }
3521
3522 static int sky2_set_ringparam(struct net_device *dev,
3523 struct ethtool_ringparam *ering)
3524 {
3525 struct sky2_port *sky2 = netdev_priv(dev);
3526 int err = 0;
3527
3528 if (ering->rx_pending > RX_MAX_PENDING ||
3529 ering->rx_pending < 8 ||
3530 ering->tx_pending < MAX_SKB_TX_LE ||
3531 ering->tx_pending > TX_RING_SIZE - 1)
3532 return -EINVAL;
3533
3534 if (netif_running(dev))
3535 sky2_down(dev);
3536
3537 sky2->rx_pending = ering->rx_pending;
3538 sky2->tx_pending = ering->tx_pending;
3539
3540 if (netif_running(dev)) {
3541 err = sky2_up(dev);
3542 if (err)
3543 dev_close(dev);
3544 else
3545 sky2_set_multicast(dev);
3546 }
3547
3548 return err;
3549 }
3550
3551 static int sky2_get_regs_len(struct net_device *dev)
3552 {
3553 return 0x4000;
3554 }
3555
3556 /*
3557 * Returns copy of control register region
3558 * Note: ethtool_get_regs always provides full size (16k) buffer
3559 */
3560 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3561 void *p)
3562 {
3563 const struct sky2_port *sky2 = netdev_priv(dev);
3564 const void __iomem *io = sky2->hw->regs;
3565 unsigned int b;
3566
3567 regs->version = 1;
3568
3569 for (b = 0; b < 128; b++) {
3570 /* This complicated switch statement is to make sure and
3571 * only access regions that are unreserved.
3572 * Some blocks are only valid on dual port cards.
3573 * and block 3 has some special diagnostic registers that
3574 * are poison.
3575 */
3576 switch (b) {
3577 case 3:
3578 /* skip diagnostic ram region */
3579 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3580 break;
3581
3582 /* dual port cards only */
3583 case 5: /* Tx Arbiter 2 */
3584 case 9: /* RX2 */
3585 case 14 ... 15: /* TX2 */
3586 case 17: case 19: /* Ram Buffer 2 */
3587 case 22 ... 23: /* Tx Ram Buffer 2 */
3588 case 25: /* Rx MAC Fifo 1 */
3589 case 27: /* Tx MAC Fifo 2 */
3590 case 31: /* GPHY 2 */
3591 case 40 ... 47: /* Pattern Ram 2 */
3592 case 52: case 54: /* TCP Segmentation 2 */
3593 case 112 ... 116: /* GMAC 2 */
3594 if (sky2->hw->ports == 1)
3595 goto reserved;
3596 /* fall through */
3597 case 0: /* Control */
3598 case 2: /* Mac address */
3599 case 4: /* Tx Arbiter 1 */
3600 case 7: /* PCI express reg */
3601 case 8: /* RX1 */
3602 case 12 ... 13: /* TX1 */
3603 case 16: case 18:/* Rx Ram Buffer 1 */
3604 case 20 ... 21: /* Tx Ram Buffer 1 */
3605 case 24: /* Rx MAC Fifo 1 */
3606 case 26: /* Tx MAC Fifo 1 */
3607 case 28 ... 29: /* Descriptor and status unit */
3608 case 30: /* GPHY 1*/
3609 case 32 ... 39: /* Pattern Ram 1 */
3610 case 48: case 50: /* TCP Segmentation 1 */
3611 case 56 ... 60: /* PCI space */
3612 case 80 ... 84: /* GMAC 1 */
3613 memcpy_fromio(p, io, 128);
3614 break;
3615 default:
3616 reserved:
3617 memset(p, 0, 128);
3618 }
3619
3620 p += 128;
3621 io += 128;
3622 }
3623 }
3624
3625 /* In order to do Jumbo packets on these chips, need to turn off the
3626 * transmit store/forward. Therefore checksum offload won't work.
3627 */
3628 static int no_tx_offload(struct net_device *dev)
3629 {
3630 const struct sky2_port *sky2 = netdev_priv(dev);
3631 const struct sky2_hw *hw = sky2->hw;
3632
3633 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3634 }
3635
3636 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3637 {
3638 if (data && no_tx_offload(dev))
3639 return -EINVAL;
3640
3641 return ethtool_op_set_tx_csum(dev, data);
3642 }
3643
3644
3645 static int sky2_set_tso(struct net_device *dev, u32 data)
3646 {
3647 if (data && no_tx_offload(dev))
3648 return -EINVAL;
3649
3650 return ethtool_op_set_tso(dev, data);
3651 }
3652
3653 static int sky2_get_eeprom_len(struct net_device *dev)
3654 {
3655 struct sky2_port *sky2 = netdev_priv(dev);
3656 struct sky2_hw *hw = sky2->hw;
3657 u16 reg2;
3658
3659 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3660 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3661 }
3662
3663 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3664 {
3665 u32 val;
3666
3667 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3668
3669 do {
3670 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3671 } while (!(offset & PCI_VPD_ADDR_F));
3672
3673 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3674 return val;
3675 }
3676
3677 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3678 {
3679 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3680 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3681 do {
3682 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3683 } while (offset & PCI_VPD_ADDR_F);
3684 }
3685
3686 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3687 u8 *data)
3688 {
3689 struct sky2_port *sky2 = netdev_priv(dev);
3690 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3691 int length = eeprom->len;
3692 u16 offset = eeprom->offset;
3693
3694 if (!cap)
3695 return -EINVAL;
3696
3697 eeprom->magic = SKY2_EEPROM_MAGIC;
3698
3699 while (length > 0) {
3700 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3701 int n = min_t(int, length, sizeof(val));
3702
3703 memcpy(data, &val, n);
3704 length -= n;
3705 data += n;
3706 offset += n;
3707 }
3708 return 0;
3709 }
3710
3711 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3712 u8 *data)
3713 {
3714 struct sky2_port *sky2 = netdev_priv(dev);
3715 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3716 int length = eeprom->len;
3717 u16 offset = eeprom->offset;
3718
3719 if (!cap)
3720 return -EINVAL;
3721
3722 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3723 return -EINVAL;
3724
3725 while (length > 0) {
3726 u32 val;
3727 int n = min_t(int, length, sizeof(val));
3728
3729 if (n < sizeof(val))
3730 val = sky2_vpd_read(sky2->hw, cap, offset);
3731 memcpy(&val, data, n);
3732
3733 sky2_vpd_write(sky2->hw, cap, offset, val);
3734
3735 length -= n;
3736 data += n;
3737 offset += n;
3738 }
3739 return 0;
3740 }
3741
3742
3743 static const struct ethtool_ops sky2_ethtool_ops = {
3744 .get_settings = sky2_get_settings,
3745 .set_settings = sky2_set_settings,
3746 .get_drvinfo = sky2_get_drvinfo,
3747 .get_wol = sky2_get_wol,
3748 .set_wol = sky2_set_wol,
3749 .get_msglevel = sky2_get_msglevel,
3750 .set_msglevel = sky2_set_msglevel,
3751 .nway_reset = sky2_nway_reset,
3752 .get_regs_len = sky2_get_regs_len,
3753 .get_regs = sky2_get_regs,
3754 .get_link = ethtool_op_get_link,
3755 .get_eeprom_len = sky2_get_eeprom_len,
3756 .get_eeprom = sky2_get_eeprom,
3757 .set_eeprom = sky2_set_eeprom,
3758 .set_sg = ethtool_op_set_sg,
3759 .set_tx_csum = sky2_set_tx_csum,
3760 .set_tso = sky2_set_tso,
3761 .get_rx_csum = sky2_get_rx_csum,
3762 .set_rx_csum = sky2_set_rx_csum,
3763 .get_strings = sky2_get_strings,
3764 .get_coalesce = sky2_get_coalesce,
3765 .set_coalesce = sky2_set_coalesce,
3766 .get_ringparam = sky2_get_ringparam,
3767 .set_ringparam = sky2_set_ringparam,
3768 .get_pauseparam = sky2_get_pauseparam,
3769 .set_pauseparam = sky2_set_pauseparam,
3770 .phys_id = sky2_phys_id,
3771 .get_sset_count = sky2_get_sset_count,
3772 .get_ethtool_stats = sky2_get_ethtool_stats,
3773 };
3774
3775 #ifdef CONFIG_SKY2_DEBUG
3776
3777 static struct dentry *sky2_debug;
3778
3779 static int sky2_debug_show(struct seq_file *seq, void *v)
3780 {
3781 struct net_device *dev = seq->private;
3782 const struct sky2_port *sky2 = netdev_priv(dev);
3783 struct sky2_hw *hw = sky2->hw;
3784 unsigned port = sky2->port;
3785 unsigned idx, last;
3786 int sop;
3787
3788 if (!netif_running(dev))
3789 return -ENETDOWN;
3790
3791 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3792 sky2_read32(hw, B0_ISRC),
3793 sky2_read32(hw, B0_IMSK),
3794 sky2_read32(hw, B0_Y2_SP_ICR));
3795
3796 napi_disable(&hw->napi);
3797 last = sky2_read16(hw, STAT_PUT_IDX);
3798
3799 if (hw->st_idx == last)
3800 seq_puts(seq, "Status ring (empty)\n");
3801 else {
3802 seq_puts(seq, "Status ring\n");
3803 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3804 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3805 const struct sky2_status_le *le = hw->st_le + idx;
3806 seq_printf(seq, "[%d] %#x %d %#x\n",
3807 idx, le->opcode, le->length, le->status);
3808 }
3809 seq_puts(seq, "\n");
3810 }
3811
3812 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3813 sky2->tx_cons, sky2->tx_prod,
3814 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3815 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3816
3817 /* Dump contents of tx ring */
3818 sop = 1;
3819 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3820 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3821 const struct sky2_tx_le *le = sky2->tx_le + idx;
3822 u32 a = le32_to_cpu(le->addr);
3823
3824 if (sop)
3825 seq_printf(seq, "%u:", idx);
3826 sop = 0;
3827
3828 switch(le->opcode & ~HW_OWNER) {
3829 case OP_ADDR64:
3830 seq_printf(seq, " %#x:", a);
3831 break;
3832 case OP_LRGLEN:
3833 seq_printf(seq, " mtu=%d", a);
3834 break;
3835 case OP_VLAN:
3836 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3837 break;
3838 case OP_TCPLISW:
3839 seq_printf(seq, " csum=%#x", a);
3840 break;
3841 case OP_LARGESEND:
3842 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3843 break;
3844 case OP_PACKET:
3845 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3846 break;
3847 case OP_BUFFER:
3848 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3849 break;
3850 default:
3851 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3852 a, le16_to_cpu(le->length));
3853 }
3854
3855 if (le->ctrl & EOP) {
3856 seq_putc(seq, '\n');
3857 sop = 1;
3858 }
3859 }
3860
3861 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3862 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3863 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3864 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3865
3866 sky2_read32(hw, B0_Y2_SP_LISR);
3867 napi_enable(&hw->napi);
3868 return 0;
3869 }
3870
3871 static int sky2_debug_open(struct inode *inode, struct file *file)
3872 {
3873 return single_open(file, sky2_debug_show, inode->i_private);
3874 }
3875
3876 static const struct file_operations sky2_debug_fops = {
3877 .owner = THIS_MODULE,
3878 .open = sky2_debug_open,
3879 .read = seq_read,
3880 .llseek = seq_lseek,
3881 .release = single_release,
3882 };
3883
3884 /*
3885 * Use network device events to create/remove/rename
3886 * debugfs file entries
3887 */
3888 static int sky2_device_event(struct notifier_block *unused,
3889 unsigned long event, void *ptr)
3890 {
3891 struct net_device *dev = ptr;
3892 struct sky2_port *sky2 = netdev_priv(dev);
3893
3894 if (dev->open != sky2_up || !sky2_debug)
3895 return NOTIFY_DONE;
3896
3897 switch(event) {
3898 case NETDEV_CHANGENAME:
3899 if (sky2->debugfs) {
3900 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3901 sky2_debug, dev->name);
3902 }
3903 break;
3904
3905 case NETDEV_GOING_DOWN:
3906 if (sky2->debugfs) {
3907 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3908 dev->name);
3909 debugfs_remove(sky2->debugfs);
3910 sky2->debugfs = NULL;
3911 }
3912 break;
3913
3914 case NETDEV_UP:
3915 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3916 sky2_debug, dev,
3917 &sky2_debug_fops);
3918 if (IS_ERR(sky2->debugfs))
3919 sky2->debugfs = NULL;
3920 }
3921
3922 return NOTIFY_DONE;
3923 }
3924
3925 static struct notifier_block sky2_notifier = {
3926 .notifier_call = sky2_device_event,
3927 };
3928
3929
3930 static __init void sky2_debug_init(void)
3931 {
3932 struct dentry *ent;
3933
3934 ent = debugfs_create_dir("sky2", NULL);
3935 if (!ent || IS_ERR(ent))
3936 return;
3937
3938 sky2_debug = ent;
3939 register_netdevice_notifier(&sky2_notifier);
3940 }
3941
3942 static __exit void sky2_debug_cleanup(void)
3943 {
3944 if (sky2_debug) {
3945 unregister_netdevice_notifier(&sky2_notifier);
3946 debugfs_remove(sky2_debug);
3947 sky2_debug = NULL;
3948 }
3949 }
3950
3951 #else
3952 #define sky2_debug_init()
3953 #define sky2_debug_cleanup()
3954 #endif
3955
3956
3957 /* Initialize network device */
3958 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3959 unsigned port,
3960 int highmem, int wol)
3961 {
3962 struct sky2_port *sky2;
3963 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3964
3965 if (!dev) {
3966 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3967 return NULL;
3968 }
3969
3970 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3971 dev->irq = hw->pdev->irq;
3972 dev->open = sky2_up;
3973 dev->stop = sky2_down;
3974 dev->do_ioctl = sky2_ioctl;
3975 dev->hard_start_xmit = sky2_xmit_frame;
3976 dev->set_multicast_list = sky2_set_multicast;
3977 dev->set_mac_address = sky2_set_mac_address;
3978 dev->change_mtu = sky2_change_mtu;
3979 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3980 dev->tx_timeout = sky2_tx_timeout;
3981 dev->watchdog_timeo = TX_WATCHDOG;
3982 #ifdef CONFIG_NET_POLL_CONTROLLER
3983 if (port == 0)
3984 dev->poll_controller = sky2_netpoll;
3985 #endif
3986
3987 sky2 = netdev_priv(dev);
3988 sky2->netdev = dev;
3989 sky2->hw = hw;
3990 sky2->msg_enable = netif_msg_init(debug, default_msg);
3991
3992 /* Auto speed and flow control */
3993 sky2->autoneg = AUTONEG_ENABLE;
3994 sky2->flow_mode = FC_BOTH;
3995
3996 sky2->duplex = -1;
3997 sky2->speed = -1;
3998 sky2->advertising = sky2_supported_modes(hw);
3999 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4000 sky2->wol = wol;
4001
4002 spin_lock_init(&sky2->phy_lock);
4003 sky2->tx_pending = TX_DEF_PENDING;
4004 sky2->rx_pending = RX_DEF_PENDING;
4005
4006 hw->dev[port] = dev;
4007
4008 sky2->port = port;
4009
4010 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4011 if (highmem)
4012 dev->features |= NETIF_F_HIGHDMA;
4013
4014 #ifdef SKY2_VLAN_TAG_USED
4015 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4016 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4017 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4018 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4019 dev->vlan_rx_register = sky2_vlan_rx_register;
4020 }
4021 #endif
4022
4023 /* read the mac address */
4024 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4025 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4026
4027 return dev;
4028 }
4029
4030 static void __devinit sky2_show_addr(struct net_device *dev)
4031 {
4032 const struct sky2_port *sky2 = netdev_priv(dev);
4033 DECLARE_MAC_BUF(mac);
4034
4035 if (netif_msg_probe(sky2))
4036 printk(KERN_INFO PFX "%s: addr %s\n",
4037 dev->name, print_mac(mac, dev->dev_addr));
4038 }
4039
4040 /* Handle software interrupt used during MSI test */
4041 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4042 {
4043 struct sky2_hw *hw = dev_id;
4044 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4045
4046 if (status == 0)
4047 return IRQ_NONE;
4048
4049 if (status & Y2_IS_IRQ_SW) {
4050 hw->flags |= SKY2_HW_USE_MSI;
4051 wake_up(&hw->msi_wait);
4052 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4053 }
4054 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4055
4056 return IRQ_HANDLED;
4057 }
4058
4059 /* Test interrupt path by forcing a a software IRQ */
4060 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4061 {
4062 struct pci_dev *pdev = hw->pdev;
4063 int err;
4064
4065 init_waitqueue_head (&hw->msi_wait);
4066
4067 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4068
4069 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4070 if (err) {
4071 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4072 return err;
4073 }
4074
4075 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4076 sky2_read8(hw, B0_CTST);
4077
4078 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4079
4080 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4081 /* MSI test failed, go back to INTx mode */
4082 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4083 "switching to INTx mode.\n");
4084
4085 err = -EOPNOTSUPP;
4086 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4087 }
4088
4089 sky2_write32(hw, B0_IMSK, 0);
4090 sky2_read32(hw, B0_IMSK);
4091
4092 free_irq(pdev->irq, hw);
4093
4094 return err;
4095 }
4096
4097 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4098 {
4099 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4100 u16 value;
4101
4102 if (!pm)
4103 return 0;
4104 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4105 return 0;
4106 return value & PCI_PM_CTRL_PME_ENABLE;
4107 }
4108
4109 static int __devinit sky2_probe(struct pci_dev *pdev,
4110 const struct pci_device_id *ent)
4111 {
4112 struct net_device *dev;
4113 struct sky2_hw *hw;
4114 int err, using_dac = 0, wol_default;
4115
4116 err = pci_enable_device(pdev);
4117 if (err) {
4118 dev_err(&pdev->dev, "cannot enable PCI device\n");
4119 goto err_out;
4120 }
4121
4122 err = pci_request_regions(pdev, DRV_NAME);
4123 if (err) {
4124 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4125 goto err_out_disable;
4126 }
4127
4128 pci_set_master(pdev);
4129
4130 if (sizeof(dma_addr_t) > sizeof(u32) &&
4131 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4132 using_dac = 1;
4133 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4134 if (err < 0) {
4135 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4136 "for consistent allocations\n");
4137 goto err_out_free_regions;
4138 }
4139 } else {
4140 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4141 if (err) {
4142 dev_err(&pdev->dev, "no usable DMA configuration\n");
4143 goto err_out_free_regions;
4144 }
4145 }
4146
4147 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4148
4149 err = -ENOMEM;
4150 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4151 if (!hw) {
4152 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4153 goto err_out_free_regions;
4154 }
4155
4156 hw->pdev = pdev;
4157
4158 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4159 if (!hw->regs) {
4160 dev_err(&pdev->dev, "cannot map device registers\n");
4161 goto err_out_free_hw;
4162 }
4163
4164 #ifdef __BIG_ENDIAN
4165 /* The sk98lin vendor driver uses hardware byte swapping but
4166 * this driver uses software swapping.
4167 */
4168 {
4169 u32 reg;
4170 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4171 reg &= ~PCI_REV_DESC;
4172 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4173 }
4174 #endif
4175
4176 /* ring for status responses */
4177 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4178 if (!hw->st_le)
4179 goto err_out_iounmap;
4180
4181 err = sky2_init(hw);
4182 if (err)
4183 goto err_out_iounmap;
4184
4185 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4186 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4187 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4188 hw->chip_id, hw->chip_rev);
4189
4190 sky2_reset(hw);
4191
4192 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4193 if (!dev) {
4194 err = -ENOMEM;
4195 goto err_out_free_pci;
4196 }
4197
4198 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4199 err = sky2_test_msi(hw);
4200 if (err == -EOPNOTSUPP)
4201 pci_disable_msi(pdev);
4202 else if (err)
4203 goto err_out_free_netdev;
4204 }
4205
4206 err = register_netdev(dev);
4207 if (err) {
4208 dev_err(&pdev->dev, "cannot register net device\n");
4209 goto err_out_free_netdev;
4210 }
4211
4212 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4213
4214 err = request_irq(pdev->irq, sky2_intr,
4215 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4216 dev->name, hw);
4217 if (err) {
4218 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4219 goto err_out_unregister;
4220 }
4221 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4222 napi_enable(&hw->napi);
4223
4224 sky2_show_addr(dev);
4225
4226 if (hw->ports > 1) {
4227 struct net_device *dev1;
4228
4229 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4230 if (!dev1)
4231 dev_warn(&pdev->dev, "allocation for second device failed\n");
4232 else if ((err = register_netdev(dev1))) {
4233 dev_warn(&pdev->dev,
4234 "register of second port failed (%d)\n", err);
4235 hw->dev[1] = NULL;
4236 free_netdev(dev1);
4237 } else
4238 sky2_show_addr(dev1);
4239 }
4240
4241 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4242 INIT_WORK(&hw->restart_work, sky2_restart);
4243
4244 pci_set_drvdata(pdev, hw);
4245
4246 return 0;
4247
4248 err_out_unregister:
4249 if (hw->flags & SKY2_HW_USE_MSI)
4250 pci_disable_msi(pdev);
4251 unregister_netdev(dev);
4252 err_out_free_netdev:
4253 free_netdev(dev);
4254 err_out_free_pci:
4255 sky2_write8(hw, B0_CTST, CS_RST_SET);
4256 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4257 err_out_iounmap:
4258 iounmap(hw->regs);
4259 err_out_free_hw:
4260 kfree(hw);
4261 err_out_free_regions:
4262 pci_release_regions(pdev);
4263 err_out_disable:
4264 pci_disable_device(pdev);
4265 err_out:
4266 pci_set_drvdata(pdev, NULL);
4267 return err;
4268 }
4269
4270 static void __devexit sky2_remove(struct pci_dev *pdev)
4271 {
4272 struct sky2_hw *hw = pci_get_drvdata(pdev);
4273 int i;
4274
4275 if (!hw)
4276 return;
4277
4278 del_timer_sync(&hw->watchdog_timer);
4279 cancel_work_sync(&hw->restart_work);
4280
4281 for (i = hw->ports-1; i >= 0; --i)
4282 unregister_netdev(hw->dev[i]);
4283
4284 sky2_write32(hw, B0_IMSK, 0);
4285
4286 sky2_power_aux(hw);
4287
4288 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4289 sky2_write8(hw, B0_CTST, CS_RST_SET);
4290 sky2_read8(hw, B0_CTST);
4291
4292 free_irq(pdev->irq, hw);
4293 if (hw->flags & SKY2_HW_USE_MSI)
4294 pci_disable_msi(pdev);
4295 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4296 pci_release_regions(pdev);
4297 pci_disable_device(pdev);
4298
4299 for (i = hw->ports-1; i >= 0; --i)
4300 free_netdev(hw->dev[i]);
4301
4302 iounmap(hw->regs);
4303 kfree(hw);
4304
4305 pci_set_drvdata(pdev, NULL);
4306 }
4307
4308 #ifdef CONFIG_PM
4309 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4310 {
4311 struct sky2_hw *hw = pci_get_drvdata(pdev);
4312 int i, wol = 0;
4313
4314 if (!hw)
4315 return 0;
4316
4317 for (i = 0; i < hw->ports; i++) {
4318 struct net_device *dev = hw->dev[i];
4319 struct sky2_port *sky2 = netdev_priv(dev);
4320
4321 if (netif_running(dev))
4322 sky2_down(dev);
4323
4324 if (sky2->wol)
4325 sky2_wol_init(sky2);
4326
4327 wol |= sky2->wol;
4328 }
4329
4330 sky2_write32(hw, B0_IMSK, 0);
4331 napi_disable(&hw->napi);
4332 sky2_power_aux(hw);
4333
4334 pci_save_state(pdev);
4335 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4336 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4337
4338 return 0;
4339 }
4340
4341 static int sky2_resume(struct pci_dev *pdev)
4342 {
4343 struct sky2_hw *hw = pci_get_drvdata(pdev);
4344 int i, err;
4345
4346 if (!hw)
4347 return 0;
4348
4349 err = pci_set_power_state(pdev, PCI_D0);
4350 if (err)
4351 goto out;
4352
4353 err = pci_restore_state(pdev);
4354 if (err)
4355 goto out;
4356
4357 pci_enable_wake(pdev, PCI_D0, 0);
4358
4359 /* Re-enable all clocks */
4360 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4361 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4362 hw->chip_id == CHIP_ID_YUKON_FE_P)
4363 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4364
4365 sky2_reset(hw);
4366 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4367 napi_enable(&hw->napi);
4368
4369 for (i = 0; i < hw->ports; i++) {
4370 struct net_device *dev = hw->dev[i];
4371 if (netif_running(dev)) {
4372 err = sky2_up(dev);
4373 if (err) {
4374 printk(KERN_ERR PFX "%s: could not up: %d\n",
4375 dev->name, err);
4376 dev_close(dev);
4377 goto out;
4378 }
4379
4380 sky2_set_multicast(dev);
4381 }
4382 }
4383
4384 return 0;
4385 out:
4386 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4387 pci_disable_device(pdev);
4388 return err;
4389 }
4390 #endif
4391
4392 static void sky2_shutdown(struct pci_dev *pdev)
4393 {
4394 struct sky2_hw *hw = pci_get_drvdata(pdev);
4395 int i, wol = 0;
4396
4397 if (!hw)
4398 return;
4399
4400 del_timer_sync(&hw->watchdog_timer);
4401
4402 for (i = 0; i < hw->ports; i++) {
4403 struct net_device *dev = hw->dev[i];
4404 struct sky2_port *sky2 = netdev_priv(dev);
4405
4406 if (sky2->wol) {
4407 wol = 1;
4408 sky2_wol_init(sky2);
4409 }
4410 }
4411
4412 if (wol)
4413 sky2_power_aux(hw);
4414
4415 pci_enable_wake(pdev, PCI_D3hot, wol);
4416 pci_enable_wake(pdev, PCI_D3cold, wol);
4417
4418 pci_disable_device(pdev);
4419 pci_set_power_state(pdev, PCI_D3hot);
4420
4421 }
4422
4423 static struct pci_driver sky2_driver = {
4424 .name = DRV_NAME,
4425 .id_table = sky2_id_table,
4426 .probe = sky2_probe,
4427 .remove = __devexit_p(sky2_remove),
4428 #ifdef CONFIG_PM
4429 .suspend = sky2_suspend,
4430 .resume = sky2_resume,
4431 #endif
4432 .shutdown = sky2_shutdown,
4433 };
4434
4435 static int __init sky2_init_module(void)
4436 {
4437 sky2_debug_init();
4438 return pci_register_driver(&sky2_driver);
4439 }
4440
4441 static void __exit sky2_cleanup_module(void)
4442 {
4443 pci_unregister_driver(&sky2_driver);
4444 sky2_debug_cleanup();
4445 }
4446
4447 module_init(sky2_init_module);
4448 module_exit(sky2_cleanup_module);
4449
4450 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4451 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4452 MODULE_LICENSE("GPL");
4453 MODULE_VERSION(DRV_VERSION);
SocketAccessConTroL development