2 * arch/ppc64/kernel/pSeries_iommu.c
4 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
8 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
10 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/config.h>
29 #include <linux/init.h>
30 #include <linux/types.h>
31 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/string.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
40 #include <asm/ppcdebug.h>
41 #include <asm/iommu.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/machdep.h>
44 #include <asm/abs_addr.h>
45 #include <asm/plpar_wrappers.h>
46 #include <asm/pSeries_reconfig.h>
47 #include <asm/systemcfg.h>
48 #include <asm/firmware.h>
54 extern int is_python(struct device_node
*);
56 static void tce_build_pSeries(struct iommu_table
*tbl
, long index
,
57 long npages
, unsigned long uaddr
,
58 enum dma_data_direction direction
)
63 index
<<= TCE_PAGE_FACTOR
;
64 npages
<<= TCE_PAGE_FACTOR
;
67 t
.te_rdwr
= 1; // Read allowed
69 if (direction
!= DMA_TO_DEVICE
)
72 tp
= ((union tce_entry
*)tbl
->it_base
) + index
;
75 /* can't move this out since we might cross LMB boundary */
76 t
.te_rpn
= (virt_to_abs(uaddr
)) >> TCE_SHIFT
;
78 tp
->te_word
= t
.te_word
;
80 uaddr
+= TCE_PAGE_SIZE
;
86 static void tce_free_pSeries(struct iommu_table
*tbl
, long index
, long npages
)
91 npages
<<= TCE_PAGE_FACTOR
;
92 index
<<= TCE_PAGE_FACTOR
;
95 tp
= ((union tce_entry
*)tbl
->it_base
) + index
;
98 tp
->te_word
= t
.te_word
;
105 static void tce_build_pSeriesLP(struct iommu_table
*tbl
, long tcenum
,
106 long npages
, unsigned long uaddr
,
107 enum dma_data_direction direction
)
113 tce
.te_rpn
= (virt_to_abs(uaddr
)) >> TCE_SHIFT
;
115 if (direction
!= DMA_TO_DEVICE
)
119 rc
= plpar_tce_put((u64
)tbl
->it_index
,
123 if (rc
&& printk_ratelimit()) {
124 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc
);
125 printk("\tindex = 0x%lx\n", (u64
)tbl
->it_index
);
126 printk("\ttcenum = 0x%lx\n", (u64
)tcenum
);
127 printk("\ttce val = 0x%lx\n", tce
.te_word
);
128 show_stack(current
, (unsigned long *)__get_SP());
136 static DEFINE_PER_CPU(void *, tce_page
) = NULL
;
138 static void tce_buildmulti_pSeriesLP(struct iommu_table
*tbl
, long tcenum
,
139 long npages
, unsigned long uaddr
,
140 enum dma_data_direction direction
)
143 union tce_entry tce
, *tcep
;
146 tcenum
<<= TCE_PAGE_FACTOR
;
147 npages
<<= TCE_PAGE_FACTOR
;
150 return tce_build_pSeriesLP(tbl
, tcenum
, npages
, uaddr
,
153 tcep
= __get_cpu_var(tce_page
);
155 /* This is safe to do since interrupts are off when we're called
156 * from iommu_alloc{,_sg}()
159 tcep
= (void *)__get_free_page(GFP_ATOMIC
);
160 /* If allocation fails, fall back to the loop implementation */
162 return tce_build_pSeriesLP(tbl
, tcenum
, npages
,
164 __get_cpu_var(tce_page
) = tcep
;
168 tce
.te_rpn
= (virt_to_abs(uaddr
)) >> TCE_SHIFT
;
170 if (direction
!= DMA_TO_DEVICE
)
173 /* We can map max one pageful of TCEs at a time */
176 * Set up the page with TCE data, looping through and setting
179 limit
= min_t(long, npages
, 4096/sizeof(union tce_entry
));
181 for (l
= 0; l
< limit
; l
++) {
186 rc
= plpar_tce_put_indirect((u64
)tbl
->it_index
,
188 (u64
)virt_to_abs(tcep
),
193 } while (npages
> 0 && !rc
);
195 if (rc
&& printk_ratelimit()) {
196 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc
);
197 printk("\tindex = 0x%lx\n", (u64
)tbl
->it_index
);
198 printk("\tnpages = 0x%lx\n", (u64
)npages
);
199 printk("\ttce[0] val = 0x%lx\n", tcep
[0].te_word
);
200 show_stack(current
, (unsigned long *)__get_SP());
204 static void tce_free_pSeriesLP(struct iommu_table
*tbl
, long tcenum
, long npages
)
209 tcenum
<<= TCE_PAGE_FACTOR
;
210 npages
<<= TCE_PAGE_FACTOR
;
215 rc
= plpar_tce_put((u64
)tbl
->it_index
,
219 if (rc
&& printk_ratelimit()) {
220 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc
);
221 printk("\tindex = 0x%lx\n", (u64
)tbl
->it_index
);
222 printk("\ttcenum = 0x%lx\n", (u64
)tcenum
);
223 printk("\ttce val = 0x%lx\n", tce
.te_word
);
224 show_stack(current
, (unsigned long *)__get_SP());
232 static void tce_freemulti_pSeriesLP(struct iommu_table
*tbl
, long tcenum
, long npages
)
237 tcenum
<<= TCE_PAGE_FACTOR
;
238 npages
<<= TCE_PAGE_FACTOR
;
242 rc
= plpar_tce_stuff((u64
)tbl
->it_index
,
247 if (rc
&& printk_ratelimit()) {
248 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
249 printk("\trc = %ld\n", rc
);
250 printk("\tindex = 0x%lx\n", (u64
)tbl
->it_index
);
251 printk("\tnpages = 0x%lx\n", (u64
)npages
);
252 printk("\ttce val = 0x%lx\n", tce
.te_word
);
253 show_stack(current
, (unsigned long *)__get_SP());
257 static void iommu_table_setparms(struct pci_controller
*phb
,
258 struct device_node
*dn
,
259 struct iommu_table
*tbl
)
261 struct device_node
*node
;
262 unsigned long *basep
;
265 node
= (struct device_node
*)phb
->arch_data
;
267 basep
= (unsigned long *)get_property(node
, "linux,tce-base", NULL
);
268 sizep
= (unsigned int *)get_property(node
, "linux,tce-size", NULL
);
269 if (basep
== NULL
|| sizep
== NULL
) {
270 printk(KERN_ERR
"PCI_DMA: iommu_table_setparms: %s has "
271 "missing tce entries !\n", dn
->full_name
);
275 tbl
->it_base
= (unsigned long)__va(*basep
);
276 memset((void *)tbl
->it_base
, 0, *sizep
);
278 tbl
->it_busno
= phb
->bus
->number
;
280 /* Units of tce entries */
281 tbl
->it_offset
= phb
->dma_window_base_cur
>> PAGE_SHIFT
;
283 /* Test if we are going over 2GB of DMA space */
284 if (phb
->dma_window_base_cur
+ phb
->dma_window_size
> (1L << 31))
285 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
287 phb
->dma_window_base_cur
+= phb
->dma_window_size
;
289 /* Set the tce table size - measured in entries */
290 tbl
->it_size
= phb
->dma_window_size
>> PAGE_SHIFT
;
293 tbl
->it_blocksize
= 16;
294 tbl
->it_type
= TCE_PCI
;
298 * iommu_table_setparms_lpar
300 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
302 * ToDo: properly interpret the ibm,dma-window property. The definition is:
303 * logical-bus-number (1 word)
304 * phys-address (#address-cells words)
305 * size (#cell-size words)
307 * Currently we hard code these sizes (more or less).
309 static void iommu_table_setparms_lpar(struct pci_controller
*phb
,
310 struct device_node
*dn
,
311 struct iommu_table
*tbl
,
312 unsigned int *dma_window
)
314 tbl
->it_busno
= PCI_DN(dn
)->bussubno
;
316 /* TODO: Parse field size properties properly. */
317 tbl
->it_size
= (((unsigned long)dma_window
[4] << 32) |
318 (unsigned long)dma_window
[5]) >> PAGE_SHIFT
;
319 tbl
->it_offset
= (((unsigned long)dma_window
[2] << 32) |
320 (unsigned long)dma_window
[3]) >> PAGE_SHIFT
;
322 tbl
->it_index
= dma_window
[0];
323 tbl
->it_blocksize
= 16;
324 tbl
->it_type
= TCE_PCI
;
327 static void iommu_bus_setup_pSeries(struct pci_bus
*bus
)
329 struct device_node
*dn
, *pdn
;
331 struct iommu_table
*tbl
;
333 DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus
, bus
->self
);
335 /* For each (root) bus, we carve up the available DMA space in 256MB
336 * pieces. Since each piece is used by one (sub) bus/device, that would
337 * give a maximum of 7 devices per PHB. In most cases, this is plenty.
339 * The exception is on Python PHBs (pre-POWER4). Here we don't have EADS
340 * bridges below the PHB to allocate the sectioned tables to, so instead
341 * we allocate a 1GB table at the PHB level.
344 dn
= pci_bus_to_OF_node(bus
);
350 unsigned int *iohole
;
352 DBG("Python root bus %s\n", bus
->name
);
354 iohole
= (unsigned int *)get_property(dn
, "io-hole", 0);
357 /* On first bus we need to leave room for the
358 * ISA address space. Just skip the first 256MB
359 * alltogether. This leaves 768MB for the window.
361 DBG("PHB has io-hole, reserving 256MB\n");
362 pci
->phb
->dma_window_size
= 3 << 28;
363 pci
->phb
->dma_window_base_cur
= 1 << 28;
365 /* 1GB window by default */
366 pci
->phb
->dma_window_size
= 1 << 30;
367 pci
->phb
->dma_window_base_cur
= 0;
370 tbl
= kmalloc(sizeof(struct iommu_table
), GFP_KERNEL
);
372 iommu_table_setparms(pci
->phb
, dn
, tbl
);
373 pci
->iommu_table
= iommu_init_table(tbl
);
375 /* Do a 128MB table at root. This is used for the IDE
376 * controller on some SMP-mode POWER4 machines. It
377 * doesn't hurt to allocate it on other machines
378 * -- it'll just be unused since new tables are
379 * allocated on the EADS level.
381 * Allocate at offset 128MB to avoid having to deal
382 * with ISA holes; 128MB table for IDE is plenty.
384 pci
->phb
->dma_window_size
= 1 << 27;
385 pci
->phb
->dma_window_base_cur
= 1 << 27;
387 tbl
= kmalloc(sizeof(struct iommu_table
), GFP_KERNEL
);
389 iommu_table_setparms(pci
->phb
, dn
, tbl
);
390 pci
->iommu_table
= iommu_init_table(tbl
);
392 /* All child buses have 256MB tables */
393 pci
->phb
->dma_window_size
= 1 << 28;
396 pdn
= pci_bus_to_OF_node(bus
->parent
);
398 if (!bus
->parent
->self
&& !is_python(pdn
)) {
399 struct iommu_table
*tbl
;
400 /* First child and not python means this is the EADS
401 * level. Allocate new table for this slot with 256MB
405 tbl
= kmalloc(sizeof(struct iommu_table
), GFP_KERNEL
);
407 iommu_table_setparms(pci
->phb
, dn
, tbl
);
409 pci
->iommu_table
= iommu_init_table(tbl
);
411 /* Lower than first child or under python, use parent table */
412 pci
->iommu_table
= PCI_DN(pdn
)->iommu_table
;
418 static void iommu_bus_setup_pSeriesLP(struct pci_bus
*bus
)
420 struct iommu_table
*tbl
;
421 struct device_node
*dn
, *pdn
;
423 unsigned int *dma_window
= NULL
;
425 DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus
, bus
->self
);
427 dn
= pci_bus_to_OF_node(bus
);
429 /* Find nearest ibm,dma-window, walking up the device tree */
430 for (pdn
= dn
; pdn
!= NULL
; pdn
= pdn
->parent
) {
431 dma_window
= (unsigned int *)get_property(pdn
, "ibm,dma-window", NULL
);
432 if (dma_window
!= NULL
)
436 if (dma_window
== NULL
) {
437 DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn
->full_name
);
442 if (!ppci
->iommu_table
) {
443 /* Bussubno hasn't been copied yet.
444 * Do it now because iommu_table_setparms_lpar needs it.
447 ppci
->bussubno
= bus
->number
;
449 tbl
= (struct iommu_table
*)kmalloc(sizeof(struct iommu_table
),
452 iommu_table_setparms_lpar(ppci
->phb
, pdn
, tbl
, dma_window
);
454 ppci
->iommu_table
= iommu_init_table(tbl
);
458 PCI_DN(dn
)->iommu_table
= ppci
->iommu_table
;
462 static void iommu_dev_setup_pSeries(struct pci_dev
*dev
)
464 struct device_node
*dn
, *mydn
;
466 DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev
, dev
->pretty_name
);
467 /* Now copy the iommu_table ptr from the bus device down to the
468 * pci device_node. This means get_iommu_table() won't need to search
469 * up the device tree to find it.
471 mydn
= dn
= pci_device_to_OF_node(dev
);
473 while (dn
&& dn
->data
&& PCI_DN(dn
)->iommu_table
== NULL
)
476 if (dn
&& dn
->data
) {
477 PCI_DN(mydn
)->iommu_table
= PCI_DN(dn
)->iommu_table
;
479 DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev
, dev
->pretty_name
);
483 static int iommu_reconfig_notifier(struct notifier_block
*nb
, unsigned long action
, void *node
)
486 struct device_node
*np
= node
;
487 struct pci_dn
*pci
= np
->data
;
490 case PSERIES_RECONFIG_REMOVE
:
491 if (pci
->iommu_table
&&
492 get_property(np
, "ibm,dma-window", NULL
))
493 iommu_free_table(np
);
502 static struct notifier_block iommu_reconfig_nb
= {
503 .notifier_call
= iommu_reconfig_notifier
,
506 static void iommu_dev_setup_pSeriesLP(struct pci_dev
*dev
)
508 struct device_node
*pdn
, *dn
;
509 struct iommu_table
*tbl
;
510 int *dma_window
= NULL
;
513 DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev
, dev
->pretty_name
);
515 /* dev setup for LPAR is a little tricky, since the device tree might
516 * contain the dma-window properties per-device and not neccesarily
517 * for the bus. So we need to search upwards in the tree until we
518 * either hit a dma-window property, OR find a parent with a table
521 dn
= pci_device_to_OF_node(dev
);
523 for (pdn
= dn
; pdn
&& pdn
->data
&& !PCI_DN(pdn
)->iommu_table
;
525 dma_window
= (unsigned int *)
526 get_property(pdn
, "ibm,dma-window", NULL
);
531 /* Check for parent == NULL so we don't try to setup the empty EADS
532 * slots on POWER4 machines.
534 if (dma_window
== NULL
|| pdn
->parent
== NULL
) {
535 /* Fall back to regular (non-LPAR) dev setup */
536 DBG("No dma window for device, falling back to regular setup\n");
537 iommu_dev_setup_pSeries(dev
);
540 DBG("Found DMA window, allocating table\n");
544 if (!pci
->iommu_table
) {
545 /* iommu_table_setparms_lpar needs bussubno. */
546 pci
->bussubno
= pci
->phb
->bus
->number
;
548 tbl
= (struct iommu_table
*)kmalloc(sizeof(struct iommu_table
),
551 iommu_table_setparms_lpar(pci
->phb
, pdn
, tbl
, dma_window
);
553 pci
->iommu_table
= iommu_init_table(tbl
);
557 PCI_DN(dn
)->iommu_table
= pci
->iommu_table
;
560 static void iommu_bus_setup_null(struct pci_bus
*b
) { }
561 static void iommu_dev_setup_null(struct pci_dev
*d
) { }
563 /* These are called very early. */
564 void iommu_init_early_pSeries(void)
566 if (of_chosen
&& get_property(of_chosen
, "linux,iommu-off", NULL
)) {
567 /* Direct I/O, IOMMU off */
568 ppc_md
.iommu_dev_setup
= iommu_dev_setup_null
;
569 ppc_md
.iommu_bus_setup
= iommu_bus_setup_null
;
570 pci_direct_iommu_init();
575 if (systemcfg
->platform
& PLATFORM_LPAR
) {
576 if (firmware_has_feature(FW_FEATURE_MULTITCE
)) {
577 ppc_md
.tce_build
= tce_buildmulti_pSeriesLP
;
578 ppc_md
.tce_free
= tce_freemulti_pSeriesLP
;
580 ppc_md
.tce_build
= tce_build_pSeriesLP
;
581 ppc_md
.tce_free
= tce_free_pSeriesLP
;
583 ppc_md
.iommu_bus_setup
= iommu_bus_setup_pSeriesLP
;
584 ppc_md
.iommu_dev_setup
= iommu_dev_setup_pSeriesLP
;
586 ppc_md
.tce_build
= tce_build_pSeries
;
587 ppc_md
.tce_free
= tce_free_pSeries
;
588 ppc_md
.iommu_bus_setup
= iommu_bus_setup_pSeries
;
589 ppc_md
.iommu_dev_setup
= iommu_dev_setup_pSeries
;
593 pSeries_reconfig_notifier_register(&iommu_reconfig_nb
);