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[ARM SMP] Add support for shared memory attribute
[linux-2.6/sactl.git] / drivers / scsi / sata_qstor.c
blob65502c157a5497c1112c0de5a523a037de1333ec
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/sched.h>
38 #include <linux/device.h>
39 #include "scsi.h"
40 #include <scsi/scsi_host.h>
41 #include <asm/io.h>
42 #include <linux/libata.h>
43
44 #define DRV_NAME "sata_qstor"
45 #define DRV_VERSION "0.04"
46
47 enum {
48 QS_PORTS = 4,
49 QS_MAX_PRD = LIBATA_MAX_PRD,
50 QS_CPB_ORDER = 6,
51 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
52 QS_PRD_BYTES = QS_MAX_PRD * 16,
53 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
54
55 /* global register offsets */
56 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
57 QS_HID_HPHY = 0x0004, /* host physical interface info */
58 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
59 QS_HST_SFF = 0x0100, /* host status fifo offset */
60 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
61
62 /* global control bits */
63 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
64 QS_CNFG3_GSRST = 0x01, /* global chip reset */
65 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
66
67 /* per-channel register offsets */
68 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
69 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
70 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
71 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
72 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
73 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
74 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
75 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
76 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
77
78 /* channel control bits */
79 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
80 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
81 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
82 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
83 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
84
85 /* pkt sub-field headers */
86 QS_HCB_HDR = 0x01, /* Host Control Block header */
87 QS_DCB_HDR = 0x02, /* Device Control Block header */
88
89 /* pkt HCB flag bits */
90 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
91 QS_HF_DAT = (1 << 3), /* DATa pkt */
92 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
93 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
94
95 /* pkt DCB flag bits */
96 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
97 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
98
99 /* PCI device IDs */
100 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
101 };
102
103 enum {
104 QS_DMA_BOUNDARY = ~0UL
105 };
106
107 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
108
109 struct qs_port_priv {
110 u8 *pkt;
111 dma_addr_t pkt_dma;
112 qs_state_t state;
113 };
114
115 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
116 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
117 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
118 static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs);
119 static int qs_port_start(struct ata_port *ap);
120 static void qs_host_stop(struct ata_host_set *host_set);
121 static void qs_port_stop(struct ata_port *ap);
122 static void qs_phy_reset(struct ata_port *ap);
123 static void qs_qc_prep(struct ata_queued_cmd *qc);
124 static int qs_qc_issue(struct ata_queued_cmd *qc);
125 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
126 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
127 static u8 qs_bmdma_status(struct ata_port *ap);
128 static void qs_irq_clear(struct ata_port *ap);
129 static void qs_eng_timeout(struct ata_port *ap);
130
131 static Scsi_Host_Template qs_ata_sht = {
132 .module = THIS_MODULE,
133 .name = DRV_NAME,
134 .ioctl = ata_scsi_ioctl,
135 .queuecommand = ata_scsi_queuecmd,
136 .eh_strategy_handler = ata_scsi_error,
137 .can_queue = ATA_DEF_QUEUE,
138 .this_id = ATA_SHT_THIS_ID,
139 .sg_tablesize = QS_MAX_PRD,
140 .max_sectors = ATA_MAX_SECTORS,
141 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
142 .emulated = ATA_SHT_EMULATED,
143 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
144 .use_clustering = ENABLE_CLUSTERING,
145 .proc_name = DRV_NAME,
146 .dma_boundary = QS_DMA_BOUNDARY,
147 .slave_configure = ata_scsi_slave_config,
148 .bios_param = ata_std_bios_param,
149 };
150
151 static const struct ata_port_operations qs_ata_ops = {
152 .port_disable = ata_port_disable,
153 .tf_load = ata_tf_load,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .check_atapi_dma = qs_check_atapi_dma,
157 .exec_command = ata_exec_command,
158 .dev_select = ata_std_dev_select,
159 .phy_reset = qs_phy_reset,
160 .qc_prep = qs_qc_prep,
161 .qc_issue = qs_qc_issue,
162 .eng_timeout = qs_eng_timeout,
163 .irq_handler = qs_intr,
164 .irq_clear = qs_irq_clear,
165 .scr_read = qs_scr_read,
166 .scr_write = qs_scr_write,
167 .port_start = qs_port_start,
168 .port_stop = qs_port_stop,
169 .host_stop = qs_host_stop,
170 .bmdma_stop = qs_bmdma_stop,
171 .bmdma_status = qs_bmdma_status,
172 };
173
174 static struct ata_port_info qs_port_info[] = {
175 /* board_2068_idx */
176 {
177 .sht = &qs_ata_sht,
178 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_SATA_RESET |
180 //FIXME ATA_FLAG_SRST |
181 ATA_FLAG_MMIO,
182 .pio_mask = 0x10, /* pio4 */
183 .udma_mask = 0x7f, /* udma0-6 */
184 .port_ops = &qs_ata_ops,
185 },
186 };
187
188 static struct pci_device_id qs_ata_pci_tbl[] = {
189 { PCI_VENDOR_ID_PDC, 0x2068, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
190 board_2068_idx },
191
192 { } /* terminate list */
193 };
194
195 static struct pci_driver qs_ata_pci_driver = {
196 .name = DRV_NAME,
197 .id_table = qs_ata_pci_tbl,
198 .probe = qs_ata_init_one,
199 .remove = ata_pci_remove_one,
200 };
201
202 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
203 {
204 return 1; /* ATAPI DMA not supported */
205 }
206
207 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
208 {
209 /* nothing */
210 }
211
212 static u8 qs_bmdma_status(struct ata_port *ap)
213 {
214 return 0;
215 }
216
217 static void qs_irq_clear(struct ata_port *ap)
218 {
219 /* nothing */
220 }
221
222 static inline void qs_enter_reg_mode(struct ata_port *ap)
223 {
224 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
225
226 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
227 readb(chan + QS_CCT_CTR0); /* flush */
228 }
229
230 static inline void qs_reset_channel_logic(struct ata_port *ap)
231 {
232 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
233
234 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
235 readb(chan + QS_CCT_CTR0); /* flush */
236 qs_enter_reg_mode(ap);
237 }
238
239 static void qs_phy_reset(struct ata_port *ap)
240 {
241 struct qs_port_priv *pp = ap->private_data;
242
243 pp->state = qs_state_idle;
244 qs_reset_channel_logic(ap);
245 sata_phy_reset(ap);
246 }
247
248 static void qs_eng_timeout(struct ata_port *ap)
249 {
250 struct qs_port_priv *pp = ap->private_data;
251
252 if (pp->state != qs_state_idle) /* healthy paranoia */
253 pp->state = qs_state_mmio;
254 qs_reset_channel_logic(ap);
255 ata_eng_timeout(ap);
256 }
257
258 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
259 {
260 if (sc_reg > SCR_CONTROL)
261 return ~0U;
262 return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
263 }
264
265 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
266 {
267 if (sc_reg > SCR_CONTROL)
268 return;
269 writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
270 }
271
272 static void qs_fill_sg(struct ata_queued_cmd *qc)
273 {
274 struct scatterlist *sg;
275 struct ata_port *ap = qc->ap;
276 struct qs_port_priv *pp = ap->private_data;
277 unsigned int nelem;
278 u8 *prd = pp->pkt + QS_CPB_BYTES;
279
280 assert(qc->__sg != NULL);
281 assert(qc->n_elem > 0);
282
283 nelem = 0;
284 ata_for_each_sg(sg, qc) {
285 u64 addr;
286 u32 len;
287
288 addr = sg_dma_address(sg);
289 *(__le64 *)prd = cpu_to_le64(addr);
290 prd += sizeof(u64);
291
292 len = sg_dma_len(sg);
293 *(__le32 *)prd = cpu_to_le32(len);
294 prd += sizeof(u64);
295
296 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
297 (unsigned long long)addr, len);
298 nelem++;
299 }
300 }
301
302 static void qs_qc_prep(struct ata_queued_cmd *qc)
303 {
304 struct qs_port_priv *pp = qc->ap->private_data;
305 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
306 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
307 u64 addr;
308
309 VPRINTK("ENTER\n");
310
311 qs_enter_reg_mode(qc->ap);
312 if (qc->tf.protocol != ATA_PROT_DMA) {
313 ata_qc_prep(qc);
314 return;
315 }
316
317 qs_fill_sg(qc);
318
319 if ((qc->tf.flags & ATA_TFLAG_WRITE))
320 hflags |= QS_HF_DIRO;
321 if ((qc->tf.flags & ATA_TFLAG_LBA48))
322 dflags |= QS_DF_ELBA;
323
324 /* host control block (HCB) */
325 buf[ 0] = QS_HCB_HDR;
326 buf[ 1] = hflags;
327 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE);
328 *(__le32 *)(&buf[ 8]) = cpu_to_le32(qc->n_elem);
329 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
330 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
331
332 /* device control block (DCB) */
333 buf[24] = QS_DCB_HDR;
334 buf[28] = dflags;
335
336 /* frame information structure (FIS) */
337 ata_tf_to_fis(&qc->tf, &buf[32], 0);
338 }
339
340 static inline void qs_packet_start(struct ata_queued_cmd *qc)
341 {
342 struct ata_port *ap = qc->ap;
343 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
344
345 VPRINTK("ENTER, ap %p\n", ap);
346
347 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
348 wmb(); /* flush PRDs and pkt to memory */
349 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
350 readl(chan + QS_CCT_CFF); /* flush */
351 }
352
353 static int qs_qc_issue(struct ata_queued_cmd *qc)
354 {
355 struct qs_port_priv *pp = qc->ap->private_data;
356
357 switch (qc->tf.protocol) {
358 case ATA_PROT_DMA:
359
360 pp->state = qs_state_pkt;
361 qs_packet_start(qc);
362 return 0;
363
364 case ATA_PROT_ATAPI_DMA:
365 BUG();
366 break;
367
368 default:
369 break;
370 }
371
372 pp->state = qs_state_mmio;
373 return ata_qc_issue_prot(qc);
374 }
375
376 static inline unsigned int qs_intr_pkt(struct ata_host_set *host_set)
377 {
378 unsigned int handled = 0;
379 u8 sFFE;
380 u8 __iomem *mmio_base = host_set->mmio_base;
381
382 do {
383 u32 sff0 = readl(mmio_base + QS_HST_SFF);
384 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
385 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
386 sFFE = sff1 >> 31; /* empty flag */
387
388 if (sEVLD) {
389 u8 sDST = sff0 >> 16; /* dev status */
390 u8 sHST = sff1 & 0x3f; /* host status */
391 unsigned int port_no = (sff1 >> 8) & 0x03;
392 struct ata_port *ap = host_set->ports[port_no];
393
394 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
395 sff1, sff0, port_no, sHST, sDST);
396 handled = 1;
397 if (ap && !(ap->flags &
398 (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
399 struct ata_queued_cmd *qc;
400 struct qs_port_priv *pp = ap->private_data;
401 if (!pp || pp->state != qs_state_pkt)
402 continue;
403 qc = ata_qc_from_tag(ap, ap->active_tag);
404 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
405 switch (sHST) {
406 case 0: /* successful CPB */
407 case 3: /* device error */
408 pp->state = qs_state_idle;
409 qs_enter_reg_mode(qc->ap);
410 ata_qc_complete(qc,
411 ac_err_mask(sDST));
412 break;
413 default:
414 break;
415 }
416 }
417 }
418 }
419 } while (!sFFE);
420 return handled;
421 }
422
423 static inline unsigned int qs_intr_mmio(struct ata_host_set *host_set)
424 {
425 unsigned int handled = 0, port_no;
426
427 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
428 struct ata_port *ap;
429 ap = host_set->ports[port_no];
430 if (ap &&
431 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
432 struct ata_queued_cmd *qc;
433 struct qs_port_priv *pp = ap->private_data;
434 if (!pp || pp->state != qs_state_mmio)
435 continue;
436 qc = ata_qc_from_tag(ap, ap->active_tag);
437 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
438
439 /* check main status, clearing INTRQ */
440 u8 status = ata_check_status(ap);
441 if ((status & ATA_BUSY))
442 continue;
443 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
444 ap->id, qc->tf.protocol, status);
445
446 /* complete taskfile transaction */
447 pp->state = qs_state_idle;
448 ata_qc_complete(qc, ac_err_mask(status));
449 handled = 1;
450 }
451 }
452 }
453 return handled;
454 }
455
456 static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs)
457 {
458 struct ata_host_set *host_set = dev_instance;
459 unsigned int handled = 0;
460
461 VPRINTK("ENTER\n");
462
463 spin_lock(&host_set->lock);
464 handled = qs_intr_pkt(host_set) | qs_intr_mmio(host_set);
465 spin_unlock(&host_set->lock);
466
467 VPRINTK("EXIT\n");
468
469 return IRQ_RETVAL(handled);
470 }
471
472 static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base)
473 {
474 port->cmd_addr =
475 port->data_addr = base + 0x400;
476 port->error_addr =
477 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
478 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
479 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
480 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
481 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
482 port->device_addr = base + 0x430;
483 port->status_addr =
484 port->command_addr = base + 0x438;
485 port->altstatus_addr =
486 port->ctl_addr = base + 0x440;
487 port->scr_addr = base + 0xc00;
488 }
489
490 static int qs_port_start(struct ata_port *ap)
491 {
492 struct device *dev = ap->host_set->dev;
493 struct qs_port_priv *pp;
494 void __iomem *mmio_base = ap->host_set->mmio_base;
495 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
496 u64 addr;
497 int rc;
498
499 rc = ata_port_start(ap);
500 if (rc)
501 return rc;
502 qs_enter_reg_mode(ap);
503 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
504 if (!pp) {
505 rc = -ENOMEM;
506 goto err_out;
507 }
508 pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
509 GFP_KERNEL);
510 if (!pp->pkt) {
511 rc = -ENOMEM;
512 goto err_out_kfree;
513 }
514 memset(pp->pkt, 0, QS_PKT_BYTES);
515 ap->private_data = pp;
516
517 addr = (u64)pp->pkt_dma;
518 writel((u32) addr, chan + QS_CCF_CPBA);
519 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
520 return 0;
521
522 err_out_kfree:
523 kfree(pp);
524 err_out:
525 ata_port_stop(ap);
526 return rc;
527 }
528
529 static void qs_port_stop(struct ata_port *ap)
530 {
531 struct device *dev = ap->host_set->dev;
532 struct qs_port_priv *pp = ap->private_data;
533
534 if (pp != NULL) {
535 ap->private_data = NULL;
536 if (pp->pkt != NULL)
537 dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt,
538 pp->pkt_dma);
539 kfree(pp);
540 }
541 ata_port_stop(ap);
542 }
543
544 static void qs_host_stop(struct ata_host_set *host_set)
545 {
546 void __iomem *mmio_base = host_set->mmio_base;
547 struct pci_dev *pdev = to_pci_dev(host_set->dev);
548
549 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
550 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
551
552 pci_iounmap(pdev, mmio_base);
553 }
554
555 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
556 {
557 void __iomem *mmio_base = pe->mmio_base;
558 unsigned int port_no;
559
560 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
561 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
562
563 /* reset each channel in turn */
564 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
565 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
566 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
567 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
568 readb(chan + QS_CCT_CTR0); /* flush */
569 }
570 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
571
572 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
573 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
574 /* set FIFO depths to same settings as Windows driver */
575 writew(32, chan + QS_CFC_HUFT);
576 writew(32, chan + QS_CFC_HDFT);
577 writew(10, chan + QS_CFC_DUFT);
578 writew( 8, chan + QS_CFC_DDFT);
579 /* set CPB size in bytes, as a power of two */
580 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
581 }
582 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
583 }
584
585 /*
586 * The QStor understands 64-bit buses, and uses 64-bit fields
587 * for DMA pointers regardless of bus width. We just have to
588 * make sure our DMA masks are set appropriately for whatever
589 * bridge lies between us and the QStor, and then the DMA mapping
590 * code will ensure we only ever "see" appropriate buffer addresses.
591 * If we're 32-bit limited somewhere, then our 64-bit fields will
592 * just end up with zeros in the upper 32-bits, without any special
593 * logic required outside of this routine (below).
594 */
595 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
596 {
597 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
598 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
599
600 if (have_64bit_bus &&
601 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
602 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
603 if (rc) {
604 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
605 if (rc) {
606 dev_printk(KERN_ERR, &pdev->dev,
607 "64-bit DMA enable failed\n");
608 return rc;
609 }
610 }
611 } else {
612 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
613 if (rc) {
614 dev_printk(KERN_ERR, &pdev->dev,
615 "32-bit DMA enable failed\n");
616 return rc;
617 }
618 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
619 if (rc) {
620 dev_printk(KERN_ERR, &pdev->dev,
621 "32-bit consistent DMA enable failed\n");
622 return rc;
623 }
624 }
625 return 0;
626 }
627
628 static int qs_ata_init_one(struct pci_dev *pdev,
629 const struct pci_device_id *ent)
630 {
631 static int printed_version;
632 struct ata_probe_ent *probe_ent = NULL;
633 void __iomem *mmio_base;
634 unsigned int board_idx = (unsigned int) ent->driver_data;
635 int rc, port_no;
636
637 if (!printed_version++)
638 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
639
640 rc = pci_enable_device(pdev);
641 if (rc)
642 return rc;
643
644 rc = pci_request_regions(pdev, DRV_NAME);
645 if (rc)
646 goto err_out;
647
648 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
649 rc = -ENODEV;
650 goto err_out_regions;
651 }
652
653 mmio_base = pci_iomap(pdev, 4, 0);
654 if (mmio_base == NULL) {
655 rc = -ENOMEM;
656 goto err_out_regions;
657 }
658
659 rc = qs_set_dma_masks(pdev, mmio_base);
660 if (rc)
661 goto err_out_iounmap;
662
663 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
664 if (probe_ent == NULL) {
665 rc = -ENOMEM;
666 goto err_out_iounmap;
667 }
668
669 memset(probe_ent, 0, sizeof(*probe_ent));
670 probe_ent->dev = pci_dev_to_dev(pdev);
671 INIT_LIST_HEAD(&probe_ent->node);
672
673 probe_ent->sht = qs_port_info[board_idx].sht;
674 probe_ent->host_flags = qs_port_info[board_idx].host_flags;
675 probe_ent->pio_mask = qs_port_info[board_idx].pio_mask;
676 probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask;
677 probe_ent->udma_mask = qs_port_info[board_idx].udma_mask;
678 probe_ent->port_ops = qs_port_info[board_idx].port_ops;
679
680 probe_ent->irq = pdev->irq;
681 probe_ent->irq_flags = SA_SHIRQ;
682 probe_ent->mmio_base = mmio_base;
683 probe_ent->n_ports = QS_PORTS;
684
685 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
686 unsigned long chan = (unsigned long)mmio_base +
687 (port_no * 0x4000);
688 qs_ata_setup_port(&probe_ent->port[port_no], chan);
689 }
690
691 pci_set_master(pdev);
692
693 /* initialize adapter */
694 qs_host_init(board_idx, probe_ent);
695
696 rc = ata_device_add(probe_ent);
697 kfree(probe_ent);
698 if (rc != QS_PORTS)
699 goto err_out_iounmap;
700 return 0;
701
702 err_out_iounmap:
703 pci_iounmap(pdev, mmio_base);
704 err_out_regions:
705 pci_release_regions(pdev);
706 err_out:
707 pci_disable_device(pdev);
708 return rc;
709 }
710
711 static int __init qs_ata_init(void)
712 {
713 return pci_module_init(&qs_ata_pci_driver);
714 }
715
716 static void __exit qs_ata_exit(void)
717 {
718 pci_unregister_driver(&qs_ata_pci_driver);
719 }
720
721 MODULE_AUTHOR("Mark Lord");
722 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
723 MODULE_LICENSE("GPL");
724 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
725 MODULE_VERSION(DRV_VERSION);
726
727 module_init(qs_ata_init);
728 module_exit(qs_ata_exit);
SocketAccessConTroL development