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[NETFILTER]: nf_nat_sip: translate all Contact headers
[linux-2.6/sactl.git] / drivers / net / smc91x.h
blob69e97a1cb1c4d5304904986119686c2e01df2bae
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK)
44
45 /* We can only do 16-bit reads and writes in the static memory space. */
46 #define SMC_CAN_USE_8BIT 0
47 #define SMC_CAN_USE_16BIT 1
48 #define SMC_CAN_USE_32BIT 0
49 #define SMC_NOWAIT 1
50
51 /* The first two address lines aren't connected... */
52 #define SMC_IO_SHIFT 2
53
54 #define SMC_inw(a, r) readw((a) + (r))
55 #define SMC_outw(v, a, r) writew(v, (a) + (r))
56 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
57 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
58 #define SMC_IRQ_FLAGS (-1) /* from resource */
59
60 #elif defined(CONFIG_BLACKFIN)
61
62 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
63 #define RPC_LSA_DEFAULT RPC_LED_100_10
64 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
65
66 # if defined (CONFIG_BFIN561_EZKIT)
67 #define SMC_CAN_USE_8BIT 0
68 #define SMC_CAN_USE_16BIT 1
69 #define SMC_CAN_USE_32BIT 1
70 #define SMC_IO_SHIFT 0
71 #define SMC_NOWAIT 1
72 #define SMC_USE_BFIN_DMA 0
73
74
75 #define SMC_inw(a, r) readw((a) + (r))
76 #define SMC_outw(v, a, r) writew(v, (a) + (r))
77 #define SMC_inl(a, r) readl((a) + (r))
78 #define SMC_outl(v, a, r) writel(v, (a) + (r))
79 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
80 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
81 # else
82 #define SMC_CAN_USE_8BIT 0
83 #define SMC_CAN_USE_16BIT 1
84 #define SMC_CAN_USE_32BIT 0
85 #define SMC_IO_SHIFT 0
86 #define SMC_NOWAIT 1
87 #define SMC_USE_BFIN_DMA 0
88
89
90 #define SMC_inw(a, r) readw((a) + (r))
91 #define SMC_outw(v, a, r) writew(v, (a) + (r))
92 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
93 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
94 # endif
95 /* check if the mac in reg is valid */
96 #define SMC_GET_MAC_ADDR(addr) \
97 do { \
98 unsigned int __v; \
99 __v = SMC_inw(ioaddr, ADDR0_REG); \
100 addr[0] = __v; addr[1] = __v >> 8; \
101 __v = SMC_inw(ioaddr, ADDR1_REG); \
102 addr[2] = __v; addr[3] = __v >> 8; \
103 __v = SMC_inw(ioaddr, ADDR2_REG); \
104 addr[4] = __v; addr[5] = __v >> 8; \
105 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
106 random_ether_addr(addr); \
107 } \
108 } while (0)
109 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
110
111 /* We can only do 16-bit reads and writes in the static memory space. */
112 #define SMC_CAN_USE_8BIT 0
113 #define SMC_CAN_USE_16BIT 1
114 #define SMC_CAN_USE_32BIT 0
115 #define SMC_NOWAIT 1
116
117 #define SMC_IO_SHIFT 0
118
119 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
120 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
121 #define SMC_insw(a, r, p, l) \
122 do { \
123 unsigned long __port = (a) + (r); \
124 u16 *__p = (u16 *)(p); \
125 int __l = (l); \
126 insw(__port, __p, __l); \
127 while (__l > 0) { \
128 *__p = swab16(*__p); \
129 __p++; \
130 __l--; \
131 } \
132 } while (0)
133 #define SMC_outsw(a, r, p, l) \
134 do { \
135 unsigned long __port = (a) + (r); \
136 u16 *__p = (u16 *)(p); \
137 int __l = (l); \
138 while (__l > 0) { \
139 /* Believe it or not, the swab isn't needed. */ \
140 outw( /* swab16 */ (*__p++), __port); \
141 __l--; \
142 } \
143 } while (0)
144 #define SMC_IRQ_FLAGS (0)
145
146 #elif defined(CONFIG_SA1100_PLEB)
147 /* We can only do 16-bit reads and writes in the static memory space. */
148 #define SMC_CAN_USE_8BIT 1
149 #define SMC_CAN_USE_16BIT 1
150 #define SMC_CAN_USE_32BIT 0
151 #define SMC_IO_SHIFT 0
152 #define SMC_NOWAIT 1
153
154 #define SMC_inb(a, r) readb((a) + (r))
155 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
156 #define SMC_inw(a, r) readw((a) + (r))
157 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
158 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
159 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
160 #define SMC_outw(v, a, r) writew(v, (a) + (r))
161 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
162
163 #define SMC_IRQ_FLAGS (-1)
164
165 #elif defined(CONFIG_SA1100_ASSABET)
166
167 #include <asm/arch/neponset.h>
168
169 /* We can only do 8-bit reads and writes in the static memory space. */
170 #define SMC_CAN_USE_8BIT 1
171 #define SMC_CAN_USE_16BIT 0
172 #define SMC_CAN_USE_32BIT 0
173 #define SMC_NOWAIT 1
174
175 /* The first two address lines aren't connected... */
176 #define SMC_IO_SHIFT 2
177
178 #define SMC_inb(a, r) readb((a) + (r))
179 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
180 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
181 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
182 #define SMC_IRQ_FLAGS (-1) /* from resource */
183
184 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
185
186 #define SMC_CAN_USE_8BIT 0
187 #define SMC_CAN_USE_16BIT 1
188 #define SMC_CAN_USE_32BIT 0
189 #define SMC_IO_SHIFT 0
190 #define SMC_NOWAIT 1
191
192 #define SMC_inw(a, r) readw((a) + (r))
193 #define SMC_outw(v, a, r) writew(v, (a) + (r))
194 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
195 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
196
197 #elif defined(CONFIG_ARCH_INNOKOM) || \
198 defined(CONFIG_MACH_MAINSTONE) || \
199 defined(CONFIG_ARCH_PXA_IDP) || \
200 defined(CONFIG_ARCH_RAMSES) || \
201 defined(CONFIG_ARCH_PCM027)
202
203 #define SMC_CAN_USE_8BIT 1
204 #define SMC_CAN_USE_16BIT 1
205 #define SMC_CAN_USE_32BIT 1
206 #define SMC_IO_SHIFT 0
207 #define SMC_NOWAIT 1
208 #define SMC_USE_PXA_DMA 1
209
210 #define SMC_inb(a, r) readb((a) + (r))
211 #define SMC_inw(a, r) readw((a) + (r))
212 #define SMC_inl(a, r) readl((a) + (r))
213 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
214 #define SMC_outl(v, a, r) writel(v, (a) + (r))
215 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
216 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
217 #define SMC_IRQ_FLAGS (-1) /* from resource */
218
219 /* We actually can't write halfwords properly if not word aligned */
220 static inline void
221 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
222 {
223 if (reg & 2) {
224 unsigned int v = val << 16;
225 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
226 writel(v, ioaddr + (reg & ~2));
227 } else {
228 writew(val, ioaddr + reg);
229 }
230 }
231
232 #elif defined(CONFIG_MACH_ZYLONITE)
233
234 #define SMC_CAN_USE_8BIT 1
235 #define SMC_CAN_USE_16BIT 1
236 #define SMC_CAN_USE_32BIT 0
237 #define SMC_IO_SHIFT 0
238 #define SMC_NOWAIT 1
239 #define SMC_USE_PXA_DMA 1
240 #define SMC_inb(a, r) readb((a) + (r))
241 #define SMC_inw(a, r) readw((a) + (r))
242 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
243 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
244 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
245 #define SMC_outw(v, a, r) writew(v, (a) + (r))
246 #define SMC_IRQ_FLAGS (-1) /* from resource */
247
248 #elif defined(CONFIG_ARCH_OMAP)
249
250 /* We can only do 16-bit reads and writes in the static memory space. */
251 #define SMC_CAN_USE_8BIT 0
252 #define SMC_CAN_USE_16BIT 1
253 #define SMC_CAN_USE_32BIT 0
254 #define SMC_IO_SHIFT 0
255 #define SMC_NOWAIT 1
256
257 #define SMC_inw(a, r) readw((a) + (r))
258 #define SMC_outw(v, a, r) writew(v, (a) + (r))
259 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
260 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
261 #define SMC_IRQ_FLAGS (-1) /* from resource */
262
263 #elif defined(CONFIG_SH_SH4202_MICRODEV)
264
265 #define SMC_CAN_USE_8BIT 0
266 #define SMC_CAN_USE_16BIT 1
267 #define SMC_CAN_USE_32BIT 0
268
269 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
270 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
271 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
272 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
273 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
274 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
275 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
276 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
277 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
278 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
279
280 #define SMC_IRQ_FLAGS (0)
281
282 #elif defined(CONFIG_ISA)
283
284 #define SMC_CAN_USE_8BIT 1
285 #define SMC_CAN_USE_16BIT 1
286 #define SMC_CAN_USE_32BIT 0
287
288 #define SMC_inb(a, r) inb((a) + (r))
289 #define SMC_inw(a, r) inw((a) + (r))
290 #define SMC_outb(v, a, r) outb(v, (a) + (r))
291 #define SMC_outw(v, a, r) outw(v, (a) + (r))
292 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
293 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
294
295 #elif defined(CONFIG_M32R)
296
297 #define SMC_CAN_USE_8BIT 0
298 #define SMC_CAN_USE_16BIT 1
299 #define SMC_CAN_USE_32BIT 0
300
301 #define SMC_inb(a, r) inb(((u32)a) + (r))
302 #define SMC_inw(a, r) inw(((u32)a) + (r))
303 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
304 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
305 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
306 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
307
308 #define SMC_IRQ_FLAGS (0)
309
310 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
311 #define RPC_LSB_DEFAULT RPC_LED_100_10
312
313 #elif defined(CONFIG_MACH_LPD79520) \
314 || defined(CONFIG_MACH_LPD7A400) \
315 || defined(CONFIG_MACH_LPD7A404)
316
317 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
318 * way that the CPU handles chip selects and the way that the SMC chip
319 * expects the chip select to operate. Refer to
320 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
321 * IOBARRIER is a byte, in order that we read the least-common
322 * denominator. It would be wasteful to read 32 bits from an 8-bit
323 * accessible region.
324 *
325 * There is no explicit protection against interrupts intervening
326 * between the writew and the IOBARRIER. In SMC ISR there is a
327 * preamble that performs an IOBARRIER in the extremely unlikely event
328 * that the driver interrupts itself between a writew to the chip an
329 * the IOBARRIER that follows *and* the cache is large enough that the
330 * first off-chip access while handing the interrupt is to the SMC
331 * chip. Other devices in the same address space as the SMC chip must
332 * be aware of the potential for trouble and perform a similar
333 * IOBARRIER on entry to their ISR.
334 */
335
336 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
337
338 #define SMC_CAN_USE_8BIT 0
339 #define SMC_CAN_USE_16BIT 1
340 #define SMC_CAN_USE_32BIT 0
341 #define SMC_NOWAIT 0
342 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
343
344 #define SMC_inw(a,r)\
345 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
346 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
347
348 #define SMC_insw LPD7_SMC_insw
349 static inline void LPD7_SMC_insw (unsigned char* a, int r,
350 unsigned char* p, int l)
351 {
352 unsigned short* ps = (unsigned short*) p;
353 while (l-- > 0) {
354 *ps++ = readw (a + r);
355 LPD7X_IOBARRIER;
356 }
357 }
358
359 #define SMC_outsw LPD7_SMC_outsw
360 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
361 unsigned char* p, int l)
362 {
363 unsigned short* ps = (unsigned short*) p;
364 while (l-- > 0) {
365 writew (*ps++, a + r);
366 LPD7X_IOBARRIER;
367 }
368 }
369
370 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
371
372 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
373 #define RPC_LSB_DEFAULT RPC_LED_100_10
374
375 #elif defined(CONFIG_SOC_AU1X00)
376
377 #include <au1xxx.h>
378
379 /* We can only do 16-bit reads and writes in the static memory space. */
380 #define SMC_CAN_USE_8BIT 0
381 #define SMC_CAN_USE_16BIT 1
382 #define SMC_CAN_USE_32BIT 0
383 #define SMC_IO_SHIFT 0
384 #define SMC_NOWAIT 1
385
386 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
387 #define SMC_insw(a, r, p, l) \
388 do { \
389 unsigned long _a = (unsigned long)((a) + (r)); \
390 int _l = (l); \
391 u16 *_p = (u16 *)(p); \
392 while (_l-- > 0) \
393 *_p++ = au_readw(_a); \
394 } while(0)
395 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
396 #define SMC_outsw(a, r, p, l) \
397 do { \
398 unsigned long _a = (unsigned long)((a) + (r)); \
399 int _l = (l); \
400 const u16 *_p = (const u16 *)(p); \
401 while (_l-- > 0) \
402 au_writew(*_p++ , _a); \
403 } while(0)
404
405 #define SMC_IRQ_FLAGS (0)
406
407 #elif defined(CONFIG_ARCH_VERSATILE)
408
409 #define SMC_CAN_USE_8BIT 1
410 #define SMC_CAN_USE_16BIT 1
411 #define SMC_CAN_USE_32BIT 1
412 #define SMC_NOWAIT 1
413
414 #define SMC_inb(a, r) readb((a) + (r))
415 #define SMC_inw(a, r) readw((a) + (r))
416 #define SMC_inl(a, r) readl((a) + (r))
417 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
418 #define SMC_outw(v, a, r) writew(v, (a) + (r))
419 #define SMC_outl(v, a, r) writel(v, (a) + (r))
420 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
421 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
422 #define SMC_IRQ_FLAGS (-1) /* from resource */
423
424 #elif defined(CONFIG_MN10300)
425
426 /*
427 * MN10300/AM33 configuration
428 */
429
430 #include <asm/unit/smc91111.h>
431
432 #else
433
434 /*
435 * Default configuration
436 */
437
438 #define SMC_CAN_USE_8BIT 1
439 #define SMC_CAN_USE_16BIT 1
440 #define SMC_CAN_USE_32BIT 1
441 #define SMC_NOWAIT 1
442
443 #define SMC_inb(a, r) readb((a) + (r))
444 #define SMC_inw(a, r) readw((a) + (r))
445 #define SMC_inl(a, r) readl((a) + (r))
446 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
447 #define SMC_outw(v, a, r) writew(v, (a) + (r))
448 #define SMC_outl(v, a, r) writel(v, (a) + (r))
449 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
450 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
451 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
452 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
453
454 #define RPC_LSA_DEFAULT RPC_LED_100_10
455 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
456
457 #define SMC_DYNAMIC_BUS_CONFIG
458 #endif
459
460
461 /* store this information for the driver.. */
462 struct smc_local {
463 /*
464 * If I have to wait until memory is available to send a
465 * packet, I will store the skbuff here, until I get the
466 * desired memory. Then, I'll send it out and free it.
467 */
468 struct sk_buff *pending_tx_skb;
469 struct tasklet_struct tx_task;
470
471 /* version/revision of the SMC91x chip */
472 int version;
473
474 /* Contains the current active transmission mode */
475 int tcr_cur_mode;
476
477 /* Contains the current active receive mode */
478 int rcr_cur_mode;
479
480 /* Contains the current active receive/phy mode */
481 int rpc_cur_mode;
482 int ctl_rfduplx;
483 int ctl_rspeed;
484
485 u32 msg_enable;
486 u32 phy_type;
487 struct mii_if_info mii;
488
489 /* work queue */
490 struct work_struct phy_configure;
491 struct net_device *dev;
492 int work_pending;
493
494 spinlock_t lock;
495
496 #ifdef SMC_USE_PXA_DMA
497 /* DMA needs the physical address of the chip */
498 u_long physaddr;
499 struct device *device;
500 #endif
501 void __iomem *base;
502 void __iomem *datacs;
503
504 struct smc91x_platdata cfg;
505 };
506
507 #ifdef SMC_DYNAMIC_BUS_CONFIG
508 #define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
509 #define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
510 #define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
511 #else
512 #define SMC_8BIT(p) SMC_CAN_USE_8BIT
513 #define SMC_16BIT(p) SMC_CAN_USE_16BIT
514 #define SMC_32BIT(p) SMC_CAN_USE_32BIT
515 #endif
516
517 #ifdef SMC_USE_PXA_DMA
518 /*
519 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
520 * always happening in irq context so no need to worry about races. TX is
521 * different and probably not worth it for that reason, and not as critical
522 * as RX which can overrun memory and lose packets.
523 */
524 #include <linux/dma-mapping.h>
525 #include <asm/dma.h>
526 #include <asm/arch/pxa-regs.h>
527
528 #ifdef SMC_insl
529 #undef SMC_insl
530 #define SMC_insl(a, r, p, l) \
531 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
532 static inline void
533 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
534 u_char *buf, int len)
535 {
536 u_long physaddr = lp->physaddr;
537 dma_addr_t dmabuf;
538
539 /* fallback if no DMA available */
540 if (dma == (unsigned char)-1) {
541 readsl(ioaddr + reg, buf, len);
542 return;
543 }
544
545 /* 64 bit alignment is required for memory to memory DMA */
546 if ((long)buf & 4) {
547 *((u32 *)buf) = SMC_inl(ioaddr, reg);
548 buf += 4;
549 len--;
550 }
551
552 len *= 4;
553 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
554 DCSR(dma) = DCSR_NODESC;
555 DTADR(dma) = dmabuf;
556 DSADR(dma) = physaddr + reg;
557 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
558 DCMD_WIDTH4 | (DCMD_LENGTH & len));
559 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
560 while (!(DCSR(dma) & DCSR_STOPSTATE))
561 cpu_relax();
562 DCSR(dma) = 0;
563 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
564 }
565 #endif
566
567 #ifdef SMC_insw
568 #undef SMC_insw
569 #define SMC_insw(a, r, p, l) \
570 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
571 static inline void
572 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
573 u_char *buf, int len)
574 {
575 u_long physaddr = lp->physaddr;
576 dma_addr_t dmabuf;
577
578 /* fallback if no DMA available */
579 if (dma == (unsigned char)-1) {
580 readsw(ioaddr + reg, buf, len);
581 return;
582 }
583
584 /* 64 bit alignment is required for memory to memory DMA */
585 while ((long)buf & 6) {
586 *((u16 *)buf) = SMC_inw(ioaddr, reg);
587 buf += 2;
588 len--;
589 }
590
591 len *= 2;
592 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
593 DCSR(dma) = DCSR_NODESC;
594 DTADR(dma) = dmabuf;
595 DSADR(dma) = physaddr + reg;
596 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
597 DCMD_WIDTH2 | (DCMD_LENGTH & len));
598 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
599 while (!(DCSR(dma) & DCSR_STOPSTATE))
600 cpu_relax();
601 DCSR(dma) = 0;
602 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
603 }
604 #endif
605
606 static void
607 smc_pxa_dma_irq(int dma, void *dummy)
608 {
609 DCSR(dma) = 0;
610 }
611 #endif /* SMC_USE_PXA_DMA */
612
613
614 /*
615 * Everything a particular hardware setup needs should have been defined
616 * at this point. Add stubs for the undefined cases, mainly to avoid
617 * compilation warnings since they'll be optimized away, or to prevent buggy
618 * use of them.
619 */
620
621 #if ! SMC_CAN_USE_32BIT
622 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
623 #define SMC_outl(x, ioaddr, reg) BUG()
624 #define SMC_insl(a, r, p, l) BUG()
625 #define SMC_outsl(a, r, p, l) BUG()
626 #endif
627
628 #if !defined(SMC_insl) || !defined(SMC_outsl)
629 #define SMC_insl(a, r, p, l) BUG()
630 #define SMC_outsl(a, r, p, l) BUG()
631 #endif
632
633 #if ! SMC_CAN_USE_16BIT
634
635 /*
636 * Any 16-bit access is performed with two 8-bit accesses if the hardware
637 * can't do it directly. Most registers are 16-bit so those are mandatory.
638 */
639 #define SMC_outw(x, ioaddr, reg) \
640 do { \
641 unsigned int __val16 = (x); \
642 SMC_outb( __val16, ioaddr, reg ); \
643 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
644 } while (0)
645 #define SMC_inw(ioaddr, reg) \
646 ({ \
647 unsigned int __val16; \
648 __val16 = SMC_inb( ioaddr, reg ); \
649 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
650 __val16; \
651 })
652
653 #define SMC_insw(a, r, p, l) BUG()
654 #define SMC_outsw(a, r, p, l) BUG()
655
656 #endif
657
658 #if !defined(SMC_insw) || !defined(SMC_outsw)
659 #define SMC_insw(a, r, p, l) BUG()
660 #define SMC_outsw(a, r, p, l) BUG()
661 #endif
662
663 #if ! SMC_CAN_USE_8BIT
664 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
665 #define SMC_outb(x, ioaddr, reg) BUG()
666 #define SMC_insb(a, r, p, l) BUG()
667 #define SMC_outsb(a, r, p, l) BUG()
668 #endif
669
670 #if !defined(SMC_insb) || !defined(SMC_outsb)
671 #define SMC_insb(a, r, p, l) BUG()
672 #define SMC_outsb(a, r, p, l) BUG()
673 #endif
674
675 #ifndef SMC_CAN_USE_DATACS
676 #define SMC_CAN_USE_DATACS 0
677 #endif
678
679 #ifndef SMC_IO_SHIFT
680 #define SMC_IO_SHIFT 0
681 #endif
682
683 #ifndef SMC_IRQ_FLAGS
684 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
685 #endif
686
687 #ifndef SMC_INTERRUPT_PREAMBLE
688 #define SMC_INTERRUPT_PREAMBLE
689 #endif
690
691
692 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
693 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
694 #define SMC_DATA_EXTENT (4)
695
696 /*
697 . Bank Select Register:
698 .
699 . yyyy yyyy 0000 00xx
700 . xx = bank number
701 . yyyy yyyy = 0x33, for identification purposes.
702 */
703 #define BANK_SELECT (14 << SMC_IO_SHIFT)
704
705
706 // Transmit Control Register
707 /* BANK 0 */
708 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
709 #define TCR_ENABLE 0x0001 // When 1 we can transmit
710 #define TCR_LOOP 0x0002 // Controls output pin LBK
711 #define TCR_FORCOL 0x0004 // When 1 will force a collision
712 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
713 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
714 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
715 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
716 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
717 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
718 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
719
720 #define TCR_CLEAR 0 /* do NOTHING */
721 /* the default settings for the TCR register : */
722 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
723
724
725 // EPH Status Register
726 /* BANK 0 */
727 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
728 #define ES_TX_SUC 0x0001 // Last TX was successful
729 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
730 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
731 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
732 #define ES_16COL 0x0010 // 16 Collisions Reached
733 #define ES_SQET 0x0020 // Signal Quality Error Test
734 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
735 #define ES_TXDEFR 0x0080 // Transmit Deferred
736 #define ES_LATCOL 0x0200 // Late collision detected on last tx
737 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
738 #define ES_EXC_DEF 0x0800 // Excessive Deferral
739 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
740 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
741 #define ES_TXUNRN 0x8000 // Tx Underrun
742
743
744 // Receive Control Register
745 /* BANK 0 */
746 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
747 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
748 #define RCR_PRMS 0x0002 // Enable promiscuous mode
749 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
750 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
751 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
752 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
753 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
754 #define RCR_SOFTRST 0x8000 // resets the chip
755
756 /* the normal settings for the RCR register : */
757 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
758 #define RCR_CLEAR 0x0 // set it to a base state
759
760
761 // Counter Register
762 /* BANK 0 */
763 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
764
765
766 // Memory Information Register
767 /* BANK 0 */
768 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
769
770
771 // Receive/Phy Control Register
772 /* BANK 0 */
773 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
774 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
775 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
776 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
777 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
778 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
779 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
780 #define RPC_LED_RES (0x01) // LED = Reserved
781 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
782 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
783 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
784 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
785 #define RPC_LED_TX (0x06) // LED = TX packet occurred
786 #define RPC_LED_RX (0x07) // LED = RX packet occurred
787
788 #ifndef RPC_LSA_DEFAULT
789 #define RPC_LSA_DEFAULT RPC_LED_100
790 #endif
791 #ifndef RPC_LSB_DEFAULT
792 #define RPC_LSB_DEFAULT RPC_LED_FD
793 #endif
794
795 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
796
797
798 /* Bank 0 0x0C is reserved */
799
800 // Bank Select Register
801 /* All Banks */
802 #define BSR_REG 0x000E
803
804
805 // Configuration Reg
806 /* BANK 1 */
807 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
808 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
809 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
810 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
811 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
812
813 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
814 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
815
816
817 // Base Address Register
818 /* BANK 1 */
819 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
820
821
822 // Individual Address Registers
823 /* BANK 1 */
824 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
825 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
826 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
827
828
829 // General Purpose Register
830 /* BANK 1 */
831 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
832
833
834 // Control Register
835 /* BANK 1 */
836 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
837 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
838 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
839 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
840 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
841 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
842 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
843 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
844 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
845
846
847 // MMU Command Register
848 /* BANK 2 */
849 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
850 #define MC_BUSY 1 // When 1 the last release has not completed
851 #define MC_NOP (0<<5) // No Op
852 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
853 #define MC_RESET (2<<5) // Reset MMU to initial state
854 #define MC_REMOVE (3<<5) // Remove the current rx packet
855 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
856 #define MC_FREEPKT (5<<5) // Release packet in PNR register
857 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
858 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
859
860
861 // Packet Number Register
862 /* BANK 2 */
863 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
864
865
866 // Allocation Result Register
867 /* BANK 2 */
868 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
869 #define AR_FAILED 0x80 // Alocation Failed
870
871
872 // TX FIFO Ports Register
873 /* BANK 2 */
874 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
875 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
876
877 // RX FIFO Ports Register
878 /* BANK 2 */
879 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
880 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
881
882 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
883
884 // Pointer Register
885 /* BANK 2 */
886 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
887 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
888 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
889 #define PTR_READ 0x2000 // When 1 the operation is a read
890
891
892 // Data Register
893 /* BANK 2 */
894 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
895
896
897 // Interrupt Status/Acknowledge Register
898 /* BANK 2 */
899 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
900
901
902 // Interrupt Mask Register
903 /* BANK 2 */
904 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
905 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
906 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
907 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
908 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
909 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
910 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
911 #define IM_TX_INT 0x02 // Transmit Interrupt
912 #define IM_RCV_INT 0x01 // Receive Interrupt
913
914
915 // Multicast Table Registers
916 /* BANK 3 */
917 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
918 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
919 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
920 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
921
922
923 // Management Interface Register (MII)
924 /* BANK 3 */
925 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
926 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
927 #define MII_MDOE 0x0008 // MII Output Enable
928 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
929 #define MII_MDI 0x0002 // MII Input, pin MDI
930 #define MII_MDO 0x0001 // MII Output, pin MDO
931
932
933 // Revision Register
934 /* BANK 3 */
935 /* ( hi: chip id low: rev # ) */
936 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
937
938
939 // Early RCV Register
940 /* BANK 3 */
941 /* this is NOT on SMC9192 */
942 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
943 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
944 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
945
946
947 // External Register
948 /* BANK 7 */
949 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
950
951
952 #define CHIP_9192 3
953 #define CHIP_9194 4
954 #define CHIP_9195 5
955 #define CHIP_9196 6
956 #define CHIP_91100 7
957 #define CHIP_91100FD 8
958 #define CHIP_91111FD 9
959
960 static const char * chip_ids[ 16 ] = {
961 NULL, NULL, NULL,
962 /* 3 */ "SMC91C90/91C92",
963 /* 4 */ "SMC91C94",
964 /* 5 */ "SMC91C95",
965 /* 6 */ "SMC91C96",
966 /* 7 */ "SMC91C100",
967 /* 8 */ "SMC91C100FD",
968 /* 9 */ "SMC91C11xFD",
969 NULL, NULL, NULL,
970 NULL, NULL, NULL};
971
972
973 /*
974 . Receive status bits
975 */
976 #define RS_ALGNERR 0x8000
977 #define RS_BRODCAST 0x4000
978 #define RS_BADCRC 0x2000
979 #define RS_ODDFRAME 0x1000
980 #define RS_TOOLONG 0x0800
981 #define RS_TOOSHORT 0x0400
982 #define RS_MULTICAST 0x0001
983 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
984
985
986 /*
987 * PHY IDs
988 * LAN83C183 == LAN91C111 Internal PHY
989 */
990 #define PHY_LAN83C183 0x0016f840
991 #define PHY_LAN83C180 0x02821c50
992
993 /*
994 * PHY Register Addresses (LAN91C111 Internal PHY)
995 *
996 * Generic PHY registers can be found in <linux/mii.h>
997 *
998 * These phy registers are specific to our on-board phy.
999 */
1000
1001 // PHY Configuration Register 1
1002 #define PHY_CFG1_REG 0x10
1003 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
1004 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
1005 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1006 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1007 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1008 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1009 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1010 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1011 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1012 #define PHY_CFG1_TLVL_MASK 0x003C
1013 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1014
1015
1016 // PHY Configuration Register 2
1017 #define PHY_CFG2_REG 0x11
1018 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1019 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1020 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1021 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1022
1023 // PHY Status Output (and Interrupt status) Register
1024 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1025 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1026 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1027 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1028 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1029 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1030 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1031 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1032 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1033 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1034 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1035
1036 // PHY Interrupt/Status Mask Register
1037 #define PHY_MASK_REG 0x13 // Interrupt Mask
1038 // Uses the same bit definitions as PHY_INT_REG
1039
1040
1041 /*
1042 * SMC91C96 ethernet config and status registers.
1043 * These are in the "attribute" space.
1044 */
1045 #define ECOR 0x8000
1046 #define ECOR_RESET 0x80
1047 #define ECOR_LEVEL_IRQ 0x40
1048 #define ECOR_WR_ATTRIB 0x04
1049 #define ECOR_ENABLE 0x01
1050
1051 #define ECSR 0x8002
1052 #define ECSR_IOIS8 0x20
1053 #define ECSR_PWRDWN 0x04
1054 #define ECSR_INT 0x02
1055
1056 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1057
1058
1059 /*
1060 * Macros to abstract register access according to the data bus
1061 * capabilities. Please use those and not the in/out primitives.
1062 * Note: the following macros do *not* select the bank -- this must
1063 * be done separately as needed in the main code. The SMC_REG() macro
1064 * only uses the bank argument for debugging purposes (when enabled).
1065 *
1066 * Note: despite inline functions being safer, everything leading to this
1067 * should preferably be macros to let BUG() display the line number in
1068 * the core source code since we're interested in the top call site
1069 * not in any inline function location.
1070 */
1071
1072 #if SMC_DEBUG > 0
1073 #define SMC_REG(lp, reg, bank) \
1074 ({ \
1075 int __b = SMC_CURRENT_BANK(lp); \
1076 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1077 printk( "%s: bank reg screwed (0x%04x)\n", \
1078 CARDNAME, __b ); \
1079 BUG(); \
1080 } \
1081 reg<<SMC_IO_SHIFT; \
1082 })
1083 #else
1084 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1085 #endif
1086
1087 /*
1088 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1089 * aligned to a 32 bit boundary. I tell you that does exist!
1090 * Fortunately the affected register accesses can be easily worked around
1091 * since we can write zeroes to the preceeding 16 bits without adverse
1092 * effects and use a 32-bit access.
1093 *
1094 * Enforce it on any 32-bit capable setup for now.
1095 */
1096 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1097
1098 #define SMC_GET_PN(lp) \
1099 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1100 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1101
1102 #define SMC_SET_PN(lp, x) \
1103 do { \
1104 if (SMC_MUST_ALIGN_WRITE(lp)) \
1105 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1106 else if (SMC_8BIT(lp)) \
1107 SMC_outb(x, ioaddr, PN_REG(lp)); \
1108 else \
1109 SMC_outw(x, ioaddr, PN_REG(lp)); \
1110 } while (0)
1111
1112 #define SMC_GET_AR(lp) \
1113 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1114 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1115
1116 #define SMC_GET_TXFIFO(lp) \
1117 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1118 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1119
1120 #define SMC_GET_RXFIFO(lp) \
1121 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1122 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1123
1124 #define SMC_GET_INT(lp) \
1125 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1126 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1127
1128 #define SMC_ACK_INT(lp, x) \
1129 do { \
1130 if (SMC_8BIT(lp)) \
1131 SMC_outb(x, ioaddr, INT_REG(lp)); \
1132 else { \
1133 unsigned long __flags; \
1134 int __mask; \
1135 local_irq_save(__flags); \
1136 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1137 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1138 local_irq_restore(__flags); \
1139 } \
1140 } while (0)
1141
1142 #define SMC_GET_INT_MASK(lp) \
1143 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1144 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1145
1146 #define SMC_SET_INT_MASK(lp, x) \
1147 do { \
1148 if (SMC_8BIT(lp)) \
1149 SMC_outb(x, ioaddr, IM_REG(lp)); \
1150 else \
1151 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1152 } while (0)
1153
1154 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1155
1156 #define SMC_SELECT_BANK(lp, x) \
1157 do { \
1158 if (SMC_MUST_ALIGN_WRITE(lp)) \
1159 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1160 else \
1161 SMC_outw(x, ioaddr, BANK_SELECT); \
1162 } while (0)
1163
1164 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1165
1166 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1167
1168 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1169
1170 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1171
1172 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1173
1174 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1175
1176 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1177
1178 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1179
1180 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1181
1182 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1183
1184 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1185
1186 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1187
1188 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1189
1190 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1191
1192 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1193
1194 #define SMC_SET_PTR(lp, x) \
1195 do { \
1196 if (SMC_MUST_ALIGN_WRITE(lp)) \
1197 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1198 else \
1199 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1200 } while (0)
1201
1202 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1203
1204 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1205
1206 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1207
1208 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1209
1210 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1211
1212 #define SMC_SET_RPC(lp, x) \
1213 do { \
1214 if (SMC_MUST_ALIGN_WRITE(lp)) \
1215 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1216 else \
1217 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1218 } while (0)
1219
1220 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1221
1222 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1223
1224 #ifndef SMC_GET_MAC_ADDR
1225 #define SMC_GET_MAC_ADDR(lp, addr) \
1226 do { \
1227 unsigned int __v; \
1228 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1229 addr[0] = __v; addr[1] = __v >> 8; \
1230 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1231 addr[2] = __v; addr[3] = __v >> 8; \
1232 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1233 addr[4] = __v; addr[5] = __v >> 8; \
1234 } while (0)
1235 #endif
1236
1237 #define SMC_SET_MAC_ADDR(lp, addr) \
1238 do { \
1239 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1240 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1241 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1242 } while (0)
1243
1244 #define SMC_SET_MCAST(lp, x) \
1245 do { \
1246 const unsigned char *mt = (x); \
1247 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1248 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1249 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1250 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1251 } while (0)
1252
1253 #define SMC_PUT_PKT_HDR(lp, status, length) \
1254 do { \
1255 if (SMC_32BIT(lp)) \
1256 SMC_outl((status) | (length)<<16, ioaddr, \
1257 DATA_REG(lp)); \
1258 else { \
1259 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1260 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1261 } \
1262 } while (0)
1263
1264 #define SMC_GET_PKT_HDR(lp, status, length) \
1265 do { \
1266 if (SMC_32BIT(lp)) { \
1267 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1268 (status) = __val & 0xffff; \
1269 (length) = __val >> 16; \
1270 } else { \
1271 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1272 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1273 } \
1274 } while (0)
1275
1276 #define SMC_PUSH_DATA(lp, p, l) \
1277 do { \
1278 if (SMC_32BIT(lp)) { \
1279 void *__ptr = (p); \
1280 int __len = (l); \
1281 void __iomem *__ioaddr = ioaddr; \
1282 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1283 __len -= 2; \
1284 SMC_outw(*(u16 *)__ptr, ioaddr, \
1285 DATA_REG(lp)); \
1286 __ptr += 2; \
1287 } \
1288 if (SMC_CAN_USE_DATACS && lp->datacs) \
1289 __ioaddr = lp->datacs; \
1290 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1291 if (__len & 2) { \
1292 __ptr += (__len & ~3); \
1293 SMC_outw(*((u16 *)__ptr), ioaddr, \
1294 DATA_REG(lp)); \
1295 } \
1296 } else if (SMC_16BIT(lp)) \
1297 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1298 else if (SMC_8BIT(lp)) \
1299 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1300 } while (0)
1301
1302 #define SMC_PULL_DATA(lp, p, l) \
1303 do { \
1304 if (SMC_32BIT(lp)) { \
1305 void *__ptr = (p); \
1306 int __len = (l); \
1307 void __iomem *__ioaddr = ioaddr; \
1308 if ((unsigned long)__ptr & 2) { \
1309 /* \
1310 * We want 32bit alignment here. \
1311 * Since some buses perform a full \
1312 * 32bit fetch even for 16bit data \
1313 * we can't use SMC_inw() here. \
1314 * Back both source (on-chip) and \
1315 * destination pointers of 2 bytes. \
1316 * This is possible since the call to \
1317 * SMC_GET_PKT_HDR() already advanced \
1318 * the source pointer of 4 bytes, and \
1319 * the skb_reserve(skb, 2) advanced \
1320 * the destination pointer of 2 bytes. \
1321 */ \
1322 __ptr -= 2; \
1323 __len += 2; \
1324 SMC_SET_PTR(lp, \
1325 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1326 } \
1327 if (SMC_CAN_USE_DATACS && lp->datacs) \
1328 __ioaddr = lp->datacs; \
1329 __len += 2; \
1330 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1331 } else if (SMC_16BIT(lp)) \
1332 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1333 else if (SMC_8BIT(lp)) \
1334 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1335 } while (0)
1336
1337 #endif /* _SMC91X_H_ */
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