1 /* Silan SC92031 PCI Fast Ethernet Adapter driver
3 * Based on vendor drivers:
4 * Silan Fast Ethernet Netcard Driver:
5 * MODULE_AUTHOR ("gaoyonghong");
6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
7 * MODULE_LICENSE("GPL");
8 * 8139D Fast Ethernet driver:
9 * (C) 2002 by gaoyonghong
10 * MODULE_AUTHOR ("gaoyonghong");
11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
12 * MODULE_LICENSE("GPL");
13 * Both are almost identical and seem to be based on pci-skeleton.c
15 * Rewritten for 2.6 by Cesar Eduardo Barros
18 /* Note about set_mac_address: I don't know how to change the hardware
19 * matching, so you need to enable IFF_PROMISC when using it.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/pci.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/crc32.h>
34 #define PCI_VENDOR_ID_SILAN 0x1904
35 #define PCI_DEVICE_ID_SILAN_SC92031 0x2031
36 #define PCI_DEVICE_ID_SILAN_8139D 0x8139
38 #define SC92031_NAME "sc92031"
39 #define SC92031_DESCRIPTION "Silan SC92031 PCI Fast Ethernet Adapter driver"
40 #define SC92031_VERSION "2.0c"
42 /* BAR 0 is MMIO, BAR 1 is PIO */
43 #ifndef SC92031_USE_BAR
44 #define SC92031_USE_BAR 0
47 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
48 static int multicast_filter_limit
= 64;
49 module_param(multicast_filter_limit
, int, 0);
50 MODULE_PARM_DESC(multicast_filter_limit
,
51 "Maximum number of filtered multicast addresses");
54 module_param(media
, int, 0);
55 MODULE_PARM_DESC(media
, "Media type (0x00 = autodetect,"
56 " 0x01 = 10M half, 0x02 = 10M full,"
57 " 0x04 = 100M half, 0x08 = 100M full)");
59 /* Size of the in-memory receive ring. */
60 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
61 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
63 /* Number of Tx descriptor registers. */
66 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
67 #define MAX_ETH_FRAME_SIZE 1536
69 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
70 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
71 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
73 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
74 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
76 /* Time in jiffies before concluding the transmitter is hung. */
77 #define TX_TIMEOUT (4*HZ)
79 #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
82 #define AUTOSELECT 0x00
85 #define M100_HALF 0x04
86 #define M100_FULL 0x08
88 /* Symbolic offsets to registers. */
89 enum silan_registers
{
90 Config0
= 0x00, // Config0
91 Config1
= 0x04, // Config1
92 RxBufWPtr
= 0x08, // Rx buffer writer poiter
93 IntrStatus
= 0x0C, // Interrupt status
94 IntrMask
= 0x10, // Interrupt mask
95 RxbufAddr
= 0x14, // Rx buffer start address
96 RxBufRPtr
= 0x18, // Rx buffer read pointer
97 Txstatusall
= 0x1C, // Transmit status of all descriptors
98 TxStatus0
= 0x20, // Transmit status (Four 32bit registers).
99 TxAddr0
= 0x30, // Tx descriptors (also four 32bit).
100 RxConfig
= 0x40, // Rx configuration
101 MAC0
= 0x44, // Ethernet hardware address.
102 MAR0
= 0x4C, // Multicast filter.
103 RxStatus0
= 0x54, // Rx status
104 TxConfig
= 0x5C, // Tx configuration
105 PhyCtrl
= 0x60, // physical control
106 FlowCtrlConfig
= 0x64, // flow control
107 Miicmd0
= 0x68, // Mii command0 register
108 Miicmd1
= 0x6C, // Mii command1 register
109 Miistatus
= 0x70, // Mii status register
110 Timercnt
= 0x74, // Timer counter register
111 TimerIntr
= 0x78, // Timer interrupt register
112 PMConfig
= 0x7C, // Power Manager configuration
113 CRC0
= 0x80, // Power Manager CRC ( Two 32bit regisers)
114 Wakeup0
= 0x88, // power Manager wakeup( Eight 64bit regiser)
115 LSBCRC0
= 0xC8, // power Manager LSBCRC(Two 32bit regiser)
121 #define MII_BMCR 0 // Basic mode control register
122 #define MII_BMSR 1 // Basic mode status register
124 #define MII_OutputStatus 24
126 #define BMCR_FULLDPLX 0x0100 // Full duplex
127 #define BMCR_ANRESTART 0x0200 // Auto negotiation restart
128 #define BMCR_ANENABLE 0x1000 // Enable auto negotiation
129 #define BMCR_SPEED100 0x2000 // Select 100Mbps
130 #define BMSR_LSTATUS 0x0004 // Link status
131 #define PHY_16_JAB_ENB 0x1000
132 #define PHY_16_PORT_ENB 0x1
134 enum IntrStatusBits
{
135 LinkFail
= 0x80000000,
137 TimeOut
= 0x20000000,
141 IntrBits
= LinkFail
|LinkOK
|TimeOut
|RxOverflow
|RxOK
|TxOK
,
145 TxCarrierLost
= 0x20000000,
146 TxAborted
= 0x10000000,
147 TxOutOfWindow
= 0x08000000,
149 EarlyTxThresShift
= 16,
156 RxStatesOK
= 0x80000,
157 RxBadAlign
= 0x40000,
158 RxHugeFrame
= 0x20000,
159 RxSmallFrame
= 0x10000,
162 Rx_Broadcast
= 0x2000,
163 Rx_Multicast
= 0x1000,
164 RxAddrMatch
= 0x0800,
169 RxFullDx
= 0x80000000,
171 RxSmall
= 0x20000000,
174 RxAllphys
= 0x04000000,
175 RxMulticast
= 0x02000000,
176 RxBroadcast
= 0x01000000,
177 RxLoopBack
= (1 << 23) | (1 << 22),
178 LowThresholdShift
= 12,
179 HighThresholdShift
= 2,
183 TxFullDx
= 0x80000000,
185 TxEnbPad
= 0x20000000,
186 TxEnbHuge
= 0x10000000,
187 TxEnbFCS
= 0x08000000,
188 TxNoBackOff
= 0x04000000,
189 TxEnbPrem
= 0x02000000,
190 TxCareLostCrs
= 0x1000000,
191 TxExdCollNum
= 0xf00000,
192 TxDataRate
= 0x80000,
195 enum PhyCtrlconfigbits
{
196 PhyCtrlAne
= 0x80000000,
197 PhyCtrlSpd100
= 0x40000000,
198 PhyCtrlSpd10
= 0x20000000,
199 PhyCtrlPhyBaseAddr
= 0x1f000000,
200 PhyCtrlDux
= 0x800000,
201 PhyCtrlReset
= 0x400000,
204 enum FlowCtrlConfigBits
{
205 FlowCtrlFullDX
= 0x80000000,
206 FlowCtrlEnb
= 0x40000000,
210 Cfg0_Reset
= 0x80000000,
211 Cfg0_Anaoff
= 0x40000000,
212 Cfg0_LDPS
= 0x20000000,
216 Cfg1_EarlyRx
= 1 << 31,
217 Cfg1_EarlyTx
= 1 << 30,
228 Mii_Divider
= 0x20000000,
229 Mii_WRITE
= 0x400000,
233 Mii_Drvmod
= 0x40000,
241 Mii_StatusBusy
= 0x80000000,
248 PM_LANWake
= 1 << 28,
249 PM_LWPTN
= (1 << 27 | 1<< 26),
255 * priv->lock protects most of the fields of priv and most of the
256 * hardware registers. It does not have to protect against softirqs
257 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
258 * it also does not need to be used in ->open and ->stop while the
259 * device interrupts are off.
260 * Not having to protect against softirqs is very useful due to heavy
261 * use of mdelay() at _sc92031_reset.
262 * Functions prefixed with _sc92031_ must be called with the lock held;
263 * functions prefixed with sc92031_ must be called without the lock held.
264 * Use mmiowb() before unlocking if the hardware was written to.
267 /* Locking rules for the interrupt:
268 * - the interrupt and the tasklet never run at the same time
269 * - neither run between sc92031_disable_interrupts and
270 * sc92031_enable_interrupt
273 struct sc92031_priv
{
276 void __iomem
*port_base
;
277 /* pci device structure */
278 struct pci_dev
*pdev
;
280 struct tasklet_struct tasklet
;
282 /* CPU address of rx ring */
284 /* PCI address of rx ring */
285 dma_addr_t rx_ring_dma_addr
;
286 /* PCI address of rx ring read pointer */
287 dma_addr_t rx_ring_tail
;
289 /* tx ring write index */
291 /* tx ring read index */
293 /* CPU address of tx bounce buffer */
295 /* PCI address of tx bounce buffer */
296 dma_addr_t tx_bufs_dma_addr
;
298 /* copies of some hardware registers */
305 /* copy of some flags from dev->flags */
306 unsigned int mc_flags
;
308 /* for ETHTOOL_GSTATS */
312 /* for dev->get_stats */
314 struct net_device_stats stats
;
317 /* I don't know which registers can be safely read; however, I can guess
318 * MAC0 is one of them. */
319 static inline void _sc92031_dummy_read(void __iomem
*port_base
)
321 ioread32(port_base
+ MAC0
);
324 static u32
_sc92031_mii_wait(void __iomem
*port_base
)
330 mii_status
= ioread32(port_base
+ Miistatus
);
331 } while (mii_status
& Mii_StatusBusy
);
336 static u32
_sc92031_mii_cmd(void __iomem
*port_base
, u32 cmd0
, u32 cmd1
)
338 iowrite32(Mii_Divider
, port_base
+ Miicmd0
);
340 _sc92031_mii_wait(port_base
);
342 iowrite32(cmd1
, port_base
+ Miicmd1
);
343 iowrite32(Mii_Divider
| cmd0
, port_base
+ Miicmd0
);
345 return _sc92031_mii_wait(port_base
);
348 static void _sc92031_mii_scan(void __iomem
*port_base
)
350 _sc92031_mii_cmd(port_base
, Mii_SCAN
, 0x1 << 6);
353 static u16
_sc92031_mii_read(void __iomem
*port_base
, unsigned reg
)
355 return _sc92031_mii_cmd(port_base
, Mii_READ
, reg
<< 6) >> 13;
358 static void _sc92031_mii_write(void __iomem
*port_base
, unsigned reg
, u16 val
)
360 _sc92031_mii_cmd(port_base
, Mii_WRITE
, (reg
<< 6) | ((u32
)val
<< 11));
363 static void sc92031_disable_interrupts(struct net_device
*dev
)
365 struct sc92031_priv
*priv
= netdev_priv(dev
);
366 void __iomem
*port_base
= priv
->port_base
;
368 /* tell the tasklet/interrupt not to enable interrupts */
369 atomic_set(&priv
->intr_mask
, 0);
372 /* stop interrupts */
373 iowrite32(0, port_base
+ IntrMask
);
374 _sc92031_dummy_read(port_base
);
377 /* wait for any concurrent interrupt/tasklet to finish */
378 synchronize_irq(dev
->irq
);
379 tasklet_disable(&priv
->tasklet
);
382 static void sc92031_enable_interrupts(struct net_device
*dev
)
384 struct sc92031_priv
*priv
= netdev_priv(dev
);
385 void __iomem
*port_base
= priv
->port_base
;
387 tasklet_enable(&priv
->tasklet
);
389 atomic_set(&priv
->intr_mask
, IntrBits
);
392 iowrite32(IntrBits
, port_base
+ IntrMask
);
396 static void _sc92031_disable_tx_rx(struct net_device
*dev
)
398 struct sc92031_priv
*priv
= netdev_priv(dev
);
399 void __iomem
*port_base
= priv
->port_base
;
401 priv
->rx_config
&= ~RxEnb
;
402 priv
->tx_config
&= ~TxEnb
;
403 iowrite32(priv
->rx_config
, port_base
+ RxConfig
);
404 iowrite32(priv
->tx_config
, port_base
+ TxConfig
);
407 static void _sc92031_enable_tx_rx(struct net_device
*dev
)
409 struct sc92031_priv
*priv
= netdev_priv(dev
);
410 void __iomem
*port_base
= priv
->port_base
;
412 priv
->rx_config
|= RxEnb
;
413 priv
->tx_config
|= TxEnb
;
414 iowrite32(priv
->rx_config
, port_base
+ RxConfig
);
415 iowrite32(priv
->tx_config
, port_base
+ TxConfig
);
418 static void _sc92031_tx_clear(struct net_device
*dev
)
420 struct sc92031_priv
*priv
= netdev_priv(dev
);
422 while (priv
->tx_head
- priv
->tx_tail
> 0) {
424 priv
->stats
.tx_dropped
++;
426 priv
->tx_head
= priv
->tx_tail
= 0;
429 static void _sc92031_set_mar(struct net_device
*dev
)
431 struct sc92031_priv
*priv
= netdev_priv(dev
);
432 void __iomem
*port_base
= priv
->port_base
;
433 u32 mar0
= 0, mar1
= 0;
435 if ((dev
->flags
& IFF_PROMISC
)
436 || dev
->mc_count
> multicast_filter_limit
437 || (dev
->flags
& IFF_ALLMULTI
))
438 mar0
= mar1
= 0xffffffff;
439 else if (dev
->flags
& IFF_MULTICAST
) {
440 struct dev_mc_list
*mc_list
;
442 for (mc_list
= dev
->mc_list
; mc_list
; mc_list
= mc_list
->next
) {
446 crc
= ~ether_crc(ETH_ALEN
, mc_list
->dmi_addr
);
449 if (crc
& 0x01) bit
|= 0x02;
450 if (crc
& 0x02) bit
|= 0x01;
451 if (crc
& 0x10) bit
|= 0x20;
452 if (crc
& 0x20) bit
|= 0x10;
453 if (crc
& 0x40) bit
|= 0x08;
454 if (crc
& 0x80) bit
|= 0x04;
457 mar0
|= 0x1 << (bit
- 32);
463 iowrite32(mar0
, port_base
+ MAR0
);
464 iowrite32(mar1
, port_base
+ MAR0
+ 4);
467 static void _sc92031_set_rx_config(struct net_device
*dev
)
469 struct sc92031_priv
*priv
= netdev_priv(dev
);
470 void __iomem
*port_base
= priv
->port_base
;
471 unsigned int old_mc_flags
;
472 u32 rx_config_bits
= 0;
474 old_mc_flags
= priv
->mc_flags
;
476 if (dev
->flags
& IFF_PROMISC
)
477 rx_config_bits
|= RxSmall
| RxHuge
| RxErr
| RxBroadcast
478 | RxMulticast
| RxAllphys
;
480 if (dev
->flags
& (IFF_ALLMULTI
| IFF_MULTICAST
))
481 rx_config_bits
|= RxMulticast
;
483 if (dev
->flags
& IFF_BROADCAST
)
484 rx_config_bits
|= RxBroadcast
;
486 priv
->rx_config
&= ~(RxSmall
| RxHuge
| RxErr
| RxBroadcast
487 | RxMulticast
| RxAllphys
);
488 priv
->rx_config
|= rx_config_bits
;
490 priv
->mc_flags
= dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
491 | IFF_MULTICAST
| IFF_BROADCAST
);
493 if (netif_carrier_ok(dev
) && priv
->mc_flags
!= old_mc_flags
)
494 iowrite32(priv
->rx_config
, port_base
+ RxConfig
);
497 static bool _sc92031_check_media(struct net_device
*dev
)
499 struct sc92031_priv
*priv
= netdev_priv(dev
);
500 void __iomem
*port_base
= priv
->port_base
;
503 bmsr
= _sc92031_mii_read(port_base
, MII_BMSR
);
505 if (bmsr
& BMSR_LSTATUS
) {
506 bool speed_100
, duplex_full
;
507 u32 flow_ctrl_config
= 0;
508 u16 output_status
= _sc92031_mii_read(port_base
,
510 _sc92031_mii_scan(port_base
);
512 speed_100
= output_status
& 0x2;
513 duplex_full
= output_status
& 0x4;
515 /* Initial Tx/Rx configuration */
516 priv
->rx_config
= (0x40 << LowThresholdShift
) | (0x1c0 << HighThresholdShift
);
517 priv
->tx_config
= 0x48800000;
519 /* NOTE: vendor driver had dead code here to enable tx padding */
522 priv
->tx_config
|= 0x80000;
525 _sc92031_set_rx_config(dev
);
528 priv
->rx_config
|= RxFullDx
;
529 priv
->tx_config
|= TxFullDx
;
530 flow_ctrl_config
= FlowCtrlFullDX
| FlowCtrlEnb
;
532 priv
->rx_config
&= ~RxFullDx
;
533 priv
->tx_config
&= ~TxFullDx
;
536 _sc92031_set_mar(dev
);
537 _sc92031_set_rx_config(dev
);
538 _sc92031_enable_tx_rx(dev
);
539 iowrite32(flow_ctrl_config
, port_base
+ FlowCtrlConfig
);
541 netif_carrier_on(dev
);
543 if (printk_ratelimit())
544 printk(KERN_INFO
"%s: link up, %sMbps, %s-duplex\n",
546 speed_100
? "100" : "10",
547 duplex_full
? "full" : "half");
550 _sc92031_mii_scan(port_base
);
552 netif_carrier_off(dev
);
554 _sc92031_disable_tx_rx(dev
);
556 if (printk_ratelimit())
557 printk(KERN_INFO
"%s: link down\n", dev
->name
);
562 static void _sc92031_phy_reset(struct net_device
*dev
)
564 struct sc92031_priv
*priv
= netdev_priv(dev
);
565 void __iomem
*port_base
= priv
->port_base
;
568 phy_ctrl
= ioread32(port_base
+ PhyCtrl
);
569 phy_ctrl
&= ~(PhyCtrlDux
| PhyCtrlSpd100
| PhyCtrlSpd10
);
570 phy_ctrl
|= PhyCtrlAne
| PhyCtrlReset
;
575 phy_ctrl
|= PhyCtrlDux
| PhyCtrlSpd100
| PhyCtrlSpd10
;
578 phy_ctrl
|= PhyCtrlSpd10
;
581 phy_ctrl
|= PhyCtrlDux
| PhyCtrlSpd10
;
584 phy_ctrl
|= PhyCtrlSpd100
;
587 phy_ctrl
|= PhyCtrlDux
| PhyCtrlSpd100
;
591 iowrite32(phy_ctrl
, port_base
+ PhyCtrl
);
594 phy_ctrl
&= ~PhyCtrlReset
;
595 iowrite32(phy_ctrl
, port_base
+ PhyCtrl
);
598 _sc92031_mii_write(port_base
, MII_JAB
,
599 PHY_16_JAB_ENB
| PHY_16_PORT_ENB
);
600 _sc92031_mii_scan(port_base
);
602 netif_carrier_off(dev
);
603 netif_stop_queue(dev
);
606 static void _sc92031_reset(struct net_device
*dev
)
608 struct sc92031_priv
*priv
= netdev_priv(dev
);
609 void __iomem
*port_base
= priv
->port_base
;
612 iowrite32(0, port_base
+ PMConfig
);
614 /* soft reset the chip */
615 iowrite32(Cfg0_Reset
, port_base
+ Config0
);
618 iowrite32(0, port_base
+ Config0
);
621 /* disable interrupts */
622 iowrite32(0, port_base
+ IntrMask
);
624 /* clear multicast address */
625 iowrite32(0, port_base
+ MAR0
);
626 iowrite32(0, port_base
+ MAR0
+ 4);
629 iowrite32(priv
->rx_ring_dma_addr
, port_base
+ RxbufAddr
);
630 priv
->rx_ring_tail
= priv
->rx_ring_dma_addr
;
633 _sc92031_tx_clear(dev
);
635 /* clear old register values */
636 priv
->intr_status
= 0;
637 atomic_set(&priv
->intr_mask
, 0);
642 /* configure rx buffer size */
643 /* NOTE: vendor driver had dead code here to enable early tx/rx */
644 iowrite32(Cfg1_Rcv64K
, port_base
+ Config1
);
646 _sc92031_phy_reset(dev
);
647 _sc92031_check_media(dev
);
649 /* calculate rx fifo overflow */
653 iowrite32(priv
->pm_config
, port_base
+ PMConfig
);
655 /* clear intr register */
656 ioread32(port_base
+ IntrStatus
);
659 static void _sc92031_tx_tasklet(struct net_device
*dev
)
661 struct sc92031_priv
*priv
= netdev_priv(dev
);
662 void __iomem
*port_base
= priv
->port_base
;
664 unsigned old_tx_tail
;
668 old_tx_tail
= priv
->tx_tail
;
669 while (priv
->tx_head
- priv
->tx_tail
> 0) {
670 entry
= priv
->tx_tail
% NUM_TX_DESC
;
671 tx_status
= ioread32(port_base
+ TxStatus0
+ entry
* 4);
673 if (!(tx_status
& (TxStatOK
| TxUnderrun
| TxAborted
)))
678 if (tx_status
& TxStatOK
) {
679 priv
->stats
.tx_bytes
+= tx_status
& 0x1fff;
680 priv
->stats
.tx_packets
++;
681 /* Note: TxCarrierLost is always asserted at 100mbps. */
682 priv
->stats
.collisions
+= (tx_status
>> 22) & 0xf;
685 if (tx_status
& (TxOutOfWindow
| TxAborted
)) {
686 priv
->stats
.tx_errors
++;
688 if (tx_status
& TxAborted
)
689 priv
->stats
.tx_aborted_errors
++;
691 if (tx_status
& TxCarrierLost
)
692 priv
->stats
.tx_carrier_errors
++;
694 if (tx_status
& TxOutOfWindow
)
695 priv
->stats
.tx_window_errors
++;
698 if (tx_status
& TxUnderrun
)
699 priv
->stats
.tx_fifo_errors
++;
702 if (priv
->tx_tail
!= old_tx_tail
)
703 if (netif_queue_stopped(dev
))
704 netif_wake_queue(dev
);
707 static void _sc92031_rx_tasklet_error(u32 rx_status
,
708 struct sc92031_priv
*priv
, unsigned rx_size
)
710 if(rx_size
> (MAX_ETH_FRAME_SIZE
+ 4) || rx_size
< 16) {
711 priv
->stats
.rx_errors
++;
712 priv
->stats
.rx_length_errors
++;
715 if (!(rx_status
& RxStatesOK
)) {
716 priv
->stats
.rx_errors
++;
718 if (rx_status
& (RxHugeFrame
| RxSmallFrame
))
719 priv
->stats
.rx_length_errors
++;
721 if (rx_status
& RxBadAlign
)
722 priv
->stats
.rx_frame_errors
++;
724 if (!(rx_status
& RxCRCOK
))
725 priv
->stats
.rx_crc_errors
++;
730 static void _sc92031_rx_tasklet(struct net_device
*dev
)
732 struct sc92031_priv
*priv
= netdev_priv(dev
);
733 void __iomem
*port_base
= priv
->port_base
;
735 dma_addr_t rx_ring_head
;
737 unsigned rx_ring_offset
;
738 void *rx_ring
= priv
->rx_ring
;
740 rx_ring_head
= ioread32(port_base
+ RxBufWPtr
);
743 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
744 * we need to change it to 32 bits physical address
746 rx_ring_head
&= (dma_addr_t
)(RX_BUF_LEN
- 1);
747 rx_ring_head
|= priv
->rx_ring_dma_addr
& ~(dma_addr_t
)(RX_BUF_LEN
- 1);
748 if (rx_ring_head
< priv
->rx_ring_dma_addr
)
749 rx_ring_head
+= RX_BUF_LEN
;
751 if (rx_ring_head
>= priv
->rx_ring_tail
)
752 rx_len
= rx_ring_head
- priv
->rx_ring_tail
;
754 rx_len
= RX_BUF_LEN
- (priv
->rx_ring_tail
- rx_ring_head
);
759 if (unlikely(rx_len
> RX_BUF_LEN
)) {
760 if (printk_ratelimit())
761 printk(KERN_ERR
"%s: rx packets length > rx buffer\n",
766 rx_ring_offset
= (priv
->rx_ring_tail
- priv
->rx_ring_dma_addr
) % RX_BUF_LEN
;
770 unsigned rx_size
, rx_size_align
, pkt_size
;
773 rx_status
= le32_to_cpup((__le32
*)(rx_ring
+ rx_ring_offset
));
776 rx_size
= rx_status
>> 20;
777 rx_size_align
= (rx_size
+ 3) & ~3; // for 4 bytes aligned
778 pkt_size
= rx_size
- 4; // Omit the four octet CRC from the length.
780 rx_ring_offset
= (rx_ring_offset
+ 4) % RX_BUF_LEN
;
782 if (unlikely(rx_status
== 0
783 || rx_size
> (MAX_ETH_FRAME_SIZE
+ 4)
785 || !(rx_status
& RxStatesOK
))) {
786 _sc92031_rx_tasklet_error(rx_status
, priv
, rx_size
);
790 if (unlikely(rx_size_align
+ 4 > rx_len
)) {
791 if (printk_ratelimit())
792 printk(KERN_ERR
"%s: rx_len is too small\n", dev
->name
);
796 rx_len
-= rx_size_align
+ 4;
798 skb
= dev_alloc_skb(pkt_size
+ NET_IP_ALIGN
);
799 if (unlikely(!skb
)) {
800 if (printk_ratelimit())
801 printk(KERN_ERR
"%s: Couldn't allocate a skb_buff for a packet of size %u\n",
802 dev
->name
, pkt_size
);
806 skb_reserve(skb
, NET_IP_ALIGN
);
808 if ((rx_ring_offset
+ pkt_size
) > RX_BUF_LEN
) {
809 memcpy(skb_put(skb
, RX_BUF_LEN
- rx_ring_offset
),
810 rx_ring
+ rx_ring_offset
, RX_BUF_LEN
- rx_ring_offset
);
811 memcpy(skb_put(skb
, pkt_size
- (RX_BUF_LEN
- rx_ring_offset
)),
812 rx_ring
, pkt_size
- (RX_BUF_LEN
- rx_ring_offset
));
814 memcpy(skb_put(skb
, pkt_size
), rx_ring
+ rx_ring_offset
, pkt_size
);
817 skb
->protocol
= eth_type_trans(skb
, dev
);
818 dev
->last_rx
= jiffies
;
821 priv
->stats
.rx_bytes
+= pkt_size
;
822 priv
->stats
.rx_packets
++;
824 if (rx_status
& Rx_Multicast
)
825 priv
->stats
.multicast
++;
828 rx_ring_offset
= (rx_ring_offset
+ rx_size_align
) % RX_BUF_LEN
;
832 priv
->rx_ring_tail
= rx_ring_head
;
833 iowrite32(priv
->rx_ring_tail
, port_base
+ RxBufRPtr
);
836 static void _sc92031_link_tasklet(struct net_device
*dev
)
838 struct sc92031_priv
*priv
= netdev_priv(dev
);
840 if (_sc92031_check_media(dev
))
841 netif_wake_queue(dev
);
843 netif_stop_queue(dev
);
844 priv
->stats
.tx_carrier_errors
++;
848 static void sc92031_tasklet(unsigned long data
)
850 struct net_device
*dev
= (struct net_device
*)data
;
851 struct sc92031_priv
*priv
= netdev_priv(dev
);
852 void __iomem
*port_base
= priv
->port_base
;
853 u32 intr_status
, intr_mask
;
855 intr_status
= priv
->intr_status
;
857 spin_lock(&priv
->lock
);
859 if (unlikely(!netif_running(dev
)))
862 if (intr_status
& TxOK
)
863 _sc92031_tx_tasklet(dev
);
865 if (intr_status
& RxOK
)
866 _sc92031_rx_tasklet(dev
);
868 if (intr_status
& RxOverflow
)
869 priv
->stats
.rx_errors
++;
871 if (intr_status
& TimeOut
) {
872 priv
->stats
.rx_errors
++;
873 priv
->stats
.rx_length_errors
++;
876 if (intr_status
& (LinkFail
| LinkOK
))
877 _sc92031_link_tasklet(dev
);
880 intr_mask
= atomic_read(&priv
->intr_mask
);
883 iowrite32(intr_mask
, port_base
+ IntrMask
);
886 spin_unlock(&priv
->lock
);
889 static irqreturn_t
sc92031_interrupt(int irq
, void *dev_id
)
891 struct net_device
*dev
= dev_id
;
892 struct sc92031_priv
*priv
= netdev_priv(dev
);
893 void __iomem
*port_base
= priv
->port_base
;
894 u32 intr_status
, intr_mask
;
896 /* mask interrupts before clearing IntrStatus */
897 iowrite32(0, port_base
+ IntrMask
);
898 _sc92031_dummy_read(port_base
);
900 intr_status
= ioread32(port_base
+ IntrStatus
);
901 if (unlikely(intr_status
== 0xffffffff))
902 return IRQ_NONE
; // hardware has gone missing
904 intr_status
&= IntrBits
;
908 priv
->intr_status
= intr_status
;
909 tasklet_schedule(&priv
->tasklet
);
914 intr_mask
= atomic_read(&priv
->intr_mask
);
917 iowrite32(intr_mask
, port_base
+ IntrMask
);
923 static struct net_device_stats
*sc92031_get_stats(struct net_device
*dev
)
925 struct sc92031_priv
*priv
= netdev_priv(dev
);
926 void __iomem
*port_base
= priv
->port_base
;
928 // FIXME I do not understand what is this trying to do.
929 if (netif_running(dev
)) {
932 spin_lock_bh(&priv
->lock
);
934 /* Update the error count. */
935 temp
= (ioread32(port_base
+ RxStatus0
) >> 16) & 0xffff;
937 if (temp
== 0xffff) {
938 priv
->rx_value
+= temp
;
939 priv
->stats
.rx_fifo_errors
= priv
->rx_value
;
941 priv
->stats
.rx_fifo_errors
= temp
+ priv
->rx_value
;
944 spin_unlock_bh(&priv
->lock
);
950 static int sc92031_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
953 struct sc92031_priv
*priv
= netdev_priv(dev
);
954 void __iomem
*port_base
= priv
->port_base
;
960 if (unlikely(skb
->len
> TX_BUF_SIZE
)) {
962 priv
->stats
.tx_dropped
++;
966 spin_lock(&priv
->lock
);
968 if (unlikely(!netif_carrier_ok(dev
))) {
970 priv
->stats
.tx_dropped
++;
974 BUG_ON(priv
->tx_head
- priv
->tx_tail
>= NUM_TX_DESC
);
976 entry
= priv
->tx_head
++ % NUM_TX_DESC
;
978 skb_copy_and_csum_dev(skb
, priv
->tx_bufs
+ entry
* TX_BUF_SIZE
);
981 if (unlikely(len
< ETH_ZLEN
)) {
982 memset(priv
->tx_bufs
+ entry
* TX_BUF_SIZE
+ len
,
992 tx_status
= 0x30000 | len
;
994 tx_status
= 0x50000 | len
;
996 iowrite32(priv
->tx_bufs_dma_addr
+ entry
* TX_BUF_SIZE
,
997 port_base
+ TxAddr0
+ entry
* 4);
998 iowrite32(tx_status
, port_base
+ TxStatus0
+ entry
* 4);
1001 dev
->trans_start
= jiffies
;
1003 if (priv
->tx_head
- priv
->tx_tail
>= NUM_TX_DESC
)
1004 netif_stop_queue(dev
);
1007 spin_unlock(&priv
->lock
);
1015 static int sc92031_open(struct net_device
*dev
)
1018 struct sc92031_priv
*priv
= netdev_priv(dev
);
1019 struct pci_dev
*pdev
= priv
->pdev
;
1021 priv
->rx_ring
= pci_alloc_consistent(pdev
, RX_BUF_LEN
,
1022 &priv
->rx_ring_dma_addr
);
1023 if (unlikely(!priv
->rx_ring
)) {
1025 goto out_alloc_rx_ring
;
1028 priv
->tx_bufs
= pci_alloc_consistent(pdev
, TX_BUF_TOT_LEN
,
1029 &priv
->tx_bufs_dma_addr
);
1030 if (unlikely(!priv
->tx_bufs
)) {
1032 goto out_alloc_tx_bufs
;
1034 priv
->tx_head
= priv
->tx_tail
= 0;
1036 err
= request_irq(pdev
->irq
, sc92031_interrupt
,
1037 IRQF_SHARED
, dev
->name
, dev
);
1038 if (unlikely(err
< 0))
1039 goto out_request_irq
;
1041 priv
->pm_config
= 0;
1043 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1044 spin_lock_bh(&priv
->lock
);
1046 _sc92031_reset(dev
);
1049 spin_unlock_bh(&priv
->lock
);
1050 sc92031_enable_interrupts(dev
);
1052 if (netif_carrier_ok(dev
))
1053 netif_start_queue(dev
);
1055 netif_tx_disable(dev
);
1060 pci_free_consistent(pdev
, TX_BUF_TOT_LEN
, priv
->tx_bufs
,
1061 priv
->tx_bufs_dma_addr
);
1063 pci_free_consistent(pdev
, RX_BUF_LEN
, priv
->rx_ring
,
1064 priv
->rx_ring_dma_addr
);
1069 static int sc92031_stop(struct net_device
*dev
)
1071 struct sc92031_priv
*priv
= netdev_priv(dev
);
1072 struct pci_dev
*pdev
= priv
->pdev
;
1074 netif_tx_disable(dev
);
1076 /* Disable interrupts, stop Tx and Rx. */
1077 sc92031_disable_interrupts(dev
);
1079 spin_lock_bh(&priv
->lock
);
1081 _sc92031_disable_tx_rx(dev
);
1082 _sc92031_tx_clear(dev
);
1085 spin_unlock_bh(&priv
->lock
);
1087 free_irq(pdev
->irq
, dev
);
1088 pci_free_consistent(pdev
, TX_BUF_TOT_LEN
, priv
->tx_bufs
,
1089 priv
->tx_bufs_dma_addr
);
1090 pci_free_consistent(pdev
, RX_BUF_LEN
, priv
->rx_ring
,
1091 priv
->rx_ring_dma_addr
);
1096 static void sc92031_set_multicast_list(struct net_device
*dev
)
1098 struct sc92031_priv
*priv
= netdev_priv(dev
);
1100 spin_lock_bh(&priv
->lock
);
1102 _sc92031_set_mar(dev
);
1103 _sc92031_set_rx_config(dev
);
1106 spin_unlock_bh(&priv
->lock
);
1109 static void sc92031_tx_timeout(struct net_device
*dev
)
1111 struct sc92031_priv
*priv
= netdev_priv(dev
);
1113 /* Disable interrupts by clearing the interrupt mask.*/
1114 sc92031_disable_interrupts(dev
);
1116 spin_lock(&priv
->lock
);
1118 priv
->tx_timeouts
++;
1120 _sc92031_reset(dev
);
1123 spin_unlock(&priv
->lock
);
1125 /* enable interrupts */
1126 sc92031_enable_interrupts(dev
);
1128 if (netif_carrier_ok(dev
))
1129 netif_wake_queue(dev
);
1132 #ifdef CONFIG_NET_POLL_CONTROLLER
1133 static void sc92031_poll_controller(struct net_device
*dev
)
1135 disable_irq(dev
->irq
);
1136 if (sc92031_interrupt(dev
->irq
, dev
) != IRQ_NONE
)
1137 sc92031_tasklet((unsigned long)dev
);
1138 enable_irq(dev
->irq
);
1142 static int sc92031_ethtool_get_settings(struct net_device
*dev
,
1143 struct ethtool_cmd
*cmd
)
1145 struct sc92031_priv
*priv
= netdev_priv(dev
);
1146 void __iomem
*port_base
= priv
->port_base
;
1151 spin_lock_bh(&priv
->lock
);
1153 phy_address
= ioread32(port_base
+ Miicmd1
) >> 27;
1154 phy_ctrl
= ioread32(port_base
+ PhyCtrl
);
1156 output_status
= _sc92031_mii_read(port_base
, MII_OutputStatus
);
1157 _sc92031_mii_scan(port_base
);
1160 spin_unlock_bh(&priv
->lock
);
1162 cmd
->supported
= SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
1163 | SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
1164 | SUPPORTED_Autoneg
| SUPPORTED_TP
| SUPPORTED_MII
;
1166 cmd
->advertising
= ADVERTISED_TP
| ADVERTISED_MII
;
1168 if ((phy_ctrl
& (PhyCtrlDux
| PhyCtrlSpd100
| PhyCtrlSpd10
))
1169 == (PhyCtrlDux
| PhyCtrlSpd100
| PhyCtrlSpd10
))
1170 cmd
->advertising
|= ADVERTISED_Autoneg
;
1172 if ((phy_ctrl
& PhyCtrlSpd10
) == PhyCtrlSpd10
)
1173 cmd
->advertising
|= ADVERTISED_10baseT_Half
;
1175 if ((phy_ctrl
& (PhyCtrlSpd10
| PhyCtrlDux
))
1176 == (PhyCtrlSpd10
| PhyCtrlDux
))
1177 cmd
->advertising
|= ADVERTISED_10baseT_Full
;
1179 if ((phy_ctrl
& PhyCtrlSpd100
) == PhyCtrlSpd100
)
1180 cmd
->advertising
|= ADVERTISED_100baseT_Half
;
1182 if ((phy_ctrl
& (PhyCtrlSpd100
| PhyCtrlDux
))
1183 == (PhyCtrlSpd100
| PhyCtrlDux
))
1184 cmd
->advertising
|= ADVERTISED_100baseT_Full
;
1186 if (phy_ctrl
& PhyCtrlAne
)
1187 cmd
->advertising
|= ADVERTISED_Autoneg
;
1189 cmd
->speed
= (output_status
& 0x2) ? SPEED_100
: SPEED_10
;
1190 cmd
->duplex
= (output_status
& 0x4) ? DUPLEX_FULL
: DUPLEX_HALF
;
1191 cmd
->port
= PORT_MII
;
1192 cmd
->phy_address
= phy_address
;
1193 cmd
->transceiver
= XCVR_INTERNAL
;
1194 cmd
->autoneg
= (phy_ctrl
& PhyCtrlAne
) ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
1199 static int sc92031_ethtool_set_settings(struct net_device
*dev
,
1200 struct ethtool_cmd
*cmd
)
1202 struct sc92031_priv
*priv
= netdev_priv(dev
);
1203 void __iomem
*port_base
= priv
->port_base
;
1207 if (!(cmd
->speed
== SPEED_10
|| cmd
->speed
== SPEED_100
))
1209 if (!(cmd
->duplex
== DUPLEX_HALF
|| cmd
->duplex
== DUPLEX_FULL
))
1211 if (!(cmd
->port
== PORT_MII
))
1213 if (!(cmd
->phy_address
== 0x1f))
1215 if (!(cmd
->transceiver
== XCVR_INTERNAL
))
1217 if (!(cmd
->autoneg
== AUTONEG_DISABLE
|| cmd
->autoneg
== AUTONEG_ENABLE
))
1220 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1221 if (!(cmd
->advertising
& (ADVERTISED_Autoneg
1222 | ADVERTISED_100baseT_Full
1223 | ADVERTISED_100baseT_Half
1224 | ADVERTISED_10baseT_Full
1225 | ADVERTISED_10baseT_Half
)))
1228 phy_ctrl
= PhyCtrlAne
;
1230 // FIXME: I'm not sure what the original code was trying to do
1231 if (cmd
->advertising
& ADVERTISED_Autoneg
)
1232 phy_ctrl
|= PhyCtrlDux
| PhyCtrlSpd100
| PhyCtrlSpd10
;
1233 if (cmd
->advertising
& ADVERTISED_100baseT_Full
)
1234 phy_ctrl
|= PhyCtrlDux
| PhyCtrlSpd100
;
1235 if (cmd
->advertising
& ADVERTISED_100baseT_Half
)
1236 phy_ctrl
|= PhyCtrlSpd100
;
1237 if (cmd
->advertising
& ADVERTISED_10baseT_Full
)
1238 phy_ctrl
|= PhyCtrlSpd10
| PhyCtrlDux
;
1239 if (cmd
->advertising
& ADVERTISED_10baseT_Half
)
1240 phy_ctrl
|= PhyCtrlSpd10
;
1242 // FIXME: Whole branch guessed
1245 if (cmd
->speed
== SPEED_10
)
1246 phy_ctrl
|= PhyCtrlSpd10
;
1247 else /* cmd->speed == SPEED_100 */
1248 phy_ctrl
|= PhyCtrlSpd100
;
1250 if (cmd
->duplex
== DUPLEX_FULL
)
1251 phy_ctrl
|= PhyCtrlDux
;
1254 spin_lock_bh(&priv
->lock
);
1256 old_phy_ctrl
= ioread32(port_base
+ PhyCtrl
);
1257 phy_ctrl
|= old_phy_ctrl
& ~(PhyCtrlAne
| PhyCtrlDux
1258 | PhyCtrlSpd100
| PhyCtrlSpd10
);
1259 if (phy_ctrl
!= old_phy_ctrl
)
1260 iowrite32(phy_ctrl
, port_base
+ PhyCtrl
);
1262 spin_unlock_bh(&priv
->lock
);
1267 static void sc92031_ethtool_get_drvinfo(struct net_device
*dev
,
1268 struct ethtool_drvinfo
*drvinfo
)
1270 struct sc92031_priv
*priv
= netdev_priv(dev
);
1271 struct pci_dev
*pdev
= priv
->pdev
;
1273 strcpy(drvinfo
->driver
, SC92031_NAME
);
1274 strcpy(drvinfo
->version
, SC92031_VERSION
);
1275 strcpy(drvinfo
->bus_info
, pci_name(pdev
));
1278 static void sc92031_ethtool_get_wol(struct net_device
*dev
,
1279 struct ethtool_wolinfo
*wolinfo
)
1281 struct sc92031_priv
*priv
= netdev_priv(dev
);
1282 void __iomem
*port_base
= priv
->port_base
;
1285 spin_lock_bh(&priv
->lock
);
1286 pm_config
= ioread32(port_base
+ PMConfig
);
1287 spin_unlock_bh(&priv
->lock
);
1290 wolinfo
->supported
= WAKE_PHY
| WAKE_MAGIC
1291 | WAKE_UCAST
| WAKE_MCAST
| WAKE_BCAST
;
1292 wolinfo
->wolopts
= 0;
1294 if (pm_config
& PM_LinkUp
)
1295 wolinfo
->wolopts
|= WAKE_PHY
;
1297 if (pm_config
& PM_Magic
)
1298 wolinfo
->wolopts
|= WAKE_MAGIC
;
1300 if (pm_config
& PM_WakeUp
)
1302 wolinfo
->wolopts
|= WAKE_UCAST
| WAKE_MCAST
| WAKE_BCAST
;
1305 static int sc92031_ethtool_set_wol(struct net_device
*dev
,
1306 struct ethtool_wolinfo
*wolinfo
)
1308 struct sc92031_priv
*priv
= netdev_priv(dev
);
1309 void __iomem
*port_base
= priv
->port_base
;
1312 spin_lock_bh(&priv
->lock
);
1314 pm_config
= ioread32(port_base
+ PMConfig
)
1315 & ~(PM_LinkUp
| PM_Magic
| PM_WakeUp
);
1317 if (wolinfo
->wolopts
& WAKE_PHY
)
1318 pm_config
|= PM_LinkUp
;
1320 if (wolinfo
->wolopts
& WAKE_MAGIC
)
1321 pm_config
|= PM_Magic
;
1324 if (wolinfo
->wolopts
& (WAKE_UCAST
| WAKE_MCAST
| WAKE_BCAST
))
1325 pm_config
|= PM_WakeUp
;
1327 priv
->pm_config
= pm_config
;
1328 iowrite32(pm_config
, port_base
+ PMConfig
);
1331 spin_unlock_bh(&priv
->lock
);
1336 static int sc92031_ethtool_nway_reset(struct net_device
*dev
)
1339 struct sc92031_priv
*priv
= netdev_priv(dev
);
1340 void __iomem
*port_base
= priv
->port_base
;
1343 spin_lock_bh(&priv
->lock
);
1345 bmcr
= _sc92031_mii_read(port_base
, MII_BMCR
);
1346 if (!(bmcr
& BMCR_ANENABLE
)) {
1351 _sc92031_mii_write(port_base
, MII_BMCR
, bmcr
| BMCR_ANRESTART
);
1354 _sc92031_mii_scan(port_base
);
1357 spin_unlock_bh(&priv
->lock
);
1362 static const char sc92031_ethtool_stats_strings
[SILAN_STATS_NUM
][ETH_GSTRING_LEN
] = {
1367 static void sc92031_ethtool_get_strings(struct net_device
*dev
,
1368 u32 stringset
, u8
*data
)
1370 if (stringset
== ETH_SS_STATS
)
1371 memcpy(data
, sc92031_ethtool_stats_strings
,
1372 SILAN_STATS_NUM
* ETH_GSTRING_LEN
);
1375 static int sc92031_ethtool_get_sset_count(struct net_device
*dev
, int sset
)
1379 return SILAN_STATS_NUM
;
1385 static void sc92031_ethtool_get_ethtool_stats(struct net_device
*dev
,
1386 struct ethtool_stats
*stats
, u64
*data
)
1388 struct sc92031_priv
*priv
= netdev_priv(dev
);
1390 spin_lock_bh(&priv
->lock
);
1391 data
[0] = priv
->tx_timeouts
;
1392 data
[1] = priv
->rx_loss
;
1393 spin_unlock_bh(&priv
->lock
);
1396 static struct ethtool_ops sc92031_ethtool_ops
= {
1397 .get_settings
= sc92031_ethtool_get_settings
,
1398 .set_settings
= sc92031_ethtool_set_settings
,
1399 .get_drvinfo
= sc92031_ethtool_get_drvinfo
,
1400 .get_wol
= sc92031_ethtool_get_wol
,
1401 .set_wol
= sc92031_ethtool_set_wol
,
1402 .nway_reset
= sc92031_ethtool_nway_reset
,
1403 .get_link
= ethtool_op_get_link
,
1404 .get_strings
= sc92031_ethtool_get_strings
,
1405 .get_sset_count
= sc92031_ethtool_get_sset_count
,
1406 .get_ethtool_stats
= sc92031_ethtool_get_ethtool_stats
,
1409 static int __devinit
sc92031_probe(struct pci_dev
*pdev
,
1410 const struct pci_device_id
*id
)
1413 void __iomem
* port_base
;
1414 struct net_device
*dev
;
1415 struct sc92031_priv
*priv
;
1418 err
= pci_enable_device(pdev
);
1419 if (unlikely(err
< 0))
1420 goto out_enable_device
;
1422 pci_set_master(pdev
);
1424 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1425 if (unlikely(err
< 0))
1426 goto out_set_dma_mask
;
1428 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1429 if (unlikely(err
< 0))
1430 goto out_set_dma_mask
;
1432 err
= pci_request_regions(pdev
, SC92031_NAME
);
1433 if (unlikely(err
< 0))
1434 goto out_request_regions
;
1436 port_base
= pci_iomap(pdev
, SC92031_USE_BAR
, 0);
1437 if (unlikely(!port_base
)) {
1442 dev
= alloc_etherdev(sizeof(struct sc92031_priv
));
1443 if (unlikely(!dev
)) {
1445 goto out_alloc_etherdev
;
1448 pci_set_drvdata(pdev
, dev
);
1450 #if SC92031_USE_BAR == 0
1451 dev
->mem_start
= pci_resource_start(pdev
, SC92031_USE_BAR
);
1452 dev
->mem_end
= pci_resource_end(pdev
, SC92031_USE_BAR
);
1453 #elif SC92031_USE_BAR == 1
1454 dev
->base_addr
= pci_resource_start(pdev
, SC92031_USE_BAR
);
1456 dev
->irq
= pdev
->irq
;
1458 /* faked with skb_copy_and_csum_dev */
1459 dev
->features
= NETIF_F_SG
| NETIF_F_HW_CSUM
| NETIF_F_HIGHDMA
;
1461 dev
->get_stats
= sc92031_get_stats
;
1462 dev
->ethtool_ops
= &sc92031_ethtool_ops
;
1463 dev
->hard_start_xmit
= sc92031_start_xmit
;
1464 dev
->watchdog_timeo
= TX_TIMEOUT
;
1465 dev
->open
= sc92031_open
;
1466 dev
->stop
= sc92031_stop
;
1467 dev
->set_multicast_list
= sc92031_set_multicast_list
;
1468 dev
->tx_timeout
= sc92031_tx_timeout
;
1469 #ifdef CONFIG_NET_POLL_CONTROLLER
1470 dev
->poll_controller
= sc92031_poll_controller
;
1473 priv
= netdev_priv(dev
);
1474 spin_lock_init(&priv
->lock
);
1475 priv
->port_base
= port_base
;
1477 tasklet_init(&priv
->tasklet
, sc92031_tasklet
, (unsigned long)dev
);
1478 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1479 * sc92031_open will work correctly */
1480 tasklet_disable_nosync(&priv
->tasklet
);
1483 iowrite32((~PM_LongWF
& ~PM_LWPTN
) | PM_Enable
, port_base
+ PMConfig
);
1485 mac0
= ioread32(port_base
+ MAC0
);
1486 mac1
= ioread32(port_base
+ MAC0
+ 4);
1487 dev
->dev_addr
[0] = dev
->perm_addr
[0] = mac0
>> 24;
1488 dev
->dev_addr
[1] = dev
->perm_addr
[1] = mac0
>> 16;
1489 dev
->dev_addr
[2] = dev
->perm_addr
[2] = mac0
>> 8;
1490 dev
->dev_addr
[3] = dev
->perm_addr
[3] = mac0
;
1491 dev
->dev_addr
[4] = dev
->perm_addr
[4] = mac1
>> 8;
1492 dev
->dev_addr
[5] = dev
->perm_addr
[5] = mac1
;
1494 err
= register_netdev(dev
);
1496 goto out_register_netdev
;
1500 out_register_netdev
:
1503 pci_iounmap(pdev
, port_base
);
1505 pci_release_regions(pdev
);
1506 out_request_regions
:
1508 pci_disable_device(pdev
);
1513 static void __devexit
sc92031_remove(struct pci_dev
*pdev
)
1515 struct net_device
*dev
= pci_get_drvdata(pdev
);
1516 struct sc92031_priv
*priv
= netdev_priv(dev
);
1517 void __iomem
* port_base
= priv
->port_base
;
1519 unregister_netdev(dev
);
1521 pci_iounmap(pdev
, port_base
);
1522 pci_release_regions(pdev
);
1523 pci_disable_device(pdev
);
1526 static int sc92031_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1528 struct net_device
*dev
= pci_get_drvdata(pdev
);
1529 struct sc92031_priv
*priv
= netdev_priv(dev
);
1531 pci_save_state(pdev
);
1533 if (!netif_running(dev
))
1536 netif_device_detach(dev
);
1538 /* Disable interrupts, stop Tx and Rx. */
1539 sc92031_disable_interrupts(dev
);
1541 spin_lock_bh(&priv
->lock
);
1543 _sc92031_disable_tx_rx(dev
);
1544 _sc92031_tx_clear(dev
);
1547 spin_unlock_bh(&priv
->lock
);
1550 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1555 static int sc92031_resume(struct pci_dev
*pdev
)
1557 struct net_device
*dev
= pci_get_drvdata(pdev
);
1558 struct sc92031_priv
*priv
= netdev_priv(dev
);
1560 pci_restore_state(pdev
);
1561 pci_set_power_state(pdev
, PCI_D0
);
1563 if (!netif_running(dev
))
1566 /* Interrupts already disabled by sc92031_suspend */
1567 spin_lock_bh(&priv
->lock
);
1569 _sc92031_reset(dev
);
1572 spin_unlock_bh(&priv
->lock
);
1573 sc92031_enable_interrupts(dev
);
1575 netif_device_attach(dev
);
1577 if (netif_carrier_ok(dev
))
1578 netif_wake_queue(dev
);
1580 netif_tx_disable(dev
);
1586 static struct pci_device_id sc92031_pci_device_id_table
[] __devinitdata
= {
1587 { PCI_DEVICE(PCI_VENDOR_ID_SILAN
, PCI_DEVICE_ID_SILAN_SC92031
) },
1588 { PCI_DEVICE(PCI_VENDOR_ID_SILAN
, PCI_DEVICE_ID_SILAN_8139D
) },
1591 MODULE_DEVICE_TABLE(pci
, sc92031_pci_device_id_table
);
1593 static struct pci_driver sc92031_pci_driver
= {
1594 .name
= SC92031_NAME
,
1595 .id_table
= sc92031_pci_device_id_table
,
1596 .probe
= sc92031_probe
,
1597 .remove
= __devexit_p(sc92031_remove
),
1598 .suspend
= sc92031_suspend
,
1599 .resume
= sc92031_resume
,
1602 static int __init
sc92031_init(void)
1604 printk(KERN_INFO SC92031_DESCRIPTION
" " SC92031_VERSION
"\n");
1605 return pci_register_driver(&sc92031_pci_driver
);
1608 static void __exit
sc92031_exit(void)
1610 pci_unregister_driver(&sc92031_pci_driver
);
1613 module_init(sc92031_init
);
1614 module_exit(sc92031_exit
);
1616 MODULE_LICENSE("GPL");
1617 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1618 MODULE_DESCRIPTION(SC92031_DESCRIPTION
);
1619 MODULE_VERSION(SC92031_VERSION
);