?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ARM] 4754/1: [AT91] SSC library support
[linux-2.6/sactl.git] / arch / arm / mach-at91 / at91sam9260_devices.c
blob2e3db137bc490e2f30073376309961b0f91c672c
1 /*
2 * arch/arm/mach-at91/at91sam9260_devices.c
3 *
4 * Copyright (C) 2006 Atmel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18
19 #include <asm/arch/board.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/at91sam9260.h>
22 #include <asm/arch/at91sam926x_mc.h>
23 #include <asm/arch/at91sam9260_matrix.h>
24
25 #include "generic.h"
26
27
28 /* --------------------------------------------------------------------
29 * USB Host
30 * -------------------------------------------------------------------- */
31
32 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
33 static u64 ohci_dmamask = DMA_BIT_MASK(32);
34 static struct at91_usbh_data usbh_data;
35
36 static struct resource usbh_resources[] = {
37 [0] = {
38 .start = AT91SAM9260_UHP_BASE,
39 .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
40 .flags = IORESOURCE_MEM,
41 },
42 [1] = {
43 .start = AT91SAM9260_ID_UHP,
44 .end = AT91SAM9260_ID_UHP,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 static struct platform_device at91_usbh_device = {
50 .name = "at91_ohci",
51 .id = -1,
52 .dev = {
53 .dma_mask = &ohci_dmamask,
54 .coherent_dma_mask = DMA_BIT_MASK(32),
55 .platform_data = &usbh_data,
56 },
57 .resource = usbh_resources,
58 .num_resources = ARRAY_SIZE(usbh_resources),
59 };
60
61 void __init at91_add_device_usbh(struct at91_usbh_data *data)
62 {
63 if (!data)
64 return;
65
66 usbh_data = *data;
67 platform_device_register(&at91_usbh_device);
68 }
69 #else
70 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
71 #endif
72
73
74 /* --------------------------------------------------------------------
75 * USB Device (Gadget)
76 * -------------------------------------------------------------------- */
77
78 #ifdef CONFIG_USB_GADGET_AT91
79 static struct at91_udc_data udc_data;
80
81 static struct resource udc_resources[] = {
82 [0] = {
83 .start = AT91SAM9260_BASE_UDP,
84 .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 [1] = {
88 .start = AT91SAM9260_ID_UDP,
89 .end = AT91SAM9260_ID_UDP,
90 .flags = IORESOURCE_IRQ,
91 },
92 };
93
94 static struct platform_device at91_udc_device = {
95 .name = "at91_udc",
96 .id = -1,
97 .dev = {
98 .platform_data = &udc_data,
99 },
100 .resource = udc_resources,
101 .num_resources = ARRAY_SIZE(udc_resources),
102 };
103
104 void __init at91_add_device_udc(struct at91_udc_data *data)
105 {
106 if (!data)
107 return;
108
109 if (data->vbus_pin) {
110 at91_set_gpio_input(data->vbus_pin, 0);
111 at91_set_deglitch(data->vbus_pin, 1);
112 }
113
114 /* Pullup pin is handled internally by USB device peripheral */
115
116 udc_data = *data;
117 platform_device_register(&at91_udc_device);
118 }
119 #else
120 void __init at91_add_device_udc(struct at91_udc_data *data) {}
121 #endif
122
123
124 /* --------------------------------------------------------------------
125 * Ethernet
126 * -------------------------------------------------------------------- */
127
128 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
129 static u64 eth_dmamask = DMA_BIT_MASK(32);
130 static struct at91_eth_data eth_data;
131
132 static struct resource eth_resources[] = {
133 [0] = {
134 .start = AT91SAM9260_BASE_EMAC,
135 .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 [1] = {
139 .start = AT91SAM9260_ID_EMAC,
140 .end = AT91SAM9260_ID_EMAC,
141 .flags = IORESOURCE_IRQ,
142 },
143 };
144
145 static struct platform_device at91sam9260_eth_device = {
146 .name = "macb",
147 .id = -1,
148 .dev = {
149 .dma_mask = &eth_dmamask,
150 .coherent_dma_mask = DMA_BIT_MASK(32),
151 .platform_data = &eth_data,
152 },
153 .resource = eth_resources,
154 .num_resources = ARRAY_SIZE(eth_resources),
155 };
156
157 void __init at91_add_device_eth(struct at91_eth_data *data)
158 {
159 if (!data)
160 return;
161
162 if (data->phy_irq_pin) {
163 at91_set_gpio_input(data->phy_irq_pin, 0);
164 at91_set_deglitch(data->phy_irq_pin, 1);
165 }
166
167 /* Pins used for MII and RMII */
168 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
169 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
170 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
171 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
172 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
173 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
174 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
175 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
176 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
177 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
178
179 if (!data->is_rmii) {
180 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
181 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
182 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
183 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
184 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
185 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
186 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
187 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
188 }
189
190 eth_data = *data;
191 platform_device_register(&at91sam9260_eth_device);
192 }
193 #else
194 void __init at91_add_device_eth(struct at91_eth_data *data) {}
195 #endif
196
197
198 /* --------------------------------------------------------------------
199 * MMC / SD
200 * -------------------------------------------------------------------- */
201
202 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
203 static u64 mmc_dmamask = DMA_BIT_MASK(32);
204 static struct at91_mmc_data mmc_data;
205
206 static struct resource mmc_resources[] = {
207 [0] = {
208 .start = AT91SAM9260_BASE_MCI,
209 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = AT91SAM9260_ID_MCI,
214 .end = AT91SAM9260_ID_MCI,
215 .flags = IORESOURCE_IRQ,
216 },
217 };
218
219 static struct platform_device at91sam9260_mmc_device = {
220 .name = "at91_mci",
221 .id = -1,
222 .dev = {
223 .dma_mask = &mmc_dmamask,
224 .coherent_dma_mask = DMA_BIT_MASK(32),
225 .platform_data = &mmc_data,
226 },
227 .resource = mmc_resources,
228 .num_resources = ARRAY_SIZE(mmc_resources),
229 };
230
231 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
232 {
233 if (!data)
234 return;
235
236 /* input/irq */
237 if (data->det_pin) {
238 at91_set_gpio_input(data->det_pin, 1);
239 at91_set_deglitch(data->det_pin, 1);
240 }
241 if (data->wp_pin)
242 at91_set_gpio_input(data->wp_pin, 1);
243 if (data->vcc_pin)
244 at91_set_gpio_output(data->vcc_pin, 0);
245
246 /* CLK */
247 at91_set_A_periph(AT91_PIN_PA8, 0);
248
249 if (data->slot_b) {
250 /* CMD */
251 at91_set_B_periph(AT91_PIN_PA1, 1);
252
253 /* DAT0, maybe DAT1..DAT3 */
254 at91_set_B_periph(AT91_PIN_PA0, 1);
255 if (data->wire4) {
256 at91_set_B_periph(AT91_PIN_PA5, 1);
257 at91_set_B_periph(AT91_PIN_PA4, 1);
258 at91_set_B_periph(AT91_PIN_PA3, 1);
259 }
260 } else {
261 /* CMD */
262 at91_set_A_periph(AT91_PIN_PA7, 1);
263
264 /* DAT0, maybe DAT1..DAT3 */
265 at91_set_A_periph(AT91_PIN_PA6, 1);
266 if (data->wire4) {
267 at91_set_A_periph(AT91_PIN_PA9, 1);
268 at91_set_A_periph(AT91_PIN_PA10, 1);
269 at91_set_A_periph(AT91_PIN_PA11, 1);
270 }
271 }
272
273 mmc_data = *data;
274 platform_device_register(&at91sam9260_mmc_device);
275 }
276 #else
277 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
278 #endif
279
280
281 /* --------------------------------------------------------------------
282 * NAND / SmartMedia
283 * -------------------------------------------------------------------- */
284
285 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
286 static struct at91_nand_data nand_data;
287
288 #define NAND_BASE AT91_CHIPSELECT_3
289
290 static struct resource nand_resources[] = {
291 {
292 .start = NAND_BASE,
293 .end = NAND_BASE + SZ_8M - 1,
294 .flags = IORESOURCE_MEM,
295 }
296 };
297
298 static struct platform_device at91sam9260_nand_device = {
299 .name = "at91_nand",
300 .id = -1,
301 .dev = {
302 .platform_data = &nand_data,
303 },
304 .resource = nand_resources,
305 .num_resources = ARRAY_SIZE(nand_resources),
306 };
307
308 void __init at91_add_device_nand(struct at91_nand_data *data)
309 {
310 unsigned long csa, mode;
311
312 if (!data)
313 return;
314
315 csa = at91_sys_read(AT91_MATRIX_EBICSA);
316 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
317
318 /* set the bus interface characteristics */
319 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
320 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
321
322 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
323 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
324
325 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
326
327 if (data->bus_width_16)
328 mode = AT91_SMC_DBW_16;
329 else
330 mode = AT91_SMC_DBW_8;
331 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
332
333 /* enable pin */
334 if (data->enable_pin)
335 at91_set_gpio_output(data->enable_pin, 1);
336
337 /* ready/busy pin */
338 if (data->rdy_pin)
339 at91_set_gpio_input(data->rdy_pin, 1);
340
341 /* card detect pin */
342 if (data->det_pin)
343 at91_set_gpio_input(data->det_pin, 1);
344
345 nand_data = *data;
346 platform_device_register(&at91sam9260_nand_device);
347 }
348 #else
349 void __init at91_add_device_nand(struct at91_nand_data *data) {}
350 #endif
351
352
353 /* --------------------------------------------------------------------
354 * TWI (i2c)
355 * -------------------------------------------------------------------- */
356
357 /*
358 * Prefer the GPIO code since the TWI controller isn't robust
359 * (gets overruns and underruns under load) and can only issue
360 * repeated STARTs in one scenario (the driver doesn't yet handle them).
361 */
362
363 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
364
365 static struct i2c_gpio_platform_data pdata = {
366 .sda_pin = AT91_PIN_PA23,
367 .sda_is_open_drain = 1,
368 .scl_pin = AT91_PIN_PA24,
369 .scl_is_open_drain = 1,
370 .udelay = 2, /* ~100 kHz */
371 };
372
373 static struct platform_device at91sam9260_twi_device = {
374 .name = "i2c-gpio",
375 .id = -1,
376 .dev.platform_data = &pdata,
377 };
378
379 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
380 {
381 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
382 at91_set_multi_drive(AT91_PIN_PA23, 1);
383
384 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
385 at91_set_multi_drive(AT91_PIN_PA24, 1);
386
387 i2c_register_board_info(0, devices, nr_devices);
388 platform_device_register(&at91sam9260_twi_device);
389 }
390
391 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
392
393 static struct resource twi_resources[] = {
394 [0] = {
395 .start = AT91SAM9260_BASE_TWI,
396 .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
397 .flags = IORESOURCE_MEM,
398 },
399 [1] = {
400 .start = AT91SAM9260_ID_TWI,
401 .end = AT91SAM9260_ID_TWI,
402 .flags = IORESOURCE_IRQ,
403 },
404 };
405
406 static struct platform_device at91sam9260_twi_device = {
407 .name = "at91_i2c",
408 .id = -1,
409 .resource = twi_resources,
410 .num_resources = ARRAY_SIZE(twi_resources),
411 };
412
413 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
414 {
415 /* pins used for TWI interface */
416 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
417 at91_set_multi_drive(AT91_PIN_PA23, 1);
418
419 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
420 at91_set_multi_drive(AT91_PIN_PA24, 1);
421
422 i2c_register_board_info(0, devices, nr_devices);
423 platform_device_register(&at91sam9260_twi_device);
424 }
425 #else
426 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
427 #endif
428
429
430 /* --------------------------------------------------------------------
431 * SPI
432 * -------------------------------------------------------------------- */
433
434 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
435 static u64 spi_dmamask = DMA_BIT_MASK(32);
436
437 static struct resource spi0_resources[] = {
438 [0] = {
439 .start = AT91SAM9260_BASE_SPI0,
440 .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
441 .flags = IORESOURCE_MEM,
442 },
443 [1] = {
444 .start = AT91SAM9260_ID_SPI0,
445 .end = AT91SAM9260_ID_SPI0,
446 .flags = IORESOURCE_IRQ,
447 },
448 };
449
450 static struct platform_device at91sam9260_spi0_device = {
451 .name = "atmel_spi",
452 .id = 0,
453 .dev = {
454 .dma_mask = &spi_dmamask,
455 .coherent_dma_mask = DMA_BIT_MASK(32),
456 },
457 .resource = spi0_resources,
458 .num_resources = ARRAY_SIZE(spi0_resources),
459 };
460
461 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
462
463 static struct resource spi1_resources[] = {
464 [0] = {
465 .start = AT91SAM9260_BASE_SPI1,
466 .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
467 .flags = IORESOURCE_MEM,
468 },
469 [1] = {
470 .start = AT91SAM9260_ID_SPI1,
471 .end = AT91SAM9260_ID_SPI1,
472 .flags = IORESOURCE_IRQ,
473 },
474 };
475
476 static struct platform_device at91sam9260_spi1_device = {
477 .name = "atmel_spi",
478 .id = 1,
479 .dev = {
480 .dma_mask = &spi_dmamask,
481 .coherent_dma_mask = DMA_BIT_MASK(32),
482 },
483 .resource = spi1_resources,
484 .num_resources = ARRAY_SIZE(spi1_resources),
485 };
486
487 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
488
489 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
490 {
491 int i;
492 unsigned long cs_pin;
493 short enable_spi0 = 0;
494 short enable_spi1 = 0;
495
496 /* Choose SPI chip-selects */
497 for (i = 0; i < nr_devices; i++) {
498 if (devices[i].controller_data)
499 cs_pin = (unsigned long) devices[i].controller_data;
500 else if (devices[i].bus_num == 0)
501 cs_pin = spi0_standard_cs[devices[i].chip_select];
502 else
503 cs_pin = spi1_standard_cs[devices[i].chip_select];
504
505 if (devices[i].bus_num == 0)
506 enable_spi0 = 1;
507 else
508 enable_spi1 = 1;
509
510 /* enable chip-select pin */
511 at91_set_gpio_output(cs_pin, 1);
512
513 /* pass chip-select pin to driver */
514 devices[i].controller_data = (void *) cs_pin;
515 }
516
517 spi_register_board_info(devices, nr_devices);
518
519 /* Configure SPI bus(es) */
520 if (enable_spi0) {
521 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
522 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
523 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
524
525 at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
526 platform_device_register(&at91sam9260_spi0_device);
527 }
528 if (enable_spi1) {
529 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
530 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
531 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
532
533 at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
534 platform_device_register(&at91sam9260_spi1_device);
535 }
536 }
537 #else
538 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
539 #endif
540
541
542 /* --------------------------------------------------------------------
543 * RTT
544 * -------------------------------------------------------------------- */
545
546 static struct resource rtt_resources[] = {
547 {
548 .start = AT91_BASE_SYS + AT91_RTT,
549 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
550 .flags = IORESOURCE_MEM,
551 }
552 };
553
554 static struct platform_device at91sam9260_rtt_device = {
555 .name = "at91_rtt",
556 .id = -1,
557 .resource = rtt_resources,
558 .num_resources = ARRAY_SIZE(rtt_resources),
559 };
560
561 static void __init at91_add_device_rtt(void)
562 {
563 platform_device_register(&at91sam9260_rtt_device);
564 }
565
566
567 /* --------------------------------------------------------------------
568 * Watchdog
569 * -------------------------------------------------------------------- */
570
571 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
572 static struct platform_device at91sam9260_wdt_device = {
573 .name = "at91_wdt",
574 .id = -1,
575 .num_resources = 0,
576 };
577
578 static void __init at91_add_device_watchdog(void)
579 {
580 platform_device_register(&at91sam9260_wdt_device);
581 }
582 #else
583 static void __init at91_add_device_watchdog(void) {}
584 #endif
585
586
587 /* --------------------------------------------------------------------
588 * LEDs
589 * -------------------------------------------------------------------- */
590
591 #if defined(CONFIG_LEDS)
592 u8 at91_leds_cpu;
593 u8 at91_leds_timer;
594
595 void __init at91_init_leds(u8 cpu_led, u8 timer_led)
596 {
597 /* Enable GPIO to access the LEDs */
598 at91_set_gpio_output(cpu_led, 1);
599 at91_set_gpio_output(timer_led, 1);
600
601 at91_leds_cpu = cpu_led;
602 at91_leds_timer = timer_led;
603 }
604 #else
605 void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
606 #endif
607
608
609 /* --------------------------------------------------------------------
610 * SSC -- Synchronous Serial Controller
611 * -------------------------------------------------------------------- */
612
613 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
614 static u64 ssc_dmamask = DMA_BIT_MASK(32);
615
616 static struct resource ssc_resources[] = {
617 [0] = {
618 .start = AT91SAM9260_BASE_SSC,
619 .end = AT91SAM9260_BASE_SSC + SZ_16K - 1,
620 .flags = IORESOURCE_MEM,
621 },
622 [1] = {
623 .start = AT91SAM9260_ID_SSC,
624 .end = AT91SAM9260_ID_SSC,
625 .flags = IORESOURCE_IRQ,
626 },
627 };
628
629 static struct platform_device at91sam9260_ssc_device = {
630 .name = "ssc",
631 .id = 0,
632 .dev = {
633 .dma_mask = &ssc_dmamask,
634 .coherent_dma_mask = DMA_BIT_MASK(32),
635 },
636 .resource = ssc_resources,
637 .num_resources = ARRAY_SIZE(ssc_resources),
638 };
639
640 static inline void configure_ssc_pins(unsigned pins)
641 {
642 if (pins & ATMEL_SSC_TF)
643 at91_set_A_periph(AT91_PIN_PB17, 1);
644 if (pins & ATMEL_SSC_TK)
645 at91_set_A_periph(AT91_PIN_PB16, 1);
646 if (pins & ATMEL_SSC_TD)
647 at91_set_A_periph(AT91_PIN_PB18, 1);
648 if (pins & ATMEL_SSC_RD)
649 at91_set_A_periph(AT91_PIN_PB19, 1);
650 if (pins & ATMEL_SSC_RK)
651 at91_set_A_periph(AT91_PIN_PB20, 1);
652 if (pins & ATMEL_SSC_RF)
653 at91_set_A_periph(AT91_PIN_PB21, 1);
654 }
655
656 /*
657 * SSC controllers are accessed through library code, instead of any
658 * kind of all-singing/all-dancing driver. For example one could be
659 * used by a particular I2S audio codec's driver, while another one
660 * on the same system might be used by a custom data capture driver.
661 */
662 void __init at91_add_device_ssc(unsigned id, unsigned pins)
663 {
664 struct platform_device *pdev;
665
666 /*
667 * NOTE: caller is responsible for passing information matching
668 * "pins" to whatever will be using each particular controller.
669 */
670 switch (id) {
671 case AT91SAM9260_ID_SSC:
672 pdev = &at91sam9260_ssc_device;
673 configure_ssc_pins(pins);
674 at91_clock_associate("ssc_clk", &pdev->dev, "pclk");
675 break;
676 default:
677 return;
678 }
679
680 platform_device_register(pdev);
681 }
682
683 #else
684 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
685 #endif
686
687
688 /* --------------------------------------------------------------------
689 * UART
690 * -------------------------------------------------------------------- */
691 #if defined(CONFIG_SERIAL_ATMEL)
692 static struct resource dbgu_resources[] = {
693 [0] = {
694 .start = AT91_VA_BASE_SYS + AT91_DBGU,
695 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
696 .flags = IORESOURCE_MEM,
697 },
698 [1] = {
699 .start = AT91_ID_SYS,
700 .end = AT91_ID_SYS,
701 .flags = IORESOURCE_IRQ,
702 },
703 };
704
705 static struct atmel_uart_data dbgu_data = {
706 .use_dma_tx = 0,
707 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
708 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
709 };
710
711 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
712
713 static struct platform_device at91sam9260_dbgu_device = {
714 .name = "atmel_usart",
715 .id = 0,
716 .dev = {
717 .dma_mask = &dbgu_dmamask,
718 .coherent_dma_mask = DMA_BIT_MASK(32),
719 .platform_data = &dbgu_data,
720 },
721 .resource = dbgu_resources,
722 .num_resources = ARRAY_SIZE(dbgu_resources),
723 };
724
725 static inline void configure_dbgu_pins(void)
726 {
727 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
728 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
729 }
730
731 static struct resource uart0_resources[] = {
732 [0] = {
733 .start = AT91SAM9260_BASE_US0,
734 .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
735 .flags = IORESOURCE_MEM,
736 },
737 [1] = {
738 .start = AT91SAM9260_ID_US0,
739 .end = AT91SAM9260_ID_US0,
740 .flags = IORESOURCE_IRQ,
741 },
742 };
743
744 static struct atmel_uart_data uart0_data = {
745 .use_dma_tx = 1,
746 .use_dma_rx = 1,
747 };
748
749 static u64 uart0_dmamask = DMA_BIT_MASK(32);
750
751 static struct platform_device at91sam9260_uart0_device = {
752 .name = "atmel_usart",
753 .id = 1,
754 .dev = {
755 .dma_mask = &uart0_dmamask,
756 .coherent_dma_mask = DMA_BIT_MASK(32),
757 .platform_data = &uart0_data,
758 },
759 .resource = uart0_resources,
760 .num_resources = ARRAY_SIZE(uart0_resources),
761 };
762
763 static inline void configure_usart0_pins(void)
764 {
765 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
766 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
767 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
768 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
769 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
770 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
771 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
772 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
773 }
774
775 static struct resource uart1_resources[] = {
776 [0] = {
777 .start = AT91SAM9260_BASE_US1,
778 .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
779 .flags = IORESOURCE_MEM,
780 },
781 [1] = {
782 .start = AT91SAM9260_ID_US1,
783 .end = AT91SAM9260_ID_US1,
784 .flags = IORESOURCE_IRQ,
785 },
786 };
787
788 static struct atmel_uart_data uart1_data = {
789 .use_dma_tx = 1,
790 .use_dma_rx = 1,
791 };
792
793 static u64 uart1_dmamask = DMA_BIT_MASK(32);
794
795 static struct platform_device at91sam9260_uart1_device = {
796 .name = "atmel_usart",
797 .id = 2,
798 .dev = {
799 .dma_mask = &uart1_dmamask,
800 .coherent_dma_mask = DMA_BIT_MASK(32),
801 .platform_data = &uart1_data,
802 },
803 .resource = uart1_resources,
804 .num_resources = ARRAY_SIZE(uart1_resources),
805 };
806
807 static inline void configure_usart1_pins(void)
808 {
809 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
810 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
811 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
812 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
813 }
814
815 static struct resource uart2_resources[] = {
816 [0] = {
817 .start = AT91SAM9260_BASE_US2,
818 .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
819 .flags = IORESOURCE_MEM,
820 },
821 [1] = {
822 .start = AT91SAM9260_ID_US2,
823 .end = AT91SAM9260_ID_US2,
824 .flags = IORESOURCE_IRQ,
825 },
826 };
827
828 static struct atmel_uart_data uart2_data = {
829 .use_dma_tx = 1,
830 .use_dma_rx = 1,
831 };
832
833 static u64 uart2_dmamask = DMA_BIT_MASK(32);
834
835 static struct platform_device at91sam9260_uart2_device = {
836 .name = "atmel_usart",
837 .id = 3,
838 .dev = {
839 .dma_mask = &uart2_dmamask,
840 .coherent_dma_mask = DMA_BIT_MASK(32),
841 .platform_data = &uart2_data,
842 },
843 .resource = uart2_resources,
844 .num_resources = ARRAY_SIZE(uart2_resources),
845 };
846
847 static inline void configure_usart2_pins(void)
848 {
849 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
850 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
851 }
852
853 static struct resource uart3_resources[] = {
854 [0] = {
855 .start = AT91SAM9260_BASE_US3,
856 .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
857 .flags = IORESOURCE_MEM,
858 },
859 [1] = {
860 .start = AT91SAM9260_ID_US3,
861 .end = AT91SAM9260_ID_US3,
862 .flags = IORESOURCE_IRQ,
863 },
864 };
865
866 static struct atmel_uart_data uart3_data = {
867 .use_dma_tx = 1,
868 .use_dma_rx = 1,
869 };
870
871 static u64 uart3_dmamask = DMA_BIT_MASK(32);
872
873 static struct platform_device at91sam9260_uart3_device = {
874 .name = "atmel_usart",
875 .id = 4,
876 .dev = {
877 .dma_mask = &uart3_dmamask,
878 .coherent_dma_mask = DMA_BIT_MASK(32),
879 .platform_data = &uart3_data,
880 },
881 .resource = uart3_resources,
882 .num_resources = ARRAY_SIZE(uart3_resources),
883 };
884
885 static inline void configure_usart3_pins(void)
886 {
887 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
888 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
889 }
890
891 static struct resource uart4_resources[] = {
892 [0] = {
893 .start = AT91SAM9260_BASE_US4,
894 .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
895 .flags = IORESOURCE_MEM,
896 },
897 [1] = {
898 .start = AT91SAM9260_ID_US4,
899 .end = AT91SAM9260_ID_US4,
900 .flags = IORESOURCE_IRQ,
901 },
902 };
903
904 static struct atmel_uart_data uart4_data = {
905 .use_dma_tx = 1,
906 .use_dma_rx = 1,
907 };
908
909 static u64 uart4_dmamask = DMA_BIT_MASK(32);
910
911 static struct platform_device at91sam9260_uart4_device = {
912 .name = "atmel_usart",
913 .id = 5,
914 .dev = {
915 .dma_mask = &uart4_dmamask,
916 .coherent_dma_mask = DMA_BIT_MASK(32),
917 .platform_data = &uart4_data,
918 },
919 .resource = uart4_resources,
920 .num_resources = ARRAY_SIZE(uart4_resources),
921 };
922
923 static inline void configure_usart4_pins(void)
924 {
925 at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
926 at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
927 }
928
929 static struct resource uart5_resources[] = {
930 [0] = {
931 .start = AT91SAM9260_BASE_US5,
932 .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
933 .flags = IORESOURCE_MEM,
934 },
935 [1] = {
936 .start = AT91SAM9260_ID_US5,
937 .end = AT91SAM9260_ID_US5,
938 .flags = IORESOURCE_IRQ,
939 },
940 };
941
942 static struct atmel_uart_data uart5_data = {
943 .use_dma_tx = 1,
944 .use_dma_rx = 1,
945 };
946
947 static u64 uart5_dmamask = DMA_BIT_MASK(32);
948
949 static struct platform_device at91sam9260_uart5_device = {
950 .name = "atmel_usart",
951 .id = 6,
952 .dev = {
953 .dma_mask = &uart5_dmamask,
954 .coherent_dma_mask = DMA_BIT_MASK(32),
955 .platform_data = &uart5_data,
956 },
957 .resource = uart5_resources,
958 .num_resources = ARRAY_SIZE(uart5_resources),
959 };
960
961 static inline void configure_usart5_pins(void)
962 {
963 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
964 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
965 }
966
967 static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
968 struct platform_device *atmel_default_console_device; /* the serial console device */
969
970 void __init at91_init_serial(struct at91_uart_config *config)
971 {
972 int i;
973
974 /* Fill in list of supported UARTs */
975 for (i = 0; i < config->nr_tty; i++) {
976 switch (config->tty_map[i]) {
977 case 0:
978 configure_usart0_pins();
979 at91_uarts[i] = &at91sam9260_uart0_device;
980 at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
981 break;
982 case 1:
983 configure_usart1_pins();
984 at91_uarts[i] = &at91sam9260_uart1_device;
985 at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
986 break;
987 case 2:
988 configure_usart2_pins();
989 at91_uarts[i] = &at91sam9260_uart2_device;
990 at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
991 break;
992 case 3:
993 configure_usart3_pins();
994 at91_uarts[i] = &at91sam9260_uart3_device;
995 at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
996 break;
997 case 4:
998 configure_usart4_pins();
999 at91_uarts[i] = &at91sam9260_uart4_device;
1000 at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
1001 break;
1002 case 5:
1003 configure_usart5_pins();
1004 at91_uarts[i] = &at91sam9260_uart5_device;
1005 at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
1006 break;
1007 case 6:
1008 configure_dbgu_pins();
1009 at91_uarts[i] = &at91sam9260_dbgu_device;
1010 at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
1011 break;
1012 default:
1013 continue;
1014 }
1015 at91_uarts[i]->id = i; /* update ID number to mapped ID */
1016 }
1017
1018 /* Set serial console device */
1019 if (config->console_tty < ATMEL_MAX_UART)
1020 atmel_default_console_device = at91_uarts[config->console_tty];
1021 if (!atmel_default_console_device)
1022 printk(KERN_INFO "AT91: No default serial console defined.\n");
1023 }
1024
1025 void __init at91_add_device_serial(void)
1026 {
1027 int i;
1028
1029 for (i = 0; i < ATMEL_MAX_UART; i++) {
1030 if (at91_uarts[i])
1031 platform_device_register(at91_uarts[i]);
1032 }
1033 }
1034 #else
1035 void __init at91_init_serial(struct at91_uart_config *config) {}
1036 void __init at91_add_device_serial(void) {}
1037 #endif
1038
1039
1040 /* -------------------------------------------------------------------- */
1041 /*
1042 * These devices are always present and don't need any board-specific
1043 * setup.
1044 */
1045 static int __init at91_add_standard_devices(void)
1046 {
1047 at91_add_device_rtt();
1048 at91_add_device_watchdog();
1049 return 0;
1050 }
1051
1052 arch_initcall(at91_add_standard_devices);
SocketAccessConTroL development