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[PATCH] cpqarray section fix
[linux-2.6/sactl.git] / drivers / block / cpqarray.c
blob5eb6fb7b5cfacfba6c84672cd38aaf631f401c85
1 /*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22 #include <linux/config.h> /* CONFIG_PROC_FS */
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/pci.h>
26 #include <linux/bio.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/major.h>
32 #include <linux/fs.h>
33 #include <linux/blkpg.h>
34 #include <linux/timer.h>
35 #include <linux/proc_fs.h>
36 #include <linux/devfs_fs_kernel.h>
37 #include <linux/init.h>
38 #include <linux/hdreg.h>
39 #include <linux/spinlock.h>
40 #include <linux/blkdev.h>
41 #include <linux/genhd.h>
42 #include <asm/uaccess.h>
43 #include <asm/io.h>
44
45
46 #define SMART2_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
47
48 #define DRIVER_NAME "Compaq SMART2 Driver (v 2.6.0)"
49 #define DRIVER_VERSION SMART2_DRIVER_VERSION(2,6,0)
50
51 /* Embedded module documentation macros - see modules.h */
52 /* Original author Chris Frantz - Compaq Computer Corporation */
53 MODULE_AUTHOR("Compaq Computer Corporation");
54 MODULE_DESCRIPTION("Driver for Compaq Smart2 Array Controllers version 2.6.0");
55 MODULE_LICENSE("GPL");
56
57 #include "cpqarray.h"
58 #include "ida_cmd.h"
59 #include "smart1,2.h"
60 #include "ida_ioctl.h"
61
62 #define READ_AHEAD 128
63 #define NR_CMDS 128 /* This could probably go as high as ~400 */
64
65 #define MAX_CTLR 8
66 #define CTLR_SHIFT 8
67
68 #define CPQARRAY_DMA_MASK 0xFFFFFFFF /* 32 bit DMA */
69
70 static int nr_ctlr;
71 static ctlr_info_t *hba[MAX_CTLR];
72
73 static int eisa[8];
74
75 #define NR_PRODUCTS ARRAY_SIZE(products)
76
77 /* board_id = Subsystem Device ID & Vendor ID
78 * product = Marketing Name for the board
79 * access = Address of the struct of function pointers
80 */
81 static struct board_type products[] = {
82 { 0x0040110E, "IDA", &smart1_access },
83 { 0x0140110E, "IDA-2", &smart1_access },
84 { 0x1040110E, "IAES", &smart1_access },
85 { 0x2040110E, "SMART", &smart1_access },
86 { 0x3040110E, "SMART-2/E", &smart2e_access },
87 { 0x40300E11, "SMART-2/P", &smart2_access },
88 { 0x40310E11, "SMART-2SL", &smart2_access },
89 { 0x40320E11, "Smart Array 3200", &smart2_access },
90 { 0x40330E11, "Smart Array 3100ES", &smart2_access },
91 { 0x40340E11, "Smart Array 221", &smart2_access },
92 { 0x40400E11, "Integrated Array", &smart4_access },
93 { 0x40480E11, "Compaq Raid LC2", &smart4_access },
94 { 0x40500E11, "Smart Array 4200", &smart4_access },
95 { 0x40510E11, "Smart Array 4250ES", &smart4_access },
96 { 0x40580E11, "Smart Array 431", &smart4_access },
97 };
98
99 /* define the PCI info for the PCI cards this driver can control */
100 static const struct pci_device_id cpqarray_pci_device_id[] =
101 {
102 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
103 0x0E11, 0x4058, 0, 0, 0}, /* SA431 */
104 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
105 0x0E11, 0x4051, 0, 0, 0}, /* SA4250ES */
106 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
107 0x0E11, 0x4050, 0, 0, 0}, /* SA4200 */
108 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
109 0x0E11, 0x4048, 0, 0, 0}, /* LC2 */
110 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
111 0x0E11, 0x4040, 0, 0, 0}, /* Integrated Array */
112 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
113 0x0E11, 0x4034, 0, 0, 0}, /* SA 221 */
114 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
115 0x0E11, 0x4033, 0, 0, 0}, /* SA 3100ES*/
116 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
117 0x0E11, 0x4032, 0, 0, 0}, /* SA 3200*/
118 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
119 0x0E11, 0x4031, 0, 0, 0}, /* SA 2SL*/
120 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
121 0x0E11, 0x4030, 0, 0, 0}, /* SA 2P */
122 { 0 }
123 };
124
125 MODULE_DEVICE_TABLE(pci, cpqarray_pci_device_id);
126
127 static struct gendisk *ida_gendisk[MAX_CTLR][NWD];
128
129 /* Debug... */
130 #define DBG(s) do { s } while(0)
131 /* Debug (general info)... */
132 #define DBGINFO(s) do { } while(0)
133 /* Debug Paranoid... */
134 #define DBGP(s) do { } while(0)
135 /* Debug Extra Paranoid... */
136 #define DBGPX(s) do { } while(0)
137
138 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev);
139 static void __iomem *remap_pci_mem(ulong base, ulong size);
140 static int cpqarray_eisa_detect(void);
141 static int pollcomplete(int ctlr);
142 static void getgeometry(int ctlr);
143 static void start_fwbk(int ctlr);
144
145 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool);
146 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool);
147
148 static void free_hba(int i);
149 static int alloc_cpqarray_hba(void);
150
151 static int sendcmd(
152 __u8 cmd,
153 int ctlr,
154 void *buff,
155 size_t size,
156 unsigned int blk,
157 unsigned int blkcnt,
158 unsigned int log_unit );
159
160 static int ida_open(struct inode *inode, struct file *filep);
161 static int ida_release(struct inode *inode, struct file *filep);
162 static int ida_ioctl(struct inode *inode, struct file *filep, unsigned int cmd, unsigned long arg);
163 static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo);
164 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io);
165
166 static void do_ida_request(request_queue_t *q);
167 static void start_io(ctlr_info_t *h);
168
169 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c);
170 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c);
171 static inline void complete_buffers(struct bio *bio, int ok);
172 static inline void complete_command(cmdlist_t *cmd, int timeout);
173
174 static irqreturn_t do_ida_intr(int irq, void *dev_id, struct pt_regs * regs);
175 static void ida_timer(unsigned long tdata);
176 static int ida_revalidate(struct gendisk *disk);
177 static int revalidate_allvol(ctlr_info_t *host);
178 static int cpqarray_register_ctlr(int ctlr, struct pci_dev *pdev);
179
180 #ifdef CONFIG_PROC_FS
181 static void ida_procinit(int i);
182 static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data);
183 #else
184 static void ida_procinit(int i) {}
185 #endif
186
187 static inline drv_info_t *get_drv(struct gendisk *disk)
188 {
189 return disk->private_data;
190 }
191
192 static inline ctlr_info_t *get_host(struct gendisk *disk)
193 {
194 return disk->queue->queuedata;
195 }
196
197
198 static struct block_device_operations ida_fops = {
199 .owner = THIS_MODULE,
200 .open = ida_open,
201 .release = ida_release,
202 .ioctl = ida_ioctl,
203 .getgeo = ida_getgeo,
204 .revalidate_disk= ida_revalidate,
205 };
206
207
208 #ifdef CONFIG_PROC_FS
209
210 static struct proc_dir_entry *proc_array;
211
212 /*
213 * Get us a file in /proc/array that says something about each controller.
214 * Create /proc/array if it doesn't exist yet.
215 */
216 static void __init ida_procinit(int i)
217 {
218 if (proc_array == NULL) {
219 proc_array = proc_mkdir("cpqarray", proc_root_driver);
220 if (!proc_array) return;
221 }
222
223 create_proc_read_entry(hba[i]->devname, 0, proc_array,
224 ida_proc_get_info, hba[i]);
225 }
226
227 /*
228 * Report information about this controller.
229 */
230 static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data)
231 {
232 off_t pos = 0;
233 off_t len = 0;
234 int size, i, ctlr;
235 ctlr_info_t *h = (ctlr_info_t*)data;
236 drv_info_t *drv;
237 #ifdef CPQ_PROC_PRINT_QUEUES
238 cmdlist_t *c;
239 unsigned long flags;
240 #endif
241
242 ctlr = h->ctlr;
243 size = sprintf(buffer, "%s: Compaq %s Controller\n"
244 " Board ID: 0x%08lx\n"
245 " Firmware Revision: %c%c%c%c\n"
246 " Controller Sig: 0x%08lx\n"
247 " Memory Address: 0x%08lx\n"
248 " I/O Port: 0x%04x\n"
249 " IRQ: %d\n"
250 " Logical drives: %d\n"
251 " Physical drives: %d\n\n"
252 " Current Q depth: %d\n"
253 " Max Q depth since init: %d\n\n",
254 h->devname,
255 h->product_name,
256 (unsigned long)h->board_id,
257 h->firm_rev[0], h->firm_rev[1], h->firm_rev[2], h->firm_rev[3],
258 (unsigned long)h->ctlr_sig, (unsigned long)h->vaddr,
259 (unsigned int) h->io_mem_addr, (unsigned int)h->intr,
260 h->log_drives, h->phys_drives,
261 h->Qdepth, h->maxQsinceinit);
262
263 pos += size; len += size;
264
265 size = sprintf(buffer+len, "Logical Drive Info:\n");
266 pos += size; len += size;
267
268 for(i=0; i<h->log_drives; i++) {
269 drv = &h->drv[i];
270 size = sprintf(buffer+len, "ida/c%dd%d: blksz=%d nr_blks=%d\n",
271 ctlr, i, drv->blk_size, drv->nr_blks);
272 pos += size; len += size;
273 }
274
275 #ifdef CPQ_PROC_PRINT_QUEUES
276 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
277 size = sprintf(buffer+len, "\nCurrent Queues:\n");
278 pos += size; len += size;
279
280 c = h->reqQ;
281 size = sprintf(buffer+len, "reqQ = %p", c); pos += size; len += size;
282 if (c) c=c->next;
283 while(c && c != h->reqQ) {
284 size = sprintf(buffer+len, "->%p", c);
285 pos += size; len += size;
286 c=c->next;
287 }
288
289 c = h->cmpQ;
290 size = sprintf(buffer+len, "\ncmpQ = %p", c); pos += size; len += size;
291 if (c) c=c->next;
292 while(c && c != h->cmpQ) {
293 size = sprintf(buffer+len, "->%p", c);
294 pos += size; len += size;
295 c=c->next;
296 }
297
298 size = sprintf(buffer+len, "\n"); pos += size; len += size;
299 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
300 #endif
301 size = sprintf(buffer+len, "nr_allocs = %d\nnr_frees = %d\n",
302 h->nr_allocs, h->nr_frees);
303 pos += size; len += size;
304
305 *eof = 1;
306 *start = buffer+offset;
307 len -= offset;
308 if (len>length)
309 len = length;
310 return len;
311 }
312 #endif /* CONFIG_PROC_FS */
313
314 module_param_array(eisa, int, NULL, 0);
315
316 static void release_io_mem(ctlr_info_t *c)
317 {
318 /* if IO mem was not protected do nothing */
319 if( c->io_mem_addr == 0)
320 return;
321 release_region(c->io_mem_addr, c->io_mem_length);
322 c->io_mem_addr = 0;
323 c->io_mem_length = 0;
324 }
325
326 static void __devexit cpqarray_remove_one(int i)
327 {
328 int j;
329 char buff[4];
330
331 /* sendcmd will turn off interrupt, and send the flush...
332 * To write all data in the battery backed cache to disks
333 * no data returned, but don't want to send NULL to sendcmd */
334 if( sendcmd(FLUSH_CACHE, i, buff, 4, 0, 0, 0))
335 {
336 printk(KERN_WARNING "Unable to flush cache on controller %d\n",
337 i);
338 }
339 free_irq(hba[i]->intr, hba[i]);
340 iounmap(hba[i]->vaddr);
341 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
342 del_timer(&hba[i]->timer);
343 remove_proc_entry(hba[i]->devname, proc_array);
344 pci_free_consistent(hba[i]->pci_dev,
345 NR_CMDS * sizeof(cmdlist_t), (hba[i]->cmd_pool),
346 hba[i]->cmd_pool_dhandle);
347 kfree(hba[i]->cmd_pool_bits);
348 for(j = 0; j < NWD; j++) {
349 if (ida_gendisk[i][j]->flags & GENHD_FL_UP)
350 del_gendisk(ida_gendisk[i][j]);
351 devfs_remove("ida/c%dd%d",i,j);
352 put_disk(ida_gendisk[i][j]);
353 }
354 blk_cleanup_queue(hba[i]->queue);
355 release_io_mem(hba[i]);
356 free_hba(i);
357 }
358
359 static void __devexit cpqarray_remove_one_pci (struct pci_dev *pdev)
360 {
361 int i;
362 ctlr_info_t *tmp_ptr;
363
364 if (pci_get_drvdata(pdev) == NULL) {
365 printk( KERN_ERR "cpqarray: Unable to remove device \n");
366 return;
367 }
368
369 tmp_ptr = pci_get_drvdata(pdev);
370 i = tmp_ptr->ctlr;
371 if (hba[i] == NULL) {
372 printk(KERN_ERR "cpqarray: controller %d appears to have"
373 "already been removed \n", i);
374 return;
375 }
376 pci_set_drvdata(pdev, NULL);
377
378 cpqarray_remove_one(i);
379 }
380
381 /* removing an instance that was not removed automatically..
382 * must be an eisa card.
383 */
384 static void __devexit cpqarray_remove_one_eisa (int i)
385 {
386 if (hba[i] == NULL) {
387 printk(KERN_ERR "cpqarray: controller %d appears to have"
388 "already been removed \n", i);
389 return;
390 }
391 cpqarray_remove_one(i);
392 }
393
394 /* pdev is NULL for eisa */
395 static int __init cpqarray_register_ctlr( int i, struct pci_dev *pdev)
396 {
397 request_queue_t *q;
398 int j;
399
400 /*
401 * register block devices
402 * Find disks and fill in structs
403 * Get an interrupt, set the Q depth and get into /proc
404 */
405
406 /* If this successful it should insure that we are the only */
407 /* instance of the driver */
408 if (register_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname)) {
409 goto Enomem4;
410 }
411 hba[i]->access.set_intr_mask(hba[i], 0);
412 if (request_irq(hba[i]->intr, do_ida_intr,
413 SA_INTERRUPT|SA_SHIRQ, hba[i]->devname, hba[i]))
414 {
415 printk(KERN_ERR "cpqarray: Unable to get irq %d for %s\n",
416 hba[i]->intr, hba[i]->devname);
417 goto Enomem3;
418 }
419
420 for (j=0; j<NWD; j++) {
421 ida_gendisk[i][j] = alloc_disk(1 << NWD_SHIFT);
422 if (!ida_gendisk[i][j])
423 goto Enomem2;
424 }
425
426 hba[i]->cmd_pool = (cmdlist_t *)pci_alloc_consistent(
427 hba[i]->pci_dev, NR_CMDS * sizeof(cmdlist_t),
428 &(hba[i]->cmd_pool_dhandle));
429 hba[i]->cmd_pool_bits = kmalloc(
430 ((NR_CMDS+BITS_PER_LONG-1)/BITS_PER_LONG)*sizeof(unsigned long),
431 GFP_KERNEL);
432
433 if (!hba[i]->cmd_pool_bits || !hba[i]->cmd_pool)
434 goto Enomem1;
435
436 memset(hba[i]->cmd_pool, 0, NR_CMDS * sizeof(cmdlist_t));
437 memset(hba[i]->cmd_pool_bits, 0, ((NR_CMDS+BITS_PER_LONG-1)/BITS_PER_LONG)*sizeof(unsigned long));
438 printk(KERN_INFO "cpqarray: Finding drives on %s",
439 hba[i]->devname);
440
441 spin_lock_init(&hba[i]->lock);
442 q = blk_init_queue(do_ida_request, &hba[i]->lock);
443 if (!q)
444 goto Enomem1;
445
446 hba[i]->queue = q;
447 q->queuedata = hba[i];
448
449 getgeometry(i);
450 start_fwbk(i);
451
452 ida_procinit(i);
453
454 if (pdev)
455 blk_queue_bounce_limit(q, hba[i]->pci_dev->dma_mask);
456
457 /* This is a hardware imposed limit. */
458 blk_queue_max_hw_segments(q, SG_MAX);
459
460 /* This is a driver limit and could be eliminated. */
461 blk_queue_max_phys_segments(q, SG_MAX);
462
463 init_timer(&hba[i]->timer);
464 hba[i]->timer.expires = jiffies + IDA_TIMER;
465 hba[i]->timer.data = (unsigned long)hba[i];
466 hba[i]->timer.function = ida_timer;
467 add_timer(&hba[i]->timer);
468
469 /* Enable IRQ now that spinlock and rate limit timer are set up */
470 hba[i]->access.set_intr_mask(hba[i], FIFO_NOT_EMPTY);
471
472 for(j=0; j<NWD; j++) {
473 struct gendisk *disk = ida_gendisk[i][j];
474 drv_info_t *drv = &hba[i]->drv[j];
475 sprintf(disk->disk_name, "ida/c%dd%d", i, j);
476 disk->major = COMPAQ_SMART2_MAJOR + i;
477 disk->first_minor = j<<NWD_SHIFT;
478 disk->fops = &ida_fops;
479 if (j && !drv->nr_blks)
480 continue;
481 blk_queue_hardsect_size(hba[i]->queue, drv->blk_size);
482 set_capacity(disk, drv->nr_blks);
483 disk->queue = hba[i]->queue;
484 disk->private_data = drv;
485 add_disk(disk);
486 }
487
488 /* done ! */
489 return(i);
490
491 Enomem1:
492 nr_ctlr = i;
493 kfree(hba[i]->cmd_pool_bits);
494 if (hba[i]->cmd_pool)
495 pci_free_consistent(hba[i]->pci_dev, NR_CMDS*sizeof(cmdlist_t),
496 hba[i]->cmd_pool, hba[i]->cmd_pool_dhandle);
497 Enomem2:
498 while (j--) {
499 put_disk(ida_gendisk[i][j]);
500 ida_gendisk[i][j] = NULL;
501 }
502 free_irq(hba[i]->intr, hba[i]);
503 Enomem3:
504 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
505 Enomem4:
506 if (pdev)
507 pci_set_drvdata(pdev, NULL);
508 release_io_mem(hba[i]);
509 free_hba(i);
510
511 printk( KERN_ERR "cpqarray: out of memory");
512
513 return -1;
514 }
515
516 static int __init cpqarray_init_one( struct pci_dev *pdev,
517 const struct pci_device_id *ent)
518 {
519 int i;
520
521 printk(KERN_DEBUG "cpqarray: Device 0x%x has been found at"
522 " bus %d dev %d func %d\n",
523 pdev->device, pdev->bus->number, PCI_SLOT(pdev->devfn),
524 PCI_FUNC(pdev->devfn));
525 i = alloc_cpqarray_hba();
526 if( i < 0 )
527 return (-1);
528 memset(hba[i], 0, sizeof(ctlr_info_t));
529 sprintf(hba[i]->devname, "ida%d", i);
530 hba[i]->ctlr = i;
531 /* Initialize the pdev driver private data */
532 pci_set_drvdata(pdev, hba[i]);
533
534 if (cpqarray_pci_init(hba[i], pdev) != 0) {
535 pci_set_drvdata(pdev, NULL);
536 release_io_mem(hba[i]);
537 free_hba(i);
538 return -1;
539 }
540
541 return (cpqarray_register_ctlr(i, pdev));
542 }
543
544 static struct pci_driver cpqarray_pci_driver = {
545 .name = "cpqarray",
546 .probe = cpqarray_init_one,
547 .remove = __devexit_p(cpqarray_remove_one_pci),
548 .id_table = cpqarray_pci_device_id,
549 };
550
551 /*
552 * This is it. Find all the controllers and register them.
553 * returns the number of block devices registered.
554 */
555 static int __init cpqarray_init(void)
556 {
557 int num_cntlrs_reg = 0;
558 int i;
559 int rc = 0;
560
561 /* detect controllers */
562 printk(DRIVER_NAME "\n");
563
564 rc = pci_register_driver(&cpqarray_pci_driver);
565 if (rc)
566 return rc;
567 cpqarray_eisa_detect();
568
569 for (i=0; i < MAX_CTLR; i++) {
570 if (hba[i] != NULL)
571 num_cntlrs_reg++;
572 }
573
574 return(num_cntlrs_reg);
575 }
576
577 /* Function to find the first free pointer into our hba[] array */
578 /* Returns -1 if no free entries are left. */
579 static int alloc_cpqarray_hba(void)
580 {
581 int i;
582
583 for(i=0; i< MAX_CTLR; i++) {
584 if (hba[i] == NULL) {
585 hba[i] = kmalloc(sizeof(ctlr_info_t), GFP_KERNEL);
586 if(hba[i]==NULL) {
587 printk(KERN_ERR "cpqarray: out of memory.\n");
588 return (-1);
589 }
590 return (i);
591 }
592 }
593 printk(KERN_WARNING "cpqarray: This driver supports a maximum"
594 " of 8 controllers.\n");
595 return(-1);
596 }
597
598 static void free_hba(int i)
599 {
600 kfree(hba[i]);
601 hba[i]=NULL;
602 }
603
604 /*
605 * Find the IO address of the controller, its IRQ and so forth. Fill
606 * in some basic stuff into the ctlr_info_t structure.
607 */
608 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
609 {
610 ushort vendor_id, device_id, command;
611 unchar cache_line_size, latency_timer;
612 unchar irq, revision;
613 unsigned long addr[6];
614 __u32 board_id;
615
616 int i;
617
618 c->pci_dev = pdev;
619 if (pci_enable_device(pdev)) {
620 printk(KERN_ERR "cpqarray: Unable to Enable PCI device\n");
621 return -1;
622 }
623 vendor_id = pdev->vendor;
624 device_id = pdev->device;
625 irq = pdev->irq;
626
627 for(i=0; i<6; i++)
628 addr[i] = pci_resource_start(pdev, i);
629
630 if (pci_set_dma_mask(pdev, CPQARRAY_DMA_MASK) != 0)
631 {
632 printk(KERN_ERR "cpqarray: Unable to set DMA mask\n");
633 return -1;
634 }
635
636 pci_read_config_word(pdev, PCI_COMMAND, &command);
637 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
638 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
639 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency_timer);
640
641 pci_read_config_dword(pdev, 0x2c, &board_id);
642
643 /* check to see if controller has been disabled */
644 if(!(command & 0x02)) {
645 printk(KERN_WARNING
646 "cpqarray: controller appears to be disabled\n");
647 return(-1);
648 }
649
650 DBGINFO(
651 printk("vendor_id = %x\n", vendor_id);
652 printk("device_id = %x\n", device_id);
653 printk("command = %x\n", command);
654 for(i=0; i<6; i++)
655 printk("addr[%d] = %lx\n", i, addr[i]);
656 printk("revision = %x\n", revision);
657 printk("irq = %x\n", irq);
658 printk("cache_line_size = %x\n", cache_line_size);
659 printk("latency_timer = %x\n", latency_timer);
660 printk("board_id = %x\n", board_id);
661 );
662
663 c->intr = irq;
664
665 for(i=0; i<6; i++) {
666 if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO)
667 { /* IO space */
668 c->io_mem_addr = addr[i];
669 c->io_mem_length = pci_resource_end(pdev, i)
670 - pci_resource_start(pdev, i) + 1;
671 if(!request_region( c->io_mem_addr, c->io_mem_length,
672 "cpqarray"))
673 {
674 printk( KERN_WARNING "cpqarray I/O memory range already in use addr %lx length = %ld\n", c->io_mem_addr, c->io_mem_length);
675 c->io_mem_addr = 0;
676 c->io_mem_length = 0;
677 }
678 break;
679 }
680 }
681
682 c->paddr = 0;
683 for(i=0; i<6; i++)
684 if (!(pci_resource_flags(pdev, i) &
685 PCI_BASE_ADDRESS_SPACE_IO)) {
686 c->paddr = pci_resource_start (pdev, i);
687 break;
688 }
689 if (!c->paddr)
690 return -1;
691 c->vaddr = remap_pci_mem(c->paddr, 128);
692 if (!c->vaddr)
693 return -1;
694 c->board_id = board_id;
695
696 for(i=0; i<NR_PRODUCTS; i++) {
697 if (board_id == products[i].board_id) {
698 c->product_name = products[i].product_name;
699 c->access = *(products[i].access);
700 break;
701 }
702 }
703 if (i == NR_PRODUCTS) {
704 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
705 " to access the SMART Array controller %08lx\n",
706 (unsigned long)board_id);
707 return -1;
708 }
709
710 return 0;
711 }
712
713 /*
714 * Map (physical) PCI mem into (virtual) kernel space
715 */
716 static void __iomem *remap_pci_mem(ulong base, ulong size)
717 {
718 ulong page_base = ((ulong) base) & PAGE_MASK;
719 ulong page_offs = ((ulong) base) - page_base;
720 void __iomem *page_remapped = ioremap(page_base, page_offs+size);
721
722 return (page_remapped ? (page_remapped + page_offs) : NULL);
723 }
724
725 #ifndef MODULE
726 /*
727 * Config string is a comma separated set of i/o addresses of EISA cards.
728 */
729 static int cpqarray_setup(char *str)
730 {
731 int i, ints[9];
732
733 (void)get_options(str, ARRAY_SIZE(ints), ints);
734
735 for(i=0; i<ints[0] && i<8; i++)
736 eisa[i] = ints[i+1];
737 return 1;
738 }
739
740 __setup("smart2=", cpqarray_setup);
741
742 #endif
743
744 /*
745 * Find an EISA controller's signature. Set up an hba if we find it.
746 */
747 static int __init cpqarray_eisa_detect(void)
748 {
749 int i=0, j;
750 __u32 board_id;
751 int intr;
752 int ctlr;
753 int num_ctlr = 0;
754
755 while(i<8 && eisa[i]) {
756 ctlr = alloc_cpqarray_hba();
757 if(ctlr == -1)
758 break;
759 board_id = inl(eisa[i]+0xC80);
760 for(j=0; j < NR_PRODUCTS; j++)
761 if (board_id == products[j].board_id)
762 break;
763
764 if (j == NR_PRODUCTS) {
765 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
766 " to access the SMART Array controller %08lx\n", (unsigned long)board_id);
767 continue;
768 }
769
770 memset(hba[ctlr], 0, sizeof(ctlr_info_t));
771 hba[ctlr]->io_mem_addr = eisa[i];
772 hba[ctlr]->io_mem_length = 0x7FF;
773 if(!request_region(hba[ctlr]->io_mem_addr,
774 hba[ctlr]->io_mem_length,
775 "cpqarray"))
776 {
777 printk(KERN_WARNING "cpqarray: I/O range already in "
778 "use addr = %lx length = %ld\n",
779 hba[ctlr]->io_mem_addr,
780 hba[ctlr]->io_mem_length);
781 free_hba(ctlr);
782 continue;
783 }
784
785 /*
786 * Read the config register to find our interrupt
787 */
788 intr = inb(eisa[i]+0xCC0) >> 4;
789 if (intr & 1) intr = 11;
790 else if (intr & 2) intr = 10;
791 else if (intr & 4) intr = 14;
792 else if (intr & 8) intr = 15;
793
794 hba[ctlr]->intr = intr;
795 sprintf(hba[ctlr]->devname, "ida%d", nr_ctlr);
796 hba[ctlr]->product_name = products[j].product_name;
797 hba[ctlr]->access = *(products[j].access);
798 hba[ctlr]->ctlr = ctlr;
799 hba[ctlr]->board_id = board_id;
800 hba[ctlr]->pci_dev = NULL; /* not PCI */
801
802 DBGINFO(
803 printk("i = %d, j = %d\n", i, j);
804 printk("irq = %x\n", intr);
805 printk("product name = %s\n", products[j].product_name);
806 printk("board_id = %x\n", board_id);
807 );
808
809 num_ctlr++;
810 i++;
811
812 if (cpqarray_register_ctlr(ctlr, NULL) == -1)
813 printk(KERN_WARNING
814 "cpqarray: Can't register EISA controller %d\n",
815 ctlr);
816
817 }
818
819 return num_ctlr;
820 }
821
822 /*
823 * Open. Make sure the device is really there.
824 */
825 static int ida_open(struct inode *inode, struct file *filep)
826 {
827 drv_info_t *drv = get_drv(inode->i_bdev->bd_disk);
828 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
829
830 DBGINFO(printk("ida_open %s\n", inode->i_bdev->bd_disk->disk_name));
831 /*
832 * Root is allowed to open raw volume zero even if it's not configured
833 * so array config can still work. I don't think I really like this,
834 * but I'm already using way to many device nodes to claim another one
835 * for "raw controller".
836 */
837 if (!drv->nr_blks) {
838 if (!capable(CAP_SYS_RAWIO))
839 return -ENXIO;
840 if (!capable(CAP_SYS_ADMIN) && drv != host->drv)
841 return -ENXIO;
842 }
843 host->usage_count++;
844 return 0;
845 }
846
847 /*
848 * Close. Sync first.
849 */
850 static int ida_release(struct inode *inode, struct file *filep)
851 {
852 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
853 host->usage_count--;
854 return 0;
855 }
856
857 /*
858 * Enqueuing and dequeuing functions for cmdlists.
859 */
860 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c)
861 {
862 if (*Qptr == NULL) {
863 *Qptr = c;
864 c->next = c->prev = c;
865 } else {
866 c->prev = (*Qptr)->prev;
867 c->next = (*Qptr);
868 (*Qptr)->prev->next = c;
869 (*Qptr)->prev = c;
870 }
871 }
872
873 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c)
874 {
875 if (c && c->next != c) {
876 if (*Qptr == c) *Qptr = c->next;
877 c->prev->next = c->next;
878 c->next->prev = c->prev;
879 } else {
880 *Qptr = NULL;
881 }
882 return c;
883 }
884
885 /*
886 * Get a request and submit it to the controller.
887 * This routine needs to grab all the requests it possibly can from the
888 * req Q and submit them. Interrupts are off (and need to be off) when you
889 * are in here (either via the dummy do_ida_request functions or by being
890 * called from the interrupt handler
891 */
892 static void do_ida_request(request_queue_t *q)
893 {
894 ctlr_info_t *h = q->queuedata;
895 cmdlist_t *c;
896 struct request *creq;
897 struct scatterlist tmp_sg[SG_MAX];
898 int i, dir, seg;
899
900 if (blk_queue_plugged(q))
901 goto startio;
902
903 queue_next:
904 creq = elv_next_request(q);
905 if (!creq)
906 goto startio;
907
908 BUG_ON(creq->nr_phys_segments > SG_MAX);
909
910 if ((c = cmd_alloc(h,1)) == NULL)
911 goto startio;
912
913 blkdev_dequeue_request(creq);
914
915 c->ctlr = h->ctlr;
916 c->hdr.unit = (drv_info_t *)(creq->rq_disk->private_data) - h->drv;
917 c->hdr.size = sizeof(rblk_t) >> 2;
918 c->size += sizeof(rblk_t);
919
920 c->req.hdr.blk = creq->sector;
921 c->rq = creq;
922 DBGPX(
923 printk("sector=%d, nr_sectors=%d\n", creq->sector, creq->nr_sectors);
924 );
925 seg = blk_rq_map_sg(q, creq, tmp_sg);
926
927 /* Now do all the DMA Mappings */
928 if (rq_data_dir(creq) == READ)
929 dir = PCI_DMA_FROMDEVICE;
930 else
931 dir = PCI_DMA_TODEVICE;
932 for( i=0; i < seg; i++)
933 {
934 c->req.sg[i].size = tmp_sg[i].length;
935 c->req.sg[i].addr = (__u32) pci_map_page(h->pci_dev,
936 tmp_sg[i].page,
937 tmp_sg[i].offset,
938 tmp_sg[i].length, dir);
939 }
940 DBGPX( printk("Submitting %d sectors in %d segments\n", creq->nr_sectors, seg); );
941 c->req.hdr.sg_cnt = seg;
942 c->req.hdr.blk_cnt = creq->nr_sectors;
943 c->req.hdr.cmd = (rq_data_dir(creq) == READ) ? IDA_READ : IDA_WRITE;
944 c->type = CMD_RWREQ;
945
946 /* Put the request on the tail of the request queue */
947 addQ(&h->reqQ, c);
948 h->Qdepth++;
949 if (h->Qdepth > h->maxQsinceinit)
950 h->maxQsinceinit = h->Qdepth;
951
952 goto queue_next;
953
954 startio:
955 start_io(h);
956 }
957
958 /*
959 * start_io submits everything on a controller's request queue
960 * and moves it to the completion queue.
961 *
962 * Interrupts had better be off if you're in here
963 */
964 static void start_io(ctlr_info_t *h)
965 {
966 cmdlist_t *c;
967
968 while((c = h->reqQ) != NULL) {
969 /* Can't do anything if we're busy */
970 if (h->access.fifo_full(h) == 0)
971 return;
972
973 /* Get the first entry from the request Q */
974 removeQ(&h->reqQ, c);
975 h->Qdepth--;
976
977 /* Tell the controller to do our bidding */
978 h->access.submit_command(h, c);
979
980 /* Get onto the completion Q */
981 addQ(&h->cmpQ, c);
982 }
983 }
984
985 static inline void complete_buffers(struct bio *bio, int ok)
986 {
987 struct bio *xbh;
988 while(bio) {
989 int nr_sectors = bio_sectors(bio);
990
991 xbh = bio->bi_next;
992 bio->bi_next = NULL;
993
994 blk_finished_io(nr_sectors);
995 bio_endio(bio, nr_sectors << 9, ok ? 0 : -EIO);
996
997 bio = xbh;
998 }
999 }
1000 /*
1001 * Mark all buffers that cmd was responsible for
1002 */
1003 static inline void complete_command(cmdlist_t *cmd, int timeout)
1004 {
1005 int ok=1;
1006 int i, ddir;
1007
1008 if (cmd->req.hdr.rcode & RCODE_NONFATAL &&
1009 (hba[cmd->ctlr]->misc_tflags & MISC_NONFATAL_WARN) == 0) {
1010 printk(KERN_NOTICE "Non Fatal error on ida/c%dd%d\n",
1011 cmd->ctlr, cmd->hdr.unit);
1012 hba[cmd->ctlr]->misc_tflags |= MISC_NONFATAL_WARN;
1013 }
1014 if (cmd->req.hdr.rcode & RCODE_FATAL) {
1015 printk(KERN_WARNING "Fatal error on ida/c%dd%d\n",
1016 cmd->ctlr, cmd->hdr.unit);
1017 ok = 0;
1018 }
1019 if (cmd->req.hdr.rcode & RCODE_INVREQ) {
1020 printk(KERN_WARNING "Invalid request on ida/c%dd%d = (cmd=%x sect=%d cnt=%d sg=%d ret=%x)\n",
1021 cmd->ctlr, cmd->hdr.unit, cmd->req.hdr.cmd,
1022 cmd->req.hdr.blk, cmd->req.hdr.blk_cnt,
1023 cmd->req.hdr.sg_cnt, cmd->req.hdr.rcode);
1024 ok = 0;
1025 }
1026 if (timeout) ok = 0;
1027 /* unmap the DMA mapping for all the scatter gather elements */
1028 if (cmd->req.hdr.cmd == IDA_READ)
1029 ddir = PCI_DMA_FROMDEVICE;
1030 else
1031 ddir = PCI_DMA_TODEVICE;
1032 for(i=0; i<cmd->req.hdr.sg_cnt; i++)
1033 pci_unmap_page(hba[cmd->ctlr]->pci_dev, cmd->req.sg[i].addr,
1034 cmd->req.sg[i].size, ddir);
1035
1036 complete_buffers(cmd->rq->bio, ok);
1037
1038 add_disk_randomness(cmd->rq->rq_disk);
1039
1040 DBGPX(printk("Done with %p\n", cmd->rq););
1041 end_that_request_last(cmd->rq, ok ? 1 : -EIO);
1042 }
1043
1044 /*
1045 * The controller will interrupt us upon completion of commands.
1046 * Find the command on the completion queue, remove it, tell the OS and
1047 * try to queue up more IO
1048 */
1049 static irqreturn_t do_ida_intr(int irq, void *dev_id, struct pt_regs *regs)
1050 {
1051 ctlr_info_t *h = dev_id;
1052 cmdlist_t *c;
1053 unsigned long istat;
1054 unsigned long flags;
1055 __u32 a,a1;
1056
1057 istat = h->access.intr_pending(h);
1058 /* Is this interrupt for us? */
1059 if (istat == 0)
1060 return IRQ_NONE;
1061
1062 /*
1063 * If there are completed commands in the completion queue,
1064 * we had better do something about it.
1065 */
1066 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
1067 if (istat & FIFO_NOT_EMPTY) {
1068 while((a = h->access.command_completed(h))) {
1069 a1 = a; a &= ~3;
1070 if ((c = h->cmpQ) == NULL)
1071 {
1072 printk(KERN_WARNING "cpqarray: Completion of %08lx ignored\n", (unsigned long)a1);
1073 continue;
1074 }
1075 while(c->busaddr != a) {
1076 c = c->next;
1077 if (c == h->cmpQ)
1078 break;
1079 }
1080 /*
1081 * If we've found the command, take it off the
1082 * completion Q and free it
1083 */
1084 if (c->busaddr == a) {
1085 removeQ(&h->cmpQ, c);
1086 /* Check for invalid command.
1087 * Controller returns command error,
1088 * But rcode = 0.
1089 */
1090
1091 if((a1 & 0x03) && (c->req.hdr.rcode == 0))
1092 {
1093 c->req.hdr.rcode = RCODE_INVREQ;
1094 }
1095 if (c->type == CMD_RWREQ) {
1096 complete_command(c, 0);
1097 cmd_free(h, c, 1);
1098 } else if (c->type == CMD_IOCTL_PEND) {
1099 c->type = CMD_IOCTL_DONE;
1100 }
1101 continue;
1102 }
1103 }
1104 }
1105
1106 /*
1107 * See if we can queue up some more IO
1108 */
1109 do_ida_request(h->queue);
1110 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
1111 return IRQ_HANDLED;
1112 }
1113
1114 /*
1115 * This timer was for timing out requests that haven't happened after
1116 * IDA_TIMEOUT. That wasn't such a good idea. This timer is used to
1117 * reset a flags structure so we don't flood the user with
1118 * "Non-Fatal error" messages.
1119 */
1120 static void ida_timer(unsigned long tdata)
1121 {
1122 ctlr_info_t *h = (ctlr_info_t*)tdata;
1123
1124 h->timer.expires = jiffies + IDA_TIMER;
1125 add_timer(&h->timer);
1126 h->misc_tflags = 0;
1127 }
1128
1129 static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1130 {
1131 drv_info_t *drv = get_drv(bdev->bd_disk);
1132
1133 if (drv->cylinders) {
1134 geo->heads = drv->heads;
1135 geo->sectors = drv->sectors;
1136 geo->cylinders = drv->cylinders;
1137 } else {
1138 geo->heads = 0xff;
1139 geo->sectors = 0x3f;
1140 geo->cylinders = drv->nr_blks / (0xff*0x3f);
1141 }
1142
1143 return 0;
1144 }
1145
1146 /*
1147 * ida_ioctl does some miscellaneous stuff like reporting drive geometry,
1148 * setting readahead and submitting commands from userspace to the controller.
1149 */
1150 static int ida_ioctl(struct inode *inode, struct file *filep, unsigned int cmd, unsigned long arg)
1151 {
1152 drv_info_t *drv = get_drv(inode->i_bdev->bd_disk);
1153 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
1154 int error;
1155 ida_ioctl_t __user *io = (ida_ioctl_t __user *)arg;
1156 ida_ioctl_t *my_io;
1157
1158 switch(cmd) {
1159 case IDAGETDRVINFO:
1160 if (copy_to_user(&io->c.drv, drv, sizeof(drv_info_t)))
1161 return -EFAULT;
1162 return 0;
1163 case IDAPASSTHRU:
1164 if (!capable(CAP_SYS_RAWIO))
1165 return -EPERM;
1166 my_io = kmalloc(sizeof(ida_ioctl_t), GFP_KERNEL);
1167 if (!my_io)
1168 return -ENOMEM;
1169 error = -EFAULT;
1170 if (copy_from_user(my_io, io, sizeof(*my_io)))
1171 goto out_passthru;
1172 error = ida_ctlr_ioctl(host, drv - host->drv, my_io);
1173 if (error)
1174 goto out_passthru;
1175 error = -EFAULT;
1176 if (copy_to_user(io, my_io, sizeof(*my_io)))
1177 goto out_passthru;
1178 error = 0;
1179 out_passthru:
1180 kfree(my_io);
1181 return error;
1182 case IDAGETCTLRSIG:
1183 if (!arg) return -EINVAL;
1184 put_user(host->ctlr_sig, (int __user *)arg);
1185 return 0;
1186 case IDAREVALIDATEVOLS:
1187 if (iminor(inode) != 0)
1188 return -ENXIO;
1189 return revalidate_allvol(host);
1190 case IDADRIVERVERSION:
1191 if (!arg) return -EINVAL;
1192 put_user(DRIVER_VERSION, (unsigned long __user *)arg);
1193 return 0;
1194 case IDAGETPCIINFO:
1195 {
1196
1197 ida_pci_info_struct pciinfo;
1198
1199 if (!arg) return -EINVAL;
1200 pciinfo.bus = host->pci_dev->bus->number;
1201 pciinfo.dev_fn = host->pci_dev->devfn;
1202 pciinfo.board_id = host->board_id;
1203 if(copy_to_user((void __user *) arg, &pciinfo,
1204 sizeof( ida_pci_info_struct)))
1205 return -EFAULT;
1206 return(0);
1207 }
1208
1209 default:
1210 return -EINVAL;
1211 }
1212
1213 }
1214 /*
1215 * ida_ctlr_ioctl is for passing commands to the controller from userspace.
1216 * The command block (io) has already been copied to kernel space for us,
1217 * however, any elements in the sglist need to be copied to kernel space
1218 * or copied back to userspace.
1219 *
1220 * Only root may perform a controller passthru command, however I'm not doing
1221 * any serious sanity checking on the arguments. Doing an IDA_WRITE_MEDIA and
1222 * putting a 64M buffer in the sglist is probably a *bad* idea.
1223 */
1224 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io)
1225 {
1226 int ctlr = h->ctlr;
1227 cmdlist_t *c;
1228 void *p = NULL;
1229 unsigned long flags;
1230 int error;
1231
1232 if ((c = cmd_alloc(h, 0)) == NULL)
1233 return -ENOMEM;
1234 c->ctlr = ctlr;
1235 c->hdr.unit = (io->unit & UNITVALID) ? (io->unit & ~UNITVALID) : dsk;
1236 c->hdr.size = sizeof(rblk_t) >> 2;
1237 c->size += sizeof(rblk_t);
1238
1239 c->req.hdr.cmd = io->cmd;
1240 c->req.hdr.blk = io->blk;
1241 c->req.hdr.blk_cnt = io->blk_cnt;
1242 c->type = CMD_IOCTL_PEND;
1243
1244 /* Pre submit processing */
1245 switch(io->cmd) {
1246 case PASSTHRU_A:
1247 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1248 if (!p)
1249 {
1250 error = -ENOMEM;
1251 cmd_free(h, c, 0);
1252 return(error);
1253 }
1254 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1255 kfree(p);
1256 cmd_free(h, c, 0);
1257 return -EFAULT;
1258 }
1259 c->req.hdr.blk = pci_map_single(h->pci_dev, &(io->c),
1260 sizeof(ida_ioctl_t),
1261 PCI_DMA_BIDIRECTIONAL);
1262 c->req.sg[0].size = io->sg[0].size;
1263 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1264 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1265 c->req.hdr.sg_cnt = 1;
1266 break;
1267 case IDA_READ:
1268 case READ_FLASH_ROM:
1269 case SENSE_CONTROLLER_PERFORMANCE:
1270 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1271 if (!p)
1272 {
1273 error = -ENOMEM;
1274 cmd_free(h, c, 0);
1275 return(error);
1276 }
1277
1278 c->req.sg[0].size = io->sg[0].size;
1279 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1280 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1281 c->req.hdr.sg_cnt = 1;
1282 break;
1283 case IDA_WRITE:
1284 case IDA_WRITE_MEDIA:
1285 case DIAG_PASS_THRU:
1286 case COLLECT_BUFFER:
1287 case WRITE_FLASH_ROM:
1288 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1289 if (!p)
1290 {
1291 error = -ENOMEM;
1292 cmd_free(h, c, 0);
1293 return(error);
1294 }
1295 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1296 kfree(p);
1297 cmd_free(h, c, 0);
1298 return -EFAULT;
1299 }
1300 c->req.sg[0].size = io->sg[0].size;
1301 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1302 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1303 c->req.hdr.sg_cnt = 1;
1304 break;
1305 default:
1306 c->req.sg[0].size = sizeof(io->c);
1307 c->req.sg[0].addr = pci_map_single(h->pci_dev,&io->c,
1308 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1309 c->req.hdr.sg_cnt = 1;
1310 }
1311
1312 /* Put the request on the tail of the request queue */
1313 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1314 addQ(&h->reqQ, c);
1315 h->Qdepth++;
1316 start_io(h);
1317 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1318
1319 /* Wait for completion */
1320 while(c->type != CMD_IOCTL_DONE)
1321 schedule();
1322
1323 /* Unmap the DMA */
1324 pci_unmap_single(h->pci_dev, c->req.sg[0].addr, c->req.sg[0].size,
1325 PCI_DMA_BIDIRECTIONAL);
1326 /* Post submit processing */
1327 switch(io->cmd) {
1328 case PASSTHRU_A:
1329 pci_unmap_single(h->pci_dev, c->req.hdr.blk,
1330 sizeof(ida_ioctl_t),
1331 PCI_DMA_BIDIRECTIONAL);
1332 case IDA_READ:
1333 case DIAG_PASS_THRU:
1334 case SENSE_CONTROLLER_PERFORMANCE:
1335 case READ_FLASH_ROM:
1336 if (copy_to_user(io->sg[0].addr, p, io->sg[0].size)) {
1337 kfree(p);
1338 return -EFAULT;
1339 }
1340 /* fall through and free p */
1341 case IDA_WRITE:
1342 case IDA_WRITE_MEDIA:
1343 case COLLECT_BUFFER:
1344 case WRITE_FLASH_ROM:
1345 kfree(p);
1346 break;
1347 default:;
1348 /* Nothing to do */
1349 }
1350
1351 io->rcode = c->req.hdr.rcode;
1352 cmd_free(h, c, 0);
1353 return(0);
1354 }
1355
1356 /*
1357 * Commands are pre-allocated in a large block. Here we use a simple bitmap
1358 * scheme to suballocte them to the driver. Operations that are not time
1359 * critical (and can wait for kmalloc and possibly sleep) can pass in NULL
1360 * as the first argument to get a new command.
1361 */
1362 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool)
1363 {
1364 cmdlist_t * c;
1365 int i;
1366 dma_addr_t cmd_dhandle;
1367
1368 if (!get_from_pool) {
1369 c = (cmdlist_t*)pci_alloc_consistent(h->pci_dev,
1370 sizeof(cmdlist_t), &cmd_dhandle);
1371 if(c==NULL)
1372 return NULL;
1373 } else {
1374 do {
1375 i = find_first_zero_bit(h->cmd_pool_bits, NR_CMDS);
1376 if (i == NR_CMDS)
1377 return NULL;
1378 } while(test_and_set_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG)) != 0);
1379 c = h->cmd_pool + i;
1380 cmd_dhandle = h->cmd_pool_dhandle + i*sizeof(cmdlist_t);
1381 h->nr_allocs++;
1382 }
1383
1384 memset(c, 0, sizeof(cmdlist_t));
1385 c->busaddr = cmd_dhandle;
1386 return c;
1387 }
1388
1389 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool)
1390 {
1391 int i;
1392
1393 if (!got_from_pool) {
1394 pci_free_consistent(h->pci_dev, sizeof(cmdlist_t), c,
1395 c->busaddr);
1396 } else {
1397 i = c - h->cmd_pool;
1398 clear_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG));
1399 h->nr_frees++;
1400 }
1401 }
1402
1403 /***********************************************************************
1404 name: sendcmd
1405 Send a command to an IDA using the memory mapped FIFO interface
1406 and wait for it to complete.
1407 This routine should only be called at init time.
1408 ***********************************************************************/
1409 static int sendcmd(
1410 __u8 cmd,
1411 int ctlr,
1412 void *buff,
1413 size_t size,
1414 unsigned int blk,
1415 unsigned int blkcnt,
1416 unsigned int log_unit )
1417 {
1418 cmdlist_t *c;
1419 int complete;
1420 unsigned long temp;
1421 unsigned long i;
1422 ctlr_info_t *info_p = hba[ctlr];
1423
1424 c = cmd_alloc(info_p, 1);
1425 if(!c)
1426 return IO_ERROR;
1427 c->ctlr = ctlr;
1428 c->hdr.unit = log_unit;
1429 c->hdr.prio = 0;
1430 c->hdr.size = sizeof(rblk_t) >> 2;
1431 c->size += sizeof(rblk_t);
1432
1433 /* The request information. */
1434 c->req.hdr.next = 0;
1435 c->req.hdr.rcode = 0;
1436 c->req.bp = 0;
1437 c->req.hdr.sg_cnt = 1;
1438 c->req.hdr.reserved = 0;
1439
1440 if (size == 0)
1441 c->req.sg[0].size = 512;
1442 else
1443 c->req.sg[0].size = size;
1444
1445 c->req.hdr.blk = blk;
1446 c->req.hdr.blk_cnt = blkcnt;
1447 c->req.hdr.cmd = (unsigned char) cmd;
1448 c->req.sg[0].addr = (__u32) pci_map_single(info_p->pci_dev,
1449 buff, c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1450 /*
1451 * Disable interrupt
1452 */
1453 info_p->access.set_intr_mask(info_p, 0);
1454 /* Make sure there is room in the command FIFO */
1455 /* Actually it should be completely empty at this time. */
1456 for (i = 200000; i > 0; i--) {
1457 temp = info_p->access.fifo_full(info_p);
1458 if (temp != 0) {
1459 break;
1460 }
1461 udelay(10);
1462 DBG(
1463 printk(KERN_WARNING "cpqarray ida%d: idaSendPciCmd FIFO full,"
1464 " waiting!\n", ctlr);
1465 );
1466 }
1467 /*
1468 * Send the cmd
1469 */
1470 info_p->access.submit_command(info_p, c);
1471 complete = pollcomplete(ctlr);
1472
1473 pci_unmap_single(info_p->pci_dev, (dma_addr_t) c->req.sg[0].addr,
1474 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1475 if (complete != 1) {
1476 if (complete != c->busaddr) {
1477 printk( KERN_WARNING
1478 "cpqarray ida%d: idaSendPciCmd "
1479 "Invalid command list address returned! (%08lx)\n",
1480 ctlr, (unsigned long)complete);
1481 cmd_free(info_p, c, 1);
1482 return (IO_ERROR);
1483 }
1484 } else {
1485 printk( KERN_WARNING
1486 "cpqarray ida%d: idaSendPciCmd Timeout out, "
1487 "No command list address returned!\n",
1488 ctlr);
1489 cmd_free(info_p, c, 1);
1490 return (IO_ERROR);
1491 }
1492
1493 if (c->req.hdr.rcode & 0x00FE) {
1494 if (!(c->req.hdr.rcode & BIG_PROBLEM)) {
1495 printk( KERN_WARNING
1496 "cpqarray ida%d: idaSendPciCmd, error: "
1497 "Controller failed at init time "
1498 "cmd: 0x%x, return code = 0x%x\n",
1499 ctlr, c->req.hdr.cmd, c->req.hdr.rcode);
1500
1501 cmd_free(info_p, c, 1);
1502 return (IO_ERROR);
1503 }
1504 }
1505 cmd_free(info_p, c, 1);
1506 return (IO_OK);
1507 }
1508
1509 /*
1510 * revalidate_allvol is for online array config utilities. After a
1511 * utility reconfigures the drives in the array, it can use this function
1512 * (through an ioctl) to make the driver zap any previous disk structs for
1513 * that controller and get new ones.
1514 *
1515 * Right now I'm using the getgeometry() function to do this, but this
1516 * function should probably be finer grained and allow you to revalidate one
1517 * particualar logical volume (instead of all of them on a particular
1518 * controller).
1519 */
1520 static int revalidate_allvol(ctlr_info_t *host)
1521 {
1522 int ctlr = host->ctlr;
1523 int i;
1524 unsigned long flags;
1525
1526 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1527 if (host->usage_count > 1) {
1528 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1529 printk(KERN_WARNING "cpqarray: Device busy for volume"
1530 " revalidation (usage=%d)\n", host->usage_count);
1531 return -EBUSY;
1532 }
1533 host->usage_count++;
1534 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1535
1536 /*
1537 * Set the partition and block size structures for all volumes
1538 * on this controller to zero. We will reread all of this data
1539 */
1540 set_capacity(ida_gendisk[ctlr][0], 0);
1541 for (i = 1; i < NWD; i++) {
1542 struct gendisk *disk = ida_gendisk[ctlr][i];
1543 if (disk->flags & GENHD_FL_UP)
1544 del_gendisk(disk);
1545 }
1546 memset(host->drv, 0, sizeof(drv_info_t)*NWD);
1547
1548 /*
1549 * Tell the array controller not to give us any interrupts while
1550 * we check the new geometry. Then turn interrupts back on when
1551 * we're done.
1552 */
1553 host->access.set_intr_mask(host, 0);
1554 getgeometry(ctlr);
1555 host->access.set_intr_mask(host, FIFO_NOT_EMPTY);
1556
1557 for(i=0; i<NWD; i++) {
1558 struct gendisk *disk = ida_gendisk[ctlr][i];
1559 drv_info_t *drv = &host->drv[i];
1560 if (i && !drv->nr_blks)
1561 continue;
1562 blk_queue_hardsect_size(host->queue, drv->blk_size);
1563 set_capacity(disk, drv->nr_blks);
1564 disk->queue = host->queue;
1565 disk->private_data = drv;
1566 if (i)
1567 add_disk(disk);
1568 }
1569
1570 host->usage_count--;
1571 return 0;
1572 }
1573
1574 static int ida_revalidate(struct gendisk *disk)
1575 {
1576 drv_info_t *drv = disk->private_data;
1577 set_capacity(disk, drv->nr_blks);
1578 return 0;
1579 }
1580
1581 /********************************************************************
1582 name: pollcomplete
1583 Wait polling for a command to complete.
1584 The memory mapped FIFO is polled for the completion.
1585 Used only at init time, interrupts disabled.
1586 ********************************************************************/
1587 static int pollcomplete(int ctlr)
1588 {
1589 int done;
1590 int i;
1591
1592 /* Wait (up to 2 seconds) for a command to complete */
1593
1594 for (i = 200000; i > 0; i--) {
1595 done = hba[ctlr]->access.command_completed(hba[ctlr]);
1596 if (done == 0) {
1597 udelay(10); /* a short fixed delay */
1598 } else
1599 return (done);
1600 }
1601 /* Invalid address to tell caller we ran out of time */
1602 return 1;
1603 }
1604 /*****************************************************************
1605 start_fwbk
1606 Starts controller firmwares background processing.
1607 Currently only the Integrated Raid controller needs this done.
1608 If the PCI mem address registers are written to after this,
1609 data corruption may occur
1610 *****************************************************************/
1611 static void start_fwbk(int ctlr)
1612 {
1613 id_ctlr_t *id_ctlr_buf;
1614 int ret_code;
1615
1616 if( (hba[ctlr]->board_id != 0x40400E11)
1617 && (hba[ctlr]->board_id != 0x40480E11) )
1618
1619 /* Not a Integrated Raid, so there is nothing for us to do */
1620 return;
1621 printk(KERN_DEBUG "cpqarray: Starting firmware's background"
1622 " processing\n");
1623 /* Command does not return anything, but idasend command needs a
1624 buffer */
1625 id_ctlr_buf = (id_ctlr_t *)kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1626 if(id_ctlr_buf==NULL)
1627 {
1628 printk(KERN_WARNING "cpqarray: Out of memory. "
1629 "Unable to start background processing.\n");
1630 return;
1631 }
1632 ret_code = sendcmd(RESUME_BACKGROUND_ACTIVITY, ctlr,
1633 id_ctlr_buf, 0, 0, 0, 0);
1634 if(ret_code != IO_OK)
1635 printk(KERN_WARNING "cpqarray: Unable to start"
1636 " background processing\n");
1637
1638 kfree(id_ctlr_buf);
1639 }
1640 /*****************************************************************
1641 getgeometry
1642 Get ida logical volume geometry from the controller
1643 This is a large bit of code which once existed in two flavors,
1644 It is used only at init time.
1645 *****************************************************************/
1646 static void getgeometry(int ctlr)
1647 {
1648 id_log_drv_t *id_ldrive;
1649 id_ctlr_t *id_ctlr_buf;
1650 sense_log_drv_stat_t *id_lstatus_buf;
1651 config_t *sense_config_buf;
1652 unsigned int log_unit, log_index;
1653 int ret_code, size;
1654 drv_info_t *drv;
1655 ctlr_info_t *info_p = hba[ctlr];
1656 int i;
1657
1658 info_p->log_drv_map = 0;
1659
1660 id_ldrive = (id_log_drv_t *)kmalloc(sizeof(id_log_drv_t), GFP_KERNEL);
1661 if(id_ldrive == NULL)
1662 {
1663 printk( KERN_ERR "cpqarray: out of memory.\n");
1664 return;
1665 }
1666
1667 id_ctlr_buf = (id_ctlr_t *)kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1668 if(id_ctlr_buf == NULL)
1669 {
1670 kfree(id_ldrive);
1671 printk( KERN_ERR "cpqarray: out of memory.\n");
1672 return;
1673 }
1674
1675 id_lstatus_buf = (sense_log_drv_stat_t *)kmalloc(sizeof(sense_log_drv_stat_t), GFP_KERNEL);
1676 if(id_lstatus_buf == NULL)
1677 {
1678 kfree(id_ctlr_buf);
1679 kfree(id_ldrive);
1680 printk( KERN_ERR "cpqarray: out of memory.\n");
1681 return;
1682 }
1683
1684 sense_config_buf = (config_t *)kmalloc(sizeof(config_t), GFP_KERNEL);
1685 if(sense_config_buf == NULL)
1686 {
1687 kfree(id_lstatus_buf);
1688 kfree(id_ctlr_buf);
1689 kfree(id_ldrive);
1690 printk( KERN_ERR "cpqarray: out of memory.\n");
1691 return;
1692 }
1693
1694 memset(id_ldrive, 0, sizeof(id_log_drv_t));
1695 memset(id_ctlr_buf, 0, sizeof(id_ctlr_t));
1696 memset(id_lstatus_buf, 0, sizeof(sense_log_drv_stat_t));
1697 memset(sense_config_buf, 0, sizeof(config_t));
1698
1699 info_p->phys_drives = 0;
1700 info_p->log_drv_map = 0;
1701 info_p->drv_assign_map = 0;
1702 info_p->drv_spare_map = 0;
1703 info_p->mp_failed_drv_map = 0; /* only initialized here */
1704 /* Get controllers info for this logical drive */
1705 ret_code = sendcmd(ID_CTLR, ctlr, id_ctlr_buf, 0, 0, 0, 0);
1706 if (ret_code == IO_ERROR) {
1707 /*
1708 * If can't get controller info, set the logical drive map to 0,
1709 * so the idastubopen will fail on all logical drives
1710 * on the controller.
1711 */
1712 /* Free all the buffers and return */
1713 printk(KERN_ERR "cpqarray: error sending ID controller\n");
1714 kfree(sense_config_buf);
1715 kfree(id_lstatus_buf);
1716 kfree(id_ctlr_buf);
1717 kfree(id_ldrive);
1718 return;
1719 }
1720
1721 info_p->log_drives = id_ctlr_buf->nr_drvs;
1722 for(i=0;i<4;i++)
1723 info_p->firm_rev[i] = id_ctlr_buf->firm_rev[i];
1724 info_p->ctlr_sig = id_ctlr_buf->cfg_sig;
1725
1726 printk(" (%s)\n", info_p->product_name);
1727 /*
1728 * Initialize logical drive map to zero
1729 */
1730 log_index = 0;
1731 /*
1732 * Get drive geometry for all logical drives
1733 */
1734 if (id_ctlr_buf->nr_drvs > 16)
1735 printk(KERN_WARNING "cpqarray ida%d: This driver supports "
1736 "16 logical drives per controller.\n. "
1737 " Additional drives will not be "
1738 "detected\n", ctlr);
1739
1740 for (log_unit = 0;
1741 (log_index < id_ctlr_buf->nr_drvs)
1742 && (log_unit < NWD);
1743 log_unit++) {
1744 struct gendisk *disk = ida_gendisk[ctlr][log_unit];
1745
1746 size = sizeof(sense_log_drv_stat_t);
1747
1748 /*
1749 Send "Identify logical drive status" cmd
1750 */
1751 ret_code = sendcmd(SENSE_LOG_DRV_STAT,
1752 ctlr, id_lstatus_buf, size, 0, 0, log_unit);
1753 if (ret_code == IO_ERROR) {
1754 /*
1755 If can't get logical drive status, set
1756 the logical drive map to 0, so the
1757 idastubopen will fail for all logical drives
1758 on the controller.
1759 */
1760 info_p->log_drv_map = 0;
1761 printk( KERN_WARNING
1762 "cpqarray ida%d: idaGetGeometry - Controller"
1763 " failed to report status of logical drive %d\n"
1764 "Access to this controller has been disabled\n",
1765 ctlr, log_unit);
1766 /* Free all the buffers and return */
1767 kfree(sense_config_buf);
1768 kfree(id_lstatus_buf);
1769 kfree(id_ctlr_buf);
1770 kfree(id_ldrive);
1771 return;
1772 }
1773 /*
1774 Make sure the logical drive is configured
1775 */
1776 if (id_lstatus_buf->status != LOG_NOT_CONF) {
1777 ret_code = sendcmd(ID_LOG_DRV, ctlr, id_ldrive,
1778 sizeof(id_log_drv_t), 0, 0, log_unit);
1779 /*
1780 If error, the bit for this
1781 logical drive won't be set and
1782 idastubopen will return error.
1783 */
1784 if (ret_code != IO_ERROR) {
1785 drv = &info_p->drv[log_unit];
1786 drv->blk_size = id_ldrive->blk_size;
1787 drv->nr_blks = id_ldrive->nr_blks;
1788 drv->cylinders = id_ldrive->drv.cyl;
1789 drv->heads = id_ldrive->drv.heads;
1790 drv->sectors = id_ldrive->drv.sect_per_track;
1791 info_p->log_drv_map |= (1 << log_unit);
1792
1793 printk(KERN_INFO "cpqarray ida/c%dd%d: blksz=%d nr_blks=%d\n",
1794 ctlr, log_unit, drv->blk_size, drv->nr_blks);
1795 ret_code = sendcmd(SENSE_CONFIG,
1796 ctlr, sense_config_buf,
1797 sizeof(config_t), 0, 0, log_unit);
1798 if (ret_code == IO_ERROR) {
1799 info_p->log_drv_map = 0;
1800 /* Free all the buffers and return */
1801 printk(KERN_ERR "cpqarray: error sending sense config\n");
1802 kfree(sense_config_buf);
1803 kfree(id_lstatus_buf);
1804 kfree(id_ctlr_buf);
1805 kfree(id_ldrive);
1806 return;
1807
1808 }
1809
1810 sprintf(disk->devfs_name, "ida/c%dd%d", ctlr, log_unit);
1811
1812 info_p->phys_drives =
1813 sense_config_buf->ctlr_phys_drv;
1814 info_p->drv_assign_map
1815 |= sense_config_buf->drv_asgn_map;
1816 info_p->drv_assign_map
1817 |= sense_config_buf->spare_asgn_map;
1818 info_p->drv_spare_map
1819 |= sense_config_buf->spare_asgn_map;
1820 } /* end of if no error on id_ldrive */
1821 log_index = log_index + 1;
1822 } /* end of if logical drive configured */
1823 } /* end of for log_unit */
1824 kfree(sense_config_buf);
1825 kfree(id_ldrive);
1826 kfree(id_lstatus_buf);
1827 kfree(id_ctlr_buf);
1828 return;
1829
1830 }
1831
1832 static void __exit cpqarray_exit(void)
1833 {
1834 int i;
1835
1836 pci_unregister_driver(&cpqarray_pci_driver);
1837
1838 /* Double check that all controller entries have been removed */
1839 for(i=0; i<MAX_CTLR; i++) {
1840 if (hba[i] != NULL) {
1841 printk(KERN_WARNING "cpqarray: Removing EISA "
1842 "controller %d\n", i);
1843 cpqarray_remove_one_eisa(i);
1844 }
1845 }
1846
1847 devfs_remove("ida");
1848 remove_proc_entry("cpqarray", proc_root_driver);
1849 }
1850
1851 module_init(cpqarray_init)
1852 module_exit(cpqarray_exit)
SocketAccessConTroL development