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fix irq flags in mac80211 code
[linux-2.6/sactl.git] / drivers / video / arkfb.c
blob5001bd4ef466331ba9c5498c3cd6fc7e9e4a8e21
1 /*
2 * linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
3 * with ICS 5342 dac (it is easy to add support for different dacs).
4 *
5 * Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * Code is based on s3fb
12 */
13
14 #include <linux/version.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/fb.h>
24 #include <linux/svga.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
28 #include <video/vga.h>
29
30 #ifdef CONFIG_MTRR
31 #include <asm/mtrr.h>
32 #endif
33
34 struct arkfb_info {
35 int mclk_freq;
36 int mtrr_reg;
37
38 struct dac_info *dac;
39 struct vgastate state;
40 struct mutex open_lock;
41 unsigned int ref_count;
42 u32 pseudo_palette[16];
43 };
44
45
46 /* ------------------------------------------------------------------------- */
47
48
49 static const struct svga_fb_format arkfb_formats[] = {
50 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
51 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8},
52 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
54 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
55 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
56 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
58 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
59 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
60 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
62 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
63 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8},
64 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
65 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
66 SVGA_FORMAT_END
67 };
68
69
70 /* CRT timing register sets */
71
72 static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
73 static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
74 static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
75 static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END};
76 static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
77 static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
78
79 static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
80 static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
81 static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
82 // const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END};
83 static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
84 static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
85 static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
86
87 static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
88 static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
89 static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
90
91 static const struct svga_timing_regs ark_timing_regs = {
92 ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
93 ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
94 ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
95 ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
96 };
97
98
99 /* ------------------------------------------------------------------------- */
100
101
102 /* Module parameters */
103
104 static char *mode_option __devinitdata = "640x480-8@60";
105
106 #ifdef CONFIG_MTRR
107 static int mtrr = 1;
108 #endif
109
110 MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>");
111 MODULE_LICENSE("GPL");
112 MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
113
114 module_param(mode_option, charp, 0444);
115 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
116 module_param_named(mode, mode_option, charp, 0444);
117 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
118
119 #ifdef CONFIG_MTRR
120 module_param(mtrr, int, 0444);
121 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
122 #endif
123
124 static int threshold = 4;
125
126 module_param(threshold, int, 0644);
127 MODULE_PARM_DESC(threshold, "FIFO threshold");
128
129
130 /* ------------------------------------------------------------------------- */
131
132
133 static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
134 {
135 const u8 *font = map->data;
136 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
137 int i, c;
138
139 if ((map->width != 8) || (map->height != 16) ||
140 (map->depth != 1) || (map->length != 256)) {
141 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, "
142 "height %d, depth %d, length %d\n", info->node,
143 map->width, map->height, map->depth, map->length);
144 return;
145 }
146
147 fb += 2;
148 for (c = 0; c < map->length; c++) {
149 for (i = 0; i < map->height; i++) {
150 fb_writeb(font[i], &fb[i * 4]);
151 fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
152 }
153 fb += 128;
154
155 if ((c % 8) == 7)
156 fb += 128*8;
157
158 font += map->height;
159 }
160 }
161
162 static struct fb_tile_ops arkfb_tile_ops = {
163 .fb_settile = arkfb_settile,
164 .fb_tilecopy = svga_tilecopy,
165 .fb_tilefill = svga_tilefill,
166 .fb_tileblit = svga_tileblit,
167 .fb_tilecursor = svga_tilecursor,
168 .fb_get_tilemax = svga_get_tilemax,
169 };
170
171
172 /* ------------------------------------------------------------------------- */
173
174
175 /* image data is MSB-first, fb structure is MSB-first too */
176 static inline u32 expand_color(u32 c)
177 {
178 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
179 }
180
181 /* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
182 static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
183 {
184 u32 fg = expand_color(image->fg_color);
185 u32 bg = expand_color(image->bg_color);
186 const u8 *src1, *src;
187 u8 __iomem *dst1;
188 u32 __iomem *dst;
189 u32 val;
190 int x, y;
191
192 src1 = image->data;
193 dst1 = info->screen_base + (image->dy * info->fix.line_length)
194 + ((image->dx / 8) * 4);
195
196 for (y = 0; y < image->height; y++) {
197 src = src1;
198 dst = (u32 __iomem *) dst1;
199 for (x = 0; x < image->width; x += 8) {
200 val = *(src++) * 0x01010101;
201 val = (val & fg) | (~val & bg);
202 fb_writel(val, dst++);
203 }
204 src1 += image->width / 8;
205 dst1 += info->fix.line_length;
206 }
207
208 }
209
210 /* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
211 static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
212 {
213 u32 fg = expand_color(rect->color);
214 u8 __iomem *dst1;
215 u32 __iomem *dst;
216 int x, y;
217
218 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
219 + ((rect->dx / 8) * 4);
220
221 for (y = 0; y < rect->height; y++) {
222 dst = (u32 __iomem *) dst1;
223 for (x = 0; x < rect->width; x += 8) {
224 fb_writel(fg, dst++);
225 }
226 dst1 += info->fix.line_length;
227 }
228
229 }
230
231
232 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
233 static inline u32 expand_pixel(u32 c)
234 {
235 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
236 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
237 }
238
239 /* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
240 static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
241 {
242 u32 fg = image->fg_color * 0x11111111;
243 u32 bg = image->bg_color * 0x11111111;
244 const u8 *src1, *src;
245 u8 __iomem *dst1;
246 u32 __iomem *dst;
247 u32 val;
248 int x, y;
249
250 src1 = image->data;
251 dst1 = info->screen_base + (image->dy * info->fix.line_length)
252 + ((image->dx / 8) * 4);
253
254 for (y = 0; y < image->height; y++) {
255 src = src1;
256 dst = (u32 __iomem *) dst1;
257 for (x = 0; x < image->width; x += 8) {
258 val = expand_pixel(*(src++));
259 val = (val & fg) | (~val & bg);
260 fb_writel(val, dst++);
261 }
262 src1 += image->width / 8;
263 dst1 += info->fix.line_length;
264 }
265
266 }
267
268 static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
269 {
270 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
271 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
272 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
273 arkfb_iplan_imageblit(info, image);
274 else
275 arkfb_cfb4_imageblit(info, image);
276 } else
277 cfb_imageblit(info, image);
278 }
279
280 static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
281 {
282 if ((info->var.bits_per_pixel == 4)
283 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
284 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
285 arkfb_iplan_fillrect(info, rect);
286 else
287 cfb_fillrect(info, rect);
288 }
289
290
291 /* ------------------------------------------------------------------------- */
292
293
294 enum
295 {
296 DAC_PSEUDO8_8,
297 DAC_RGB1555_8,
298 DAC_RGB0565_8,
299 DAC_RGB0888_8,
300 DAC_RGB8888_8,
301 DAC_PSEUDO8_16,
302 DAC_RGB1555_16,
303 DAC_RGB0565_16,
304 DAC_RGB0888_16,
305 DAC_RGB8888_16,
306 DAC_MAX
307 };
308
309 struct dac_ops {
310 int (*dac_get_mode)(struct dac_info *info);
311 int (*dac_set_mode)(struct dac_info *info, int mode);
312 int (*dac_get_freq)(struct dac_info *info, int channel);
313 int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
314 void (*dac_release)(struct dac_info *info);
315 };
316
317 typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
318 typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
319
320 struct dac_info
321 {
322 struct dac_ops *dacops;
323 dac_read_regs_t dac_read_regs;
324 dac_write_regs_t dac_write_regs;
325 void *data;
326 };
327
328
329 static inline u8 dac_read_reg(struct dac_info *info, u8 reg)
330 {
331 u8 code[2] = {reg, 0};
332 info->dac_read_regs(info->data, code, 1);
333 return code[1];
334 }
335
336 static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
337 {
338 info->dac_read_regs(info->data, code, count);
339 }
340
341 static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
342 {
343 u8 code[2] = {reg, val};
344 info->dac_write_regs(info->data, code, 1);
345 }
346
347 static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
348 {
349 info->dac_write_regs(info->data, code, count);
350 }
351
352 static inline int dac_set_mode(struct dac_info *info, int mode)
353 {
354 return info->dacops->dac_set_mode(info, mode);
355 }
356
357 static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
358 {
359 return info->dacops->dac_set_freq(info, channel, freq);
360 }
361
362 static inline void dac_release(struct dac_info *info)
363 {
364 info->dacops->dac_release(info);
365 }
366
367
368 /* ------------------------------------------------------------------------- */
369
370
371 /* ICS5342 DAC */
372
373 struct ics5342_info
374 {
375 struct dac_info dac;
376 u8 mode;
377 };
378
379 #define DAC_PAR(info) ((struct ics5342_info *) info)
380
381 /* LSB is set to distinguish unused slots */
382 static const u8 ics5342_mode_table[DAC_MAX] = {
383 [DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61,
384 [DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
385 [DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
386 };
387
388 static int ics5342_set_mode(struct dac_info *info, int mode)
389 {
390 u8 code;
391
392 if (mode >= DAC_MAX)
393 return -EINVAL;
394
395 code = ics5342_mode_table[mode];
396
397 if (! code)
398 return -EINVAL;
399
400 dac_write_reg(info, 6, code & 0xF0);
401 DAC_PAR(info)->mode = mode;
402
403 return 0;
404 }
405
406 static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
407 60000, 250000, 14318};
408
409 /* pd4 - allow only posdivider 4 (r=2) */
410 static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
411 60000, 335000, 14318};
412
413 /* 270 MHz should be upper bound for VCO clock according to specs,
414 but that is too restrictive in pd4 case */
415
416 static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
417 {
418 u16 m, n, r;
419
420 /* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
421 int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
422 ? &ics5342_pll_pd4 : &ics5342_pll,
423 freq, &m, &n, &r, 0);
424
425 if (rv < 0) {
426 return -EINVAL;
427 } else {
428 u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
429 dac_write_regs(info, code, 3);
430 return 0;
431 }
432 }
433
434 static void ics5342_release(struct dac_info *info)
435 {
436 ics5342_set_mode(info, DAC_PSEUDO8_8);
437 kfree(info);
438 }
439
440 static struct dac_ops ics5342_ops = {
441 .dac_set_mode = ics5342_set_mode,
442 .dac_set_freq = ics5342_set_freq,
443 .dac_release = ics5342_release
444 };
445
446
447 static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
448 {
449 struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL);
450
451 if (! info)
452 return NULL;
453
454 info->dacops = &ics5342_ops;
455 info->dac_read_regs = drr;
456 info->dac_write_regs = dwr;
457 info->data = data;
458 DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
459 return info;
460 }
461
462
463 /* ------------------------------------------------------------------------- */
464
465
466 static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
467
468 static void ark_dac_read_regs(void *data, u8 *code, int count)
469 {
470 u8 regval = vga_rseq(NULL, 0x1C);
471
472 while (count != 0)
473 {
474 vga_wseq(NULL, 0x1C, regval | (code[0] & 4) ? 0x80 : 0);
475 code[1] = vga_r(NULL, dac_regs[code[0] & 3]);
476 count--;
477 code += 2;
478 }
479
480 vga_wseq(NULL, 0x1C, regval);
481 }
482
483 static void ark_dac_write_regs(void *data, u8 *code, int count)
484 {
485 u8 regval = vga_rseq(NULL, 0x1C);
486
487 while (count != 0)
488 {
489 vga_wseq(NULL, 0x1C, regval | (code[0] & 4) ? 0x80 : 0);
490 vga_w(NULL, dac_regs[code[0] & 3], code[1]);
491 count--;
492 code += 2;
493 }
494
495 vga_wseq(NULL, 0x1C, regval);
496 }
497
498
499 static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
500 {
501 struct arkfb_info *par = info->par;
502 u8 regval;
503
504 int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
505 if (rv < 0) {
506 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
507 return;
508 }
509
510 /* Set VGA misc register */
511 regval = vga_r(NULL, VGA_MIS_R);
512 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
513 }
514
515
516 /* Open framebuffer */
517
518 static int arkfb_open(struct fb_info *info, int user)
519 {
520 struct arkfb_info *par = info->par;
521
522 mutex_lock(&(par->open_lock));
523 if (par->ref_count == 0) {
524 memset(&(par->state), 0, sizeof(struct vgastate));
525 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
526 par->state.num_crtc = 0x60;
527 par->state.num_seq = 0x30;
528 save_vga(&(par->state));
529 }
530
531 par->ref_count++;
532 mutex_unlock(&(par->open_lock));
533
534 return 0;
535 }
536
537 /* Close framebuffer */
538
539 static int arkfb_release(struct fb_info *info, int user)
540 {
541 struct arkfb_info *par = info->par;
542
543 mutex_lock(&(par->open_lock));
544 if (par->ref_count == 0) {
545 mutex_unlock(&(par->open_lock));
546 return -EINVAL;
547 }
548
549 if (par->ref_count == 1) {
550 restore_vga(&(par->state));
551 dac_set_mode(par->dac, DAC_PSEUDO8_8);
552 }
553
554 par->ref_count--;
555 mutex_unlock(&(par->open_lock));
556
557 return 0;
558 }
559
560 /* Validate passed in var */
561
562 static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
563 {
564 int rv, mem, step;
565
566 /* Find appropriate format */
567 rv = svga_match_format (arkfb_formats, var, NULL);
568 if (rv < 0)
569 {
570 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
571 return rv;
572 }
573
574 /* Do not allow to have real resoulution larger than virtual */
575 if (var->xres > var->xres_virtual)
576 var->xres_virtual = var->xres;
577
578 if (var->yres > var->yres_virtual)
579 var->yres_virtual = var->yres;
580
581 /* Round up xres_virtual to have proper alignment of lines */
582 step = arkfb_formats[rv].xresstep - 1;
583 var->xres_virtual = (var->xres_virtual+step) & ~step;
584
585
586 /* Check whether have enough memory */
587 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
588 if (mem > info->screen_size)
589 {
590 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
591 return -EINVAL;
592 }
593
594 rv = svga_check_timings (&ark_timing_regs, var, info->node);
595 if (rv < 0)
596 {
597 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
598 return rv;
599 }
600
601 /* Interlaced mode is broken */
602 if (var->vmode & FB_VMODE_INTERLACED)
603 return -EINVAL;
604
605 return 0;
606 }
607
608 /* Set video mode from par */
609
610 static int arkfb_set_par(struct fb_info *info)
611 {
612 struct arkfb_info *par = info->par;
613 u32 value, mode, hmul, hdiv, offset_value, screen_size;
614 u32 bpp = info->var.bits_per_pixel;
615 u8 regval;
616
617 if (bpp != 0) {
618 info->fix.ypanstep = 1;
619 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
620
621 info->flags &= ~FBINFO_MISC_TILEBLITTING;
622 info->tileops = NULL;
623
624 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
625 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
626 info->pixmap.blit_y = ~(u32)0;
627
628 offset_value = (info->var.xres_virtual * bpp) / 64;
629 screen_size = info->var.yres_virtual * info->fix.line_length;
630 } else {
631 info->fix.ypanstep = 16;
632 info->fix.line_length = 0;
633
634 info->flags |= FBINFO_MISC_TILEBLITTING;
635 info->tileops = &arkfb_tile_ops;
636
637 /* supports 8x16 tiles only */
638 info->pixmap.blit_x = 1 << (8 - 1);
639 info->pixmap.blit_y = 1 << (16 - 1);
640
641 offset_value = info->var.xres_virtual / 16;
642 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
643 }
644
645 info->var.xoffset = 0;
646 info->var.yoffset = 0;
647 info->var.activate = FB_ACTIVATE_NOW;
648
649 /* Unlock registers */
650 svga_wcrt_mask(0x11, 0x00, 0x80);
651
652 /* Blank screen and turn off sync */
653 svga_wseq_mask(0x01, 0x20, 0x20);
654 svga_wcrt_mask(0x17, 0x00, 0x80);
655
656 /* Set default values */
657 svga_set_default_gfx_regs();
658 svga_set_default_atc_regs();
659 svga_set_default_seq_regs();
660 svga_set_default_crt_regs();
661 svga_wcrt_multi(ark_line_compare_regs, 0xFFFFFFFF);
662 svga_wcrt_multi(ark_start_address_regs, 0);
663
664 /* ARK specific initialization */
665 svga_wseq_mask(0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
666 svga_wseq_mask(0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
667
668 vga_wseq(NULL, 0x13, info->fix.smem_start >> 16);
669 vga_wseq(NULL, 0x14, info->fix.smem_start >> 24);
670 vga_wseq(NULL, 0x15, 0);
671 vga_wseq(NULL, 0x16, 0);
672
673 /* Set the FIFO threshold register */
674 /* It is fascinating way to store 5-bit value in 8-bit register */
675 regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
676 vga_wseq(NULL, 0x18, regval);
677
678 /* Set the offset register */
679 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
680 svga_wcrt_multi(ark_offset_regs, offset_value);
681
682 /* fix for hi-res textmode */
683 svga_wcrt_mask(0x40, 0x08, 0x08);
684
685 if (info->var.vmode & FB_VMODE_DOUBLE)
686 svga_wcrt_mask(0x09, 0x80, 0x80);
687 else
688 svga_wcrt_mask(0x09, 0x00, 0x80);
689
690 if (info->var.vmode & FB_VMODE_INTERLACED)
691 svga_wcrt_mask(0x44, 0x04, 0x04);
692 else
693 svga_wcrt_mask(0x44, 0x00, 0x04);
694
695 hmul = 1;
696 hdiv = 1;
697 mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
698
699 /* Set mode-specific register values */
700 switch (mode) {
701 case 0:
702 pr_debug("fb%d: text mode\n", info->node);
703 svga_set_textmode_vga_regs();
704
705 vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
706 svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
707 dac_set_mode(par->dac, DAC_PSEUDO8_8);
708
709 break;
710 case 1:
711 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
712 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
713
714 vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
715 svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
716 dac_set_mode(par->dac, DAC_PSEUDO8_8);
717 break;
718 case 2:
719 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
720
721 vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
722 svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
723 dac_set_mode(par->dac, DAC_PSEUDO8_8);
724 break;
725 case 3:
726 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
727
728 vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode */
729
730 if (info->var.pixclock > 20000) {
731 pr_debug("fb%d: not using multiplex\n", info->node);
732 svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
733 dac_set_mode(par->dac, DAC_PSEUDO8_8);
734 } else {
735 pr_debug("fb%d: using multiplex\n", info->node);
736 svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
737 dac_set_mode(par->dac, DAC_PSEUDO8_16);
738 hdiv = 2;
739 }
740 break;
741 case 4:
742 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
743
744 vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */
745 svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
746 dac_set_mode(par->dac, DAC_RGB1555_16);
747 break;
748 case 5:
749 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
750
751 vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */
752 svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
753 dac_set_mode(par->dac, DAC_RGB0565_16);
754 break;
755 case 6:
756 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
757
758 vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode ??? */
759 svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
760 dac_set_mode(par->dac, DAC_RGB0888_16);
761 hmul = 3;
762 hdiv = 2;
763 break;
764 case 7:
765 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
766
767 vga_wseq(NULL, 0x11, 0x1E); /* 32bpp accel mode */
768 svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
769 dac_set_mode(par->dac, DAC_RGB8888_16);
770 hmul = 2;
771 break;
772 default:
773 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
774 return -EINVAL;
775 }
776
777 ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul);
778 svga_set_timings(&ark_timing_regs, &(info->var), hmul, hdiv,
779 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
780 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
781 hmul, info->node);
782
783 /* Set interlaced mode start/end register */
784 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
785 value = ((value * hmul / hdiv) / 8) - 5;
786 vga_wcrt(NULL, 0x42, (value + 1) / 2);
787
788 memset_io(info->screen_base, 0x00, screen_size);
789 /* Device and screen back on */
790 svga_wcrt_mask(0x17, 0x80, 0x80);
791 svga_wseq_mask(0x01, 0x00, 0x20);
792
793 return 0;
794 }
795
796 /* Set a colour register */
797
798 static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
799 u_int transp, struct fb_info *fb)
800 {
801 switch (fb->var.bits_per_pixel) {
802 case 0:
803 case 4:
804 if (regno >= 16)
805 return -EINVAL;
806
807 if ((fb->var.bits_per_pixel == 4) &&
808 (fb->var.nonstd == 0)) {
809 outb(0xF0, VGA_PEL_MSK);
810 outb(regno*16, VGA_PEL_IW);
811 } else {
812 outb(0x0F, VGA_PEL_MSK);
813 outb(regno, VGA_PEL_IW);
814 }
815 outb(red >> 10, VGA_PEL_D);
816 outb(green >> 10, VGA_PEL_D);
817 outb(blue >> 10, VGA_PEL_D);
818 break;
819 case 8:
820 if (regno >= 256)
821 return -EINVAL;
822
823 outb(0xFF, VGA_PEL_MSK);
824 outb(regno, VGA_PEL_IW);
825 outb(red >> 10, VGA_PEL_D);
826 outb(green >> 10, VGA_PEL_D);
827 outb(blue >> 10, VGA_PEL_D);
828 break;
829 case 16:
830 if (regno >= 16)
831 return 0;
832
833 if (fb->var.green.length == 5)
834 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
835 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
836 else if (fb->var.green.length == 6)
837 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
838 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
839 else
840 return -EINVAL;
841 break;
842 case 24:
843 case 32:
844 if (regno >= 16)
845 return 0;
846
847 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
848 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
849 break;
850 default:
851 return -EINVAL;
852 }
853
854 return 0;
855 }
856
857 /* Set the display blanking state */
858
859 static int arkfb_blank(int blank_mode, struct fb_info *info)
860 {
861 switch (blank_mode) {
862 case FB_BLANK_UNBLANK:
863 pr_debug("fb%d: unblank\n", info->node);
864 svga_wseq_mask(0x01, 0x00, 0x20);
865 svga_wcrt_mask(0x17, 0x80, 0x80);
866 break;
867 case FB_BLANK_NORMAL:
868 pr_debug("fb%d: blank\n", info->node);
869 svga_wseq_mask(0x01, 0x20, 0x20);
870 svga_wcrt_mask(0x17, 0x80, 0x80);
871 break;
872 case FB_BLANK_POWERDOWN:
873 case FB_BLANK_HSYNC_SUSPEND:
874 case FB_BLANK_VSYNC_SUSPEND:
875 pr_debug("fb%d: sync down\n", info->node);
876 svga_wseq_mask(0x01, 0x20, 0x20);
877 svga_wcrt_mask(0x17, 0x00, 0x80);
878 break;
879 }
880 return 0;
881 }
882
883
884 /* Pan the display */
885
886 static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
887 {
888 unsigned int offset;
889
890 /* Calculate the offset */
891 if (var->bits_per_pixel == 0) {
892 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
893 offset = offset >> 2;
894 } else {
895 offset = (var->yoffset * info->fix.line_length) +
896 (var->xoffset * var->bits_per_pixel / 8);
897 offset = offset >> ((var->bits_per_pixel == 4) ? 2 : 3);
898 }
899
900 /* Set the offset */
901 svga_wcrt_multi(ark_start_address_regs, offset);
902
903 return 0;
904 }
905
906
907 /* ------------------------------------------------------------------------- */
908
909
910 /* Frame buffer operations */
911
912 static struct fb_ops arkfb_ops = {
913 .owner = THIS_MODULE,
914 .fb_open = arkfb_open,
915 .fb_release = arkfb_release,
916 .fb_check_var = arkfb_check_var,
917 .fb_set_par = arkfb_set_par,
918 .fb_setcolreg = arkfb_setcolreg,
919 .fb_blank = arkfb_blank,
920 .fb_pan_display = arkfb_pan_display,
921 .fb_fillrect = arkfb_fillrect,
922 .fb_copyarea = cfb_copyarea,
923 .fb_imageblit = arkfb_imageblit,
924 .fb_get_caps = svga_get_caps,
925 };
926
927
928 /* ------------------------------------------------------------------------- */
929
930
931 /* PCI probe */
932 static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
933 {
934 struct fb_info *info;
935 struct arkfb_info *par;
936 int rc;
937 u8 regval;
938
939 /* Ignore secondary VGA device because there is no VGA arbitration */
940 if (! svga_primary_device(dev)) {
941 dev_info(&(dev->dev), "ignoring secondary device\n");
942 return -ENODEV;
943 }
944
945 /* Allocate and fill driver data structure */
946 info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev));
947 if (! info) {
948 dev_err(&(dev->dev), "cannot allocate memory\n");
949 return -ENOMEM;
950 }
951
952 par = info->par;
953 mutex_init(&par->open_lock);
954
955 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
956 info->fbops = &arkfb_ops;
957
958 /* Prepare PCI device */
959 rc = pci_enable_device(dev);
960 if (rc < 0) {
961 dev_err(info->dev, "cannot enable PCI device\n");
962 goto err_enable_device;
963 }
964
965 rc = pci_request_regions(dev, "arkfb");
966 if (rc < 0) {
967 dev_err(info->dev, "cannot reserve framebuffer region\n");
968 goto err_request_regions;
969 }
970
971 par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
972 if (! par->dac) {
973 rc = -ENOMEM;
974 dev_err(info->dev, "RAMDAC initialization failed\n");
975 goto err_dac;
976 }
977
978 info->fix.smem_start = pci_resource_start(dev, 0);
979 info->fix.smem_len = pci_resource_len(dev, 0);
980
981 /* Map physical IO memory address into kernel space */
982 info->screen_base = pci_iomap(dev, 0, 0);
983 if (! info->screen_base) {
984 rc = -ENOMEM;
985 dev_err(info->dev, "iomap for framebuffer failed\n");
986 goto err_iomap;
987 }
988
989 /* FIXME get memsize */
990 regval = vga_rseq(NULL, 0x10);
991 info->screen_size = (1 << (regval >> 6)) << 20;
992 info->fix.smem_len = info->screen_size;
993
994 strcpy(info->fix.id, "ARK 2000PV");
995 info->fix.mmio_start = 0;
996 info->fix.mmio_len = 0;
997 info->fix.type = FB_TYPE_PACKED_PIXELS;
998 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
999 info->fix.ypanstep = 0;
1000 info->fix.accel = FB_ACCEL_NONE;
1001 info->pseudo_palette = (void*) (par->pseudo_palette);
1002
1003 /* Prepare startup mode */
1004 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
1005 if (! ((rc == 1) || (rc == 2))) {
1006 rc = -EINVAL;
1007 dev_err(info->dev, "mode %s not found\n", mode_option);
1008 goto err_find_mode;
1009 }
1010
1011 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1012 if (rc < 0) {
1013 dev_err(info->dev, "cannot allocate colormap\n");
1014 goto err_alloc_cmap;
1015 }
1016
1017 rc = register_framebuffer(info);
1018 if (rc < 0) {
1019 dev_err(info->dev, "cannot register framebugger\n");
1020 goto err_reg_fb;
1021 }
1022
1023 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id,
1024 pci_name(dev), info->fix.smem_len >> 20);
1025
1026 /* Record a reference to the driver data */
1027 pci_set_drvdata(dev, info);
1028
1029 #ifdef CONFIG_MTRR
1030 if (mtrr) {
1031 par->mtrr_reg = -1;
1032 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1033 }
1034 #endif
1035
1036 return 0;
1037
1038 /* Error handling */
1039 err_reg_fb:
1040 fb_dealloc_cmap(&info->cmap);
1041 err_alloc_cmap:
1042 err_find_mode:
1043 pci_iounmap(dev, info->screen_base);
1044 err_iomap:
1045 dac_release(par->dac);
1046 err_dac:
1047 pci_release_regions(dev);
1048 err_request_regions:
1049 /* pci_disable_device(dev); */
1050 err_enable_device:
1051 framebuffer_release(info);
1052 return rc;
1053 }
1054
1055 /* PCI remove */
1056
1057 static void __devexit ark_pci_remove(struct pci_dev *dev)
1058 {
1059 struct fb_info *info = pci_get_drvdata(dev);
1060
1061 if (info) {
1062 struct arkfb_info *par = info->par;
1063
1064 #ifdef CONFIG_MTRR
1065 if (par->mtrr_reg >= 0) {
1066 mtrr_del(par->mtrr_reg, 0, 0);
1067 par->mtrr_reg = -1;
1068 }
1069 #endif
1070
1071 dac_release(par->dac);
1072 unregister_framebuffer(info);
1073 fb_dealloc_cmap(&info->cmap);
1074
1075 pci_iounmap(dev, info->screen_base);
1076 pci_release_regions(dev);
1077 /* pci_disable_device(dev); */
1078
1079 pci_set_drvdata(dev, NULL);
1080 framebuffer_release(info);
1081 }
1082 }
1083
1084
1085 #ifdef CONFIG_PM
1086 /* PCI suspend */
1087
1088 static int ark_pci_suspend (struct pci_dev* dev, pm_message_t state)
1089 {
1090 struct fb_info *info = pci_get_drvdata(dev);
1091 struct arkfb_info *par = info->par;
1092
1093 dev_info(info->dev, "suspend\n");
1094
1095 acquire_console_sem();
1096 mutex_lock(&(par->open_lock));
1097
1098 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1099 mutex_unlock(&(par->open_lock));
1100 release_console_sem();
1101 return 0;
1102 }
1103
1104 fb_set_suspend(info, 1);
1105
1106 pci_save_state(dev);
1107 pci_disable_device(dev);
1108 pci_set_power_state(dev, pci_choose_state(dev, state));
1109
1110 mutex_unlock(&(par->open_lock));
1111 release_console_sem();
1112
1113 return 0;
1114 }
1115
1116
1117 /* PCI resume */
1118
1119 static int ark_pci_resume (struct pci_dev* dev)
1120 {
1121 struct fb_info *info = pci_get_drvdata(dev);
1122 struct arkfb_info *par = info->par;
1123
1124 dev_info(info->dev, "resume\n");
1125
1126 acquire_console_sem();
1127 mutex_lock(&(par->open_lock));
1128
1129 if (par->ref_count == 0) {
1130 mutex_unlock(&(par->open_lock));
1131 release_console_sem();
1132 return 0;
1133 }
1134
1135 pci_set_power_state(dev, PCI_D0);
1136 pci_restore_state(dev);
1137
1138 if (pci_enable_device(dev))
1139 goto fail;
1140
1141 pci_set_master(dev);
1142
1143 arkfb_set_par(info);
1144 fb_set_suspend(info, 0);
1145
1146 mutex_unlock(&(par->open_lock));
1147 fail:
1148 release_console_sem();
1149 return 0;
1150 }
1151 #else
1152 #define ark_pci_suspend NULL
1153 #define ark_pci_resume NULL
1154 #endif /* CONFIG_PM */
1155
1156 /* List of boards that we are trying to support */
1157
1158 static struct pci_device_id ark_devices[] __devinitdata = {
1159 {PCI_DEVICE(0xEDD8, 0xA099)},
1160 {0, 0, 0, 0, 0, 0, 0}
1161 };
1162
1163
1164 MODULE_DEVICE_TABLE(pci, ark_devices);
1165
1166 static struct pci_driver arkfb_pci_driver = {
1167 .name = "arkfb",
1168 .id_table = ark_devices,
1169 .probe = ark_pci_probe,
1170 .remove = __devexit_p(ark_pci_remove),
1171 .suspend = ark_pci_suspend,
1172 .resume = ark_pci_resume,
1173 };
1174
1175 /* Cleanup */
1176
1177 static void __exit arkfb_cleanup(void)
1178 {
1179 pr_debug("arkfb: cleaning up\n");
1180 pci_unregister_driver(&arkfb_pci_driver);
1181 }
1182
1183 /* Driver Initialisation */
1184
1185 static int __init arkfb_init(void)
1186 {
1187
1188 #ifndef MODULE
1189 char *option = NULL;
1190
1191 if (fb_get_options("arkfb", &option))
1192 return -ENODEV;
1193
1194 if (option && *option)
1195 mode_option = option;
1196 #endif
1197
1198 pr_debug("arkfb: initializing\n");
1199 return pci_register_driver(&arkfb_pci_driver);
1200 }
1201
1202 module_init(arkfb_init);
1203 module_exit(arkfb_cleanup);
SocketAccessConTroL development