2 * arch/ppc/platforms/85xx/mpc85xx_devices.c
4 * MPC85xx Device descriptions
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
8 * Copyright 2005 Freescale Semiconductor Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/serial_8250.h>
20 #include <linux/fsl_devices.h>
21 #include <asm/mpc85xx.h>
23 #include <asm/ppc_sys.h>
25 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
28 struct gianfar_mdio_data mpc85xx_mdio_pdata
= {
29 .paddr
= MPC85xx_MIIM_OFFSET
,
32 static struct gianfar_platform_data mpc85xx_tsec1_pdata
= {
33 .device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
34 FSL_GIANFAR_DEV_HAS_COALESCE
| FSL_GIANFAR_DEV_HAS_RMON
|
35 FSL_GIANFAR_DEV_HAS_MULTI_INTR
,
38 static struct gianfar_platform_data mpc85xx_tsec2_pdata
= {
39 .device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
40 FSL_GIANFAR_DEV_HAS_COALESCE
| FSL_GIANFAR_DEV_HAS_RMON
|
41 FSL_GIANFAR_DEV_HAS_MULTI_INTR
,
44 static struct gianfar_platform_data mpc85xx_etsec1_pdata
= {
45 .device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
46 FSL_GIANFAR_DEV_HAS_COALESCE
| FSL_GIANFAR_DEV_HAS_RMON
|
47 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
48 FSL_GIANFAR_DEV_HAS_CSUM
| FSL_GIANFAR_DEV_HAS_VLAN
|
49 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
,
52 static struct gianfar_platform_data mpc85xx_etsec2_pdata
= {
53 .device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
54 FSL_GIANFAR_DEV_HAS_COALESCE
| FSL_GIANFAR_DEV_HAS_RMON
|
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
56 FSL_GIANFAR_DEV_HAS_CSUM
| FSL_GIANFAR_DEV_HAS_VLAN
|
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
,
60 static struct gianfar_platform_data mpc85xx_etsec3_pdata
= {
61 .device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
62 FSL_GIANFAR_DEV_HAS_COALESCE
| FSL_GIANFAR_DEV_HAS_RMON
|
63 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
64 FSL_GIANFAR_DEV_HAS_CSUM
| FSL_GIANFAR_DEV_HAS_VLAN
|
65 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
,
68 static struct gianfar_platform_data mpc85xx_etsec4_pdata
= {
69 .device_flags
= FSL_GIANFAR_DEV_HAS_GIGABIT
|
70 FSL_GIANFAR_DEV_HAS_COALESCE
| FSL_GIANFAR_DEV_HAS_RMON
|
71 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
72 FSL_GIANFAR_DEV_HAS_CSUM
| FSL_GIANFAR_DEV_HAS_VLAN
|
73 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
,
76 static struct gianfar_platform_data mpc85xx_fec_pdata
= {
80 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata
= {
81 .device_flags
= FSL_I2C_DEV_SEPARATE_DFSRR
,
84 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata
= {
85 .device_flags
= FSL_I2C_DEV_SEPARATE_DFSRR
,
88 static struct plat_serial8250_port serial_platform_data
[] = {
91 .irq
= MPC85xx_IRQ_DUART
,
93 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_SHARE_IRQ
,
97 .irq
= MPC85xx_IRQ_DUART
,
99 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_SHARE_IRQ
,
104 struct platform_device ppc_sys_platform_devices
[] = {
106 .name
= "fsl-gianfar",
108 .dev
.platform_data
= &mpc85xx_tsec1_pdata
,
110 .resource
= (struct resource
[]) {
112 .start
= MPC85xx_ENET1_OFFSET
,
113 .end
= MPC85xx_ENET1_OFFSET
+
114 MPC85xx_ENET1_SIZE
- 1,
115 .flags
= IORESOURCE_MEM
,
119 .start
= MPC85xx_IRQ_TSEC1_TX
,
120 .end
= MPC85xx_IRQ_TSEC1_TX
,
121 .flags
= IORESOURCE_IRQ
,
125 .start
= MPC85xx_IRQ_TSEC1_RX
,
126 .end
= MPC85xx_IRQ_TSEC1_RX
,
127 .flags
= IORESOURCE_IRQ
,
131 .start
= MPC85xx_IRQ_TSEC1_ERROR
,
132 .end
= MPC85xx_IRQ_TSEC1_ERROR
,
133 .flags
= IORESOURCE_IRQ
,
138 .name
= "fsl-gianfar",
140 .dev
.platform_data
= &mpc85xx_tsec2_pdata
,
142 .resource
= (struct resource
[]) {
144 .start
= MPC85xx_ENET2_OFFSET
,
145 .end
= MPC85xx_ENET2_OFFSET
+
146 MPC85xx_ENET2_SIZE
- 1,
147 .flags
= IORESOURCE_MEM
,
151 .start
= MPC85xx_IRQ_TSEC2_TX
,
152 .end
= MPC85xx_IRQ_TSEC2_TX
,
153 .flags
= IORESOURCE_IRQ
,
157 .start
= MPC85xx_IRQ_TSEC2_RX
,
158 .end
= MPC85xx_IRQ_TSEC2_RX
,
159 .flags
= IORESOURCE_IRQ
,
163 .start
= MPC85xx_IRQ_TSEC2_ERROR
,
164 .end
= MPC85xx_IRQ_TSEC2_ERROR
,
165 .flags
= IORESOURCE_IRQ
,
170 .name
= "fsl-gianfar",
172 .dev
.platform_data
= &mpc85xx_fec_pdata
,
174 .resource
= (struct resource
[]) {
176 .start
= MPC85xx_ENET3_OFFSET
,
177 .end
= MPC85xx_ENET3_OFFSET
+
178 MPC85xx_ENET3_SIZE
- 1,
179 .flags
= IORESOURCE_MEM
,
183 .start
= MPC85xx_IRQ_FEC
,
184 .end
= MPC85xx_IRQ_FEC
,
185 .flags
= IORESOURCE_IRQ
,
192 .dev
.platform_data
= &mpc85xx_fsl_i2c_pdata
,
194 .resource
= (struct resource
[]) {
196 .start
= MPC85xx_IIC1_OFFSET
,
197 .end
= MPC85xx_IIC1_OFFSET
+
198 MPC85xx_IIC1_SIZE
- 1,
199 .flags
= IORESOURCE_MEM
,
202 .start
= MPC85xx_IRQ_IIC1
,
203 .end
= MPC85xx_IRQ_IIC1
,
204 .flags
= IORESOURCE_IRQ
,
212 .resource
= (struct resource
[]) {
214 .start
= MPC85xx_DMA0_OFFSET
,
215 .end
= MPC85xx_DMA0_OFFSET
+
216 MPC85xx_DMA0_SIZE
- 1,
217 .flags
= IORESOURCE_MEM
,
220 .start
= MPC85xx_IRQ_DMA0
,
221 .end
= MPC85xx_IRQ_DMA0
,
222 .flags
= IORESOURCE_IRQ
,
230 .resource
= (struct resource
[]) {
232 .start
= MPC85xx_DMA1_OFFSET
,
233 .end
= MPC85xx_DMA1_OFFSET
+
234 MPC85xx_DMA1_SIZE
- 1,
235 .flags
= IORESOURCE_MEM
,
238 .start
= MPC85xx_IRQ_DMA1
,
239 .end
= MPC85xx_IRQ_DMA1
,
240 .flags
= IORESOURCE_IRQ
,
248 .resource
= (struct resource
[]) {
250 .start
= MPC85xx_DMA2_OFFSET
,
251 .end
= MPC85xx_DMA2_OFFSET
+
252 MPC85xx_DMA2_SIZE
- 1,
253 .flags
= IORESOURCE_MEM
,
256 .start
= MPC85xx_IRQ_DMA2
,
257 .end
= MPC85xx_IRQ_DMA2
,
258 .flags
= IORESOURCE_IRQ
,
266 .resource
= (struct resource
[]) {
268 .start
= MPC85xx_DMA3_OFFSET
,
269 .end
= MPC85xx_DMA3_OFFSET
+
270 MPC85xx_DMA3_SIZE
- 1,
271 .flags
= IORESOURCE_MEM
,
274 .start
= MPC85xx_IRQ_DMA3
,
275 .end
= MPC85xx_IRQ_DMA3
,
276 .flags
= IORESOURCE_IRQ
,
281 .name
= "serial8250",
282 .id
= PLAT8250_DEV_PLATFORM
,
283 .dev
.platform_data
= serial_platform_data
,
285 [MPC85xx_PERFMON
] = {
286 .name
= "fsl-perfmon",
289 .resource
= (struct resource
[]) {
291 .start
= MPC85xx_PERFMON_OFFSET
,
292 .end
= MPC85xx_PERFMON_OFFSET
+
293 MPC85xx_PERFMON_SIZE
- 1,
294 .flags
= IORESOURCE_MEM
,
297 .start
= MPC85xx_IRQ_PERFMON
,
298 .end
= MPC85xx_IRQ_PERFMON
,
299 .flags
= IORESOURCE_IRQ
,
307 .resource
= (struct resource
[]) {
309 .start
= MPC85xx_SEC2_OFFSET
,
310 .end
= MPC85xx_SEC2_OFFSET
+
311 MPC85xx_SEC2_SIZE
- 1,
312 .flags
= IORESOURCE_MEM
,
315 .start
= MPC85xx_IRQ_SEC2
,
316 .end
= MPC85xx_IRQ_SEC2
,
317 .flags
= IORESOURCE_IRQ
,
321 [MPC85xx_CPM_FCC1
] = {
322 .name
= "fsl-cpm-fcc",
325 .resource
= (struct resource
[]) {
329 .flags
= IORESOURCE_MEM
,
334 .flags
= IORESOURCE_MEM
,
337 .start
= SIU_INT_FCC1
,
339 .flags
= IORESOURCE_IRQ
,
343 [MPC85xx_CPM_FCC2
] = {
344 .name
= "fsl-cpm-fcc",
347 .resource
= (struct resource
[]) {
351 .flags
= IORESOURCE_MEM
,
356 .flags
= IORESOURCE_MEM
,
359 .start
= SIU_INT_FCC2
,
361 .flags
= IORESOURCE_IRQ
,
365 [MPC85xx_CPM_FCC3
] = {
366 .name
= "fsl-cpm-fcc",
369 .resource
= (struct resource
[]) {
373 .flags
= IORESOURCE_MEM
,
378 .flags
= IORESOURCE_MEM
,
381 .start
= SIU_INT_FCC3
,
383 .flags
= IORESOURCE_IRQ
,
387 [MPC85xx_CPM_I2C
] = {
388 .name
= "fsl-cpm-i2c",
391 .resource
= (struct resource
[]) {
395 .flags
= IORESOURCE_MEM
,
398 .start
= SIU_INT_I2C
,
400 .flags
= IORESOURCE_IRQ
,
404 [MPC85xx_CPM_SCC1
] = {
405 .name
= "fsl-cpm-scc",
408 .resource
= (struct resource
[]) {
412 .flags
= IORESOURCE_MEM
,
415 .start
= SIU_INT_SCC1
,
417 .flags
= IORESOURCE_IRQ
,
421 [MPC85xx_CPM_SCC2
] = {
422 .name
= "fsl-cpm-scc",
425 .resource
= (struct resource
[]) {
429 .flags
= IORESOURCE_MEM
,
432 .start
= SIU_INT_SCC2
,
434 .flags
= IORESOURCE_IRQ
,
438 [MPC85xx_CPM_SCC3
] = {
439 .name
= "fsl-cpm-scc",
442 .resource
= (struct resource
[]) {
446 .flags
= IORESOURCE_MEM
,
449 .start
= SIU_INT_SCC3
,
451 .flags
= IORESOURCE_IRQ
,
455 [MPC85xx_CPM_SCC4
] = {
456 .name
= "fsl-cpm-scc",
459 .resource
= (struct resource
[]) {
463 .flags
= IORESOURCE_MEM
,
466 .start
= SIU_INT_SCC4
,
468 .flags
= IORESOURCE_IRQ
,
472 [MPC85xx_CPM_SPI
] = {
473 .name
= "fsl-cpm-spi",
476 .resource
= (struct resource
[]) {
480 .flags
= IORESOURCE_MEM
,
483 .start
= SIU_INT_SPI
,
485 .flags
= IORESOURCE_IRQ
,
489 [MPC85xx_CPM_MCC1
] = {
490 .name
= "fsl-cpm-mcc",
493 .resource
= (struct resource
[]) {
497 .flags
= IORESOURCE_MEM
,
500 .start
= SIU_INT_MCC1
,
502 .flags
= IORESOURCE_IRQ
,
506 [MPC85xx_CPM_MCC2
] = {
507 .name
= "fsl-cpm-mcc",
510 .resource
= (struct resource
[]) {
514 .flags
= IORESOURCE_MEM
,
517 .start
= SIU_INT_MCC2
,
519 .flags
= IORESOURCE_IRQ
,
523 [MPC85xx_CPM_SMC1
] = {
524 .name
= "fsl-cpm-smc",
527 .resource
= (struct resource
[]) {
531 .flags
= IORESOURCE_MEM
,
534 .start
= SIU_INT_SMC1
,
536 .flags
= IORESOURCE_IRQ
,
540 [MPC85xx_CPM_SMC2
] = {
541 .name
= "fsl-cpm-smc",
544 .resource
= (struct resource
[]) {
548 .flags
= IORESOURCE_MEM
,
551 .start
= SIU_INT_SMC2
,
553 .flags
= IORESOURCE_IRQ
,
557 [MPC85xx_CPM_USB
] = {
558 .name
= "fsl-cpm-usb",
561 .resource
= (struct resource
[]) {
565 .flags
= IORESOURCE_MEM
,
568 .start
= SIU_INT_USB
,
570 .flags
= IORESOURCE_IRQ
,
575 .name
= "fsl-gianfar",
577 .dev
.platform_data
= &mpc85xx_etsec1_pdata
,
579 .resource
= (struct resource
[]) {
581 .start
= MPC85xx_ENET1_OFFSET
,
582 .end
= MPC85xx_ENET1_OFFSET
+
583 MPC85xx_ENET1_SIZE
- 1,
584 .flags
= IORESOURCE_MEM
,
588 .start
= MPC85xx_IRQ_TSEC1_TX
,
589 .end
= MPC85xx_IRQ_TSEC1_TX
,
590 .flags
= IORESOURCE_IRQ
,
594 .start
= MPC85xx_IRQ_TSEC1_RX
,
595 .end
= MPC85xx_IRQ_TSEC1_RX
,
596 .flags
= IORESOURCE_IRQ
,
600 .start
= MPC85xx_IRQ_TSEC1_ERROR
,
601 .end
= MPC85xx_IRQ_TSEC1_ERROR
,
602 .flags
= IORESOURCE_IRQ
,
607 .name
= "fsl-gianfar",
609 .dev
.platform_data
= &mpc85xx_etsec2_pdata
,
611 .resource
= (struct resource
[]) {
613 .start
= MPC85xx_ENET2_OFFSET
,
614 .end
= MPC85xx_ENET2_OFFSET
+
615 MPC85xx_ENET2_SIZE
- 1,
616 .flags
= IORESOURCE_MEM
,
620 .start
= MPC85xx_IRQ_TSEC2_TX
,
621 .end
= MPC85xx_IRQ_TSEC2_TX
,
622 .flags
= IORESOURCE_IRQ
,
626 .start
= MPC85xx_IRQ_TSEC2_RX
,
627 .end
= MPC85xx_IRQ_TSEC2_RX
,
628 .flags
= IORESOURCE_IRQ
,
632 .start
= MPC85xx_IRQ_TSEC2_ERROR
,
633 .end
= MPC85xx_IRQ_TSEC2_ERROR
,
634 .flags
= IORESOURCE_IRQ
,
639 .name
= "fsl-gianfar",
641 .dev
.platform_data
= &mpc85xx_etsec3_pdata
,
643 .resource
= (struct resource
[]) {
645 .start
= MPC85xx_ENET3_OFFSET
,
646 .end
= MPC85xx_ENET3_OFFSET
+
647 MPC85xx_ENET3_SIZE
- 1,
648 .flags
= IORESOURCE_MEM
,
652 .start
= MPC85xx_IRQ_TSEC3_TX
,
653 .end
= MPC85xx_IRQ_TSEC3_TX
,
654 .flags
= IORESOURCE_IRQ
,
658 .start
= MPC85xx_IRQ_TSEC3_RX
,
659 .end
= MPC85xx_IRQ_TSEC3_RX
,
660 .flags
= IORESOURCE_IRQ
,
664 .start
= MPC85xx_IRQ_TSEC3_ERROR
,
665 .end
= MPC85xx_IRQ_TSEC3_ERROR
,
666 .flags
= IORESOURCE_IRQ
,
671 .name
= "fsl-gianfar",
673 .dev
.platform_data
= &mpc85xx_etsec4_pdata
,
675 .resource
= (struct resource
[]) {
679 .flags
= IORESOURCE_MEM
,
683 .start
= MPC85xx_IRQ_TSEC4_TX
,
684 .end
= MPC85xx_IRQ_TSEC4_TX
,
685 .flags
= IORESOURCE_IRQ
,
689 .start
= MPC85xx_IRQ_TSEC4_RX
,
690 .end
= MPC85xx_IRQ_TSEC4_RX
,
691 .flags
= IORESOURCE_IRQ
,
695 .start
= MPC85xx_IRQ_TSEC4_ERROR
,
696 .end
= MPC85xx_IRQ_TSEC4_ERROR
,
697 .flags
= IORESOURCE_IRQ
,
704 .dev
.platform_data
= &mpc85xx_fsl_i2c2_pdata
,
706 .resource
= (struct resource
[]) {
710 .flags
= IORESOURCE_MEM
,
713 .start
= MPC85xx_IRQ_IIC1
,
714 .end
= MPC85xx_IRQ_IIC1
,
715 .flags
= IORESOURCE_IRQ
,
720 .name
= "fsl-gianfar_mdio",
722 .dev
.platform_data
= &mpc85xx_mdio_pdata
,
727 static int __init
mach_mpc85xx_fixup(struct platform_device
*pdev
)
729 ppc_sys_fixup_mem_resource(pdev
, CCSRBAR
);
733 static int __init
mach_mpc85xx_init(void)
735 ppc_sys_device_fixup
= mach_mpc85xx_fixup
;
739 postcore_initcall(mach_mpc85xx_init
);