1 /******************************************************************************
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <net/mac80211.h>
33 struct iwl_priv
; /* FIXME: remove */
34 #include "iwl-debug.h"
35 #include "iwl-eeprom.h"
36 #include "iwl-dev.h" /* FIXME: remove */
39 #include "iwl-rfkill.h"
40 #include "iwl-power.h"
43 MODULE_DESCRIPTION("iwl core");
44 MODULE_VERSION(IWLWIFI_VERSION
);
45 MODULE_AUTHOR(DRV_COPYRIGHT
);
46 MODULE_LICENSE("GPL");
48 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
69 const struct iwl_rate_info iwl_rates
[IWL_RATE_COUNT
] = {
70 IWL_DECLARE_RATE_INFO(1, INV
, INV
, 2, INV
, 2, INV
, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV
, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV
, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV
, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV
, 48, INV
, 48, INV
),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV
, 48, INV
, 48, INV
),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
85 EXPORT_SYMBOL(iwl_rates
);
88 * translate ucode response to mac80211 tx status control values
90 void iwl_hwrate_to_tx_control(struct iwl_priv
*priv
, u32 rate_n_flags
,
91 struct ieee80211_tx_info
*control
)
95 control
->antenna_sel_tx
=
96 ((rate_n_flags
& RATE_MCS_ANT_ABC_MSK
) >> RATE_MCS_ANT_POS
);
97 if (rate_n_flags
& RATE_MCS_HT_MSK
)
98 control
->flags
|= IEEE80211_TX_CTL_OFDM_HT
;
99 if (rate_n_flags
& RATE_MCS_GF_MSK
)
100 control
->flags
|= IEEE80211_TX_CTL_GREEN_FIELD
;
101 if (rate_n_flags
& RATE_MCS_FAT_MSK
)
102 control
->flags
|= IEEE80211_TX_CTL_40_MHZ_WIDTH
;
103 if (rate_n_flags
& RATE_MCS_DUP_MSK
)
104 control
->flags
|= IEEE80211_TX_CTL_DUP_DATA
;
105 if (rate_n_flags
& RATE_MCS_SGI_MSK
)
106 control
->flags
|= IEEE80211_TX_CTL_SHORT_GI
;
107 rate_index
= iwl_hwrate_to_plcp_idx(rate_n_flags
);
108 if (control
->band
== IEEE80211_BAND_5GHZ
)
109 rate_index
-= IWL_FIRST_OFDM_RATE
;
110 control
->tx_rate_idx
= rate_index
;
112 EXPORT_SYMBOL(iwl_hwrate_to_tx_control
);
114 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags
)
119 if (rate_n_flags
& RATE_MCS_HT_MSK
) {
120 idx
= (rate_n_flags
& 0xff);
122 if (idx
>= IWL_RATE_MIMO2_6M_PLCP
)
123 idx
= idx
- IWL_RATE_MIMO2_6M_PLCP
;
125 idx
+= IWL_FIRST_OFDM_RATE
;
126 /* skip 9M not supported in ht*/
127 if (idx
>= IWL_RATE_9M_INDEX
)
129 if ((idx
>= IWL_FIRST_OFDM_RATE
) && (idx
<= IWL_LAST_OFDM_RATE
))
132 /* legacy rate format, search for match in table */
134 for (idx
= 0; idx
< ARRAY_SIZE(iwl_rates
); idx
++)
135 if (iwl_rates
[idx
].plcp
== (rate_n_flags
& 0xFF))
141 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx
);
145 const u8 iwl_bcast_addr
[ETH_ALEN
] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
146 EXPORT_SYMBOL(iwl_bcast_addr
);
149 /* This function both allocates and initializes hw and priv. */
150 struct ieee80211_hw
*iwl_alloc_all(struct iwl_cfg
*cfg
,
151 struct ieee80211_ops
*hw_ops
)
153 struct iwl_priv
*priv
;
155 /* mac80211 allocates memory for this device instance, including
156 * space for this driver's private structure */
157 struct ieee80211_hw
*hw
=
158 ieee80211_alloc_hw(sizeof(struct iwl_priv
), hw_ops
);
160 IWL_ERROR("Can not allocate network device\n");
170 EXPORT_SYMBOL(iwl_alloc_all
);
172 void iwl_hw_detect(struct iwl_priv
*priv
)
174 priv
->hw_rev
= _iwl_read32(priv
, CSR_HW_REV
);
175 priv
->hw_wa_rev
= _iwl_read32(priv
, CSR_HW_REV_WA_REG
);
176 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &priv
->rev_id
);
178 EXPORT_SYMBOL(iwl_hw_detect
);
180 /* Tell nic where to find the "keep warm" buffer */
181 int iwl_kw_init(struct iwl_priv
*priv
)
186 spin_lock_irqsave(&priv
->lock
, flags
);
187 ret
= iwl_grab_nic_access(priv
);
191 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
,
192 priv
->kw
.dma_addr
>> 4);
193 iwl_release_nic_access(priv
);
195 spin_unlock_irqrestore(&priv
->lock
, flags
);
199 int iwl_kw_alloc(struct iwl_priv
*priv
)
201 struct pci_dev
*dev
= priv
->pci_dev
;
202 struct iwl_kw
*kw
= &priv
->kw
;
204 kw
->size
= IWL_KW_SIZE
;
205 kw
->v_addr
= pci_alloc_consistent(dev
, kw
->size
, &kw
->dma_addr
);
213 * iwl_kw_free - Free the "keep warm" buffer
215 void iwl_kw_free(struct iwl_priv
*priv
)
217 struct pci_dev
*dev
= priv
->pci_dev
;
218 struct iwl_kw
*kw
= &priv
->kw
;
221 pci_free_consistent(dev
, kw
->size
, kw
->v_addr
, kw
->dma_addr
);
222 memset(kw
, 0, sizeof(*kw
));
226 int iwl_hw_nic_init(struct iwl_priv
*priv
)
229 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
233 spin_lock_irqsave(&priv
->lock
, flags
);
234 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
235 iwl_write32(priv
, CSR_INT_COALESCING
, 512 / 32);
236 spin_unlock_irqrestore(&priv
->lock
, flags
);
238 ret
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
240 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
242 /* Allocate the RX queue, or reset if it is already allocated */
244 ret
= iwl_rx_queue_alloc(priv
);
246 IWL_ERROR("Unable to initialize Rx queue\n");
250 iwl_rx_queue_reset(priv
, rxq
);
252 iwl_rx_replenish(priv
);
254 iwl_rx_init(priv
, rxq
);
256 spin_lock_irqsave(&priv
->lock
, flags
);
258 rxq
->need_update
= 1;
259 iwl_rx_queue_update_write_ptr(priv
, rxq
);
261 spin_unlock_irqrestore(&priv
->lock
, flags
);
263 /* Allocate and init all Tx and Command queues */
264 ret
= iwl_txq_ctx_reset(priv
);
268 set_bit(STATUS_INIT
, &priv
->status
);
272 EXPORT_SYMBOL(iwl_hw_nic_init
);
275 * iwl_clear_stations_table - Clear the driver's station table
277 * NOTE: This does not clear or otherwise alter the device's station table.
279 void iwl_clear_stations_table(struct iwl_priv
*priv
)
283 spin_lock_irqsave(&priv
->sta_lock
, flags
);
285 if (iwl_is_alive(priv
) &&
286 !test_bit(STATUS_EXIT_PENDING
, &priv
->status
) &&
287 iwl_send_cmd_pdu_async(priv
, REPLY_REMOVE_ALL_STA
, 0, NULL
, NULL
))
288 IWL_ERROR("Couldn't clear the station table\n");
290 priv
->num_stations
= 0;
291 memset(priv
->stations
, 0, sizeof(priv
->stations
));
293 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
295 EXPORT_SYMBOL(iwl_clear_stations_table
);
297 void iwl_reset_qos(struct iwl_priv
*priv
)
306 spin_lock_irqsave(&priv
->lock
, flags
);
307 priv
->qos_data
.qos_active
= 0;
309 if (priv
->iw_mode
== NL80211_IFTYPE_ADHOC
) {
310 if (priv
->qos_data
.qos_enable
)
311 priv
->qos_data
.qos_active
= 1;
312 if (!(priv
->active_rate
& 0xfff0)) {
316 } else if (priv
->iw_mode
== NL80211_IFTYPE_AP
) {
317 if (priv
->qos_data
.qos_enable
)
318 priv
->qos_data
.qos_active
= 1;
319 } else if (!(priv
->staging_rxon
.flags
& RXON_FLG_SHORT_SLOT_MSK
)) {
324 if (priv
->qos_data
.qos_active
)
327 priv
->qos_data
.def_qos_parm
.ac
[0].cw_min
= cpu_to_le16(cw_min
);
328 priv
->qos_data
.def_qos_parm
.ac
[0].cw_max
= cpu_to_le16(cw_max
);
329 priv
->qos_data
.def_qos_parm
.ac
[0].aifsn
= aifs
;
330 priv
->qos_data
.def_qos_parm
.ac
[0].edca_txop
= 0;
331 priv
->qos_data
.def_qos_parm
.ac
[0].reserved1
= 0;
333 if (priv
->qos_data
.qos_active
) {
335 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
= cpu_to_le16(cw_min
);
336 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
= cpu_to_le16(cw_max
);
337 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 7;
338 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
= 0;
339 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
342 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
343 cpu_to_le16((cw_min
+ 1) / 2 - 1);
344 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
346 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 2;
348 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
351 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
353 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
356 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
357 cpu_to_le16((cw_min
+ 1) / 4 - 1);
358 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
359 cpu_to_le16((cw_max
+ 1) / 2 - 1);
360 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= 2;
361 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
363 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
366 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
=
369 for (i
= 1; i
< 4; i
++) {
370 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_min
=
372 priv
->qos_data
.def_qos_parm
.ac
[i
].cw_max
=
374 priv
->qos_data
.def_qos_parm
.ac
[i
].aifsn
= aifs
;
375 priv
->qos_data
.def_qos_parm
.ac
[i
].edca_txop
= 0;
376 priv
->qos_data
.def_qos_parm
.ac
[i
].reserved1
= 0;
379 IWL_DEBUG_QOS("set QoS to default \n");
381 spin_unlock_irqrestore(&priv
->lock
, flags
);
383 EXPORT_SYMBOL(iwl_reset_qos
);
385 #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
386 #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
387 static void iwlcore_init_ht_hw_capab(const struct iwl_priv
*priv
,
388 struct ieee80211_sta_ht_cap
*ht_info
,
389 enum ieee80211_band band
)
391 u16 max_bit_rate
= 0;
392 u8 rx_chains_num
= priv
->hw_params
.rx_chains_num
;
393 u8 tx_chains_num
= priv
->hw_params
.tx_chains_num
;
396 memset(&ht_info
->mcs
, 0, sizeof(ht_info
->mcs
));
398 ht_info
->ht_supported
= true;
400 ht_info
->cap
|= IEEE80211_HT_CAP_GRN_FLD
;
401 ht_info
->cap
|= IEEE80211_HT_CAP_SGI_20
;
402 ht_info
->cap
|= (IEEE80211_HT_CAP_SM_PS
&
403 (WLAN_HT_CAP_SM_PS_DISABLED
<< 2));
405 max_bit_rate
= MAX_BIT_RATE_20_MHZ
;
406 if (priv
->hw_params
.fat_channel
& BIT(band
)) {
407 ht_info
->cap
|= IEEE80211_HT_CAP_SUP_WIDTH_20_40
;
408 ht_info
->cap
|= IEEE80211_HT_CAP_SGI_40
;
409 ht_info
->mcs
.rx_mask
[4] = 0x01;
410 max_bit_rate
= MAX_BIT_RATE_40_MHZ
;
413 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
414 ht_info
->cap
|= IEEE80211_HT_CAP_MAX_AMSDU
;
416 ht_info
->ampdu_factor
= CFG_HT_RX_AMPDU_FACTOR_DEF
;
417 ht_info
->ampdu_density
= CFG_HT_MPDU_DENSITY_DEF
;
419 ht_info
->mcs
.rx_mask
[0] = 0xFF;
420 if (rx_chains_num
>= 2)
421 ht_info
->mcs
.rx_mask
[1] = 0xFF;
422 if (rx_chains_num
>= 3)
423 ht_info
->mcs
.rx_mask
[2] = 0xFF;
425 /* Highest supported Rx data rate */
426 max_bit_rate
*= rx_chains_num
;
427 WARN_ON(max_bit_rate
& ~IEEE80211_HT_MCS_RX_HIGHEST_MASK
);
428 ht_info
->mcs
.rx_highest
= cpu_to_le16(max_bit_rate
);
430 /* Tx MCS capabilities */
431 ht_info
->mcs
.tx_params
= IEEE80211_HT_MCS_TX_DEFINED
;
432 if (tx_chains_num
!= rx_chains_num
) {
433 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_RX_DIFF
;
434 ht_info
->mcs
.tx_params
|= ((tx_chains_num
- 1) <<
435 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
439 static void iwlcore_init_hw_rates(struct iwl_priv
*priv
,
440 struct ieee80211_rate
*rates
)
444 for (i
= 0; i
< IWL_RATE_COUNT
; i
++) {
445 rates
[i
].bitrate
= iwl_rates
[i
].ieee
* 5;
446 rates
[i
].hw_value
= i
; /* Rate scaling will work on indexes */
447 rates
[i
].hw_value_short
= i
;
449 if ((i
> IWL_LAST_OFDM_RATE
) || (i
< IWL_FIRST_OFDM_RATE
)) {
451 * If CCK != 1M then set short preamble rate flag.
454 (iwl_rates
[i
].plcp
== IWL_RATE_1M_PLCP
) ?
455 0 : IEEE80211_RATE_SHORT_PREAMBLE
;
461 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
463 static int iwlcore_init_geos(struct iwl_priv
*priv
)
465 struct iwl_channel_info
*ch
;
466 struct ieee80211_supported_band
*sband
;
467 struct ieee80211_channel
*channels
;
468 struct ieee80211_channel
*geo_ch
;
469 struct ieee80211_rate
*rates
;
472 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_bitrates
||
473 priv
->bands
[IEEE80211_BAND_5GHZ
].n_bitrates
) {
474 IWL_DEBUG_INFO("Geography modes already initialized.\n");
475 set_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
479 channels
= kzalloc(sizeof(struct ieee80211_channel
) *
480 priv
->channel_count
, GFP_KERNEL
);
484 rates
= kzalloc((sizeof(struct ieee80211_rate
) * (IWL_RATE_COUNT
+ 1)),
491 /* 5.2GHz channels start after the 2.4GHz channels */
492 sband
= &priv
->bands
[IEEE80211_BAND_5GHZ
];
493 sband
->channels
= &channels
[ARRAY_SIZE(iwl_eeprom_band_1
)];
495 sband
->bitrates
= &rates
[IWL_FIRST_OFDM_RATE
];
496 sband
->n_bitrates
= IWL_RATE_COUNT
- IWL_FIRST_OFDM_RATE
;
498 if (priv
->cfg
->sku
& IWL_SKU_N
)
499 iwlcore_init_ht_hw_capab(priv
, &sband
->ht_cap
,
500 IEEE80211_BAND_5GHZ
);
502 sband
= &priv
->bands
[IEEE80211_BAND_2GHZ
];
503 sband
->channels
= channels
;
505 sband
->bitrates
= rates
;
506 sband
->n_bitrates
= IWL_RATE_COUNT
;
508 if (priv
->cfg
->sku
& IWL_SKU_N
)
509 iwlcore_init_ht_hw_capab(priv
, &sband
->ht_cap
,
510 IEEE80211_BAND_2GHZ
);
512 priv
->ieee_channels
= channels
;
513 priv
->ieee_rates
= rates
;
515 iwlcore_init_hw_rates(priv
, rates
);
517 for (i
= 0; i
< priv
->channel_count
; i
++) {
518 ch
= &priv
->channel_info
[i
];
520 /* FIXME: might be removed if scan is OK */
521 if (!is_channel_valid(ch
))
524 if (is_channel_a_band(ch
))
525 sband
= &priv
->bands
[IEEE80211_BAND_5GHZ
];
527 sband
= &priv
->bands
[IEEE80211_BAND_2GHZ
];
529 geo_ch
= &sband
->channels
[sband
->n_channels
++];
531 geo_ch
->center_freq
=
532 ieee80211_channel_to_frequency(ch
->channel
);
533 geo_ch
->max_power
= ch
->max_power_avg
;
534 geo_ch
->max_antenna_gain
= 0xff;
535 geo_ch
->hw_value
= ch
->channel
;
537 if (is_channel_valid(ch
)) {
538 if (!(ch
->flags
& EEPROM_CHANNEL_IBSS
))
539 geo_ch
->flags
|= IEEE80211_CHAN_NO_IBSS
;
541 if (!(ch
->flags
& EEPROM_CHANNEL_ACTIVE
))
542 geo_ch
->flags
|= IEEE80211_CHAN_PASSIVE_SCAN
;
544 if (ch
->flags
& EEPROM_CHANNEL_RADAR
)
545 geo_ch
->flags
|= IEEE80211_CHAN_RADAR
;
547 geo_ch
->flags
|= ch
->fat_extension_channel
;
549 if (ch
->max_power_avg
> priv
->tx_power_channel_lmt
)
550 priv
->tx_power_channel_lmt
= ch
->max_power_avg
;
552 geo_ch
->flags
|= IEEE80211_CHAN_DISABLED
;
555 /* Save flags for reg domain usage */
556 geo_ch
->orig_flags
= geo_ch
->flags
;
558 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
559 ch
->channel
, geo_ch
->center_freq
,
560 is_channel_a_band(ch
) ? "5.2" : "2.4",
561 geo_ch
->flags
& IEEE80211_CHAN_DISABLED
?
562 "restricted" : "valid",
566 if ((priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
== 0) &&
567 priv
->cfg
->sku
& IWL_SKU_A
) {
568 printk(KERN_INFO DRV_NAME
569 ": Incorrectly detected BG card as ABG. Please send "
570 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
571 priv
->pci_dev
->device
, priv
->pci_dev
->subsystem_device
);
572 priv
->cfg
->sku
&= ~IWL_SKU_A
;
575 printk(KERN_INFO DRV_NAME
576 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
577 priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
,
578 priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
);
581 set_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
587 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
589 static void iwlcore_free_geos(struct iwl_priv
*priv
)
591 kfree(priv
->ieee_channels
);
592 kfree(priv
->ieee_rates
);
593 clear_bit(STATUS_GEO_CONFIGURED
, &priv
->status
);
596 static bool is_single_rx_stream(struct iwl_priv
*priv
)
598 return !priv
->current_ht_config
.is_ht
||
599 ((priv
->current_ht_config
.mcs
.rx_mask
[1] == 0) &&
600 (priv
->current_ht_config
.mcs
.rx_mask
[2] == 0));
603 static u8
iwl_is_channel_extension(struct iwl_priv
*priv
,
604 enum ieee80211_band band
,
605 u16 channel
, u8 extension_chan_offset
)
607 const struct iwl_channel_info
*ch_info
;
609 ch_info
= iwl_get_channel_info(priv
, band
, channel
);
610 if (!is_channel_valid(ch_info
))
613 if (extension_chan_offset
== IEEE80211_HT_PARAM_CHA_SEC_ABOVE
)
614 return !(ch_info
->fat_extension_channel
&
615 IEEE80211_CHAN_NO_FAT_ABOVE
);
616 else if (extension_chan_offset
== IEEE80211_HT_PARAM_CHA_SEC_BELOW
)
617 return !(ch_info
->fat_extension_channel
&
618 IEEE80211_CHAN_NO_FAT_BELOW
);
623 u8
iwl_is_fat_tx_allowed(struct iwl_priv
*priv
,
624 struct ieee80211_sta_ht_cap
*sta_ht_inf
)
626 struct iwl_ht_info
*iwl_ht_conf
= &priv
->current_ht_config
;
628 if ((!iwl_ht_conf
->is_ht
) ||
629 (iwl_ht_conf
->supported_chan_width
!= IWL_CHANNEL_WIDTH_40MHZ
) ||
630 (iwl_ht_conf
->extension_chan_offset
== IEEE80211_HT_PARAM_CHA_SEC_NONE
))
634 if ((!sta_ht_inf
->ht_supported
) ||
635 (!(sta_ht_inf
->cap
& IEEE80211_HT_CAP_SUP_WIDTH_20_40
)))
639 return iwl_is_channel_extension(priv
, priv
->band
,
640 le16_to_cpu(priv
->staging_rxon
.channel
),
641 iwl_ht_conf
->extension_chan_offset
);
643 EXPORT_SYMBOL(iwl_is_fat_tx_allowed
);
645 void iwl_set_rxon_ht(struct iwl_priv
*priv
, struct iwl_ht_info
*ht_info
)
647 struct iwl_rxon_cmd
*rxon
= &priv
->staging_rxon
;
650 if (!ht_info
->is_ht
) {
651 rxon
->flags
&= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK
|
652 RXON_FLG_CHANNEL_MODE_PURE_40_MSK
|
653 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
|
654 RXON_FLG_FAT_PROT_MSK
|
655 RXON_FLG_HT_PROT_MSK
);
659 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
660 if (iwl_is_fat_tx_allowed(priv
, NULL
))
661 rxon
->flags
|= RXON_FLG_CHANNEL_MODE_MIXED_MSK
;
663 rxon
->flags
&= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK
|
664 RXON_FLG_CHANNEL_MODE_PURE_40_MSK
);
666 /* Note: control channel is opposite of extension channel */
667 switch (ht_info
->extension_chan_offset
) {
668 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE
:
669 rxon
->flags
&= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
);
671 case IEEE80211_HT_PARAM_CHA_SEC_BELOW
:
672 rxon
->flags
|= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
;
674 case IEEE80211_HT_PARAM_CHA_SEC_NONE
:
676 rxon
->flags
&= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK
;
680 val
= ht_info
->ht_protection
;
682 rxon
->flags
|= cpu_to_le32(val
<< RXON_FLG_HT_OPERATING_MODE_POS
);
684 iwl_set_rxon_chain(priv
);
686 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
687 "rxon flags 0x%X operation mode :0x%X "
688 "extension channel offset 0x%x\n",
689 ht_info
->mcs
.rx_mask
[0],
690 ht_info
->mcs
.rx_mask
[1],
691 ht_info
->mcs
.rx_mask
[2],
692 le32_to_cpu(rxon
->flags
), ht_info
->ht_protection
,
693 ht_info
->extension_chan_offset
);
696 EXPORT_SYMBOL(iwl_set_rxon_ht
);
698 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
699 #define IWL_NUM_RX_CHAINS_SINGLE 2
700 #define IWL_NUM_IDLE_CHAINS_DUAL 2
701 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
703 /* Determine how many receiver/antenna chains to use.
704 * More provides better reception via diversity. Fewer saves power.
705 * MIMO (dual stream) requires at least 2, but works better with 3.
706 * This does not determine *which* chains to use, just how many.
708 static int iwl_get_active_rx_chain_count(struct iwl_priv
*priv
)
710 bool is_single
= is_single_rx_stream(priv
);
711 bool is_cam
= !test_bit(STATUS_POWER_PMI
, &priv
->status
);
713 /* # of Rx chains to use when expecting MIMO. */
714 if (is_single
|| (!is_cam
&& (priv
->current_ht_config
.sm_ps
==
715 WLAN_HT_CAP_SM_PS_STATIC
)))
716 return IWL_NUM_RX_CHAINS_SINGLE
;
718 return IWL_NUM_RX_CHAINS_MULTIPLE
;
721 static int iwl_get_idle_rx_chain_count(struct iwl_priv
*priv
, int active_cnt
)
724 bool is_cam
= !test_bit(STATUS_POWER_PMI
, &priv
->status
);
725 /* # Rx chains when idling and maybe trying to save power */
726 switch (priv
->current_ht_config
.sm_ps
) {
727 case WLAN_HT_CAP_SM_PS_STATIC
:
728 case WLAN_HT_CAP_SM_PS_DYNAMIC
:
729 idle_cnt
= (is_cam
) ? IWL_NUM_IDLE_CHAINS_DUAL
:
730 IWL_NUM_IDLE_CHAINS_SINGLE
;
732 case WLAN_HT_CAP_SM_PS_DISABLED
:
733 idle_cnt
= (is_cam
) ? active_cnt
: IWL_NUM_IDLE_CHAINS_SINGLE
;
735 case WLAN_HT_CAP_SM_PS_INVALID
:
737 IWL_ERROR("invalide mimo ps mode %d\n",
738 priv
->current_ht_config
.sm_ps
);
747 static u8
iwl_count_chain_bitmap(u32 chain_bitmap
)
750 res
= (chain_bitmap
& BIT(0)) >> 0;
751 res
+= (chain_bitmap
& BIT(1)) >> 1;
752 res
+= (chain_bitmap
& BIT(2)) >> 2;
753 res
+= (chain_bitmap
& BIT(4)) >> 4;
758 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
760 * Selects how many and which Rx receivers/antennas/chains to use.
761 * This should not be used for scan command ... it puts data in wrong place.
763 void iwl_set_rxon_chain(struct iwl_priv
*priv
)
765 bool is_single
= is_single_rx_stream(priv
);
766 bool is_cam
= !test_bit(STATUS_POWER_PMI
, &priv
->status
);
767 u8 idle_rx_cnt
, active_rx_cnt
, valid_rx_cnt
;
771 /* Tell uCode which antennas are actually connected.
772 * Before first association, we assume all antennas are connected.
773 * Just after first association, iwl_chain_noise_calibration()
774 * checks which antennas actually *are* connected. */
775 if (priv
->chain_noise_data
.active_chains
)
776 active_chains
= priv
->chain_noise_data
.active_chains
;
778 active_chains
= priv
->hw_params
.valid_rx_ant
;
780 rx_chain
= active_chains
<< RXON_RX_CHAIN_VALID_POS
;
782 /* How many receivers should we use? */
783 active_rx_cnt
= iwl_get_active_rx_chain_count(priv
);
784 idle_rx_cnt
= iwl_get_idle_rx_chain_count(priv
, active_rx_cnt
);
787 /* correct rx chain count according hw settings
788 * and chain noise calibration
790 valid_rx_cnt
= iwl_count_chain_bitmap(active_chains
);
791 if (valid_rx_cnt
< active_rx_cnt
)
792 active_rx_cnt
= valid_rx_cnt
;
794 if (valid_rx_cnt
< idle_rx_cnt
)
795 idle_rx_cnt
= valid_rx_cnt
;
797 rx_chain
|= active_rx_cnt
<< RXON_RX_CHAIN_MIMO_CNT_POS
;
798 rx_chain
|= idle_rx_cnt
<< RXON_RX_CHAIN_CNT_POS
;
800 priv
->staging_rxon
.rx_chain
= cpu_to_le16(rx_chain
);
802 if (!is_single
&& (active_rx_cnt
>= IWL_NUM_RX_CHAINS_SINGLE
) && is_cam
)
803 priv
->staging_rxon
.rx_chain
|= RXON_RX_CHAIN_MIMO_FORCE_MSK
;
805 priv
->staging_rxon
.rx_chain
&= ~RXON_RX_CHAIN_MIMO_FORCE_MSK
;
807 IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
808 priv
->staging_rxon
.rx_chain
,
809 active_rx_cnt
, idle_rx_cnt
);
811 WARN_ON(active_rx_cnt
== 0 || idle_rx_cnt
== 0 ||
812 active_rx_cnt
< idle_rx_cnt
);
814 EXPORT_SYMBOL(iwl_set_rxon_chain
);
817 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
818 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
819 * @channel: Any channel valid for the requested phymode
821 * In addition to setting the staging RXON, priv->phymode is also set.
823 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
824 * in the staging RXON flag structure based on the phymode
826 int iwl_set_rxon_channel(struct iwl_priv
*priv
, struct ieee80211_channel
*ch
)
828 enum ieee80211_band band
= ch
->band
;
829 u16 channel
= ieee80211_frequency_to_channel(ch
->center_freq
);
831 if (!iwl_get_channel_info(priv
, band
, channel
)) {
832 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
837 if ((le16_to_cpu(priv
->staging_rxon
.channel
) == channel
) &&
838 (priv
->band
== band
))
841 priv
->staging_rxon
.channel
= cpu_to_le16(channel
);
842 if (band
== IEEE80211_BAND_5GHZ
)
843 priv
->staging_rxon
.flags
&= ~RXON_FLG_BAND_24G_MSK
;
845 priv
->staging_rxon
.flags
|= RXON_FLG_BAND_24G_MSK
;
849 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel
, band
);
853 EXPORT_SYMBOL(iwl_set_rxon_channel
);
855 int iwl_setup_mac(struct iwl_priv
*priv
)
858 struct ieee80211_hw
*hw
= priv
->hw
;
859 hw
->rate_control_algorithm
= "iwl-agn-rs";
861 /* Tell mac80211 our characteristics */
862 hw
->flags
= IEEE80211_HW_SIGNAL_DBM
|
863 IEEE80211_HW_NOISE_DBM
;
864 hw
->wiphy
->interface_modes
=
865 BIT(NL80211_IFTYPE_AP
) |
866 BIT(NL80211_IFTYPE_STATION
) |
867 BIT(NL80211_IFTYPE_ADHOC
);
868 /* Default value; 4 EDCA QOS priorities */
870 /* queues to support 11n aggregation */
871 if (priv
->cfg
->sku
& IWL_SKU_N
)
872 hw
->ampdu_queues
= priv
->cfg
->mod_params
->num_of_ampdu_queues
;
874 hw
->conf
.beacon_int
= 100;
875 hw
->max_listen_interval
= IWL_CONN_MAX_LISTEN_INTERVAL
;
877 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
)
878 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
879 &priv
->bands
[IEEE80211_BAND_2GHZ
];
880 if (priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
)
881 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
882 &priv
->bands
[IEEE80211_BAND_5GHZ
];
884 ret
= ieee80211_register_hw(priv
->hw
);
886 IWL_ERROR("Failed to register hw (error %d)\n", ret
);
889 priv
->mac80211_registered
= 1;
893 EXPORT_SYMBOL(iwl_setup_mac
);
895 int iwl_set_hw_params(struct iwl_priv
*priv
)
897 priv
->hw_params
.sw_crypto
= priv
->cfg
->mod_params
->sw_crypto
;
898 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
899 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
900 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
901 priv
->hw_params
.rx_buf_size
= IWL_RX_BUF_SIZE_8K
;
903 priv
->hw_params
.rx_buf_size
= IWL_RX_BUF_SIZE_4K
;
904 priv
->hw_params
.max_pkt_size
= priv
->hw_params
.rx_buf_size
- 256;
906 if (priv
->cfg
->mod_params
->disable_11n
)
907 priv
->cfg
->sku
&= ~IWL_SKU_N
;
909 /* Device-specific setup */
910 return priv
->cfg
->ops
->lib
->set_hw_params(priv
);
912 EXPORT_SYMBOL(iwl_set_hw_params
);
914 int iwl_init_drv(struct iwl_priv
*priv
)
918 priv
->retry_rate
= 1;
919 priv
->ibss_beacon
= NULL
;
921 spin_lock_init(&priv
->lock
);
922 spin_lock_init(&priv
->power_data
.lock
);
923 spin_lock_init(&priv
->sta_lock
);
924 spin_lock_init(&priv
->hcmd_lock
);
926 INIT_LIST_HEAD(&priv
->free_frames
);
928 mutex_init(&priv
->mutex
);
930 /* Clear the driver's (not device's) station table */
931 iwl_clear_stations_table(priv
);
933 priv
->data_retry_limit
= -1;
934 priv
->ieee_channels
= NULL
;
935 priv
->ieee_rates
= NULL
;
936 priv
->band
= IEEE80211_BAND_2GHZ
;
938 priv
->iw_mode
= NL80211_IFTYPE_STATION
;
940 priv
->use_ant_b_for_management_frame
= 1; /* start with ant B */
941 priv
->current_ht_config
.sm_ps
= WLAN_HT_CAP_SM_PS_DISABLED
;
943 /* Choose which receivers/antennas to use */
944 iwl_set_rxon_chain(priv
);
945 iwl_init_scan_params(priv
);
947 if (priv
->cfg
->mod_params
->enable_qos
)
948 priv
->qos_data
.qos_enable
= 1;
952 priv
->qos_data
.qos_active
= 0;
953 priv
->qos_data
.qos_cap
.val
= 0;
955 priv
->rates_mask
= IWL_RATES_MASK
;
956 /* If power management is turned on, default to AC mode */
957 priv
->power_mode
= IWL_POWER_AC
;
958 priv
->tx_power_user_lmt
= IWL_TX_POWER_TARGET_POWER_MAX
;
960 ret
= iwl_init_channel_map(priv
);
962 IWL_ERROR("initializing regulatory failed: %d\n", ret
);
966 ret
= iwlcore_init_geos(priv
);
968 IWL_ERROR("initializing geos failed: %d\n", ret
);
969 goto err_free_channel_map
;
974 err_free_channel_map
:
975 iwl_free_channel_map(priv
);
979 EXPORT_SYMBOL(iwl_init_drv
);
981 int iwl_set_tx_power(struct iwl_priv
*priv
, s8 tx_power
, bool force
)
984 if (tx_power
< IWL_TX_POWER_TARGET_POWER_MIN
) {
985 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
986 priv
->tx_power_user_lmt
);
990 if (tx_power
> IWL_TX_POWER_TARGET_POWER_MAX
) {
991 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
992 priv
->tx_power_user_lmt
);
996 if (priv
->tx_power_user_lmt
!= tx_power
)
999 priv
->tx_power_user_lmt
= tx_power
;
1001 if (force
&& priv
->cfg
->ops
->lib
->send_tx_power
)
1002 ret
= priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1006 EXPORT_SYMBOL(iwl_set_tx_power
);
1008 void iwl_uninit_drv(struct iwl_priv
*priv
)
1010 iwl_calib_free_results(priv
);
1011 iwlcore_free_geos(priv
);
1012 iwl_free_channel_map(priv
);
1015 EXPORT_SYMBOL(iwl_uninit_drv
);
1017 int iwl_send_statistics_request(struct iwl_priv
*priv
, u8 flags
)
1020 struct iwl_host_cmd cmd
= {
1021 .id
= REPLY_STATISTICS_CMD
,
1022 .meta
.flags
= flags
,
1023 .len
= sizeof(stat_flags
),
1024 .data
= (u8
*) &stat_flags
,
1026 return iwl_send_cmd(priv
, &cmd
);
1028 EXPORT_SYMBOL(iwl_send_statistics_request
);
1031 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1032 * using sample data 100 bytes apart. If these sample points are good,
1033 * it's a pretty good bet that everything between them is good, too.
1035 static int iwlcore_verify_inst_sparse(struct iwl_priv
*priv
, __le32
*image
, u32 len
)
1042 IWL_DEBUG_INFO("ucode inst image size is %u\n", len
);
1044 ret
= iwl_grab_nic_access(priv
);
1048 for (i
= 0; i
< len
; i
+= 100, image
+= 100/sizeof(u32
)) {
1049 /* read data comes through single port, auto-incr addr */
1050 /* NOTE: Use the debugless read so we don't flood kernel log
1051 * if IWL_DL_IO is set */
1052 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
,
1053 i
+ RTC_INST_LOWER_BOUND
);
1054 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
1055 if (val
!= le32_to_cpu(*image
)) {
1063 iwl_release_nic_access(priv
);
1069 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1070 * looking at all data.
1072 static int iwl_verify_inst_full(struct iwl_priv
*priv
, __le32
*image
,
1080 IWL_DEBUG_INFO("ucode inst image size is %u\n", len
);
1082 ret
= iwl_grab_nic_access(priv
);
1086 iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
, RTC_INST_LOWER_BOUND
);
1089 for (; len
> 0; len
-= sizeof(u32
), image
++) {
1090 /* read data comes through single port, auto-incr addr */
1091 /* NOTE: Use the debugless read so we don't flood kernel log
1092 * if IWL_DL_IO is set */
1093 val
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
1094 if (val
!= le32_to_cpu(*image
)) {
1095 IWL_ERROR("uCode INST section is invalid at "
1096 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1097 save_len
- len
, val
, le32_to_cpu(*image
));
1105 iwl_release_nic_access(priv
);
1109 ("ucode image in INSTRUCTION memory is good\n");
1115 * iwl_verify_ucode - determine which instruction image is in SRAM,
1116 * and verify its contents
1118 int iwl_verify_ucode(struct iwl_priv
*priv
)
1125 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
1126 len
= priv
->ucode_boot
.len
;
1127 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1129 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1133 /* Try initialize */
1134 image
= (__le32
*)priv
->ucode_init
.v_addr
;
1135 len
= priv
->ucode_init
.len
;
1136 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1138 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1142 /* Try runtime/protocol */
1143 image
= (__le32
*)priv
->ucode_code
.v_addr
;
1144 len
= priv
->ucode_code
.len
;
1145 ret
= iwlcore_verify_inst_sparse(priv
, image
, len
);
1147 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1151 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1153 /* Since nothing seems to match, show first several data entries in
1154 * instruction SRAM, so maybe visual inspection will give a clue.
1155 * Selection of bootstrap image (vs. other images) is arbitrary. */
1156 image
= (__le32
*)priv
->ucode_boot
.v_addr
;
1157 len
= priv
->ucode_boot
.len
;
1158 ret
= iwl_verify_inst_full(priv
, image
, len
);
1162 EXPORT_SYMBOL(iwl_verify_ucode
);
1164 static const char *desc_lookup(int i
)
1172 return "BAD_CHECKSUM";
1174 return "NMI_INTERRUPT";
1178 return "FATAL_ERROR";
1184 #define ERROR_START_OFFSET (1 * sizeof(u32))
1185 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1187 void iwl_dump_nic_error_log(struct iwl_priv
*priv
)
1190 u32 desc
, time
, count
, base
, data1
;
1191 u32 blink1
, blink2
, ilink1
, ilink2
;
1194 if (priv
->ucode_type
== UCODE_INIT
)
1195 base
= le32_to_cpu(priv
->card_alive_init
.error_event_table_ptr
);
1197 base
= le32_to_cpu(priv
->card_alive
.error_event_table_ptr
);
1199 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
1200 IWL_ERROR("Not valid error log pointer 0x%08X\n", base
);
1204 ret
= iwl_grab_nic_access(priv
);
1206 IWL_WARNING("Can not read from adapter at this time.\n");
1210 count
= iwl_read_targ_mem(priv
, base
);
1212 if (ERROR_START_OFFSET
<= count
* ERROR_ELEM_SIZE
) {
1213 IWL_ERROR("Start IWL Error Log Dump:\n");
1214 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv
->status
, count
);
1217 desc
= iwl_read_targ_mem(priv
, base
+ 1 * sizeof(u32
));
1218 blink1
= iwl_read_targ_mem(priv
, base
+ 3 * sizeof(u32
));
1219 blink2
= iwl_read_targ_mem(priv
, base
+ 4 * sizeof(u32
));
1220 ilink1
= iwl_read_targ_mem(priv
, base
+ 5 * sizeof(u32
));
1221 ilink2
= iwl_read_targ_mem(priv
, base
+ 6 * sizeof(u32
));
1222 data1
= iwl_read_targ_mem(priv
, base
+ 7 * sizeof(u32
));
1223 data2
= iwl_read_targ_mem(priv
, base
+ 8 * sizeof(u32
));
1224 line
= iwl_read_targ_mem(priv
, base
+ 9 * sizeof(u32
));
1225 time
= iwl_read_targ_mem(priv
, base
+ 11 * sizeof(u32
));
1227 IWL_ERROR("Desc Time "
1228 "data1 data2 line\n");
1229 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1230 desc_lookup(desc
), desc
, time
, data1
, data2
, line
);
1231 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1232 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1
, blink2
,
1235 iwl_release_nic_access(priv
);
1237 EXPORT_SYMBOL(iwl_dump_nic_error_log
);
1239 #define EVENT_START_OFFSET (4 * sizeof(u32))
1242 * iwl_print_event_log - Dump error event log to syslog
1244 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
1246 static void iwl_print_event_log(struct iwl_priv
*priv
, u32 start_idx
,
1247 u32 num_events
, u32 mode
)
1250 u32 base
; /* SRAM byte address of event log header */
1251 u32 event_size
; /* 2 u32s, or 3 u32s if timestamp recorded */
1252 u32 ptr
; /* SRAM byte address of log data */
1253 u32 ev
, time
, data
; /* event log data */
1255 if (num_events
== 0)
1257 if (priv
->ucode_type
== UCODE_INIT
)
1258 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
1260 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
1263 event_size
= 2 * sizeof(u32
);
1265 event_size
= 3 * sizeof(u32
);
1267 ptr
= base
+ EVENT_START_OFFSET
+ (start_idx
* event_size
);
1269 /* "time" is actually "data" for mode 0 (no timestamp).
1270 * place event id # at far right for easier visual parsing. */
1271 for (i
= 0; i
< num_events
; i
++) {
1272 ev
= iwl_read_targ_mem(priv
, ptr
);
1274 time
= iwl_read_targ_mem(priv
, ptr
);
1278 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time
, ev
);
1280 data
= iwl_read_targ_mem(priv
, ptr
);
1282 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1288 void iwl_dump_nic_event_log(struct iwl_priv
*priv
)
1291 u32 base
; /* SRAM byte address of event log header */
1292 u32 capacity
; /* event log capacity in # entries */
1293 u32 mode
; /* 0 - no timestamp, 1 - timestamp recorded */
1294 u32 num_wraps
; /* # times uCode wrapped to top of log */
1295 u32 next_entry
; /* index of next entry to be written by uCode */
1296 u32 size
; /* # entries that we'll print */
1298 if (priv
->ucode_type
== UCODE_INIT
)
1299 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
1301 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
1303 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
1304 IWL_ERROR("Invalid event log pointer 0x%08X\n", base
);
1308 ret
= iwl_grab_nic_access(priv
);
1310 IWL_WARNING("Can not read from adapter at this time.\n");
1314 /* event log header */
1315 capacity
= iwl_read_targ_mem(priv
, base
);
1316 mode
= iwl_read_targ_mem(priv
, base
+ (1 * sizeof(u32
)));
1317 num_wraps
= iwl_read_targ_mem(priv
, base
+ (2 * sizeof(u32
)));
1318 next_entry
= iwl_read_targ_mem(priv
, base
+ (3 * sizeof(u32
)));
1320 size
= num_wraps
? capacity
: next_entry
;
1322 /* bail out if nothing in log */
1324 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1325 iwl_release_nic_access(priv
);
1329 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1332 /* if uCode has wrapped back to top of log, start at the oldest entry,
1333 * i.e the next one that uCode would fill. */
1335 iwl_print_event_log(priv
, next_entry
,
1336 capacity
- next_entry
, mode
);
1337 /* (then/else) start at top of log */
1338 iwl_print_event_log(priv
, 0, next_entry
, mode
);
1340 iwl_release_nic_access(priv
);
1342 EXPORT_SYMBOL(iwl_dump_nic_event_log
);
1344 void iwl_rf_kill_ct_config(struct iwl_priv
*priv
)
1346 struct iwl_ct_kill_config cmd
;
1347 unsigned long flags
;
1350 spin_lock_irqsave(&priv
->lock
, flags
);
1351 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
1352 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT
);
1353 spin_unlock_irqrestore(&priv
->lock
, flags
);
1355 cmd
.critical_temperature_R
=
1356 cpu_to_le32(priv
->hw_params
.ct_kill_threshold
);
1358 ret
= iwl_send_cmd_pdu(priv
, REPLY_CT_KILL_CONFIG_CMD
,
1361 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1363 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1364 "critical temperature is %d\n",
1365 cmd
.critical_temperature_R
);
1367 EXPORT_SYMBOL(iwl_rf_kill_ct_config
);
1372 * Use: Sets the device's internal card state to enable, disable, or halt
1374 * When in the 'enable' state the card operates as normal.
1375 * When in the 'disable' state, the card enters into a low power mode.
1376 * When in the 'halt' state, the card is shut down and must be fully
1377 * restarted to come back on.
1379 static int iwl_send_card_state(struct iwl_priv
*priv
, u32 flags
, u8 meta_flag
)
1381 struct iwl_host_cmd cmd
= {
1382 .id
= REPLY_CARD_STATE_CMD
,
1385 .meta
.flags
= meta_flag
,
1388 return iwl_send_cmd(priv
, &cmd
);
1391 void iwl_radio_kill_sw_disable_radio(struct iwl_priv
*priv
)
1393 unsigned long flags
;
1395 if (test_bit(STATUS_RF_KILL_SW
, &priv
->status
))
1398 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1400 iwl_scan_cancel(priv
);
1401 /* FIXME: This is a workaround for AP */
1402 if (priv
->iw_mode
!= NL80211_IFTYPE_AP
) {
1403 spin_lock_irqsave(&priv
->lock
, flags
);
1404 iwl_write32(priv
, CSR_UCODE_DRV_GP1_SET
,
1405 CSR_UCODE_SW_BIT_RFKILL
);
1406 spin_unlock_irqrestore(&priv
->lock
, flags
);
1407 /* call the host command only if no hw rf-kill set */
1408 if (!test_bit(STATUS_RF_KILL_HW
, &priv
->status
) &&
1410 iwl_send_card_state(priv
,
1411 CARD_STATE_CMD_DISABLE
, 0);
1412 set_bit(STATUS_RF_KILL_SW
, &priv
->status
);
1413 /* make sure mac80211 stop sending Tx frame */
1414 if (priv
->mac80211_registered
)
1415 ieee80211_stop_queues(priv
->hw
);
1418 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio
);
1420 int iwl_radio_kill_sw_enable_radio(struct iwl_priv
*priv
)
1422 unsigned long flags
;
1424 if (!test_bit(STATUS_RF_KILL_SW
, &priv
->status
))
1427 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1429 spin_lock_irqsave(&priv
->lock
, flags
);
1430 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1432 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1433 * notification where it will clear SW rfkill status.
1434 * Setting it here would break the handler. Only if the
1435 * interface is down we can set here since we don't
1436 * receive any further notification.
1439 clear_bit(STATUS_RF_KILL_SW
, &priv
->status
);
1440 spin_unlock_irqrestore(&priv
->lock
, flags
);
1445 spin_lock_irqsave(&priv
->lock
, flags
);
1446 iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
1447 if (!iwl_grab_nic_access(priv
))
1448 iwl_release_nic_access(priv
);
1449 spin_unlock_irqrestore(&priv
->lock
, flags
);
1451 if (test_bit(STATUS_RF_KILL_HW
, &priv
->status
)) {
1452 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1453 "disabled by HW switch\n");
1457 /* If the driver is already loaded, it will receive
1458 * CARD_STATE_NOTIFICATION notifications and the handler will
1459 * call restart to reload the driver.
1463 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio
);