2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * Implementation of transmit path.
23 #define BITS_PER_BYTE 8
24 #define OFDM_PLCP_BITS 22
25 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
32 #define HT_LTF(_ns) (4 * (_ns))
33 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 #define OFDM_SIFS_TIME 16
40 static u32 bits_per_symbol
[][2] = {
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
60 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
63 * Insert a chain of ath_buf (descriptors) on a txq and
64 * assume the descriptors are already chained together by caller.
65 * NB: must be called with txq lock held
68 static void ath_tx_txqaddbuf(struct ath_softc
*sc
,
69 struct ath_txq
*txq
, struct list_head
*head
)
71 struct ath_hal
*ah
= sc
->sc_ah
;
74 * Insert the frame on the outbound list and
75 * pass it on to the hardware.
81 bf
= list_first_entry(head
, struct ath_buf
, list
);
83 list_splice_tail_init(head
, &txq
->axq_q
);
85 txq
->axq_totalqueued
++;
86 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
88 DPRINTF(sc
, ATH_DBG_QUEUE
,
89 "%s: txq depth = %d\n", __func__
, txq
->axq_depth
);
91 if (txq
->axq_link
== NULL
) {
92 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
93 DPRINTF(sc
, ATH_DBG_XMIT
,
94 "%s: TXDP[%u] = %llx (%p)\n",
95 __func__
, txq
->axq_qnum
,
96 ito64(bf
->bf_daddr
), bf
->bf_desc
);
98 *txq
->axq_link
= bf
->bf_daddr
;
99 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: link[%u] (%p)=%llx (%p)\n",
101 txq
->axq_qnum
, txq
->axq_link
,
102 ito64(bf
->bf_daddr
), bf
->bf_desc
);
104 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
105 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
108 /* Get transmit rate index using rate in Kbps */
110 static int ath_tx_findindex(const struct ath9k_rate_table
*rt
, int rate
)
115 for (i
= 0; i
< rt
->rateCount
; i
++) {
116 if (rt
->info
[i
].rateKbps
== rate
) {
125 /* Check if it's okay to send out aggregates */
127 static int ath_aggr_query(struct ath_softc
*sc
,
128 struct ath_node
*an
, u8 tidno
)
130 struct ath_atx_tid
*tid
;
131 tid
= ATH_AN_2_TID(an
, tidno
);
133 if (tid
->addba_exchangecomplete
|| tid
->addba_exchangeinprogress
)
139 static enum ath9k_pkt_type
get_hal_packet_type(struct ieee80211_hdr
*hdr
)
141 enum ath9k_pkt_type htype
;
144 fc
= hdr
->frame_control
;
146 /* Calculate Atheros packet type from IEEE80211 packet header */
148 if (ieee80211_is_beacon(fc
))
149 htype
= ATH9K_PKT_TYPE_BEACON
;
150 else if (ieee80211_is_probe_resp(fc
))
151 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
152 else if (ieee80211_is_atim(fc
))
153 htype
= ATH9K_PKT_TYPE_ATIM
;
154 else if (ieee80211_is_pspoll(fc
))
155 htype
= ATH9K_PKT_TYPE_PSPOLL
;
157 htype
= ATH9K_PKT_TYPE_NORMAL
;
162 static void fill_min_rates(struct sk_buff
*skb
, struct ath_tx_control
*txctl
)
164 struct ieee80211_hdr
*hdr
;
165 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
166 struct ath_tx_info_priv
*tx_info_priv
;
169 hdr
= (struct ieee80211_hdr
*)skb
->data
;
170 fc
= hdr
->frame_control
;
171 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
173 if (ieee80211_is_mgmt(fc
) || ieee80211_is_ctl(fc
)) {
174 txctl
->use_minrate
= 1;
175 txctl
->min_rate
= tx_info_priv
->min_rate
;
176 } else if (ieee80211_is_data(fc
)) {
177 if (ieee80211_is_nullfunc(fc
) ||
178 /* Port Access Entity (IEEE 802.1X) */
179 (skb
->protocol
== cpu_to_be16(0x888E))) {
180 txctl
->use_minrate
= 1;
181 txctl
->min_rate
= tx_info_priv
->min_rate
;
183 if (is_multicast_ether_addr(hdr
->addr1
))
184 txctl
->mcast_rate
= tx_info_priv
->min_rate
;
189 /* This function will setup additional txctl information, mostly rate stuff */
190 /* FIXME: seqno, ps */
191 static int ath_tx_prepare(struct ath_softc
*sc
,
193 struct ath_tx_control
*txctl
)
195 struct ieee80211_hw
*hw
= sc
->hw
;
196 struct ieee80211_hdr
*hdr
;
197 struct ath_rc_series
*rcs
;
198 struct ath_txq
*txq
= NULL
;
199 const struct ath9k_rate_table
*rt
;
200 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
201 struct ath_tx_info_priv
*tx_info_priv
;
208 hdr
= (struct ieee80211_hdr
*)skb
->data
;
209 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
210 fc
= hdr
->frame_control
;
212 rt
= sc
->sc_currates
;
215 /* Fill misc fields */
217 spin_lock_bh(&sc
->node_lock
);
218 txctl
->an
= ath_node_get(sc
, hdr
->addr1
);
219 /* create a temp node, if the node is not there already */
221 txctl
->an
= ath_node_attach(sc
, hdr
->addr1
, 0);
222 spin_unlock_bh(&sc
->node_lock
);
224 if (ieee80211_is_data_qos(fc
)) {
225 qc
= ieee80211_get_qos_ctl(hdr
);
226 txctl
->tidno
= qc
[0] & 0xf;
230 txctl
->frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
231 txctl
->txpower
= MAX_RATE_POWER
; /* FIXME */
233 /* Fill Key related fields */
235 txctl
->keytype
= ATH9K_KEY_TYPE_CLEAR
;
236 txctl
->keyix
= ATH9K_TXKEYIX_INVALID
;
238 if (tx_info
->control
.hw_key
) {
239 txctl
->keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
240 txctl
->frmlen
+= tx_info
->control
.hw_key
->icv_len
;
242 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
243 txctl
->keytype
= ATH9K_KEY_TYPE_WEP
;
244 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
245 txctl
->keytype
= ATH9K_KEY_TYPE_TKIP
;
246 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
247 txctl
->keytype
= ATH9K_KEY_TYPE_AES
;
250 /* Fill packet type */
252 txctl
->atype
= get_hal_packet_type(hdr
);
256 if (unlikely(txctl
->flags
& ATH9K_TXDESC_CAB
)) {
260 txctl
->qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
261 txq
= &sc
->sc_txq
[txctl
->qnum
];
263 spin_lock_bh(&txq
->axq_lock
);
265 /* Try to avoid running out of descriptors */
266 if (txq
->axq_depth
>= (ATH_TXBUF
- 20) &&
267 !(txctl
->flags
& ATH9K_TXDESC_CAB
)) {
268 DPRINTF(sc
, ATH_DBG_FATAL
,
269 "%s: TX queue: %d is full, depth: %d\n",
273 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
275 spin_unlock_bh(&txq
->axq_lock
);
279 spin_unlock_bh(&txq
->axq_lock
);
283 fill_min_rates(skb
, txctl
);
287 txctl
->flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
289 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
290 txctl
->flags
|= ATH9K_TXDESC_NOACK
;
291 if (tx_info
->flags
& IEEE80211_TX_CTL_USE_RTS_CTS
)
292 txctl
->flags
|= ATH9K_TXDESC_RTSENA
;
295 * Setup for rate calculations.
297 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
298 rcs
= tx_info_priv
->rcs
;
300 if (ieee80211_is_data(fc
) && !txctl
->use_minrate
) {
302 /* Enable HT only for DATA frames and not for EAPOL */
303 /* XXX why AMPDU only?? */
304 txctl
->ht
= (hw
->conf
.ht
.enabled
&&
305 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
));
307 if (is_multicast_ether_addr(hdr
->addr1
)) {
309 ath_tx_findindex(rt
, txctl
->mcast_rate
);
312 * mcast packets are not re-tried.
316 /* For HT capable stations, we save tidno for later use.
317 * We also override seqno set by upper layer with the one
318 * in tx aggregation state.
320 * First, the fragmentation stat is determined.
321 * If fragmentation is on, the sequence number is
322 * not overridden, since it has been
323 * incremented by the fragmentation routine.
325 if (likely(!(txctl
->flags
& ATH9K_TXDESC_FRAG_IS_ON
)) &&
326 txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
327 struct ath_atx_tid
*tid
;
329 tid
= ATH_AN_2_TID(txctl
->an
, txctl
->tidno
);
331 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
332 IEEE80211_SEQ_SEQ_SHIFT
);
333 txctl
->seqno
= tid
->seq_next
;
334 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
337 /* for management and control frames,
338 * or for NULL and EAPOL frames */
340 rcs
[0].rix
= ath_rate_findrateix(sc
, txctl
->min_rate
);
343 rcs
[0].tries
= ATH_MGT_TXMAXTRY
;
347 if (ieee80211_has_morefrags(fc
) ||
348 (le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)) {
350 ** Force hardware to use computed duration for next
351 ** fragment by disabling multi-rate retry, which
352 ** updates duration based on the multi-rate
355 rcs
[1].tries
= rcs
[2].tries
= rcs
[3].tries
= 0;
356 rcs
[1].rix
= rcs
[2].rix
= rcs
[3].rix
= 0;
357 /* reset tries but keep rate index */
358 rcs
[0].tries
= ATH_TXMAXTRY
;
362 * Determine if a tx interrupt should be generated for
363 * this descriptor. We take a tx interrupt to reap
364 * descriptors when the h/w hits an EOL condition or
365 * when the descriptor is specifically marked to generate
366 * an interrupt. We periodically mark descriptors in this
367 * way to insure timely replenishing of the supply needed
368 * for sending frames. Defering interrupts reduces system
369 * load and potentially allows more concurrent work to be
370 * done but if done to aggressively can cause senders to
373 * NB: use >= to deal with sc_txintrperiod changing
374 * dynamically through sysctl.
376 spin_lock_bh(&txq
->axq_lock
);
377 if ((++txq
->axq_intrcnt
>= sc
->sc_txintrperiod
)) {
378 txctl
->flags
|= ATH9K_TXDESC_INTREQ
;
379 txq
->axq_intrcnt
= 0;
381 spin_unlock_bh(&txq
->axq_lock
);
383 if (is_multicast_ether_addr(hdr
->addr1
)) {
384 antenna
= sc
->sc_mcastantenna
+ 1;
385 sc
->sc_mcastantenna
= (sc
->sc_mcastantenna
+ 1) & 0x1;
391 /* To complete a chain of buffers associated a frame */
393 static void ath_tx_complete_buf(struct ath_softc
*sc
,
395 struct list_head
*bf_q
,
396 int txok
, int sendbar
)
398 struct sk_buff
*skb
= bf
->bf_mpdu
;
399 struct ath_xmit_status tx_status
;
402 * Set retry information.
403 * NB: Don't use the information in the descriptor, because the frame
404 * could be software retried.
406 tx_status
.retries
= bf
->bf_retries
;
410 tx_status
.flags
= ATH_TX_BAR
;
413 tx_status
.flags
|= ATH_TX_ERROR
;
415 if (bf_isxretried(bf
))
416 tx_status
.flags
|= ATH_TX_XRETRY
;
418 /* Unmap this frame */
419 pci_unmap_single(sc
->pdev
,
423 /* complete this frame */
424 ath_tx_complete(sc
, skb
, &tx_status
, bf
->bf_node
);
427 * Return the list of ath_buf of this mpdu to free queue
429 spin_lock_bh(&sc
->sc_txbuflock
);
430 list_splice_tail_init(bf_q
, &sc
->sc_txbuf
);
431 spin_unlock_bh(&sc
->sc_txbuflock
);
435 * queue up a dest/ac pair for tx scheduling
436 * NB: must be called with txq lock held
439 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
441 struct ath_atx_ac
*ac
= tid
->ac
;
444 * if tid is paused, hold off
450 * add tid to ac atmost once
456 list_add_tail(&tid
->list
, &ac
->tid_q
);
459 * add node ac to txq atmost once
465 list_add_tail(&ac
->list
, &txq
->axq_acq
);
470 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
472 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
474 spin_lock_bh(&txq
->axq_lock
);
478 spin_unlock_bh(&txq
->axq_lock
);
481 /* resume a tid and schedule aggregate */
483 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
485 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
487 ASSERT(tid
->paused
> 0);
488 spin_lock_bh(&txq
->axq_lock
);
495 if (list_empty(&tid
->buf_q
))
499 * Add this TID to scheduler and try to send out aggregates
501 ath_tx_queue_tid(txq
, tid
);
502 ath_txq_schedule(sc
, txq
);
504 spin_unlock_bh(&txq
->axq_lock
);
507 /* Compute the number of bad frames */
509 static int ath_tx_num_badfrms(struct ath_softc
*sc
,
510 struct ath_buf
*bf
, int txok
)
512 struct ath_node
*an
= bf
->bf_node
;
513 int isnodegone
= (an
->an_flags
& ATH_NODE_CLEAN
);
514 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
515 struct ath_desc
*ds
= bf_last
->bf_desc
;
517 u32 ba
[WME_BA_BMP_SIZE
>> 5];
522 if (isnodegone
|| ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
525 isaggr
= bf_isaggr(bf
);
527 seq_st
= ATH_DS_BA_SEQ(ds
);
528 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
532 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
533 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
542 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
545 struct ieee80211_hdr
*hdr
;
547 bf
->bf_state
.bf_type
|= BUF_RETRY
;
551 hdr
= (struct ieee80211_hdr
*)skb
->data
;
552 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
555 /* Update block ack window */
557 static void ath_tx_update_baw(struct ath_softc
*sc
,
558 struct ath_atx_tid
*tid
, int seqno
)
562 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
563 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
565 tid
->tx_buf
[cindex
] = NULL
;
567 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
568 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
569 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
574 * ath_pkt_dur - compute packet duration (NB: not NAV)
577 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
578 * width - 0 for 20 MHz, 1 for 40 MHz
579 * half_gi - to use 4us v/s 3.6 us for symbol time
582 static u32
ath_pkt_duration(struct ath_softc
*sc
,
589 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
590 u32 nbits
, nsymbits
, duration
, nsymbols
;
594 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
595 rc
= rt
->info
[rix
].rateCode
;
598 * for legacy rates, use old function to compute packet duration
601 return ath9k_hw_computetxtime(sc
->sc_ah
,
607 * find number of symbols: PLCP + data
609 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
610 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
611 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
614 duration
= SYMBOL_TIME(nsymbols
);
616 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
619 * addup duration for legacy/ht training and signal fields
621 streams
= HT_RC_2_STREAMS(rc
);
622 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
626 /* Rate module function to set rate related fields in tx descriptor */
628 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
630 struct ath_hal
*ah
= sc
->sc_ah
;
631 const struct ath9k_rate_table
*rt
;
632 struct ath_desc
*ds
= bf
->bf_desc
;
633 struct ath_desc
*lastds
= bf
->bf_lastbf
->bf_desc
;
634 struct ath9k_11n_rate_series series
[4];
635 int i
, flags
, rtsctsena
= 0, dynamic_mimops
= 0;
637 u8 rix
= 0, cix
, ctsrate
= 0;
638 u32 aggr_limit_with_rts
= ah
->ah_caps
.rts_aggr_limit
;
639 struct ath_node
*an
= (struct ath_node
*) bf
->bf_node
;
642 * get the cix for the lowest valid rix.
644 rt
= sc
->sc_currates
;
646 if (bf
->bf_rcs
[i
].tries
) {
647 rix
= bf
->bf_rcs
[i
].rix
;
651 flags
= (bf
->bf_flags
& (ATH9K_TXDESC_RTSENA
| ATH9K_TXDESC_CTSENA
));
652 cix
= rt
->info
[rix
].controlRate
;
655 * If 802.11g protection is enabled, determine whether
656 * to use RTS/CTS or just CTS. Note that this is only
657 * done for OFDM/HT unicast frames.
659 if (sc
->sc_protmode
!= PROT_M_NONE
&&
660 (rt
->info
[rix
].phy
== PHY_OFDM
||
661 rt
->info
[rix
].phy
== PHY_HT
) &&
662 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
663 if (sc
->sc_protmode
== PROT_M_RTSCTS
)
664 flags
= ATH9K_TXDESC_RTSENA
;
665 else if (sc
->sc_protmode
== PROT_M_CTSONLY
)
666 flags
= ATH9K_TXDESC_CTSENA
;
668 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
672 /* For 11n, the default behavior is to enable RTS for
673 * hw retried frames. We enable the global flag here and
674 * let rate series flags determine which rates will actually
677 if ((ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) && bf_isdata(bf
)) {
680 * 802.11g protection not needed, use our default behavior
683 flags
= ATH9K_TXDESC_RTSENA
;
685 * For dynamic MIMO PS, RTS needs to precede the first aggregate
686 * and the second aggregate should have any protection at all.
688 if (an
->an_smmode
== ATH_SM_PWRSAV_DYNAMIC
) {
689 if (!bf_isaggrburst(bf
)) {
690 flags
= ATH9K_TXDESC_RTSENA
;
699 * Set protection if aggregate protection on
701 if (sc
->sc_config
.ath_aggr_prot
&&
702 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
703 flags
= ATH9K_TXDESC_RTSENA
;
704 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
709 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
711 if (bf_isaggr(bf
) && (bf
->bf_al
> aggr_limit_with_rts
)) {
713 * Ensure that in the case of SM Dynamic power save
714 * while we are bursting the second aggregate the
717 flags
&= ~(ATH9K_TXDESC_RTSENA
);
721 * CTS transmit rate is derived from the transmit rate
722 * by looking in the h/w rate table. We must also factor
723 * in whether or not a short preamble is to be used.
725 /* NB: cix is set above where RTS/CTS is enabled */
727 ctsrate
= rt
->info
[cix
].rateCode
|
728 (bf_isshpreamble(bf
) ? rt
->info
[cix
].shortPreamble
: 0);
731 * Setup HAL rate series
733 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
735 for (i
= 0; i
< 4; i
++) {
736 if (!bf
->bf_rcs
[i
].tries
)
739 rix
= bf
->bf_rcs
[i
].rix
;
741 series
[i
].Rate
= rt
->info
[rix
].rateCode
|
742 (bf_isshpreamble(bf
) ? rt
->info
[rix
].shortPreamble
: 0);
744 series
[i
].Tries
= bf
->bf_rcs
[i
].tries
;
746 series
[i
].RateFlags
= (
747 (bf
->bf_rcs
[i
].flags
& ATH_RC_RTSCTS_FLAG
) ?
748 ATH9K_RATESERIES_RTS_CTS
: 0) |
749 ((bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) ?
750 ATH9K_RATESERIES_2040
: 0) |
751 ((bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
) ?
752 ATH9K_RATESERIES_HALFGI
: 0);
754 series
[i
].PktDuration
= ath_pkt_duration(
756 (bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) != 0,
757 (bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
),
758 bf_isshpreamble(bf
));
760 if ((an
->an_smmode
== ATH_SM_PWRSAV_STATIC
) &&
761 (bf
->bf_rcs
[i
].flags
& ATH_RC_DS_FLAG
) == 0) {
763 * When sending to an HT node that has enabled static
764 * SM/MIMO power save, send at single stream rates but
765 * use maximum allowed transmit chains per user,
766 * hardware, regulatory, or country limits for
769 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
773 ath_chainmask_sel_logic(sc
, an
);
775 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
779 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
782 * Set RTS for all rates if node is in dynamic powersave
783 * mode and we are using dual stream rates.
785 if (dynamic_mimops
&& (bf
->bf_rcs
[i
].flags
& ATH_RC_DS_FLAG
))
786 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
790 * For non-HT devices, calculate RTS/CTS duration in software
791 * and disable multi-rate retry.
793 if (flags
&& !(ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
)) {
795 * Compute the transmit duration based on the frame
796 * size and the size of an ACK frame. We call into the
797 * HAL to do the computation since it depends on the
798 * characteristics of the actual PHY being used.
800 * NB: CTS is assumed the same size as an ACK so we can
801 * use the precalculated ACK durations.
803 if (flags
& ATH9K_TXDESC_RTSENA
) { /* SIFS + CTS */
804 ctsduration
+= bf_isshpreamble(bf
) ?
805 rt
->info
[cix
].spAckDuration
:
806 rt
->info
[cix
].lpAckDuration
;
809 ctsduration
+= series
[0].PktDuration
;
811 if ((bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) { /* SIFS + ACK */
812 ctsduration
+= bf_isshpreamble(bf
) ?
813 rt
->info
[rix
].spAckDuration
:
814 rt
->info
[rix
].lpAckDuration
;
818 * Disable multi-rate retry when using RTS/CTS by clearing
821 memset(&series
[1], 0, sizeof(struct ath9k_11n_rate_series
) * 3);
825 * set dur_update_en for l-sig computation except for PS-Poll frames
827 ath9k_hw_set11n_ratescenario(ah
, ds
, lastds
,
832 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
833 ath9k_hw_set11n_burstduration(ah
, ds
, 8192);
837 * Function to send a normal HT (non-AMPDU) frame
838 * NB: must be called with txq lock held
841 static int ath_tx_send_normal(struct ath_softc
*sc
,
843 struct ath_atx_tid
*tid
,
844 struct list_head
*bf_head
)
848 struct ieee80211_tx_info
*tx_info
;
849 struct ath_tx_info_priv
*tx_info_priv
;
851 BUG_ON(list_empty(bf_head
));
853 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
854 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
; /* regular HT frame */
856 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
857 tx_info
= IEEE80211_SKB_CB(skb
);
858 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
859 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
861 /* update starting sequence number for subsequent ADDBA request */
862 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
864 /* Queue to h/w without aggregation */
866 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
867 ath_buf_set_rate(sc
, bf
);
868 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
873 /* flush tid's software queue and send frames as non-ampdu's */
875 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
877 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
879 struct list_head bf_head
;
880 INIT_LIST_HEAD(&bf_head
);
882 ASSERT(tid
->paused
> 0);
883 spin_lock_bh(&txq
->axq_lock
);
887 if (tid
->paused
> 0) {
888 spin_unlock_bh(&txq
->axq_lock
);
892 while (!list_empty(&tid
->buf_q
)) {
893 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
894 ASSERT(!bf_isretried(bf
));
895 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
896 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
899 spin_unlock_bh(&txq
->axq_lock
);
902 /* Completion routine of an aggregate */
904 static void ath_tx_complete_aggr_rifs(struct ath_softc
*sc
,
907 struct list_head
*bf_q
,
910 struct ath_node
*an
= bf
->bf_node
;
911 struct ath_atx_tid
*tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
912 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
913 struct ath_desc
*ds
= bf_last
->bf_desc
;
914 struct ath_buf
*bf_next
, *bf_lastq
= NULL
;
915 struct list_head bf_head
, bf_pending
;
917 u32 ba
[WME_BA_BMP_SIZE
>> 5];
918 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
919 int isnodegone
= (an
->an_flags
& ATH_NODE_CLEAN
);
921 isaggr
= bf_isaggr(bf
);
924 if (ATH_DS_TX_BA(ds
)) {
926 * extract starting sequence and
929 seq_st
= ATH_DS_BA_SEQ(ds
);
931 ATH_DS_BA_BITMAP(ds
),
932 WME_BA_BMP_SIZE
>> 3);
934 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
937 * AR5416 can become deaf/mute when BA
938 * issue happens. Chip needs to be reset.
939 * But AP code may have sychronization issues
940 * when perform internal reset in this routine.
941 * Only enable reset in STA mode for now.
943 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_STA
)
947 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
951 INIT_LIST_HEAD(&bf_pending
);
952 INIT_LIST_HEAD(&bf_head
);
955 txfail
= txpending
= 0;
956 bf_next
= bf
->bf_next
;
958 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
959 /* transmit completion, subframe is
960 * acked by block ack */
961 } else if (!isaggr
&& txok
) {
962 /* transmit completion */
965 if (!tid
->cleanup_inprogress
&& !isnodegone
&&
966 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
967 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
968 ath_tx_set_retry(sc
, bf
);
971 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
977 * cleanup in progress, just fail
978 * the un-acked sub-frames
984 * Remove ath_buf's of this sub-frame from aggregate queue.
986 if (bf_next
== NULL
) { /* last subframe in the aggregate */
987 ASSERT(bf
->bf_lastfrm
== bf_last
);
990 * The last descriptor of the last sub frame could be
991 * a holding descriptor for h/w. If that's the case,
992 * bf->bf_lastfrm won't be in the bf_q.
993 * Make sure we handle bf_q properly here.
996 if (!list_empty(bf_q
)) {
997 bf_lastq
= list_entry(bf_q
->prev
,
998 struct ath_buf
, list
);
999 list_cut_position(&bf_head
,
1000 bf_q
, &bf_lastq
->list
);
1003 * XXX: if the last subframe only has one
1004 * descriptor which is also being used as
1005 * a holding descriptor. Then the ath_buf
1006 * is not in the bf_q at all.
1008 INIT_LIST_HEAD(&bf_head
);
1011 ASSERT(!list_empty(bf_q
));
1012 list_cut_position(&bf_head
,
1013 bf_q
, &bf
->bf_lastfrm
->list
);
1018 * complete the acked-ones/xretried ones; update
1021 spin_lock_bh(&txq
->axq_lock
);
1022 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1023 spin_unlock_bh(&txq
->axq_lock
);
1025 /* complete this sub-frame */
1026 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
1029 * retry the un-acked ones
1032 * XXX: if the last descriptor is holding descriptor,
1033 * in order to requeue the frame to software queue, we
1034 * need to allocate a new descriptor and
1035 * copy the content of holding descriptor to it.
1037 if (bf
->bf_next
== NULL
&&
1038 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
1039 struct ath_buf
*tbf
;
1041 /* allocate new descriptor */
1042 spin_lock_bh(&sc
->sc_txbuflock
);
1043 ASSERT(!list_empty((&sc
->sc_txbuf
)));
1044 tbf
= list_first_entry(&sc
->sc_txbuf
,
1045 struct ath_buf
, list
);
1046 list_del(&tbf
->list
);
1047 spin_unlock_bh(&sc
->sc_txbuflock
);
1049 ATH_TXBUF_RESET(tbf
);
1051 /* copy descriptor content */
1052 tbf
->bf_mpdu
= bf_last
->bf_mpdu
;
1053 tbf
->bf_node
= bf_last
->bf_node
;
1054 tbf
->bf_buf_addr
= bf_last
->bf_buf_addr
;
1055 *(tbf
->bf_desc
) = *(bf_last
->bf_desc
);
1057 /* link it to the frame */
1059 bf_lastq
->bf_desc
->ds_link
=
1061 bf
->bf_lastfrm
= tbf
;
1062 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1063 bf
->bf_lastfrm
->bf_desc
);
1065 tbf
->bf_state
= bf_last
->bf_state
;
1066 tbf
->bf_lastfrm
= tbf
;
1067 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1068 tbf
->bf_lastfrm
->bf_desc
);
1070 /* copy the DMA context */
1071 tbf
->bf_dmacontext
=
1072 bf_last
->bf_dmacontext
;
1074 list_add_tail(&tbf
->list
, &bf_head
);
1077 * Clear descriptor status words for
1080 ath9k_hw_cleartxdesc(sc
->sc_ah
,
1081 bf
->bf_lastfrm
->bf_desc
);
1085 * Put this buffer to the temporary pending
1086 * queue to retain ordering
1088 list_splice_tail_init(&bf_head
, &bf_pending
);
1095 * node is already gone. no more assocication
1096 * with the node. the node might have been freed
1097 * any node acces can result in panic.note tid
1098 * is part of the node.
1103 if (tid
->cleanup_inprogress
) {
1104 /* check to see if we're done with cleaning the h/w queue */
1105 spin_lock_bh(&txq
->axq_lock
);
1107 if (tid
->baw_head
== tid
->baw_tail
) {
1108 tid
->addba_exchangecomplete
= 0;
1109 tid
->addba_exchangeattempts
= 0;
1110 spin_unlock_bh(&txq
->axq_lock
);
1112 tid
->cleanup_inprogress
= false;
1114 /* send buffered frames as singles */
1115 ath_tx_flush_tid(sc
, tid
);
1117 spin_unlock_bh(&txq
->axq_lock
);
1123 * prepend un-acked frames to the beginning of the pending frame queue
1125 if (!list_empty(&bf_pending
)) {
1126 spin_lock_bh(&txq
->axq_lock
);
1127 /* Note: we _prepend_, we _do_not_ at to
1128 * the end of the queue ! */
1129 list_splice(&bf_pending
, &tid
->buf_q
);
1130 ath_tx_queue_tid(txq
, tid
);
1131 spin_unlock_bh(&txq
->axq_lock
);
1135 ath_reset(sc
, false);
1140 /* Process completed xmit descriptors from the specified queue */
1142 static int ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1144 struct ath_hal
*ah
= sc
->sc_ah
;
1145 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
1146 struct list_head bf_head
;
1147 struct ath_desc
*ds
, *tmp_ds
;
1148 struct sk_buff
*skb
;
1149 struct ieee80211_tx_info
*tx_info
;
1150 struct ath_tx_info_priv
*tx_info_priv
;
1151 int nacked
, txok
, nbad
= 0, isrifs
= 0;
1154 DPRINTF(sc
, ATH_DBG_QUEUE
,
1155 "%s: tx queue %d (%x), link %p\n", __func__
,
1156 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
1161 spin_lock_bh(&txq
->axq_lock
);
1162 txq
->axq_intrcnt
= 0; /* reset periodic desc intr count */
1163 if (list_empty(&txq
->axq_q
)) {
1164 txq
->axq_link
= NULL
;
1165 txq
->axq_linkbuf
= NULL
;
1166 spin_unlock_bh(&txq
->axq_lock
);
1169 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1172 * There is a race condition that a BH gets scheduled
1173 * after sw writes TxE and before hw re-load the last
1174 * descriptor to get the newly chained one.
1175 * Software must keep the last DONE descriptor as a
1176 * holding descriptor - software does so by marking
1177 * it with the STALE flag.
1180 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1182 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1184 * The holding descriptor is the last
1185 * descriptor in queue. It's safe to remove
1186 * the last holding descriptor in BH context.
1188 spin_unlock_bh(&txq
->axq_lock
);
1191 /* Lets work with the next buffer now */
1192 bf
= list_entry(bf_held
->list
.next
,
1193 struct ath_buf
, list
);
1197 lastbf
= bf
->bf_lastbf
;
1198 ds
= lastbf
->bf_desc
; /* NB: last decriptor */
1200 status
= ath9k_hw_txprocdesc(ah
, ds
);
1201 if (status
== -EINPROGRESS
) {
1202 spin_unlock_bh(&txq
->axq_lock
);
1205 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1206 txq
->axq_lastdsWithCTS
= NULL
;
1207 if (ds
== txq
->axq_gatingds
)
1208 txq
->axq_gatingds
= NULL
;
1211 * Remove ath_buf's of the same transmit unit from txq,
1212 * however leave the last descriptor back as the holding
1213 * descriptor for hw.
1215 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1216 INIT_LIST_HEAD(&bf_head
);
1218 if (!list_is_singular(&lastbf
->list
))
1219 list_cut_position(&bf_head
,
1220 &txq
->axq_q
, lastbf
->list
.prev
);
1225 txq
->axq_aggr_depth
--;
1227 txok
= (ds
->ds_txstat
.ts_status
== 0);
1229 spin_unlock_bh(&txq
->axq_lock
);
1232 list_del(&bf_held
->list
);
1233 spin_lock_bh(&sc
->sc_txbuflock
);
1234 list_add_tail(&bf_held
->list
, &sc
->sc_txbuf
);
1235 spin_unlock_bh(&sc
->sc_txbuflock
);
1238 if (!bf_isampdu(bf
)) {
1240 * This frame is sent out as a single frame.
1241 * Use hardware retry status for this frame.
1243 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1244 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1245 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1248 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1251 tx_info
= IEEE80211_SKB_CB(skb
);
1252 tx_info_priv
= (struct ath_tx_info_priv
*)
1253 tx_info
->driver_data
[0];
1254 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
1255 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1256 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
1257 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
1258 if (ds
->ds_txstat
.ts_status
== 0)
1261 if (bf_isdata(bf
)) {
1263 tmp_ds
= bf
->bf_rifslast
->bf_desc
;
1266 memcpy(&tx_info_priv
->tx
,
1268 sizeof(tx_info_priv
->tx
));
1269 tx_info_priv
->n_frames
= bf
->bf_nframes
;
1270 tx_info_priv
->n_bad_frames
= nbad
;
1275 * Complete this transmit unit
1278 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, txok
);
1280 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1282 /* Wake up mac80211 queue */
1284 spin_lock_bh(&txq
->axq_lock
);
1285 if (txq
->stopped
&& ath_txq_depth(sc
, txq
->axq_qnum
) <=
1288 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1290 ieee80211_wake_queue(sc
->hw
, qnum
);
1297 * schedule any pending packets if aggregation is enabled
1299 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1300 ath_txq_schedule(sc
, txq
);
1301 spin_unlock_bh(&txq
->axq_lock
);
1306 static void ath_tx_stopdma(struct ath_softc
*sc
, struct ath_txq
*txq
)
1308 struct ath_hal
*ah
= sc
->sc_ah
;
1310 (void) ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1311 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: tx queue [%u] %x, link %p\n",
1312 __func__
, txq
->axq_qnum
,
1313 ath9k_hw_gettxbuf(ah
, txq
->axq_qnum
), txq
->axq_link
);
1316 /* Drain only the data queues */
1318 static void ath_drain_txdataq(struct ath_softc
*sc
, bool retry_tx
)
1320 struct ath_hal
*ah
= sc
->sc_ah
;
1324 /* XXX return value */
1325 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
1326 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1327 if (ATH_TXQ_SETUP(sc
, i
)) {
1328 ath_tx_stopdma(sc
, &sc
->sc_txq
[i
]);
1330 /* The TxDMA may not really be stopped.
1331 * Double check the hal tx pending count */
1332 npend
+= ath9k_hw_numtxpending(ah
,
1333 sc
->sc_txq
[i
].axq_qnum
);
1341 /* TxDMA not stopped, reset the hal */
1342 DPRINTF(sc
, ATH_DBG_XMIT
,
1343 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__
);
1345 spin_lock_bh(&sc
->sc_resetlock
);
1346 if (!ath9k_hw_reset(ah
,
1347 sc
->sc_ah
->ah_curchan
,
1348 sc
->sc_ht_info
.tx_chan_width
,
1349 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1350 sc
->sc_ht_extprotspacing
, true, &status
)) {
1352 DPRINTF(sc
, ATH_DBG_FATAL
,
1353 "%s: unable to reset hardware; hal status %u\n",
1357 spin_unlock_bh(&sc
->sc_resetlock
);
1360 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1361 if (ATH_TXQ_SETUP(sc
, i
))
1362 ath_tx_draintxq(sc
, &sc
->sc_txq
[i
], retry_tx
);
1366 /* Add a sub-frame to block ack window */
1368 static void ath_tx_addto_baw(struct ath_softc
*sc
,
1369 struct ath_atx_tid
*tid
,
1374 if (bf_isretried(bf
))
1377 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
1378 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
1380 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
1381 tid
->tx_buf
[cindex
] = bf
;
1383 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
1384 (ATH_TID_MAX_BUFS
- 1))) {
1385 tid
->baw_tail
= cindex
;
1386 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
1391 * Function to send an A-MPDU
1392 * NB: must be called with txq lock held
1395 static int ath_tx_send_ampdu(struct ath_softc
*sc
,
1396 struct ath_txq
*txq
,
1397 struct ath_atx_tid
*tid
,
1398 struct list_head
*bf_head
,
1399 struct ath_tx_control
*txctl
)
1402 struct sk_buff
*skb
;
1403 struct ieee80211_tx_info
*tx_info
;
1404 struct ath_tx_info_priv
*tx_info_priv
;
1406 BUG_ON(list_empty(bf_head
));
1408 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1409 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1410 bf
->bf_seqno
= txctl
->seqno
; /* save seqno and tidno in buffer */
1411 bf
->bf_tidno
= txctl
->tidno
;
1414 * Do not queue to h/w when any of the following conditions is true:
1415 * - there are pending frames in software queue
1416 * - the TID is currently paused for ADDBA/BAR request
1417 * - seqno is not within block-ack window
1418 * - h/w queue depth exceeds low water mark
1420 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1421 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1422 txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1424 * Add this frame to software queue for scheduling later
1427 list_splice_tail_init(bf_head
, &tid
->buf_q
);
1428 ath_tx_queue_tid(txq
, tid
);
1432 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1433 tx_info
= IEEE80211_SKB_CB(skb
);
1434 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
1435 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1437 /* Add sub-frame to BAW */
1438 ath_tx_addto_baw(sc
, tid
, bf
);
1440 /* Queue to h/w without aggregation */
1442 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
1443 ath_buf_set_rate(sc
, bf
);
1444 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1450 * returns aggr limit based on lowest of the rates
1453 static u32
ath_lookup_rate(struct ath_softc
*sc
,
1455 struct ath_atx_tid
*tid
)
1457 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1458 struct sk_buff
*skb
;
1459 struct ieee80211_tx_info
*tx_info
;
1460 struct ath_tx_info_priv
*tx_info_priv
;
1461 u32 max_4ms_framelen
, frame_length
;
1462 u16 aggr_limit
, legacy
= 0, maxampdu
;
1466 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1467 tx_info
= IEEE80211_SKB_CB(skb
);
1468 tx_info_priv
= (struct ath_tx_info_priv
*)
1469 tx_info
->driver_data
[0];
1471 tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1474 * Find the lowest frame length among the rate series that will have a
1475 * 4ms transmit duration.
1476 * TODO - TXOP limit needs to be considered.
1478 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
1480 for (i
= 0; i
< 4; i
++) {
1481 if (bf
->bf_rcs
[i
].tries
) {
1482 frame_length
= bf
->bf_rcs
[i
].max_4ms_framelen
;
1484 if (rt
->info
[bf
->bf_rcs
[i
].rix
].phy
!= PHY_HT
) {
1489 max_4ms_framelen
= min(max_4ms_framelen
, frame_length
);
1494 * limit aggregate size by the minimum rate if rate selected is
1495 * not a probe rate, if rate selected is a probe rate then
1496 * avoid aggregation of this packet.
1498 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
1501 aggr_limit
= min(max_4ms_framelen
,
1502 (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
1505 * h/w can accept aggregates upto 16 bit lengths (65535).
1506 * The IE, however can hold upto 65536, which shows up here
1507 * as zero. Ignore 65536 since we are constrained by hw.
1509 maxampdu
= tid
->an
->maxampdu
;
1511 aggr_limit
= min(aggr_limit
, maxampdu
);
1517 * returns the number of delimiters to be added to
1518 * meet the minimum required mpdudensity.
1519 * caller should make sure that the rate is HT rate .
1522 static int ath_compute_num_delims(struct ath_softc
*sc
,
1523 struct ath_atx_tid
*tid
,
1527 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1528 u32 nsymbits
, nsymbols
, mpdudensity
;
1531 int width
, half_gi
, ndelim
, mindelim
;
1533 /* Select standard number of delimiters based on frame length alone */
1534 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
1537 * If encryption enabled, hardware requires some more padding between
1539 * TODO - this could be improved to be dependent on the rate.
1540 * The hardware can keep up at lower rates, but not higher rates
1542 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
1543 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
1546 * Convert desired mpdu density from microeconds to bytes based
1547 * on highest rate in rate series (i.e. first rate) to determine
1548 * required minimum length for subframe. Take into account
1549 * whether high rate is 20 or 40Mhz and half or full GI.
1551 mpdudensity
= tid
->an
->mpdudensity
;
1554 * If there is no mpdu density restriction, no further calculation
1557 if (mpdudensity
== 0)
1560 rix
= bf
->bf_rcs
[0].rix
;
1561 flags
= bf
->bf_rcs
[0].flags
;
1562 rc
= rt
->info
[rix
].rateCode
;
1563 width
= (flags
& ATH_RC_CW40_FLAG
) ? 1 : 0;
1564 half_gi
= (flags
& ATH_RC_SGI_FLAG
) ? 1 : 0;
1567 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
1569 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
1574 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1575 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
1577 /* Is frame shorter than required minimum length? */
1578 if (frmlen
< minlen
) {
1579 /* Get the minimum number of delimiters required. */
1580 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
1581 ndelim
= max(mindelim
, ndelim
);
1588 * For aggregation from software buffer queue.
1589 * NB: must be called with txq lock held
1592 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
1593 struct ath_atx_tid
*tid
,
1594 struct list_head
*bf_q
,
1595 struct ath_buf
**bf_last
,
1596 struct aggr_rifs_param
*param
,
1599 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1600 struct ath_buf
*bf
, *tbf
, *bf_first
, *bf_prev
= NULL
;
1601 struct list_head bf_head
;
1602 int rl
= 0, nframes
= 0, ndelim
;
1603 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
1604 al_delta
, h_baw
= tid
->baw_size
/ 2;
1605 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
1606 int prev_al
= 0, is_ds_rate
= 0;
1607 INIT_LIST_HEAD(&bf_head
);
1609 BUG_ON(list_empty(&tid
->buf_q
));
1611 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1614 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1617 * do not step over block-ack window
1619 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
1620 status
= ATH_AGGR_BAW_CLOSED
;
1625 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
1628 * Is rate dual stream
1631 (bf
->bf_rcs
[0].flags
& ATH_RC_DS_FLAG
) ? 1 : 0;
1635 * do not exceed aggregation limit
1637 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
1639 if (nframes
&& (aggr_limit
<
1640 (al
+ bpad
+ al_delta
+ prev_al
))) {
1641 status
= ATH_AGGR_LIMITED
;
1646 * do not exceed subframe limit
1648 if ((nframes
+ *prev_frames
) >=
1649 min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
1650 status
= ATH_AGGR_LIMITED
;
1655 * add padding for previous frame to aggregation length
1657 al
+= bpad
+ al_delta
;
1660 * Get the delimiters needed to meet the MPDU
1661 * density for this node.
1663 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
1665 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1668 bf
->bf_lastfrm
->bf_desc
->ds_link
= 0;
1671 * this packet is part of an aggregate
1672 * - remove all descriptors belonging to this frame from
1674 * - add it to block ack window
1675 * - set up descriptors for aggregation
1677 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1678 ath_tx_addto_baw(sc
, tid
, bf
);
1680 list_for_each_entry(tbf
, &bf_head
, list
) {
1681 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
,
1682 tbf
->bf_desc
, ndelim
);
1686 * link buffers of this frame to the aggregate
1688 list_splice_tail_init(&bf_head
, bf_q
);
1692 bf_prev
->bf_next
= bf
;
1693 bf_prev
->bf_lastfrm
->bf_desc
->ds_link
= bf
->bf_daddr
;
1699 * terminate aggregation on a small packet boundary
1701 if (bf
->bf_frmlen
< ATH_AGGR_MINPLEN
) {
1702 status
= ATH_AGGR_SHORTPKT
;
1706 } while (!list_empty(&tid
->buf_q
));
1708 bf_first
->bf_al
= al
;
1709 bf_first
->bf_nframes
= nframes
;
1716 * process pending frames possibly doing a-mpdu aggregation
1717 * NB: must be called with txq lock held
1720 static void ath_tx_sched_aggr(struct ath_softc
*sc
,
1721 struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
1723 struct ath_buf
*bf
, *tbf
, *bf_last
, *bf_lastaggr
= NULL
;
1724 enum ATH_AGGR_STATUS status
;
1725 struct list_head bf_q
;
1726 struct aggr_rifs_param param
= {0, 0, 0, 0, NULL
};
1727 int prev_frames
= 0;
1730 if (list_empty(&tid
->buf_q
))
1733 INIT_LIST_HEAD(&bf_q
);
1735 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
, &bf_lastaggr
, ¶m
,
1739 * no frames picked up to be aggregated; block-ack
1740 * window is not open
1742 if (list_empty(&bf_q
))
1745 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1746 bf_last
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1747 bf
->bf_lastbf
= bf_last
;
1750 * if only one frame, send as non-aggregate
1752 if (bf
->bf_nframes
== 1) {
1753 ASSERT(bf
->bf_lastfrm
== bf_last
);
1755 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1757 * clear aggr bits for every descriptor
1758 * XXX TODO: is there a way to optimize it?
1760 list_for_each_entry(tbf
, &bf_q
, list
) {
1761 ath9k_hw_clr11n_aggr(sc
->sc_ah
, tbf
->bf_desc
);
1764 ath_buf_set_rate(sc
, bf
);
1765 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1770 * setup first desc with rate and aggr info
1772 bf
->bf_state
.bf_type
|= BUF_AGGR
;
1773 ath_buf_set_rate(sc
, bf
);
1774 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
1777 * anchor last frame of aggregate correctly
1779 ASSERT(bf_lastaggr
);
1780 ASSERT(bf_lastaggr
->bf_lastfrm
== bf_last
);
1782 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1784 /* XXX: We don't enter into this loop, consider removing this */
1785 while (!list_empty(&bf_q
) && !list_is_last(&tbf
->list
, &bf_q
)) {
1786 tbf
= list_entry(tbf
->list
.next
, struct ath_buf
, list
);
1787 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1790 txq
->axq_aggr_depth
++;
1793 * Normal aggregate, queue to hardware
1795 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1797 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
1798 status
!= ATH_AGGR_BAW_CLOSED
);
1801 /* Called with txq lock held */
1803 static void ath_tid_drain(struct ath_softc
*sc
,
1804 struct ath_txq
*txq
,
1805 struct ath_atx_tid
*tid
,
1809 struct list_head bf_head
;
1810 INIT_LIST_HEAD(&bf_head
);
1813 if (list_empty(&tid
->buf_q
))
1815 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1817 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1819 /* update baw for software retried frame */
1820 if (bf_isretried(bf
))
1821 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1824 * do not indicate packets while holding txq spinlock.
1825 * unlock is intentional here
1827 if (likely(bh_flag
))
1828 spin_unlock_bh(&txq
->axq_lock
);
1830 spin_unlock(&txq
->axq_lock
);
1832 /* complete this sub-frame */
1833 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1835 if (likely(bh_flag
))
1836 spin_lock_bh(&txq
->axq_lock
);
1838 spin_lock(&txq
->axq_lock
);
1842 * TODO: For frame(s) that are in the retry state, we will reuse the
1843 * sequence number(s) without setting the retry bit. The
1844 * alternative is to give up on these and BAR the receiver's window
1847 tid
->seq_next
= tid
->seq_start
;
1848 tid
->baw_tail
= tid
->baw_head
;
1852 * Drain all pending buffers
1853 * NB: must be called with txq lock held
1856 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1857 struct ath_txq
*txq
,
1860 struct ath_atx_ac
*ac
, *ac_tmp
;
1861 struct ath_atx_tid
*tid
, *tid_tmp
;
1863 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1864 list_del(&ac
->list
);
1866 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1867 list_del(&tid
->list
);
1869 ath_tid_drain(sc
, txq
, tid
, bh_flag
);
1874 static int ath_tx_start_dma(struct ath_softc
*sc
,
1875 struct sk_buff
*skb
,
1876 struct scatterlist
*sg
,
1878 struct ath_tx_control
*txctl
)
1880 struct ath_node
*an
= txctl
->an
;
1881 struct ath_buf
*bf
= NULL
;
1882 struct list_head bf_head
;
1883 struct ath_desc
*ds
;
1884 struct ath_hal
*ah
= sc
->sc_ah
;
1885 struct ath_txq
*txq
;
1886 struct ath_tx_info_priv
*tx_info_priv
;
1887 struct ath_rc_series
*rcs
;
1888 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1889 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1890 __le16 fc
= hdr
->frame_control
;
1892 if (unlikely(txctl
->flags
& ATH9K_TXDESC_CAB
))
1895 txq
= &sc
->sc_txq
[txctl
->qnum
];
1897 /* For each sglist entry, allocate an ath_buf for DMA */
1898 INIT_LIST_HEAD(&bf_head
);
1899 spin_lock_bh(&sc
->sc_txbuflock
);
1900 if (unlikely(list_empty(&sc
->sc_txbuf
))) {
1901 spin_unlock_bh(&sc
->sc_txbuflock
);
1905 bf
= list_first_entry(&sc
->sc_txbuf
, struct ath_buf
, list
);
1906 list_del(&bf
->list
);
1907 spin_unlock_bh(&sc
->sc_txbuflock
);
1909 list_add_tail(&bf
->list
, &bf_head
);
1911 /* set up this buffer */
1912 ATH_TXBUF_RESET(bf
);
1913 bf
->bf_frmlen
= txctl
->frmlen
;
1915 ieee80211_is_data(fc
) ?
1916 (bf
->bf_state
.bf_type
|= BUF_DATA
) :
1917 (bf
->bf_state
.bf_type
&= ~BUF_DATA
);
1918 ieee80211_is_back_req(fc
) ?
1919 (bf
->bf_state
.bf_type
|= BUF_BAR
) :
1920 (bf
->bf_state
.bf_type
&= ~BUF_BAR
);
1921 ieee80211_is_pspoll(fc
) ?
1922 (bf
->bf_state
.bf_type
|= BUF_PSPOLL
) :
1923 (bf
->bf_state
.bf_type
&= ~BUF_PSPOLL
);
1924 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
) ?
1925 (bf
->bf_state
.bf_type
|= BUF_SHORT_PREAMBLE
) :
1926 (bf
->bf_state
.bf_type
&= ~BUF_SHORT_PREAMBLE
);
1928 bf
->bf_flags
= txctl
->flags
;
1929 bf
->bf_keytype
= txctl
->keytype
;
1930 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->driver_data
[0];
1931 rcs
= tx_info_priv
->rcs
;
1932 bf
->bf_rcs
[0] = rcs
[0];
1933 bf
->bf_rcs
[1] = rcs
[1];
1934 bf
->bf_rcs
[2] = rcs
[2];
1935 bf
->bf_rcs
[3] = rcs
[3];
1938 bf
->bf_buf_addr
= sg_dma_address(sg
);
1940 /* setup descriptor */
1943 ds
->ds_data
= bf
->bf_buf_addr
;
1946 * Save the DMA context in the first ath_buf
1948 bf
->bf_dmacontext
= txctl
->dmacontext
;
1951 * Formulate first tx descriptor with tx controls.
1953 ath9k_hw_set11n_txdesc(ah
,
1955 bf
->bf_frmlen
, /* frame length */
1956 txctl
->atype
, /* Atheros packet type */
1957 min(txctl
->txpower
, (u16
)60), /* txpower */
1958 txctl
->keyix
, /* key cache index */
1959 txctl
->keytype
, /* key type */
1960 txctl
->flags
); /* flags */
1961 ath9k_hw_filltxdesc(ah
,
1963 sg_dma_len(sg
), /* segment length */
1964 true, /* first segment */
1965 (n_sg
== 1) ? true : false, /* last segment */
1966 ds
); /* first descriptor */
1968 bf
->bf_lastfrm
= bf
;
1970 (bf
->bf_state
.bf_type
|= BUF_HT
) :
1971 (bf
->bf_state
.bf_type
&= ~BUF_HT
);
1973 spin_lock_bh(&txq
->axq_lock
);
1975 if (txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
1976 struct ath_atx_tid
*tid
= ATH_AN_2_TID(an
, txctl
->tidno
);
1977 if (ath_aggr_query(sc
, an
, txctl
->tidno
)) {
1979 * Try aggregation if it's a unicast data frame
1980 * and the destination is HT capable.
1982 ath_tx_send_ampdu(sc
, txq
, tid
, &bf_head
, txctl
);
1985 * Send this frame as regular when ADDBA exchange
1986 * is neither complete nor pending.
1988 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
1993 ath_buf_set_rate(sc
, bf
);
1995 if (ieee80211_is_back_req(fc
)) {
1996 /* This is required for resuming tid
1997 * during BAR completion */
1998 bf
->bf_tidno
= txctl
->tidno
;
2001 ath_tx_txqaddbuf(sc
, txq
, &bf_head
);
2003 spin_unlock_bh(&txq
->axq_lock
);
2007 static void xmit_map_sg(struct ath_softc
*sc
,
2008 struct sk_buff
*skb
,
2009 struct ath_tx_control
*txctl
)
2011 struct ath_xmit_status tx_status
;
2012 struct ath_atx_tid
*tid
;
2013 struct scatterlist sg
;
2015 txctl
->dmacontext
= pci_map_single(sc
->pdev
, skb
->data
,
2016 skb
->len
, PCI_DMA_TODEVICE
);
2018 /* setup S/G list */
2019 memset(&sg
, 0, sizeof(struct scatterlist
));
2020 sg_dma_address(&sg
) = txctl
->dmacontext
;
2021 sg_dma_len(&sg
) = skb
->len
;
2023 if (ath_tx_start_dma(sc
, skb
, &sg
, 1, txctl
) != 0) {
2025 * We have to do drop frame here.
2027 pci_unmap_single(sc
->pdev
, txctl
->dmacontext
,
2028 skb
->len
, PCI_DMA_TODEVICE
);
2030 tx_status
.retries
= 0;
2031 tx_status
.flags
= ATH_TX_ERROR
;
2033 if (txctl
->ht
&& (sc
->sc_flags
& SC_OP_TXAGGR
)) {
2034 /* Reclaim the seqno. */
2035 tid
= ATH_AN_2_TID((struct ath_node
*)
2036 txctl
->an
, txctl
->tidno
);
2037 DECR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
2039 ath_tx_complete(sc
, skb
, &tx_status
, txctl
->an
);
2043 /* Initialize TX queue and h/w */
2045 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2050 spin_lock_init(&sc
->sc_txbuflock
);
2052 /* Setup tx descriptors */
2053 error
= ath_descdma_setup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
,
2056 DPRINTF(sc
, ATH_DBG_FATAL
,
2057 "%s: failed to allocate tx descriptors: %d\n",
2062 /* XXX allocate beacon state together with vap */
2063 error
= ath_descdma_setup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
,
2064 "beacon", ATH_BCBUF
, 1);
2066 DPRINTF(sc
, ATH_DBG_FATAL
,
2067 "%s: failed to allocate "
2068 "beacon descripotrs: %d\n",
2081 /* Reclaim all tx queue resources */
2083 int ath_tx_cleanup(struct ath_softc
*sc
)
2085 /* cleanup beacon descriptors */
2086 if (sc
->sc_bdma
.dd_desc_len
!= 0)
2087 ath_descdma_cleanup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
);
2089 /* cleanup tx descriptors */
2090 if (sc
->sc_txdma
.dd_desc_len
!= 0)
2091 ath_descdma_cleanup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
);
2096 /* Setup a h/w transmit queue */
2098 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
2100 struct ath_hal
*ah
= sc
->sc_ah
;
2101 struct ath9k_tx_queue_info qi
;
2104 memset(&qi
, 0, sizeof(qi
));
2105 qi
.tqi_subtype
= subtype
;
2106 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
2107 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
2108 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
2109 qi
.tqi_physCompBuf
= 0;
2112 * Enable interrupts only for EOL and DESC conditions.
2113 * We mark tx descriptors to receive a DESC interrupt
2114 * when a tx queue gets deep; otherwise waiting for the
2115 * EOL to reap descriptors. Note that this is done to
2116 * reduce interrupt load and this only defers reaping
2117 * descriptors, never transmitting frames. Aside from
2118 * reducing interrupts this also permits more concurrency.
2119 * The only potential downside is if the tx queue backs
2120 * up in which case the top half of the kernel may backup
2121 * due to a lack of tx descriptors.
2123 * The UAPSD queue is an exception, since we take a desc-
2124 * based intr on the EOSP frames.
2126 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
2127 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
2129 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
2130 TXQ_FLAG_TXDESCINT_ENABLE
;
2131 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
2134 * NB: don't print a message, this happens
2135 * normally on parts with too few tx queues
2139 if (qnum
>= ARRAY_SIZE(sc
->sc_txq
)) {
2140 DPRINTF(sc
, ATH_DBG_FATAL
,
2141 "%s: hal qnum %u out of range, max %u!\n",
2142 __func__
, qnum
, (unsigned int)ARRAY_SIZE(sc
->sc_txq
));
2143 ath9k_hw_releasetxqueue(ah
, qnum
);
2146 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
2147 struct ath_txq
*txq
= &sc
->sc_txq
[qnum
];
2149 txq
->axq_qnum
= qnum
;
2150 txq
->axq_link
= NULL
;
2151 INIT_LIST_HEAD(&txq
->axq_q
);
2152 INIT_LIST_HEAD(&txq
->axq_acq
);
2153 spin_lock_init(&txq
->axq_lock
);
2155 txq
->axq_aggr_depth
= 0;
2156 txq
->axq_totalqueued
= 0;
2157 txq
->axq_intrcnt
= 0;
2158 txq
->axq_linkbuf
= NULL
;
2159 sc
->sc_txqsetup
|= 1<<qnum
;
2161 return &sc
->sc_txq
[qnum
];
2164 /* Reclaim resources for a setup queue */
2166 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2168 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
2169 sc
->sc_txqsetup
&= ~(1<<txq
->axq_qnum
);
2173 * Setup a hardware data transmit queue for the specified
2174 * access control. The hal may not support all requested
2175 * queues in which case it will return a reference to a
2176 * previously setup queue. We record the mapping from ac's
2177 * to h/w queues for use by ath_tx_start and also track
2178 * the set of h/w queues being used to optimize work in the
2179 * transmit interrupt handler and related routines.
2182 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
2184 struct ath_txq
*txq
;
2186 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2187 DPRINTF(sc
, ATH_DBG_FATAL
,
2188 "%s: HAL AC %u out of range, max %zu!\n",
2189 __func__
, haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2192 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
2194 sc
->sc_haltype2q
[haltype
] = txq
->axq_qnum
;
2200 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
2205 case ATH9K_TX_QUEUE_DATA
:
2206 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2207 DPRINTF(sc
, ATH_DBG_FATAL
,
2208 "%s: HAL AC %u out of range, max %zu!\n",
2210 haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2213 qnum
= sc
->sc_haltype2q
[haltype
];
2215 case ATH9K_TX_QUEUE_BEACON
:
2216 qnum
= sc
->sc_bhalq
;
2218 case ATH9K_TX_QUEUE_CAB
:
2219 qnum
= sc
->sc_cabq
->axq_qnum
;
2227 /* Update parameters for a transmit queue */
2229 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
2230 struct ath9k_tx_queue_info
*qinfo
)
2232 struct ath_hal
*ah
= sc
->sc_ah
;
2234 struct ath9k_tx_queue_info qi
;
2236 if (qnum
== sc
->sc_bhalq
) {
2238 * XXX: for beacon queue, we just save the parameter.
2239 * It will be picked up by ath_beaconq_config when
2242 sc
->sc_beacon_qi
= *qinfo
;
2246 ASSERT(sc
->sc_txq
[qnum
].axq_qnum
== qnum
);
2248 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
2249 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
2250 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
2251 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
2252 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
2253 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
2255 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
2256 DPRINTF(sc
, ATH_DBG_FATAL
,
2257 "%s: unable to update hardware queue %u!\n",
2261 ath9k_hw_resettxqueue(ah
, qnum
); /* push to h/w */
2267 int ath_cabq_update(struct ath_softc
*sc
)
2269 struct ath9k_tx_queue_info qi
;
2270 int qnum
= sc
->sc_cabq
->axq_qnum
;
2271 struct ath_beacon_config conf
;
2273 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
2275 * Ensure the readytime % is within the bounds.
2277 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
2278 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
2279 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
2280 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
2282 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
2284 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
2285 ath_txq_update(sc
, qnum
, &qi
);
2290 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
)
2292 struct ath_tx_control txctl
;
2295 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2296 error
= ath_tx_prepare(sc
, skb
, &txctl
);
2299 * Start DMA mapping.
2300 * ath_tx_start_dma() will be called either synchronously
2301 * or asynchrounsly once DMA is complete.
2303 xmit_map_sg(sc
, skb
, &txctl
);
2305 ath_node_put(sc
, txctl
.an
, ATH9K_BH_STATUS_CHANGE
);
2307 /* failed packets will be dropped by the caller */
2311 /* Deferred processing of transmit interrupt */
2313 void ath_tx_tasklet(struct ath_softc
*sc
)
2316 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2318 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2321 * Process each active queue.
2323 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2324 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2325 ath_tx_processq(sc
, &sc
->sc_txq
[i
]);
2329 void ath_tx_draintxq(struct ath_softc
*sc
,
2330 struct ath_txq
*txq
, bool retry_tx
)
2332 struct ath_buf
*bf
, *lastbf
;
2333 struct list_head bf_head
;
2335 INIT_LIST_HEAD(&bf_head
);
2338 * NB: this assumes output has been stopped and
2339 * we do not need to block ath_tx_tasklet
2342 spin_lock_bh(&txq
->axq_lock
);
2344 if (list_empty(&txq
->axq_q
)) {
2345 txq
->axq_link
= NULL
;
2346 txq
->axq_linkbuf
= NULL
;
2347 spin_unlock_bh(&txq
->axq_lock
);
2351 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2353 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
2354 list_del(&bf
->list
);
2355 spin_unlock_bh(&txq
->axq_lock
);
2357 spin_lock_bh(&sc
->sc_txbuflock
);
2358 list_add_tail(&bf
->list
, &sc
->sc_txbuf
);
2359 spin_unlock_bh(&sc
->sc_txbuflock
);
2363 lastbf
= bf
->bf_lastbf
;
2365 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
2366 ATH9K_TX_SW_ABORTED
;
2368 /* remove ath_buf's of the same mpdu from txq */
2369 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
2372 spin_unlock_bh(&txq
->axq_lock
);
2375 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, 0);
2377 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2380 /* flush any pending frames if aggregation is enabled */
2381 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2383 spin_lock_bh(&txq
->axq_lock
);
2384 ath_txq_drain_pending_buffers(sc
, txq
,
2385 ATH9K_BH_STATUS_CHANGE
);
2386 spin_unlock_bh(&txq
->axq_lock
);
2391 /* Drain the transmit queues and reclaim resources */
2393 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
)
2395 /* stop beacon queue. The beacon will be freed when
2396 * we go to INIT state */
2397 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2398 (void) ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->sc_bhalq
);
2399 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: beacon queue %x\n", __func__
,
2400 ath9k_hw_gettxbuf(sc
->sc_ah
, sc
->sc_bhalq
));
2403 ath_drain_txdataq(sc
, retry_tx
);
2406 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
2408 return sc
->sc_txq
[qnum
].axq_depth
;
2411 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
)
2413 return sc
->sc_txq
[qnum
].axq_aggr_depth
;
2416 /* Check if an ADDBA is required. A valid node must be passed. */
2417 enum ATH_AGGR_CHECK
ath_tx_aggr_check(struct ath_softc
*sc
,
2418 struct ath_node
*an
,
2421 struct ath_atx_tid
*txtid
;
2423 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
2424 return AGGR_NOT_REQUIRED
;
2426 /* ADDBA exchange must be completed before sending aggregates */
2427 txtid
= ATH_AN_2_TID(an
, tidno
);
2429 if (txtid
->addba_exchangecomplete
)
2430 return AGGR_EXCHANGE_DONE
;
2432 if (txtid
->cleanup_inprogress
)
2433 return AGGR_CLEANUP_PROGRESS
;
2435 if (txtid
->addba_exchangeinprogress
)
2436 return AGGR_EXCHANGE_PROGRESS
;
2438 if (!txtid
->addba_exchangecomplete
) {
2439 if (!txtid
->addba_exchangeinprogress
&&
2440 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
2441 txtid
->addba_exchangeattempts
++;
2442 return AGGR_REQUIRED
;
2446 return AGGR_NOT_REQUIRED
;
2449 /* Start TX aggregation */
2451 int ath_tx_aggr_start(struct ath_softc
*sc
,
2456 struct ath_atx_tid
*txtid
;
2457 struct ath_node
*an
;
2459 spin_lock_bh(&sc
->node_lock
);
2460 an
= ath_node_find(sc
, (u8
*) addr
);
2461 spin_unlock_bh(&sc
->node_lock
);
2464 DPRINTF(sc
, ATH_DBG_AGGR
,
2465 "%s: Node not found to initialize "
2466 "TX aggregation\n", __func__
);
2470 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2471 txtid
= ATH_AN_2_TID(an
, tid
);
2472 txtid
->addba_exchangeinprogress
= 1;
2473 ath_tx_pause_tid(sc
, txtid
);
2479 /* Stop tx aggregation */
2481 int ath_tx_aggr_stop(struct ath_softc
*sc
,
2485 struct ath_node
*an
;
2487 spin_lock_bh(&sc
->node_lock
);
2488 an
= ath_node_find(sc
, (u8
*) addr
);
2489 spin_unlock_bh(&sc
->node_lock
);
2492 DPRINTF(sc
, ATH_DBG_AGGR
,
2493 "%s: TX aggr stop for non-existent node\n", __func__
);
2497 ath_tx_aggr_teardown(sc
, an
, tid
);
2502 * Performs transmit side cleanup when TID changes from aggregated to
2504 * - Pause the TID and mark cleanup in progress
2505 * - Discard all retry frames from the s/w queue.
2508 void ath_tx_aggr_teardown(struct ath_softc
*sc
,
2509 struct ath_node
*an
, u8 tid
)
2511 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
2512 struct ath_txq
*txq
= &sc
->sc_txq
[txtid
->ac
->qnum
];
2514 struct list_head bf_head
;
2515 INIT_LIST_HEAD(&bf_head
);
2517 DPRINTF(sc
, ATH_DBG_AGGR
, "%s: teardown TX aggregation\n", __func__
);
2519 if (txtid
->cleanup_inprogress
) /* cleanup is in progress */
2522 if (!txtid
->addba_exchangecomplete
) {
2523 txtid
->addba_exchangeattempts
= 0;
2527 /* TID must be paused first */
2528 ath_tx_pause_tid(sc
, txtid
);
2530 /* drop all software retried frames and mark this TID */
2531 spin_lock_bh(&txq
->axq_lock
);
2532 while (!list_empty(&txtid
->buf_q
)) {
2533 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
2534 if (!bf_isretried(bf
)) {
2536 * NB: it's based on the assumption that
2537 * software retried frame will always stay
2538 * at the head of software queue.
2542 list_cut_position(&bf_head
,
2543 &txtid
->buf_q
, &bf
->bf_lastfrm
->list
);
2544 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
2546 /* complete this sub-frame */
2547 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2550 if (txtid
->baw_head
!= txtid
->baw_tail
) {
2551 spin_unlock_bh(&txq
->axq_lock
);
2552 txtid
->cleanup_inprogress
= true;
2554 txtid
->addba_exchangecomplete
= 0;
2555 txtid
->addba_exchangeattempts
= 0;
2556 spin_unlock_bh(&txq
->axq_lock
);
2557 ath_tx_flush_tid(sc
, txtid
);
2562 * Tx scheduling logic
2563 * NB: must be called with txq lock held
2566 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
2568 struct ath_atx_ac
*ac
;
2569 struct ath_atx_tid
*tid
;
2571 /* nothing to schedule */
2572 if (list_empty(&txq
->axq_acq
))
2575 * get the first node/ac pair on the queue
2577 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
2578 list_del(&ac
->list
);
2582 * process a single tid per destination
2585 /* nothing to schedule */
2586 if (list_empty(&ac
->tid_q
))
2589 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
2590 list_del(&tid
->list
);
2593 if (tid
->paused
) /* check next tid to keep h/w busy */
2596 if (!(tid
->an
->an_smmode
== ATH_SM_PWRSAV_DYNAMIC
) ||
2597 ((txq
->axq_depth
% 2) == 0)) {
2598 ath_tx_sched_aggr(sc
, txq
, tid
);
2602 * add tid to round-robin queue if more frames
2603 * are pending for the tid
2605 if (!list_empty(&tid
->buf_q
))
2606 ath_tx_queue_tid(txq
, tid
);
2608 /* only schedule one TID at a time */
2610 } while (!list_empty(&ac
->tid_q
));
2613 * schedule AC if more TIDs need processing
2615 if (!list_empty(&ac
->tid_q
)) {
2617 * add dest ac to txq if not already added
2621 list_add_tail(&ac
->list
, &txq
->axq_acq
);
2626 /* Initialize per-node transmit state */
2628 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2630 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2631 struct ath_atx_tid
*tid
;
2632 struct ath_atx_ac
*ac
;
2635 an
->maxampdu
= ATH_AMPDU_LIMIT_DEFAULT
;
2638 * Init per tid tx state
2640 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2641 tidno
< WME_NUM_TID
;
2645 tid
->seq_start
= tid
->seq_next
= 0;
2646 tid
->baw_size
= WME_MAX_BA
;
2647 tid
->baw_head
= tid
->baw_tail
= 0;
2649 tid
->paused
= false;
2650 tid
->cleanup_inprogress
= false;
2651 INIT_LIST_HEAD(&tid
->buf_q
);
2653 acno
= TID_TO_WME_AC(tidno
);
2654 tid
->ac
= &an
->an_aggr
.tx
.ac
[acno
];
2657 tid
->addba_exchangecomplete
= 0;
2658 tid
->addba_exchangeinprogress
= 0;
2659 tid
->addba_exchangeattempts
= 0;
2663 * Init per ac tx state
2665 for (acno
= 0, ac
= &an
->an_aggr
.tx
.ac
[acno
];
2666 acno
< WME_NUM_AC
; acno
++, ac
++) {
2668 INIT_LIST_HEAD(&ac
->tid_q
);
2672 ac
->qnum
= ath_tx_get_qnum(sc
,
2673 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2676 ac
->qnum
= ath_tx_get_qnum(sc
,
2677 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2680 ac
->qnum
= ath_tx_get_qnum(sc
,
2681 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2684 ac
->qnum
= ath_tx_get_qnum(sc
,
2685 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2692 /* Cleanupthe pending buffers for the node. */
2694 void ath_tx_node_cleanup(struct ath_softc
*sc
,
2695 struct ath_node
*an
, bool bh_flag
)
2698 struct ath_atx_ac
*ac
, *ac_tmp
;
2699 struct ath_atx_tid
*tid
, *tid_tmp
;
2700 struct ath_txq
*txq
;
2701 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2702 if (ATH_TXQ_SETUP(sc
, i
)) {
2703 txq
= &sc
->sc_txq
[i
];
2705 if (likely(bh_flag
))
2706 spin_lock_bh(&txq
->axq_lock
);
2708 spin_lock(&txq
->axq_lock
);
2710 list_for_each_entry_safe(ac
,
2711 ac_tmp
, &txq
->axq_acq
, list
) {
2712 tid
= list_first_entry(&ac
->tid_q
,
2713 struct ath_atx_tid
, list
);
2714 if (tid
&& tid
->an
!= an
)
2716 list_del(&ac
->list
);
2719 list_for_each_entry_safe(tid
,
2720 tid_tmp
, &ac
->tid_q
, list
) {
2721 list_del(&tid
->list
);
2723 ath_tid_drain(sc
, txq
, tid
, bh_flag
);
2724 tid
->addba_exchangecomplete
= 0;
2725 tid
->addba_exchangeattempts
= 0;
2726 tid
->cleanup_inprogress
= false;
2730 if (likely(bh_flag
))
2731 spin_unlock_bh(&txq
->axq_lock
);
2733 spin_unlock(&txq
->axq_lock
);
2738 /* Cleanup per node transmit state */
2740 void ath_tx_node_free(struct ath_softc
*sc
, struct ath_node
*an
)
2742 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2743 struct ath_atx_tid
*tid
;
2746 /* Init per tid rx state */
2747 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2748 tidno
< WME_NUM_TID
;
2751 for (i
= 0; i
< ATH_TID_MAX_BUFS
; i
++)
2752 ASSERT(tid
->tx_buf
[i
] == NULL
);
2757 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2759 int hdrlen
, padsize
;
2760 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2761 struct ath_tx_control txctl
;
2764 * As a temporary workaround, assign seq# here; this will likely need
2765 * to be cleaned up to work better with Beacon transmission and virtual
2768 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2769 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2770 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2772 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2773 hdr
->seq_ctrl
|= cpu_to_le16(sc
->seq_no
);
2776 /* Add the padding after the header if this is not already done */
2777 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2779 padsize
= hdrlen
% 4;
2780 if (skb_headroom(skb
) < padsize
) {
2781 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX CABQ padding "
2782 "failed\n", __func__
);
2783 dev_kfree_skb_any(skb
);
2786 skb_push(skb
, padsize
);
2787 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2790 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: transmitting CABQ packet, skb: %p\n",
2794 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2795 txctl
.flags
= ATH9K_TXDESC_CAB
;
2796 if (ath_tx_prepare(sc
, skb
, &txctl
) == 0) {
2798 * Start DMA mapping.
2799 * ath_tx_start_dma() will be called either synchronously
2800 * or asynchrounsly once DMA is complete.
2802 xmit_map_sg(sc
, skb
, &txctl
);
2804 ath_node_put(sc
, txctl
.an
, ATH9K_BH_STATUS_CHANGE
);
2805 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX CABQ failed\n", __func__
);
2806 dev_kfree_skb_any(skb
);