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memcg: optimize per-cpu statistics
[linux-2.6/sactl.git] / sound / pci / intel8x0m.c
blob93449e464566c019a5a0a3c11677bd8b2654fc56
1 /*
2 * ALSA modem driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
7 * of ALSA ICH sound driver intel8x0.c .
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26 #include <asm/io.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/moduleparam.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/ac97_codec.h>
36 #include <sound/info.h>
37 #include <sound/initval.h>
38
39 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
40 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
41 "SiS 7013; NVidia MCP/2/2S/3 modems");
42 MODULE_LICENSE("GPL");
43 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
44 "{Intel,82901AB-ICH0},"
45 "{Intel,82801BA-ICH2},"
46 "{Intel,82801CA-ICH3},"
47 "{Intel,82801DB-ICH4},"
48 "{Intel,ICH5},"
49 "{Intel,ICH6},"
50 "{Intel,ICH7},"
51 "{Intel,MX440},"
52 "{SiS,7013},"
53 "{NVidia,NForce Modem},"
54 "{NVidia,NForce2 Modem},"
55 "{NVidia,NForce2s Modem},"
56 "{NVidia,NForce3 Modem},"
57 "{AMD,AMD768}}");
58
59 static int index = -2; /* Exclude the first card */
60 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
61 static int ac97_clock;
62
63 module_param(index, int, 0444);
64 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
65 module_param(id, charp, 0444);
66 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
67 module_param(ac97_clock, int, 0444);
68 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
69
70 /* just for backward compatibility */
71 static int enable;
72 module_param(enable, bool, 0444);
73
74 /*
75 * Direct registers
76 */
77 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
78
79 #define ICHREG(x) ICH_REG_##x
80
81 #define DEFINE_REGSET(name,base) \
82 enum { \
83 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
84 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
85 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
86 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
87 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
88 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
89 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
90 };
91
92 /* busmaster blocks */
93 DEFINE_REGSET(OFF, 0); /* offset */
94
95 /* values for each busmaster block */
96
97 /* LVI */
98 #define ICH_REG_LVI_MASK 0x1f
99
100 /* SR */
101 #define ICH_FIFOE 0x10 /* FIFO error */
102 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
103 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
104 #define ICH_CELV 0x02 /* current equals last valid */
105 #define ICH_DCH 0x01 /* DMA controller halted */
106
107 /* PIV */
108 #define ICH_REG_PIV_MASK 0x1f /* mask */
109
110 /* CR */
111 #define ICH_IOCE 0x10 /* interrupt on completion enable */
112 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
113 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
114 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
115 #define ICH_STARTBM 0x01 /* start busmaster operation */
116
117
118 /* global block */
119 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
120 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
121 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
122 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
123 #define ICH_ACLINK 0x00000008 /* AClink shut off */
124 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
125 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
126 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
127 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */
128 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
129 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
130 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
131 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
132 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
133 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
134 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
135 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
136 #define ICH_MD3 0x00020000 /* modem power down semaphore */
137 #define ICH_AD3 0x00010000 /* audio power down semaphore */
138 #define ICH_RCS 0x00008000 /* read completion status */
139 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
140 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
141 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
142 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
143 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
144 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
145 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
146 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
147 #define ICH_POINT 0x00000040 /* playback interrupt */
148 #define ICH_PIINT 0x00000020 /* capture interrupt */
149 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
150 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
151 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
152 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
153 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
154 #define ICH_CAS 0x01 /* codec access semaphore */
155
156 #define ICH_MAX_FRAGS 32 /* max hw frags */
157
158
159 /*
160 *
161 */
162
163 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
164 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
165
166 #define get_ichdev(substream) (substream->runtime->private_data)
167
168 struct ichdev {
169 unsigned int ichd; /* ich device number */
170 unsigned long reg_offset; /* offset to bmaddr */
171 u32 *bdbar; /* CPU address (32bit) */
172 unsigned int bdbar_addr; /* PCI bus address (32bit) */
173 struct snd_pcm_substream *substream;
174 unsigned int physbuf; /* physical address (32bit) */
175 unsigned int size;
176 unsigned int fragsize;
177 unsigned int fragsize1;
178 unsigned int position;
179 int frags;
180 int lvi;
181 int lvi_frag;
182 int civ;
183 int ack;
184 int ack_reload;
185 unsigned int ack_bit;
186 unsigned int roff_sr;
187 unsigned int roff_picb;
188 unsigned int int_sta_mask; /* interrupt status mask */
189 unsigned int ali_slot; /* ALI DMA slot */
190 struct snd_ac97 *ac97;
191 };
192
193 struct intel8x0m {
194 unsigned int device_type;
195
196 int irq;
197
198 void __iomem *addr;
199 void __iomem *bmaddr;
200
201 struct pci_dev *pci;
202 struct snd_card *card;
203
204 int pcm_devs;
205 struct snd_pcm *pcm[2];
206 struct ichdev ichd[2];
207
208 unsigned int in_ac97_init: 1;
209
210 struct snd_ac97_bus *ac97_bus;
211 struct snd_ac97 *ac97;
212
213 spinlock_t reg_lock;
214
215 struct snd_dma_buffer bdbars;
216 u32 bdbars_count;
217 u32 int_sta_reg; /* interrupt status register */
218 u32 int_sta_mask; /* interrupt status mask */
219 unsigned int pcm_pos_shift;
220 };
221
222 static struct pci_device_id snd_intel8x0m_ids[] = {
223 { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
224 { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
225 { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
226 { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
227 { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
228 { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
229 { 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */
230 { 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */
231 { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
232 { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
233 { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */
234 { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
235 { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
236 { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */
237 { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
238 #if 0
239 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
240 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
241 #endif
242 { 0, }
243 };
244
245 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
246
247 /*
248 * Lowlevel I/O - busmaster
249 */
250
251 static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
252 {
253 return ioread8(chip->bmaddr + offset);
254 }
255
256 static inline u16 igetword(struct intel8x0m *chip, u32 offset)
257 {
258 return ioread16(chip->bmaddr + offset);
259 }
260
261 static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
262 {
263 return ioread32(chip->bmaddr + offset);
264 }
265
266 static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
267 {
268 iowrite8(val, chip->bmaddr + offset);
269 }
270
271 static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
272 {
273 iowrite16(val, chip->bmaddr + offset);
274 }
275
276 static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
277 {
278 iowrite32(val, chip->bmaddr + offset);
279 }
280
281 /*
282 * Lowlevel I/O - AC'97 registers
283 */
284
285 static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
286 {
287 return ioread16(chip->addr + offset);
288 }
289
290 static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
291 {
292 iowrite16(val, chip->addr + offset);
293 }
294
295 /*
296 * Basic I/O
297 */
298
299 /*
300 * access to AC97 codec via normal i/o (for ICH and SIS7013)
301 */
302
303 /* return the GLOB_STA bit for the corresponding codec */
304 static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
305 {
306 static unsigned int codec_bit[3] = {
307 ICH_PCR, ICH_SCR, ICH_TCR
308 };
309 if (snd_BUG_ON(codec >= 3))
310 return ICH_PCR;
311 return codec_bit[codec];
312 }
313
314 static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
315 {
316 int time;
317
318 if (codec > 1)
319 return -EIO;
320 codec = get_ich_codec_bit(chip, codec);
321
322 /* codec ready ? */
323 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
324 return -EIO;
325
326 /* Anyone holding a semaphore for 1 msec should be shot... */
327 time = 100;
328 do {
329 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
330 return 0;
331 udelay(10);
332 } while (time--);
333
334 /* access to some forbidden (non existant) ac97 registers will not
335 * reset the semaphore. So even if you don't get the semaphore, still
336 * continue the access. We don't need the semaphore anyway. */
337 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
338 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
339 iagetword(chip, 0); /* clear semaphore flag */
340 /* I don't care about the semaphore */
341 return -EBUSY;
342 }
343
344 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
345 unsigned short reg,
346 unsigned short val)
347 {
348 struct intel8x0m *chip = ac97->private_data;
349
350 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
351 if (! chip->in_ac97_init)
352 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
353 }
354 iaputword(chip, reg + ac97->num * 0x80, val);
355 }
356
357 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
358 unsigned short reg)
359 {
360 struct intel8x0m *chip = ac97->private_data;
361 unsigned short res;
362 unsigned int tmp;
363
364 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
365 if (! chip->in_ac97_init)
366 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
367 res = 0xffff;
368 } else {
369 res = iagetword(chip, reg + ac97->num * 0x80);
370 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
371 /* reset RCS and preserve other R/WC bits */
372 iputdword(chip, ICHREG(GLOB_STA),
373 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
374 if (! chip->in_ac97_init)
375 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
376 res = 0xffff;
377 }
378 }
379 if (reg == AC97_GPIO_STATUS)
380 iagetword(chip, 0); /* clear semaphore */
381 return res;
382 }
383
384
385 /*
386 * DMA I/O
387 */
388 static void snd_intel8x0_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
389 {
390 int idx;
391 u32 *bdbar = ichdev->bdbar;
392 unsigned long port = ichdev->reg_offset;
393
394 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
395 if (ichdev->size == ichdev->fragsize) {
396 ichdev->ack_reload = ichdev->ack = 2;
397 ichdev->fragsize1 = ichdev->fragsize >> 1;
398 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
399 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
400 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
401 ichdev->fragsize1 >> chip->pcm_pos_shift);
402 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
403 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
404 ichdev->fragsize1 >> chip->pcm_pos_shift);
405 }
406 ichdev->frags = 2;
407 } else {
408 ichdev->ack_reload = ichdev->ack = 1;
409 ichdev->fragsize1 = ichdev->fragsize;
410 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
411 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
412 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
413 ichdev->fragsize >> chip->pcm_pos_shift);
414 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
415 }
416 ichdev->frags = ichdev->size / ichdev->fragsize;
417 }
418 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
419 ichdev->civ = 0;
420 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
421 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
422 ichdev->position = 0;
423 #if 0
424 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
425 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
426 #endif
427 /* clear interrupts */
428 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
429 }
430
431 /*
432 * Interrupt handler
433 */
434
435 static inline void snd_intel8x0_update(struct intel8x0m *chip, struct ichdev *ichdev)
436 {
437 unsigned long port = ichdev->reg_offset;
438 int civ, i, step;
439 int ack = 0;
440
441 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
442 if (civ == ichdev->civ) {
443 // snd_printd("civ same %d\n", civ);
444 step = 1;
445 ichdev->civ++;
446 ichdev->civ &= ICH_REG_LVI_MASK;
447 } else {
448 step = civ - ichdev->civ;
449 if (step < 0)
450 step += ICH_REG_LVI_MASK + 1;
451 // if (step != 1)
452 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
453 ichdev->civ = civ;
454 }
455
456 ichdev->position += step * ichdev->fragsize1;
457 ichdev->position %= ichdev->size;
458 ichdev->lvi += step;
459 ichdev->lvi &= ICH_REG_LVI_MASK;
460 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
461 for (i = 0; i < step; i++) {
462 ichdev->lvi_frag++;
463 ichdev->lvi_frag %= ichdev->frags;
464 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
465 ichdev->lvi_frag *
466 ichdev->fragsize1);
467 #if 0
468 printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
469 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
470 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
471 inl(port + 4), inb(port + ICH_REG_OFF_CR));
472 #endif
473 if (--ichdev->ack == 0) {
474 ichdev->ack = ichdev->ack_reload;
475 ack = 1;
476 }
477 }
478 if (ack && ichdev->substream) {
479 spin_unlock(&chip->reg_lock);
480 snd_pcm_period_elapsed(ichdev->substream);
481 spin_lock(&chip->reg_lock);
482 }
483 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
484 }
485
486 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
487 {
488 struct intel8x0m *chip = dev_id;
489 struct ichdev *ichdev;
490 unsigned int status;
491 unsigned int i;
492
493 spin_lock(&chip->reg_lock);
494 status = igetdword(chip, chip->int_sta_reg);
495 if (status == 0xffffffff) { /* we are not yet resumed */
496 spin_unlock(&chip->reg_lock);
497 return IRQ_NONE;
498 }
499 if ((status & chip->int_sta_mask) == 0) {
500 if (status)
501 iputdword(chip, chip->int_sta_reg, status);
502 spin_unlock(&chip->reg_lock);
503 return IRQ_NONE;
504 }
505
506 for (i = 0; i < chip->bdbars_count; i++) {
507 ichdev = &chip->ichd[i];
508 if (status & ichdev->int_sta_mask)
509 snd_intel8x0_update(chip, ichdev);
510 }
511
512 /* ack them */
513 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
514 spin_unlock(&chip->reg_lock);
515
516 return IRQ_HANDLED;
517 }
518
519 /*
520 * PCM part
521 */
522
523 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
524 {
525 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
526 struct ichdev *ichdev = get_ichdev(substream);
527 unsigned char val = 0;
528 unsigned long port = ichdev->reg_offset;
529
530 switch (cmd) {
531 case SNDRV_PCM_TRIGGER_START:
532 case SNDRV_PCM_TRIGGER_RESUME:
533 val = ICH_IOCE | ICH_STARTBM;
534 break;
535 case SNDRV_PCM_TRIGGER_STOP:
536 case SNDRV_PCM_TRIGGER_SUSPEND:
537 val = 0;
538 break;
539 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
540 val = ICH_IOCE;
541 break;
542 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
543 val = ICH_IOCE | ICH_STARTBM;
544 break;
545 default:
546 return -EINVAL;
547 }
548 iputbyte(chip, port + ICH_REG_OFF_CR, val);
549 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
550 /* wait until DMA stopped */
551 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
552 /* reset whole DMA things */
553 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
554 }
555 return 0;
556 }
557
558 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
559 struct snd_pcm_hw_params *hw_params)
560 {
561 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
562 }
563
564 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
565 {
566 return snd_pcm_lib_free_pages(substream);
567 }
568
569 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
570 {
571 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
572 struct ichdev *ichdev = get_ichdev(substream);
573 size_t ptr1, ptr;
574
575 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
576 if (ptr1 != 0)
577 ptr = ichdev->fragsize1 - ptr1;
578 else
579 ptr = 0;
580 ptr += ichdev->position;
581 if (ptr >= ichdev->size)
582 return 0;
583 return bytes_to_frames(substream->runtime, ptr);
584 }
585
586 static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
587 {
588 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
589 struct snd_pcm_runtime *runtime = substream->runtime;
590 struct ichdev *ichdev = get_ichdev(substream);
591
592 ichdev->physbuf = runtime->dma_addr;
593 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
594 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
595 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
596 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
597 snd_intel8x0_setup_periods(chip, ichdev);
598 return 0;
599 }
600
601 static struct snd_pcm_hardware snd_intel8x0m_stream =
602 {
603 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
604 SNDRV_PCM_INFO_BLOCK_TRANSFER |
605 SNDRV_PCM_INFO_MMAP_VALID |
606 SNDRV_PCM_INFO_PAUSE |
607 SNDRV_PCM_INFO_RESUME),
608 .formats = SNDRV_PCM_FMTBIT_S16_LE,
609 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
610 .rate_min = 8000,
611 .rate_max = 16000,
612 .channels_min = 1,
613 .channels_max = 1,
614 .buffer_bytes_max = 64 * 1024,
615 .period_bytes_min = 32,
616 .period_bytes_max = 64 * 1024,
617 .periods_min = 1,
618 .periods_max = 1024,
619 .fifo_size = 0,
620 };
621
622
623 static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
624 {
625 static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
626 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
627 .count = ARRAY_SIZE(rates),
628 .list = rates,
629 .mask = 0,
630 };
631 struct snd_pcm_runtime *runtime = substream->runtime;
632 int err;
633
634 ichdev->substream = substream;
635 runtime->hw = snd_intel8x0m_stream;
636 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
637 &hw_constraints_rates);
638 if ( err < 0 )
639 return err;
640 runtime->private_data = ichdev;
641 return 0;
642 }
643
644 static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
645 {
646 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
647
648 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
649 }
650
651 static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
652 {
653 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
654
655 chip->ichd[ICHD_MDMOUT].substream = NULL;
656 return 0;
657 }
658
659 static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
660 {
661 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
662
663 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
664 }
665
666 static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
667 {
668 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
669
670 chip->ichd[ICHD_MDMIN].substream = NULL;
671 return 0;
672 }
673
674
675 static struct snd_pcm_ops snd_intel8x0m_playback_ops = {
676 .open = snd_intel8x0m_playback_open,
677 .close = snd_intel8x0m_playback_close,
678 .ioctl = snd_pcm_lib_ioctl,
679 .hw_params = snd_intel8x0_hw_params,
680 .hw_free = snd_intel8x0_hw_free,
681 .prepare = snd_intel8x0m_pcm_prepare,
682 .trigger = snd_intel8x0_pcm_trigger,
683 .pointer = snd_intel8x0_pcm_pointer,
684 };
685
686 static struct snd_pcm_ops snd_intel8x0m_capture_ops = {
687 .open = snd_intel8x0m_capture_open,
688 .close = snd_intel8x0m_capture_close,
689 .ioctl = snd_pcm_lib_ioctl,
690 .hw_params = snd_intel8x0_hw_params,
691 .hw_free = snd_intel8x0_hw_free,
692 .prepare = snd_intel8x0m_pcm_prepare,
693 .trigger = snd_intel8x0_pcm_trigger,
694 .pointer = snd_intel8x0_pcm_pointer,
695 };
696
697
698 struct ich_pcm_table {
699 char *suffix;
700 struct snd_pcm_ops *playback_ops;
701 struct snd_pcm_ops *capture_ops;
702 size_t prealloc_size;
703 size_t prealloc_max_size;
704 int ac97_idx;
705 };
706
707 static int __devinit snd_intel8x0_pcm1(struct intel8x0m *chip, int device,
708 struct ich_pcm_table *rec)
709 {
710 struct snd_pcm *pcm;
711 int err;
712 char name[32];
713
714 if (rec->suffix)
715 sprintf(name, "Intel ICH - %s", rec->suffix);
716 else
717 strcpy(name, "Intel ICH");
718 err = snd_pcm_new(chip->card, name, device,
719 rec->playback_ops ? 1 : 0,
720 rec->capture_ops ? 1 : 0, &pcm);
721 if (err < 0)
722 return err;
723
724 if (rec->playback_ops)
725 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
726 if (rec->capture_ops)
727 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
728
729 pcm->private_data = chip;
730 pcm->info_flags = 0;
731 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
732 if (rec->suffix)
733 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
734 else
735 strcpy(pcm->name, chip->card->shortname);
736 chip->pcm[device] = pcm;
737
738 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
739 snd_dma_pci_data(chip->pci),
740 rec->prealloc_size,
741 rec->prealloc_max_size);
742
743 return 0;
744 }
745
746 static struct ich_pcm_table intel_pcms[] __devinitdata = {
747 {
748 .suffix = "Modem",
749 .playback_ops = &snd_intel8x0m_playback_ops,
750 .capture_ops = &snd_intel8x0m_capture_ops,
751 .prealloc_size = 32 * 1024,
752 .prealloc_max_size = 64 * 1024,
753 },
754 };
755
756 static int __devinit snd_intel8x0_pcm(struct intel8x0m *chip)
757 {
758 int i, tblsize, device, err;
759 struct ich_pcm_table *tbl, *rec;
760
761 #if 1
762 tbl = intel_pcms;
763 tblsize = 1;
764 #else
765 switch (chip->device_type) {
766 case DEVICE_NFORCE:
767 tbl = nforce_pcms;
768 tblsize = ARRAY_SIZE(nforce_pcms);
769 break;
770 case DEVICE_ALI:
771 tbl = ali_pcms;
772 tblsize = ARRAY_SIZE(ali_pcms);
773 break;
774 default:
775 tbl = intel_pcms;
776 tblsize = 2;
777 break;
778 }
779 #endif
780 device = 0;
781 for (i = 0; i < tblsize; i++) {
782 rec = tbl + i;
783 if (i > 0 && rec->ac97_idx) {
784 /* activate PCM only when associated AC'97 codec */
785 if (! chip->ichd[rec->ac97_idx].ac97)
786 continue;
787 }
788 err = snd_intel8x0_pcm1(chip, device, rec);
789 if (err < 0)
790 return err;
791 device++;
792 }
793
794 chip->pcm_devs = device;
795 return 0;
796 }
797
798
799 /*
800 * Mixer part
801 */
802
803 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
804 {
805 struct intel8x0m *chip = bus->private_data;
806 chip->ac97_bus = NULL;
807 }
808
809 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
810 {
811 struct intel8x0m *chip = ac97->private_data;
812 chip->ac97 = NULL;
813 }
814
815
816 static int __devinit snd_intel8x0_mixer(struct intel8x0m *chip, int ac97_clock)
817 {
818 struct snd_ac97_bus *pbus;
819 struct snd_ac97_template ac97;
820 struct snd_ac97 *x97;
821 int err;
822 unsigned int glob_sta = 0;
823 static struct snd_ac97_bus_ops ops = {
824 .write = snd_intel8x0_codec_write,
825 .read = snd_intel8x0_codec_read,
826 };
827
828 chip->in_ac97_init = 1;
829
830 memset(&ac97, 0, sizeof(ac97));
831 ac97.private_data = chip;
832 ac97.private_free = snd_intel8x0_mixer_free_ac97;
833 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
834
835 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
836
837 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
838 goto __err;
839 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
840 if (ac97_clock >= 8000 && ac97_clock <= 48000)
841 pbus->clock = ac97_clock;
842 chip->ac97_bus = pbus;
843
844 ac97.pci = chip->pci;
845 ac97.num = glob_sta & ICH_SCR ? 1 : 0;
846 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
847 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
848 if (ac97.num == 0)
849 goto __err;
850 return err;
851 }
852 chip->ac97 = x97;
853 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
854 chip->ichd[ICHD_MDMIN].ac97 = x97;
855 chip->ichd[ICHD_MDMOUT].ac97 = x97;
856 }
857
858 chip->in_ac97_init = 0;
859 return 0;
860
861 __err:
862 /* clear the cold-reset bit for the next chance */
863 if (chip->device_type != DEVICE_ALI)
864 iputdword(chip, ICHREG(GLOB_CNT),
865 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
866 return err;
867 }
868
869
870 /*
871 *
872 */
873
874 static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
875 {
876 unsigned long end_time;
877 unsigned int cnt, status, nstatus;
878
879 /* put logic to right state */
880 /* first clear status bits */
881 status = ICH_RCS | ICH_MIINT | ICH_MOINT;
882 cnt = igetdword(chip, ICHREG(GLOB_STA));
883 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
884
885 /* ACLink on, 2 channels */
886 cnt = igetdword(chip, ICHREG(GLOB_CNT));
887 cnt &= ~(ICH_ACLINK);
888 /* finish cold or do warm reset */
889 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
890 iputdword(chip, ICHREG(GLOB_CNT), cnt);
891 end_time = (jiffies + (HZ / 4)) + 1;
892 do {
893 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
894 goto __ok;
895 schedule_timeout_uninterruptible(1);
896 } while (time_after_eq(end_time, jiffies));
897 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
898 igetdword(chip, ICHREG(GLOB_CNT)));
899 return -EIO;
900
901 __ok:
902 if (probing) {
903 /* wait for any codec ready status.
904 * Once it becomes ready it should remain ready
905 * as long as we do not disable the ac97 link.
906 */
907 end_time = jiffies + HZ;
908 do {
909 status = igetdword(chip, ICHREG(GLOB_STA)) &
910 (ICH_PCR | ICH_SCR | ICH_TCR);
911 if (status)
912 break;
913 schedule_timeout_uninterruptible(1);
914 } while (time_after_eq(end_time, jiffies));
915 if (! status) {
916 /* no codec is found */
917 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
918 igetdword(chip, ICHREG(GLOB_STA)));
919 return -EIO;
920 }
921
922 /* up to two codecs (modem cannot be tertiary with ICH4) */
923 nstatus = ICH_PCR | ICH_SCR;
924
925 /* wait for other codecs ready status. */
926 end_time = jiffies + HZ / 4;
927 while (status != nstatus && time_after_eq(end_time, jiffies)) {
928 schedule_timeout_uninterruptible(1);
929 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
930 }
931
932 } else {
933 /* resume phase */
934 status = 0;
935 if (chip->ac97)
936 status |= get_ich_codec_bit(chip, chip->ac97->num);
937 /* wait until all the probed codecs are ready */
938 end_time = jiffies + HZ;
939 do {
940 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
941 (ICH_PCR | ICH_SCR | ICH_TCR);
942 if (status == nstatus)
943 break;
944 schedule_timeout_uninterruptible(1);
945 } while (time_after_eq(end_time, jiffies));
946 }
947
948 if (chip->device_type == DEVICE_SIS) {
949 /* unmute the output on SIS7012 */
950 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
951 }
952
953 return 0;
954 }
955
956 static int snd_intel8x0_chip_init(struct intel8x0m *chip, int probing)
957 {
958 unsigned int i;
959 int err;
960
961 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
962 return err;
963 iagetword(chip, 0); /* clear semaphore flag */
964
965 /* disable interrupts */
966 for (i = 0; i < chip->bdbars_count; i++)
967 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
968 /* reset channels */
969 for (i = 0; i < chip->bdbars_count; i++)
970 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
971 /* initialize Buffer Descriptor Lists */
972 for (i = 0; i < chip->bdbars_count; i++)
973 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
974 return 0;
975 }
976
977 static int snd_intel8x0_free(struct intel8x0m *chip)
978 {
979 unsigned int i;
980
981 if (chip->irq < 0)
982 goto __hw_end;
983 /* disable interrupts */
984 for (i = 0; i < chip->bdbars_count; i++)
985 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
986 /* reset channels */
987 for (i = 0; i < chip->bdbars_count; i++)
988 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
989 __hw_end:
990 if (chip->irq >= 0)
991 free_irq(chip->irq, chip);
992 if (chip->bdbars.area)
993 snd_dma_free_pages(&chip->bdbars);
994 if (chip->addr)
995 pci_iounmap(chip->pci, chip->addr);
996 if (chip->bmaddr)
997 pci_iounmap(chip->pci, chip->bmaddr);
998 pci_release_regions(chip->pci);
999 pci_disable_device(chip->pci);
1000 kfree(chip);
1001 return 0;
1002 }
1003
1004 #ifdef CONFIG_PM
1005 /*
1006 * power management
1007 */
1008 static int intel8x0m_suspend(struct pci_dev *pci, pm_message_t state)
1009 {
1010 struct snd_card *card = pci_get_drvdata(pci);
1011 struct intel8x0m *chip = card->private_data;
1012 int i;
1013
1014 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1015 for (i = 0; i < chip->pcm_devs; i++)
1016 snd_pcm_suspend_all(chip->pcm[i]);
1017 snd_ac97_suspend(chip->ac97);
1018 if (chip->irq >= 0) {
1019 free_irq(chip->irq, chip);
1020 chip->irq = -1;
1021 }
1022 pci_disable_device(pci);
1023 pci_save_state(pci);
1024 pci_set_power_state(pci, pci_choose_state(pci, state));
1025 return 0;
1026 }
1027
1028 static int intel8x0m_resume(struct pci_dev *pci)
1029 {
1030 struct snd_card *card = pci_get_drvdata(pci);
1031 struct intel8x0m *chip = card->private_data;
1032
1033 pci_set_power_state(pci, PCI_D0);
1034 pci_restore_state(pci);
1035 if (pci_enable_device(pci) < 0) {
1036 printk(KERN_ERR "intel8x0m: pci_enable_device failed, "
1037 "disabling device\n");
1038 snd_card_disconnect(card);
1039 return -EIO;
1040 }
1041 pci_set_master(pci);
1042 if (request_irq(pci->irq, snd_intel8x0_interrupt,
1043 IRQF_SHARED, card->shortname, chip)) {
1044 printk(KERN_ERR "intel8x0m: unable to grab IRQ %d, "
1045 "disabling device\n", pci->irq);
1046 snd_card_disconnect(card);
1047 return -EIO;
1048 }
1049 chip->irq = pci->irq;
1050 snd_intel8x0_chip_init(chip, 0);
1051 snd_ac97_resume(chip->ac97);
1052
1053 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1054 return 0;
1055 }
1056 #endif /* CONFIG_PM */
1057
1058 #ifdef CONFIG_PROC_FS
1059 static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1060 struct snd_info_buffer *buffer)
1061 {
1062 struct intel8x0m *chip = entry->private_data;
1063 unsigned int tmp;
1064
1065 snd_iprintf(buffer, "Intel8x0m\n\n");
1066 if (chip->device_type == DEVICE_ALI)
1067 return;
1068 tmp = igetdword(chip, ICHREG(GLOB_STA));
1069 snd_iprintf(buffer, "Global control : 0x%08x\n",
1070 igetdword(chip, ICHREG(GLOB_CNT)));
1071 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1072 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1073 tmp & ICH_PCR ? " primary" : "",
1074 tmp & ICH_SCR ? " secondary" : "",
1075 tmp & ICH_TCR ? " tertiary" : "",
1076 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1077 }
1078
1079 static void __devinit snd_intel8x0m_proc_init(struct intel8x0m * chip)
1080 {
1081 struct snd_info_entry *entry;
1082
1083 if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1084 snd_info_set_text_ops(entry, chip, snd_intel8x0m_proc_read);
1085 }
1086 #else /* !CONFIG_PROC_FS */
1087 #define snd_intel8x0m_proc_init(chip)
1088 #endif /* CONFIG_PROC_FS */
1089
1090
1091 static int snd_intel8x0_dev_free(struct snd_device *device)
1092 {
1093 struct intel8x0m *chip = device->device_data;
1094 return snd_intel8x0_free(chip);
1095 }
1096
1097 struct ich_reg_info {
1098 unsigned int int_sta_mask;
1099 unsigned int offset;
1100 };
1101
1102 static int __devinit snd_intel8x0m_create(struct snd_card *card,
1103 struct pci_dev *pci,
1104 unsigned long device_type,
1105 struct intel8x0m ** r_intel8x0)
1106 {
1107 struct intel8x0m *chip;
1108 int err;
1109 unsigned int i;
1110 unsigned int int_sta_masks;
1111 struct ichdev *ichdev;
1112 static struct snd_device_ops ops = {
1113 .dev_free = snd_intel8x0_dev_free,
1114 };
1115 static struct ich_reg_info intel_regs[2] = {
1116 { ICH_MIINT, 0 },
1117 { ICH_MOINT, 0x10 },
1118 };
1119 struct ich_reg_info *tbl;
1120
1121 *r_intel8x0 = NULL;
1122
1123 if ((err = pci_enable_device(pci)) < 0)
1124 return err;
1125
1126 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1127 if (chip == NULL) {
1128 pci_disable_device(pci);
1129 return -ENOMEM;
1130 }
1131 spin_lock_init(&chip->reg_lock);
1132 chip->device_type = device_type;
1133 chip->card = card;
1134 chip->pci = pci;
1135 chip->irq = -1;
1136
1137 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1138 kfree(chip);
1139 pci_disable_device(pci);
1140 return err;
1141 }
1142
1143 if (device_type == DEVICE_ALI) {
1144 /* ALI5455 has no ac97 region */
1145 chip->bmaddr = pci_iomap(pci, 0, 0);
1146 goto port_inited;
1147 }
1148
1149 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
1150 chip->addr = pci_iomap(pci, 2, 0);
1151 else
1152 chip->addr = pci_iomap(pci, 0, 0);
1153 if (!chip->addr) {
1154 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1155 snd_intel8x0_free(chip);
1156 return -EIO;
1157 }
1158 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
1159 chip->bmaddr = pci_iomap(pci, 3, 0);
1160 else
1161 chip->bmaddr = pci_iomap(pci, 1, 0);
1162 if (!chip->bmaddr) {
1163 snd_printk(KERN_ERR "Controller space ioremap problem\n");
1164 snd_intel8x0_free(chip);
1165 return -EIO;
1166 }
1167
1168 port_inited:
1169 if (request_irq(pci->irq, snd_intel8x0_interrupt, IRQF_SHARED,
1170 card->shortname, chip)) {
1171 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1172 snd_intel8x0_free(chip);
1173 return -EBUSY;
1174 }
1175 chip->irq = pci->irq;
1176 pci_set_master(pci);
1177 synchronize_irq(chip->irq);
1178
1179 /* initialize offsets */
1180 chip->bdbars_count = 2;
1181 tbl = intel_regs;
1182
1183 for (i = 0; i < chip->bdbars_count; i++) {
1184 ichdev = &chip->ichd[i];
1185 ichdev->ichd = i;
1186 ichdev->reg_offset = tbl[i].offset;
1187 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1188 if (device_type == DEVICE_SIS) {
1189 /* SiS 7013 swaps the registers */
1190 ichdev->roff_sr = ICH_REG_OFF_PICB;
1191 ichdev->roff_picb = ICH_REG_OFF_SR;
1192 } else {
1193 ichdev->roff_sr = ICH_REG_OFF_SR;
1194 ichdev->roff_picb = ICH_REG_OFF_PICB;
1195 }
1196 if (device_type == DEVICE_ALI)
1197 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1198 }
1199 /* SIS7013 handles the pcm data in bytes, others are in words */
1200 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1201
1202 /* allocate buffer descriptor lists */
1203 /* the start of each lists must be aligned to 8 bytes */
1204 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1205 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1206 &chip->bdbars) < 0) {
1207 snd_intel8x0_free(chip);
1208 return -ENOMEM;
1209 }
1210 /* tables must be aligned to 8 bytes here, but the kernel pages
1211 are much bigger, so we don't care (on i386) */
1212 int_sta_masks = 0;
1213 for (i = 0; i < chip->bdbars_count; i++) {
1214 ichdev = &chip->ichd[i];
1215 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1216 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1217 int_sta_masks |= ichdev->int_sta_mask;
1218 }
1219 chip->int_sta_reg = ICH_REG_GLOB_STA;
1220 chip->int_sta_mask = int_sta_masks;
1221
1222 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1223 snd_intel8x0_free(chip);
1224 return err;
1225 }
1226
1227 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1228 snd_intel8x0_free(chip);
1229 return err;
1230 }
1231
1232 snd_card_set_dev(card, &pci->dev);
1233
1234 *r_intel8x0 = chip;
1235 return 0;
1236 }
1237
1238 static struct shortname_table {
1239 unsigned int id;
1240 const char *s;
1241 } shortnames[] __devinitdata = {
1242 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1243 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1244 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1245 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1246 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1247 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1248 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1249 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1250 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1251 { 0x7446, "AMD AMD768" },
1252 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1253 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1254 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1255 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1256 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1257 #if 0
1258 { 0x5455, "ALi M5455" },
1259 { 0x746d, "AMD AMD8111" },
1260 #endif
1261 { 0 },
1262 };
1263
1264 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1265 const struct pci_device_id *pci_id)
1266 {
1267 struct snd_card *card;
1268 struct intel8x0m *chip;
1269 int err;
1270 struct shortname_table *name;
1271
1272 card = snd_card_new(index, id, THIS_MODULE, 0);
1273 if (card == NULL)
1274 return -ENOMEM;
1275
1276 strcpy(card->driver, "ICH-MODEM");
1277 strcpy(card->shortname, "Intel ICH");
1278 for (name = shortnames; name->id; name++) {
1279 if (pci->device == name->id) {
1280 strcpy(card->shortname, name->s);
1281 break;
1282 }
1283 }
1284 strcat(card->shortname," Modem");
1285
1286 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1287 snd_card_free(card);
1288 return err;
1289 }
1290 card->private_data = chip;
1291
1292 if ((err = snd_intel8x0_mixer(chip, ac97_clock)) < 0) {
1293 snd_card_free(card);
1294 return err;
1295 }
1296 if ((err = snd_intel8x0_pcm(chip)) < 0) {
1297 snd_card_free(card);
1298 return err;
1299 }
1300
1301 snd_intel8x0m_proc_init(chip);
1302
1303 sprintf(card->longname, "%s at irq %i",
1304 card->shortname, chip->irq);
1305
1306 if ((err = snd_card_register(card)) < 0) {
1307 snd_card_free(card);
1308 return err;
1309 }
1310 pci_set_drvdata(pci, card);
1311 return 0;
1312 }
1313
1314 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1315 {
1316 snd_card_free(pci_get_drvdata(pci));
1317 pci_set_drvdata(pci, NULL);
1318 }
1319
1320 static struct pci_driver driver = {
1321 .name = "Intel ICH Modem",
1322 .id_table = snd_intel8x0m_ids,
1323 .probe = snd_intel8x0m_probe,
1324 .remove = __devexit_p(snd_intel8x0m_remove),
1325 #ifdef CONFIG_PM
1326 .suspend = intel8x0m_suspend,
1327 .resume = intel8x0m_resume,
1328 #endif
1329 };
1330
1331
1332 static int __init alsa_card_intel8x0m_init(void)
1333 {
1334 return pci_register_driver(&driver);
1335 }
1336
1337 static void __exit alsa_card_intel8x0m_exit(void)
1338 {
1339 pci_unregister_driver(&driver);
1340 }
1341
1342 module_init(alsa_card_intel8x0m_init)
1343 module_exit(alsa_card_intel8x0m_exit)
SocketAccessConTroL development