include/asm-arm/arch-omap/hardware.h

   1 /*
   2  * linux/include/asm-arm/arch-omap/hardware.h
   3  *
   4  * Hardware definitions for TI OMAP processors and boards
   5  *
   6  * NOTE: Please put device driver specific defines into a separate header
   7  *       file for each driver.
   8  *
   9  * Copyright (C) 2001 RidgeRun, Inc.
  10  * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
  11  *
  12  * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
  13  *                          and Dirk Behme <dirk.behme@de.bosch.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License as published by the
  17  * Free Software Foundation; either version 2 of the License, or (at your
  18  * option) any later version.
  19  *
  20  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * You should have received a copy of the GNU General Public License along
  32  * with this program; if not, write to the Free Software Foundation, Inc.,
  33  * 675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35
  36 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
  37 #define __ASM_ARCH_OMAP_HARDWARE_H
  38
  39 #include <asm/sizes.h>
  40 #include <linux/config.h>
  41 #ifndef __ASSEMBLER__
  42 #include <asm/types.h>
  43 #include <asm/arch/cpu.h>
  44 #endif
  45 #include <asm/arch/io.h>
  46
  47 /*
  48  * ---------------------------------------------------------------------------
  49  * Common definitions for all OMAP processors
  50  * NOTE: Put all processor or board specific parts to the special header
  51  *       files.
  52  * ---------------------------------------------------------------------------
  53  */
  54
  55 /*
  56  * ----------------------------------------------------------------------------
  57  * Timers
  58  * ----------------------------------------------------------------------------
  59  */
  60 #define OMAP_MPU_TIMER1_BASE    (0xfffec500)
  61 #define OMAP_MPU_TIMER2_BASE    (0xfffec600)
  62 #define OMAP_MPU_TIMER3_BASE    (0xfffec700)
  63 #define MPU_TIMER_FREE          (1 << 6)
  64 #define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
  65 #define MPU_TIMER_AR            (1 << 1)
  66 #define MPU_TIMER_ST            (1 << 0)
  67
  68 /*
  69  * ----------------------------------------------------------------------------
  70  * Clocks
  71  * ----------------------------------------------------------------------------
  72  */
  73 #define CLKGEN_REG_BASE         (0xfffece00)
  74 #define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
  75 #define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
  76 #define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
  77 #define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
  78 #define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
  79 #define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
  80 #define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
  81 #define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
  82
  83 #define CK_RATEF                1
  84 #define CK_IDLEF                2
  85 #define CK_ENABLEF              4
  86 #define CK_SELECTF              8
  87 #define SETARM_IDLE_SHIFT
  88
  89 /* DPLL control registers */
  90 #define DPLL_CTL                (0xfffecf00)
  91
  92 /* DSP clock control */
  93 #define DSP_CONFIG_REG_BASE     (0xe1008000)
  94 #define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
  95 #define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
  96 #define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
  97
  98 /*
  99  * ---------------------------------------------------------------------------
 100  * UPLD
 101  * ---------------------------------------------------------------------------
 102  */
 103 #define ULPD_REG_BASE           (0xfffe0800)
 104 #define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
 105 #define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
 106 #define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
 107 #       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
 108 #       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
 109 #define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
 110 #       define SOFT_UDC_REQ             (1 << 4)
 111 #       define SOFT_USB_CLK_REQ         (1 << 3)
 112 #       define SOFT_DPLL_REQ            (1 << 0)
 113 #define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
 114 #define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
 115 #define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
 116 #define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
 117 #define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
 118 #       define DIS_MMC2_DPLL_REQ        (1 << 11)
 119 #       define DIS_MMC1_DPLL_REQ        (1 << 10)
 120 #       define DIS_UART3_DPLL_REQ       (1 << 9)
 121 #       define DIS_UART2_DPLL_REQ       (1 << 8)
 122 #       define DIS_UART1_DPLL_REQ       (1 << 7)
 123 #       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
 124 #define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
 125 #define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
 126
 127 /*
 128  * ---------------------------------------------------------------------------
 129  * Watchdog timer
 130  * ---------------------------------------------------------------------------
 131  */
 132
 133 /* Watchdog timer within the OMAP3.2 gigacell */
 134 #define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
 135 #define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
 136 #define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
 137 #define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
 138 #define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
 139
 140 /*
 141  * ---------------------------------------------------------------------------
 142  * Interrupts
 143  * ---------------------------------------------------------------------------
 144  */
 145 #define OMAP_IH1_BASE           0xfffecb00
 146 #define OMAP_IH2_BASE           0xfffe0000
 147
 148 #define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
 149 #define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
 150 #define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
 151 #define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
 152 #define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
 153 #define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
 154 #define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
 155
 156 #define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
 157 #define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
 158 #define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
 159 #define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
 160 #define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
 161 #define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
 162 #define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
 163
 164 #define IRQ_ITR_REG_OFFSET      0x00
 165 #define IRQ_MIR_REG_OFFSET      0x04
 166 #define IRQ_SIR_IRQ_REG_OFFSET  0x10
 167 #define IRQ_SIR_FIQ_REG_OFFSET  0x14
 168 #define IRQ_CONTROL_REG_OFFSET  0x18
 169 #define IRQ_ISR_REG_OFFSET      0x9c
 170 #define IRQ_ILR0_REG_OFFSET     0x1c
 171 #define IRQ_GMR_REG_OFFSET      0xa0
 172
 173 /*
 174  * ----------------------------------------------------------------------------
 175  * System control registers
 176  * ----------------------------------------------------------------------------
 177  */
 178 #define MOD_CONF_CTRL_0         0xfffe1080
 179 #define MOD_CONF_CTRL_1         0xfffe1110
 180
 181 /*
 182  * ----------------------------------------------------------------------------
 183  * Pin multiplexing registers
 184  * ----------------------------------------------------------------------------
 185  */
 186 #define FUNC_MUX_CTRL_0         0xfffe1000
 187 #define FUNC_MUX_CTRL_1         0xfffe1004
 188 #define FUNC_MUX_CTRL_2         0xfffe1008
 189 #define COMP_MODE_CTRL_0        0xfffe100c
 190 #define FUNC_MUX_CTRL_3         0xfffe1010
 191 #define FUNC_MUX_CTRL_4         0xfffe1014
 192 #define FUNC_MUX_CTRL_5         0xfffe1018
 193 #define FUNC_MUX_CTRL_6         0xfffe101C
 194 #define FUNC_MUX_CTRL_7         0xfffe1020
 195 #define FUNC_MUX_CTRL_8         0xfffe1024
 196 #define FUNC_MUX_CTRL_9         0xfffe1028
 197 #define FUNC_MUX_CTRL_A         0xfffe102C
 198 #define FUNC_MUX_CTRL_B         0xfffe1030
 199 #define FUNC_MUX_CTRL_C         0xfffe1034
 200 #define FUNC_MUX_CTRL_D         0xfffe1038
 201 #define PULL_DWN_CTRL_0         0xfffe1040
 202 #define PULL_DWN_CTRL_1         0xfffe1044
 203 #define PULL_DWN_CTRL_2         0xfffe1048
 204 #define PULL_DWN_CTRL_3         0xfffe104c
 205 #define PULL_DWN_CTRL_4         0xfffe10ac
 206
 207 /* OMAP-1610 specific multiplexing registers */
 208 #define FUNC_MUX_CTRL_E         0xfffe1090
 209 #define FUNC_MUX_CTRL_F         0xfffe1094
 210 #define FUNC_MUX_CTRL_10        0xfffe1098
 211 #define FUNC_MUX_CTRL_11        0xfffe109c
 212 #define FUNC_MUX_CTRL_12        0xfffe10a0
 213 #define PU_PD_SEL_0             0xfffe10b4
 214 #define PU_PD_SEL_1             0xfffe10b8
 215 #define PU_PD_SEL_2             0xfffe10bc
 216 #define PU_PD_SEL_3             0xfffe10c0
 217 #define PU_PD_SEL_4             0xfffe10c4
 218
 219 /* Timer32K for 1610 and 1710*/
 220 #define OMAP_TIMER32K_BASE      0xFFFBC400
 221
 222 /*
 223  * ---------------------------------------------------------------------------
 224  * TIPB bus interface
 225  * ---------------------------------------------------------------------------
 226  */
 227 #define TIPB_PUBLIC_CNTL_BASE           0xfffed300
 228 #define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
 229 #define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
 230 #define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
 231
 232 /*
 233  * ----------------------------------------------------------------------------
 234  * MPUI interface
 235  * ----------------------------------------------------------------------------
 236  */
 237 #define MPUI_BASE                       (0xfffec900)
 238 #define MPUI_CTRL                       (MPUI_BASE + 0x0)
 239 #define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
 240 #define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
 241 #define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
 242 #define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
 243 #define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
 244 #define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
 245 #define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
 246
 247 /*
 248  * ----------------------------------------------------------------------------
 249  * LED Pulse Generator
 250  * ----------------------------------------------------------------------------
 251  */
 252 #define OMAP_LPG1_BASE                  0xfffbd000
 253 #define OMAP_LPG2_BASE                  0xfffbd800
 254 #define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
 255 #define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
 256 #define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
 257 #define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
 258
 259 #ifndef __ASSEMBLER__
 260
 261 /*
 262  * ---------------------------------------------------------------------------
 263  * Serial ports
 264  * ---------------------------------------------------------------------------
 265  */
 266 #define OMAP_UART1_BASE         (unsigned char *)0xfffb0000
 267 #define OMAP_UART2_BASE         (unsigned char *)0xfffb0800
 268 #define OMAP_UART3_BASE         (unsigned char *)0xfffb9800
 269 #define OMAP_MAX_NR_PORTS       3
 270 #define OMAP1510_BASE_BAUD      (12000000/16)
 271 #define OMAP16XX_BASE_BAUD      (48000000/16)
 272
 273 #define is_omap_port(p) ({int __ret = 0;                        \
 274                         if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
 275                             p == IO_ADDRESS(OMAP_UART2_BASE) || \
 276                             p == IO_ADDRESS(OMAP_UART3_BASE))   \
 277                                 __ret = 1;                      \
 278                         __ret;                                  \
 279                         })
 280
 281 /*
 282  * ---------------------------------------------------------------------------
 283  * Processor specific defines
 284  * ---------------------------------------------------------------------------
 285  */
 286
 287 #include "omap730.h"
 288 #include "omap1510.h"
 289 #include "omap16xx.h"
 290
 291 /*
 292  * ---------------------------------------------------------------------------
 293  * Board specific defines
 294  * ---------------------------------------------------------------------------
 295  */
 296
 297 #ifdef CONFIG_MACH_OMAP_INNOVATOR
 298 #include "board-innovator.h"
 299 #endif
 300
 301 #ifdef CONFIG_MACH_OMAP_H2
 302 #include "board-h2.h"
 303 #endif
 304
 305 #ifdef CONFIG_MACH_OMAP_PERSEUS2
 306 #include "board-perseus2.h"
 307 #endif
 308
 309 #ifdef CONFIG_MACH_OMAP_H3
 310 #include "board-h3.h"
 311 #endif
 312
 313 #ifdef CONFIG_MACH_OMAP_H4
 314 #include "board-h4.h"
 315 #error "Support for H4 board not yet implemented."
 316 #endif
 317
 318 #ifdef CONFIG_MACH_OMAP_OSK
 319 #include "board-osk.h"
 320 #endif
 321
 322 #ifdef CONFIG_MACH_VOICEBLUE
 323 #include "board-voiceblue.h"
 324 #endif
 325
 326 #ifdef CONFIG_MACH_NETSTAR
 327 #include "board-netstar.h"
 328 #endif
 329
 330 #endif /* !__ASSEMBLER__ */
 331
 332 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */