2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h> /* PAGE_SIZE */
22 /* NVIDIA K8 registers */
23 #define NVIDIA_X86_64_0_APBASE 0x10
24 #define NVIDIA_X86_64_1_APBASE1 0x50
25 #define NVIDIA_X86_64_1_APLIMIT1 0x54
26 #define NVIDIA_X86_64_1_APSIZE 0xa8
27 #define NVIDIA_X86_64_1_APBASE2 0xd8
28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
30 /* ULi K8 registers */
31 #define ULI_X86_64_BASE_ADDR 0x10
32 #define ULI_X86_64_HTT_FEA_REG 0x50
33 #define ULI_X86_64_ENU_SCR_REG 0x54
35 static struct resource
*aperture_resource
;
36 static int __initdata agp_try_unsupported
= 1;
37 static int agp_bridges_found
;
39 static void amd64_tlbflush(struct agp_memory
*temp
)
44 static int amd64_insert_memory(struct agp_memory
*mem
, off_t pg_start
, int type
)
46 int i
, j
, num_entries
;
49 struct agp_bridge_data
*bridge
= mem
->bridge
;
52 num_entries
= agp_num_entries();
54 if (type
!= mem
->type
)
56 mask_type
= bridge
->driver
->agp_type_to_mask_type(bridge
, type
);
61 /* Make sure we can fit the range in the gatt table. */
62 /* FIXME: could wrap */
63 if (((unsigned long)pg_start
+ mem
->page_count
) > num_entries
)
68 /* gatt table should be empty. */
69 while (j
< (pg_start
+ mem
->page_count
)) {
70 if (!PGE_EMPTY(agp_bridge
, readl(agp_bridge
->gatt_table
+j
)))
75 if (!mem
->is_flushed
) {
77 mem
->is_flushed
= true;
80 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
81 tmp
= agp_bridge
->driver
->mask_memory(agp_bridge
,
82 mem
->memory
[i
], mask_type
);
84 BUG_ON(tmp
& 0xffffff0000000ffcULL
);
85 pte
= (tmp
& 0x000000ff00000000ULL
) >> 28;
86 pte
|=(tmp
& 0x00000000fffff000ULL
);
87 pte
|= GPTE_VALID
| GPTE_COHERENT
;
89 writel(pte
, agp_bridge
->gatt_table
+j
);
90 readl(agp_bridge
->gatt_table
+j
); /* PCI Posting. */
97 * This hack alters the order element according
98 * to the size of a long. It sucks. I totally disown this, even
99 * though it does appear to work for the most part.
101 static struct aper_size_info_32 amd64_aperture_sizes
[7] =
103 {32, 8192, 3+(sizeof(long)/8), 0 },
104 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
105 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
106 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
107 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
108 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
109 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
114 * Get the current Aperture size from the x86-64.
115 * Note, that there may be multiple x86-64's, but we just return
116 * the value from the first one we find. The set_size functions
117 * keep the rest coherent anyway. Or at least should do.
119 static int amd64_fetch_size(void)
124 struct aper_size_info_32
*values
;
126 dev
= k8_northbridges
[0];
130 pci_read_config_dword(dev
, AMD64_GARTAPERTURECTL
, &temp
);
132 values
= A_SIZE_32(amd64_aperture_sizes
);
134 for (i
= 0; i
< agp_bridge
->driver
->num_aperture_sizes
; i
++) {
135 if (temp
== values
[i
].size_value
) {
136 agp_bridge
->previous_size
=
137 agp_bridge
->current_size
= (void *) (values
+ i
);
139 agp_bridge
->aperture_size_idx
= i
;
140 return values
[i
].size
;
147 * In a multiprocessor x86-64 system, this function gets
148 * called once for each CPU.
150 static u64
amd64_configure(struct pci_dev
*hammer
, u64 gatt_table
)
156 /* Address to map to */
157 pci_read_config_dword(hammer
, AMD64_GARTAPERTUREBASE
, &tmp
);
158 aperturebase
= tmp
<< 25;
159 aper_base
= (aperturebase
& PCI_BASE_ADDRESS_MEM_MASK
);
161 enable_gart_translation(hammer
, gatt_table
);
167 static const struct aper_size_info_32 amd_8151_sizes
[7] =
169 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
170 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
171 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
172 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
173 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
174 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
175 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
178 static int amd_8151_configure(void)
180 unsigned long gatt_bus
= virt_to_gart(agp_bridge
->gatt_table_real
);
183 /* Configure AGP regs in each x86-64 host bridge. */
184 for (i
= 0; i
< num_k8_northbridges
; i
++) {
185 agp_bridge
->gart_bus_addr
=
186 amd64_configure(k8_northbridges
[i
], gatt_bus
);
193 static void amd64_cleanup(void)
197 for (i
= 0; i
< num_k8_northbridges
; i
++) {
198 struct pci_dev
*dev
= k8_northbridges
[i
];
199 /* disable gart translation */
200 pci_read_config_dword(dev
, AMD64_GARTAPERTURECTL
, &tmp
);
201 tmp
&= ~AMD64_GARTEN
;
202 pci_write_config_dword(dev
, AMD64_GARTAPERTURECTL
, tmp
);
207 static const struct agp_bridge_driver amd_8151_driver
= {
208 .owner
= THIS_MODULE
,
209 .aperture_sizes
= amd_8151_sizes
,
210 .size_type
= U32_APER_SIZE
,
211 .num_aperture_sizes
= 7,
212 .configure
= amd_8151_configure
,
213 .fetch_size
= amd64_fetch_size
,
214 .cleanup
= amd64_cleanup
,
215 .tlb_flush
= amd64_tlbflush
,
216 .mask_memory
= agp_generic_mask_memory
,
218 .agp_enable
= agp_generic_enable
,
219 .cache_flush
= global_cache_flush
,
220 .create_gatt_table
= agp_generic_create_gatt_table
,
221 .free_gatt_table
= agp_generic_free_gatt_table
,
222 .insert_memory
= amd64_insert_memory
,
223 .remove_memory
= agp_generic_remove_memory
,
224 .alloc_by_type
= agp_generic_alloc_by_type
,
225 .free_by_type
= agp_generic_free_by_type
,
226 .agp_alloc_page
= agp_generic_alloc_page
,
227 .agp_alloc_pages
= agp_generic_alloc_pages
,
228 .agp_destroy_page
= agp_generic_destroy_page
,
229 .agp_destroy_pages
= agp_generic_destroy_pages
,
230 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
233 /* Some basic sanity checks for the aperture. */
234 static int __devinit
agp_aperture_valid(u64 aper
, u32 size
)
236 if (!aperture_valid(aper
, size
, 32*1024*1024))
239 /* Request the Aperture. This catches cases when someone else
240 already put a mapping in there - happens with some very broken BIOS
242 Maybe better to use pci_assign_resource/pci_enable_device instead
243 trusting the bridges? */
244 if (!aperture_resource
&&
245 !(aperture_resource
= request_mem_region(aper
, size
, "aperture"))) {
246 printk(KERN_ERR PFX
"Aperture conflicts with PCI mapping.\n");
253 * W*s centric BIOS sometimes only set up the aperture in the AGP
254 * bridge, not the northbridge. On AMD64 this is handled early
255 * in aperture.c, but when IOMMU is not enabled or we run
256 * on a 32bit kernel this needs to be redone.
257 * Unfortunately it is impossible to fix the aperture here because it's too late
258 * to allocate that much memory. But at least error out cleanly instead of
261 static __devinit
int fix_northbridge(struct pci_dev
*nb
, struct pci_dev
*agp
,
264 u32 aper_low
, aper_hi
;
267 u32 nb_order
, nb_base
;
270 pci_read_config_dword(nb
, AMD64_GARTAPERTURECTL
, &nb_order
);
271 nb_order
= (nb_order
>> 1) & 7;
272 pci_read_config_dword(nb
, AMD64_GARTAPERTUREBASE
, &nb_base
);
273 nb_aper
= nb_base
<< 25;
274 if (agp_aperture_valid(nb_aper
, (32*1024*1024)<<nb_order
)) {
278 /* Northbridge seems to contain crap. Try the AGP bridge. */
280 pci_read_config_word(agp
, cap
+0x14, &apsize
);
281 if (apsize
== 0xffff)
285 /* Some BIOS use weird encodings not in the AGPv3 table. */
288 order
= 7 - hweight16(apsize
);
290 pci_read_config_dword(agp
, 0x10, &aper_low
);
291 pci_read_config_dword(agp
, 0x14, &aper_hi
);
292 aper
= (aper_low
& ~((1<<22)-1)) | ((u64
)aper_hi
<< 32);
295 * On some sick chips APSIZE is 0. This means it wants 4G
296 * so let double check that order, and lets trust the AMD NB settings
298 if (order
>=0 && aper
+ (32ULL<<(20 + order
)) > 0x100000000ULL
) {
299 dev_info(&agp
->dev
, "aperture size %u MB is not right, using settings from NB\n",
304 dev_info(&agp
->dev
, "aperture from AGP @ %Lx size %u MB\n",
306 if (order
< 0 || !agp_aperture_valid(aper
, (32*1024*1024)<<order
))
309 pci_write_config_dword(nb
, AMD64_GARTAPERTURECTL
, order
<< 1);
310 pci_write_config_dword(nb
, AMD64_GARTAPERTUREBASE
, aper
>> 25);
315 static __devinit
int cache_nbs (struct pci_dev
*pdev
, u32 cap_ptr
)
319 if (cache_k8_northbridges() < 0)
323 for (i
= 0; i
< num_k8_northbridges
; i
++) {
324 struct pci_dev
*dev
= k8_northbridges
[i
];
325 if (fix_northbridge(dev
, pdev
, cap_ptr
) < 0) {
326 dev_err(&dev
->dev
, "no usable aperture found\n");
328 /* should port this to i386 */
329 dev_err(&dev
->dev
, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
337 /* Handle AMD 8151 quirks */
338 static void __devinit
amd8151_init(struct pci_dev
*pdev
, struct agp_bridge_data
*bridge
)
342 switch (pdev
->revision
) {
343 case 0x01: revstring
="A0"; break;
344 case 0x02: revstring
="A1"; break;
345 case 0x11: revstring
="B0"; break;
346 case 0x12: revstring
="B1"; break;
347 case 0x13: revstring
="B2"; break;
348 case 0x14: revstring
="B3"; break;
349 default: revstring
="??"; break;
352 dev_info(&pdev
->dev
, "AMD 8151 AGP Bridge rev %s\n", revstring
);
355 * Work around errata.
356 * Chips before B2 stepping incorrectly reporting v3.5
358 if (pdev
->revision
< 0x13) {
359 dev_info(&pdev
->dev
, "correcting AGP revision (reports 3.5, is really 3.0)\n");
360 bridge
->major_version
= 3;
361 bridge
->minor_version
= 0;
366 static const struct aper_size_info_32 uli_sizes
[7] =
376 static int __devinit
uli_agp_init(struct pci_dev
*pdev
)
378 u32 httfea
,baseaddr
,enuscr
;
379 struct pci_dev
*dev1
;
381 unsigned size
= amd64_fetch_size();
383 dev_info(&pdev
->dev
, "setting up ULi AGP\n");
384 dev1
= pci_get_slot (pdev
->bus
,PCI_DEVFN(0,0));
386 dev_info(&pdev
->dev
, "can't find ULi secondary device\n");
390 for (i
= 0; i
< ARRAY_SIZE(uli_sizes
); i
++)
391 if (uli_sizes
[i
].size
== size
)
394 if (i
== ARRAY_SIZE(uli_sizes
)) {
395 dev_info(&pdev
->dev
, "no ULi size found for %d\n", size
);
399 /* shadow x86-64 registers into ULi registers */
400 pci_read_config_dword (k8_northbridges
[0], AMD64_GARTAPERTUREBASE
, &httfea
);
402 /* if x86-64 aperture base is beyond 4G, exit here */
403 if ((httfea
& 0x7fff) >> (32 - 25))
406 httfea
= (httfea
& 0x7fff) << 25;
408 pci_read_config_dword(pdev
, ULI_X86_64_BASE_ADDR
, &baseaddr
);
409 baseaddr
&= ~PCI_BASE_ADDRESS_MEM_MASK
;
411 pci_write_config_dword(pdev
, ULI_X86_64_BASE_ADDR
, baseaddr
);
413 enuscr
= httfea
+ (size
* 1024 * 1024) - 1;
414 pci_write_config_dword(dev1
, ULI_X86_64_HTT_FEA_REG
, httfea
);
415 pci_write_config_dword(dev1
, ULI_X86_64_ENU_SCR_REG
, enuscr
);
422 static const struct aper_size_info_32 nforce3_sizes
[5] =
424 {512, 131072, 7, 0x00000000 },
425 {256, 65536, 6, 0x00000008 },
426 {128, 32768, 5, 0x0000000C },
427 {64, 16384, 4, 0x0000000E },
428 {32, 8192, 3, 0x0000000F }
431 /* Handle shadow device of the Nvidia NForce3 */
432 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
433 static int nforce3_agp_init(struct pci_dev
*pdev
)
435 u32 tmp
, apbase
, apbar
, aplimit
;
436 struct pci_dev
*dev1
;
438 unsigned size
= amd64_fetch_size();
440 dev_info(&pdev
->dev
, "setting up Nforce3 AGP\n");
442 dev1
= pci_get_slot(pdev
->bus
, PCI_DEVFN(11, 0));
444 dev_info(&pdev
->dev
, "can't find Nforce3 secondary device\n");
448 for (i
= 0; i
< ARRAY_SIZE(nforce3_sizes
); i
++)
449 if (nforce3_sizes
[i
].size
== size
)
452 if (i
== ARRAY_SIZE(nforce3_sizes
)) {
453 dev_info(&pdev
->dev
, "no NForce3 size found for %d\n", size
);
457 pci_read_config_dword(dev1
, NVIDIA_X86_64_1_APSIZE
, &tmp
);
459 tmp
|= nforce3_sizes
[i
].size_value
;
460 pci_write_config_dword(dev1
, NVIDIA_X86_64_1_APSIZE
, tmp
);
462 /* shadow x86-64 registers into NVIDIA registers */
463 pci_read_config_dword (k8_northbridges
[0], AMD64_GARTAPERTUREBASE
, &apbase
);
465 /* if x86-64 aperture base is beyond 4G, exit here */
466 if ( (apbase
& 0x7fff) >> (32 - 25) ) {
467 dev_info(&pdev
->dev
, "aperture base > 4G\n");
471 apbase
= (apbase
& 0x7fff) << 25;
473 pci_read_config_dword(pdev
, NVIDIA_X86_64_0_APBASE
, &apbar
);
474 apbar
&= ~PCI_BASE_ADDRESS_MEM_MASK
;
476 pci_write_config_dword(pdev
, NVIDIA_X86_64_0_APBASE
, apbar
);
478 aplimit
= apbase
+ (size
* 1024 * 1024) - 1;
479 pci_write_config_dword(dev1
, NVIDIA_X86_64_1_APBASE1
, apbase
);
480 pci_write_config_dword(dev1
, NVIDIA_X86_64_1_APLIMIT1
, aplimit
);
481 pci_write_config_dword(dev1
, NVIDIA_X86_64_1_APBASE2
, apbase
);
482 pci_write_config_dword(dev1
, NVIDIA_X86_64_1_APLIMIT2
, aplimit
);
489 static int __devinit
agp_amd64_probe(struct pci_dev
*pdev
,
490 const struct pci_device_id
*ent
)
492 struct agp_bridge_data
*bridge
;
496 cap_ptr
= pci_find_capability(pdev
, PCI_CAP_ID_AGP
);
500 /* Could check for AGPv3 here */
502 bridge
= agp_alloc_bridge();
506 if (pdev
->vendor
== PCI_VENDOR_ID_AMD
&&
507 pdev
->device
== PCI_DEVICE_ID_AMD_8151_0
) {
508 amd8151_init(pdev
, bridge
);
510 dev_info(&pdev
->dev
, "AGP bridge [%04x/%04x]\n",
511 pdev
->vendor
, pdev
->device
);
514 bridge
->driver
= &amd_8151_driver
;
516 bridge
->capndx
= cap_ptr
;
518 /* Fill in the mode register */
519 pci_read_config_dword(pdev
, bridge
->capndx
+PCI_AGP_STATUS
, &bridge
->mode
);
521 if (cache_nbs(pdev
, cap_ptr
) == -1) {
522 agp_put_bridge(bridge
);
526 if (pdev
->vendor
== PCI_VENDOR_ID_NVIDIA
) {
527 int ret
= nforce3_agp_init(pdev
);
529 agp_put_bridge(bridge
);
534 if (pdev
->vendor
== PCI_VENDOR_ID_AL
) {
535 int ret
= uli_agp_init(pdev
);
537 agp_put_bridge(bridge
);
542 pci_set_drvdata(pdev
, bridge
);
543 err
= agp_add_bridge(bridge
);
551 static void __devexit
agp_amd64_remove(struct pci_dev
*pdev
)
553 struct agp_bridge_data
*bridge
= pci_get_drvdata(pdev
);
555 release_mem_region(virt_to_gart(bridge
->gatt_table_real
),
556 amd64_aperture_sizes
[bridge
->aperture_size_idx
].size
);
557 agp_remove_bridge(bridge
);
558 agp_put_bridge(bridge
);
563 static int agp_amd64_suspend(struct pci_dev
*pdev
, pm_message_t state
)
565 pci_save_state(pdev
);
566 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
571 static int agp_amd64_resume(struct pci_dev
*pdev
)
573 pci_set_power_state(pdev
, PCI_D0
);
574 pci_restore_state(pdev
);
576 if (pdev
->vendor
== PCI_VENDOR_ID_NVIDIA
)
577 nforce3_agp_init(pdev
);
579 return amd_8151_configure();
582 #endif /* CONFIG_PM */
584 static struct pci_device_id agp_amd64_pci_table
[] = {
586 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
588 .vendor
= PCI_VENDOR_ID_AMD
,
589 .device
= PCI_DEVICE_ID_AMD_8151_0
,
590 .subvendor
= PCI_ANY_ID
,
591 .subdevice
= PCI_ANY_ID
,
595 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
597 .vendor
= PCI_VENDOR_ID_AL
,
598 .device
= PCI_DEVICE_ID_AL_M1689
,
599 .subvendor
= PCI_ANY_ID
,
600 .subdevice
= PCI_ANY_ID
,
604 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
606 .vendor
= PCI_VENDOR_ID_VIA
,
607 .device
= PCI_DEVICE_ID_VIA_K8T800PRO_0
,
608 .subvendor
= PCI_ANY_ID
,
609 .subdevice
= PCI_ANY_ID
,
613 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
615 .vendor
= PCI_VENDOR_ID_VIA
,
616 .device
= PCI_DEVICE_ID_VIA_8385_0
,
617 .subvendor
= PCI_ANY_ID
,
618 .subdevice
= PCI_ANY_ID
,
620 /* VIA K8M800 / K8N800 */
622 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
624 .vendor
= PCI_VENDOR_ID_VIA
,
625 .device
= PCI_DEVICE_ID_VIA_8380_0
,
626 .subvendor
= PCI_ANY_ID
,
627 .subdevice
= PCI_ANY_ID
,
629 /* VIA K8M890 / K8N890 */
631 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
633 .vendor
= PCI_VENDOR_ID_VIA
,
634 .device
= PCI_DEVICE_ID_VIA_VT3336
,
635 .subvendor
= PCI_ANY_ID
,
636 .subdevice
= PCI_ANY_ID
,
640 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
642 .vendor
= PCI_VENDOR_ID_VIA
,
643 .device
= PCI_DEVICE_ID_VIA_3238_0
,
644 .subvendor
= PCI_ANY_ID
,
645 .subdevice
= PCI_ANY_ID
,
647 /* VIA K8T800/K8M800/K8N800 */
649 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
651 .vendor
= PCI_VENDOR_ID_VIA
,
652 .device
= PCI_DEVICE_ID_VIA_838X_1
,
653 .subvendor
= PCI_ANY_ID
,
654 .subdevice
= PCI_ANY_ID
,
658 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
660 .vendor
= PCI_VENDOR_ID_NVIDIA
,
661 .device
= PCI_DEVICE_ID_NVIDIA_NFORCE3
,
662 .subvendor
= PCI_ANY_ID
,
663 .subdevice
= PCI_ANY_ID
,
666 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
668 .vendor
= PCI_VENDOR_ID_NVIDIA
,
669 .device
= PCI_DEVICE_ID_NVIDIA_NFORCE3S
,
670 .subvendor
= PCI_ANY_ID
,
671 .subdevice
= PCI_ANY_ID
,
675 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
677 .vendor
= PCI_VENDOR_ID_SI
,
678 .device
= PCI_DEVICE_ID_SI_755
,
679 .subvendor
= PCI_ANY_ID
,
680 .subdevice
= PCI_ANY_ID
,
684 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
686 .vendor
= PCI_VENDOR_ID_SI
,
687 .device
= PCI_DEVICE_ID_SI_760
,
688 .subvendor
= PCI_ANY_ID
,
689 .subdevice
= PCI_ANY_ID
,
693 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
695 .vendor
= PCI_VENDOR_ID_AL
,
697 .subvendor
= PCI_ANY_ID
,
698 .subdevice
= PCI_ANY_ID
,
704 MODULE_DEVICE_TABLE(pci
, agp_amd64_pci_table
);
706 static struct pci_driver agp_amd64_pci_driver
= {
707 .name
= "agpgart-amd64",
708 .id_table
= agp_amd64_pci_table
,
709 .probe
= agp_amd64_probe
,
710 .remove
= agp_amd64_remove
,
712 .suspend
= agp_amd64_suspend
,
713 .resume
= agp_amd64_resume
,
718 /* Not static due to IOMMU code calling it early. */
719 int __init
agp_amd64_init(void)
725 err
= pci_register_driver(&agp_amd64_pci_driver
);
729 if (agp_bridges_found
== 0) {
731 if (!agp_try_unsupported
&& !agp_try_unsupported_boot
) {
732 printk(KERN_INFO PFX
"No supported AGP bridge found.\n");
734 printk(KERN_INFO PFX
"You can try agp_try_unsupported=1\n");
736 printk(KERN_INFO PFX
"You can boot with agp=try_unsupported\n");
741 /* First check that we have at least one AMD64 NB */
742 if (!pci_dev_present(k8_nb_ids
))
745 /* Look for any AGP bridge */
748 for_each_pci_dev(dev
) {
749 if (!pci_find_capability(dev
, PCI_CAP_ID_AGP
))
751 /* Only one bridge supported right now */
752 if (agp_amd64_probe(dev
, NULL
) == 0) {
761 static void __exit
agp_amd64_cleanup(void)
763 if (aperture_resource
)
764 release_resource(aperture_resource
);
765 pci_unregister_driver(&agp_amd64_pci_driver
);
768 /* On AMD64 the PCI driver needs to initialize this driver early
769 for the IOMMU, so it has to be called via a backdoor. */
770 #ifndef CONFIG_GART_IOMMU
771 module_init(agp_amd64_init
);
772 module_exit(agp_amd64_cleanup
);
775 MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
776 module_param(agp_try_unsupported
, bool, 0);
777 MODULE_LICENSE("GPL");