2 * process.c: handle interruption inject for guests.
3 * Copyright (c) 2005, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 * Shaofan Li (Susue Li) <susie.li@intel.com>
19 * Xiaoyan Feng (Fleming Feng) <fleming.feng@intel.com>
20 * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
21 * Xiantao Zhang (xiantao.zhang@intel.com)
27 #include <asm/fpswa.h>
28 #include <asm/kregs.h>
31 fpswa_interface_t
*vmm_fpswa_interface
;
33 #define IA64_VHPT_TRANS_VECTOR 0x0000
34 #define IA64_INST_TLB_VECTOR 0x0400
35 #define IA64_DATA_TLB_VECTOR 0x0800
36 #define IA64_ALT_INST_TLB_VECTOR 0x0c00
37 #define IA64_ALT_DATA_TLB_VECTOR 0x1000
38 #define IA64_DATA_NESTED_TLB_VECTOR 0x1400
39 #define IA64_INST_KEY_MISS_VECTOR 0x1800
40 #define IA64_DATA_KEY_MISS_VECTOR 0x1c00
41 #define IA64_DIRTY_BIT_VECTOR 0x2000
42 #define IA64_INST_ACCESS_BIT_VECTOR 0x2400
43 #define IA64_DATA_ACCESS_BIT_VECTOR 0x2800
44 #define IA64_BREAK_VECTOR 0x2c00
45 #define IA64_EXTINT_VECTOR 0x3000
46 #define IA64_PAGE_NOT_PRESENT_VECTOR 0x5000
47 #define IA64_KEY_PERMISSION_VECTOR 0x5100
48 #define IA64_INST_ACCESS_RIGHTS_VECTOR 0x5200
49 #define IA64_DATA_ACCESS_RIGHTS_VECTOR 0x5300
50 #define IA64_GENEX_VECTOR 0x5400
51 #define IA64_DISABLED_FPREG_VECTOR 0x5500
52 #define IA64_NAT_CONSUMPTION_VECTOR 0x5600
53 #define IA64_SPECULATION_VECTOR 0x5700 /* UNUSED */
54 #define IA64_DEBUG_VECTOR 0x5900
55 #define IA64_UNALIGNED_REF_VECTOR 0x5a00
56 #define IA64_UNSUPPORTED_DATA_REF_VECTOR 0x5b00
57 #define IA64_FP_FAULT_VECTOR 0x5c00
58 #define IA64_FP_TRAP_VECTOR 0x5d00
59 #define IA64_LOWERPRIV_TRANSFER_TRAP_VECTOR 0x5e00
60 #define IA64_TAKEN_BRANCH_TRAP_VECTOR 0x5f00
61 #define IA64_SINGLE_STEP_TRAP_VECTOR 0x6000
63 /* SDM vol2 5.5 - IVA based interruption handling */
64 #define INITIAL_PSR_VALUE_AT_INTERRUPTION (IA64_PSR_UP | IA64_PSR_MFL |\
65 IA64_PSR_MFH | IA64_PSR_PK | IA64_PSR_DT | \
66 IA64_PSR_RT | IA64_PSR_MC|IA64_PSR_IT)
68 #define DOMN_PAL_REQUEST 0x110000
69 #define DOMN_SAL_REQUEST 0x110001
71 static u64 vec2off
[68] = {0x0, 0x400, 0x800, 0xc00, 0x1000, 0x1400, 0x1800,
72 0x1c00, 0x2000, 0x2400, 0x2800, 0x2c00, 0x3000, 0x3400, 0x3800, 0x3c00,
73 0x4000, 0x4400, 0x4800, 0x4c00, 0x5000, 0x5100, 0x5200, 0x5300, 0x5400,
74 0x5500, 0x5600, 0x5700, 0x5800, 0x5900, 0x5a00, 0x5b00, 0x5c00, 0x5d00,
75 0x5e00, 0x5f00, 0x6000, 0x6100, 0x6200, 0x6300, 0x6400, 0x6500, 0x6600,
76 0x6700, 0x6800, 0x6900, 0x6a00, 0x6b00, 0x6c00, 0x6d00, 0x6e00, 0x6f00,
77 0x7000, 0x7100, 0x7200, 0x7300, 0x7400, 0x7500, 0x7600, 0x7700, 0x7800,
78 0x7900, 0x7a00, 0x7b00, 0x7c00, 0x7d00, 0x7e00, 0x7f00
81 static void collect_interruption(struct kvm_vcpu
*vcpu
)
87 struct kvm_pt_regs
*regs
= vcpu_regs(vcpu
);
89 vpsr
= vcpu_get_psr(vcpu
);
91 if (vpsr
& IA64_PSR_IC
) {
93 /* Sync mpsr id/da/dd/ss/ed bits to vipsr
94 * since after guest do rfi, we still want these bits on in
99 vpsr
= vpsr
| (ipsr
& (IA64_PSR_ID
| IA64_PSR_DA
100 | IA64_PSR_DD
| IA64_PSR_SS
102 vcpu_set_ipsr(vcpu
, vpsr
);
104 /* Currently, for trap, we do not advance IIP to next
105 * instruction. That's because we assume caller already
106 * set up IIP correctly
109 vcpu_set_iip(vcpu
, regs
->cr_iip
);
111 /* set vifs.v to zero */
112 vifs
= VCPU(vcpu
, ifs
);
114 vcpu_set_ifs(vcpu
, vifs
);
116 vcpu_set_iipa(vcpu
, VMX(vcpu
, cr_iipa
));
119 vdcr
= VCPU(vcpu
, dcr
);
122 * up/mfl/mfh/pk/dt/rt/mc/it keeps unchanged
123 * be: set to the value of dcr.be
124 * pp: set to the value of dcr.pp
126 vpsr
&= INITIAL_PSR_VALUE_AT_INTERRUPTION
;
127 vpsr
|= (vdcr
& IA64_DCR_BE
);
129 /* VDCR pp bit position is different from VPSR pp bit */
130 if (vdcr
& IA64_DCR_PP
) {
133 vpsr
&= ~IA64_PSR_PP
;;
136 vcpu_set_psr(vcpu
, vpsr
);
140 void inject_guest_interruption(struct kvm_vcpu
*vcpu
, u64 vec
)
143 struct kvm_pt_regs
*regs
;
144 union ia64_isr pt_isr
;
146 regs
= vcpu_regs(vcpu
);
148 /* clear cr.isr.ir (incomplete register frame)*/
149 pt_isr
.val
= VMX(vcpu
, cr_isr
);
151 VMX(vcpu
, cr_isr
) = pt_isr
.val
;
153 collect_interruption(vcpu
);
155 viva
= vcpu_get_iva(vcpu
);
156 regs
->cr_iip
= viva
+ vec
;
159 static u64
vcpu_get_itir_on_fault(struct kvm_vcpu
*vcpu
, u64 ifa
)
161 union ia64_rr rr
, rr1
;
163 rr
.val
= vcpu_get_rr(vcpu
, ifa
);
172 * Set vIFA & vITIR & vIHA, when vPSR.ic =1
174 * set_ifa: if true, set vIFA
175 * set_itir: if true, set vITIR
176 * set_iha: if true, set vIHA
178 void set_ifa_itir_iha(struct kvm_vcpu
*vcpu
, u64 vadr
,
179 int set_ifa
, int set_itir
, int set_iha
)
184 vpsr
= VCPU(vcpu
, vpsr
);
185 /* Vol2, Table 8-1 */
186 if (vpsr
& IA64_PSR_IC
) {
188 vcpu_set_ifa(vcpu
, vadr
);
190 value
= vcpu_get_itir_on_fault(vcpu
, vadr
);
191 vcpu_set_itir(vcpu
, value
);
195 value
= vcpu_thash(vcpu
, vadr
);
196 vcpu_set_iha(vcpu
, value
);
204 * Refer to SDM Vol2 Table 5-6 & 8-1
206 void dtlb_fault(struct kvm_vcpu
*vcpu
, u64 vadr
)
208 /* If vPSR.ic, IFA, ITIR, IHA */
209 set_ifa_itir_iha(vcpu
, vadr
, 1, 1, 1);
210 inject_guest_interruption(vcpu
, IA64_DATA_TLB_VECTOR
);
214 * Instruction TLB Fault
215 * @ Instruction TLB vector
216 * Refer to SDM Vol2 Table 5-6 & 8-1
218 void itlb_fault(struct kvm_vcpu
*vcpu
, u64 vadr
)
220 /* If vPSR.ic, IFA, ITIR, IHA */
221 set_ifa_itir_iha(vcpu
, vadr
, 1, 1, 1);
222 inject_guest_interruption(vcpu
, IA64_INST_TLB_VECTOR
);
228 * Data Nested TLB Fault
229 * @ Data Nested TLB Vector
230 * Refer to SDM Vol2 Table 5-6 & 8-1
232 void nested_dtlb(struct kvm_vcpu
*vcpu
)
234 inject_guest_interruption(vcpu
, IA64_DATA_NESTED_TLB_VECTOR
);
238 * Alternate Data TLB Fault
239 * @ Alternate Data TLB vector
240 * Refer to SDM Vol2 Table 5-6 & 8-1
242 void alt_dtlb(struct kvm_vcpu
*vcpu
, u64 vadr
)
244 set_ifa_itir_iha(vcpu
, vadr
, 1, 1, 0);
245 inject_guest_interruption(vcpu
, IA64_ALT_DATA_TLB_VECTOR
);
252 * Refer to SDM Vol2 Table 5-6 & 8-1
254 void alt_itlb(struct kvm_vcpu
*vcpu
, u64 vadr
)
256 set_ifa_itir_iha(vcpu
, vadr
, 1, 1, 0);
257 inject_guest_interruption(vcpu
, IA64_ALT_INST_TLB_VECTOR
);
261 * VHPT Translation Vector
263 static void _vhpt_fault(struct kvm_vcpu
*vcpu
, u64 vadr
)
265 /* If vPSR.ic, IFA, ITIR, IHA*/
266 set_ifa_itir_iha(vcpu
, vadr
, 1, 1, 1);
267 inject_guest_interruption(vcpu
, IA64_VHPT_TRANS_VECTOR
);
273 * VHPT Instruction Fault
274 * @ VHPT Translation vector
275 * Refer to SDM Vol2 Table 5-6 & 8-1
277 void ivhpt_fault(struct kvm_vcpu
*vcpu
, u64 vadr
)
279 _vhpt_fault(vcpu
, vadr
);
285 * @ VHPT Translation vector
286 * Refer to SDM Vol2 Table 5-6 & 8-1
288 void dvhpt_fault(struct kvm_vcpu
*vcpu
, u64 vadr
)
290 _vhpt_fault(vcpu
, vadr
);
297 * General Exception vector
299 void _general_exception(struct kvm_vcpu
*vcpu
)
301 inject_guest_interruption(vcpu
, IA64_GENEX_VECTOR
);
306 * Illegal Operation Fault
307 * @ General Exception Vector
308 * Refer to SDM Vol2 Table 5-6 & 8-1
310 void illegal_op(struct kvm_vcpu
*vcpu
)
312 _general_exception(vcpu
);
316 * Illegal Dependency Fault
317 * @ General Exception Vector
318 * Refer to SDM Vol2 Table 5-6 & 8-1
320 void illegal_dep(struct kvm_vcpu
*vcpu
)
322 _general_exception(vcpu
);
326 * Reserved Register/Field Fault
327 * @ General Exception Vector
328 * Refer to SDM Vol2 Table 5-6 & 8-1
330 void rsv_reg_field(struct kvm_vcpu
*vcpu
)
332 _general_exception(vcpu
);
335 * Privileged Operation Fault
336 * @ General Exception Vector
337 * Refer to SDM Vol2 Table 5-6 & 8-1
340 void privilege_op(struct kvm_vcpu
*vcpu
)
342 _general_exception(vcpu
);
346 * Unimplement Data Address Fault
347 * @ General Exception Vector
348 * Refer to SDM Vol2 Table 5-6 & 8-1
350 void unimpl_daddr(struct kvm_vcpu
*vcpu
)
352 _general_exception(vcpu
);
356 * Privileged Register Fault
357 * @ General Exception Vector
358 * Refer to SDM Vol2 Table 5-6 & 8-1
360 void privilege_reg(struct kvm_vcpu
*vcpu
)
362 _general_exception(vcpu
);
366 * Nat consumption vector
368 * vaddr: Optional, if t == REGISTER
370 static void _nat_consumption_fault(struct kvm_vcpu
*vcpu
, u64 vadr
,
371 enum tlb_miss_type t
)
373 /* If vPSR.ic && t == DATA/INST, IFA */
374 if (t
== DATA
|| t
== INSTRUCTION
) {
376 set_ifa_itir_iha(vcpu
, vadr
, 1, 0, 0);
379 inject_guest_interruption(vcpu
, IA64_NAT_CONSUMPTION_VECTOR
);
383 * Instruction Nat Page Consumption Fault
384 * @ Nat Consumption Vector
385 * Refer to SDM Vol2 Table 5-6 & 8-1
387 void inat_page_consumption(struct kvm_vcpu
*vcpu
, u64 vadr
)
389 _nat_consumption_fault(vcpu
, vadr
, INSTRUCTION
);
393 * Register Nat Consumption Fault
394 * @ Nat Consumption Vector
395 * Refer to SDM Vol2 Table 5-6 & 8-1
397 void rnat_consumption(struct kvm_vcpu
*vcpu
)
399 _nat_consumption_fault(vcpu
, 0, REGISTER
);
403 * Data Nat Page Consumption Fault
404 * @ Nat Consumption Vector
405 * Refer to SDM Vol2 Table 5-6 & 8-1
407 void dnat_page_consumption(struct kvm_vcpu
*vcpu
, u64 vadr
)
409 _nat_consumption_fault(vcpu
, vadr
, DATA
);
413 * Page not present vector
415 static void __page_not_present(struct kvm_vcpu
*vcpu
, u64 vadr
)
417 /* If vPSR.ic, IFA, ITIR */
418 set_ifa_itir_iha(vcpu
, vadr
, 1, 1, 0);
419 inject_guest_interruption(vcpu
, IA64_PAGE_NOT_PRESENT_VECTOR
);
423 void data_page_not_present(struct kvm_vcpu
*vcpu
, u64 vadr
)
425 __page_not_present(vcpu
, vadr
);
429 void inst_page_not_present(struct kvm_vcpu
*vcpu
, u64 vadr
)
431 __page_not_present(vcpu
, vadr
);
436 * Data access rights vector
438 void data_access_rights(struct kvm_vcpu
*vcpu
, u64 vadr
)
440 /* If vPSR.ic, IFA, ITIR */
441 set_ifa_itir_iha(vcpu
, vadr
, 1, 1, 0);
442 inject_guest_interruption(vcpu
, IA64_DATA_ACCESS_RIGHTS_VECTOR
);
445 fpswa_ret_t
vmm_fp_emulate(int fp_fault
, void *bundle
, unsigned long *ipsr
,
446 unsigned long *fpsr
, unsigned long *isr
, unsigned long *pr
,
447 unsigned long *ifs
, struct kvm_pt_regs
*regs
)
451 struct kvm_vcpu
*vcpu
= current_vcpu
;
453 uint64_t old_rr7
= ia64_get_rr(7UL<<61);
455 if (!vmm_fpswa_interface
)
456 return (fpswa_ret_t
) {-1, 0, 0, 0};
459 * Just let fpswa driver to use hardware fp registers.
460 * No fp register is valid in memory.
462 memset(&fp_state
, 0, sizeof(fp_state_t
));
465 * unsigned long (*EFI_FPSWA) (
466 * unsigned long trap_type,
468 * unsigned long *pipsr,
469 * unsigned long *pfsr,
470 * unsigned long *pisr,
471 * unsigned long *ppreds,
472 * unsigned long *pifs,
475 /*Call host fpswa interface directly to virtualize
476 *guest fpswa request!
478 ia64_set_rr(7UL << 61, vcpu
->arch
.host
.rr
[7]);
481 ret
= (*vmm_fpswa_interface
->fpswa
) (fp_fault
, bundle
,
482 ipsr
, fpsr
, isr
, pr
, ifs
, &fp_state
);
483 ia64_set_rr(7UL << 61, old_rr7
);
489 * Handle floating-point assist faults and traps for domain.
491 unsigned long vmm_handle_fpu_swa(int fp_fault
, struct kvm_pt_regs
*regs
,
494 struct kvm_vcpu
*v
= current_vcpu
;
496 unsigned long fault_ip
;
499 fault_ip
= regs
->cr_iip
;
501 * When the FP trap occurs, the trapping instruction is completed.
502 * If ipsr.ri == 0, there is the trapping instruction in previous
505 if (!fp_fault
&& (ia64_psr(regs
)->ri
== 0))
508 if (fetch_code(v
, fault_ip
, &bundle
))
511 if (!bundle
.i64
[0] && !bundle
.i64
[1])
514 ret
= vmm_fp_emulate(fp_fault
, &bundle
, ®s
->cr_ipsr
, ®s
->ar_fpsr
,
515 &isr
, ®s
->pr
, ®s
->cr_ifs
, regs
);
519 void reflect_interruption(u64 ifa
, u64 isr
, u64 iim
,
520 u64 vec
, struct kvm_pt_regs
*regs
)
524 struct kvm_vcpu
*vcpu
= current_vcpu
;
525 u64 vpsr
= VCPU(vcpu
, vpsr
);
527 vector
= vec2off
[vec
];
529 if (!(vpsr
& IA64_PSR_IC
) && (vector
!= IA64_DATA_NESTED_TLB_VECTOR
)) {
530 panic_vm(vcpu
, "Interruption with vector :0x%lx occurs "
531 "with psr.ic = 0\n", vector
);
536 case 32: /*IA64_FP_FAULT_VECTOR*/
537 status
= vmm_handle_fpu_swa(1, regs
, isr
);
539 vcpu_increment_iip(vcpu
);
541 } else if (-EAGAIN
== status
)
544 case 33: /*IA64_FP_TRAP_VECTOR*/
545 status
= vmm_handle_fpu_swa(0, regs
, isr
);
548 else if (-EAGAIN
== status
) {
549 vcpu_decrement_iip(vcpu
);
555 VCPU(vcpu
, isr
) = isr
;
556 VCPU(vcpu
, iipa
) = regs
->cr_iip
;
557 if (vector
== IA64_BREAK_VECTOR
|| vector
== IA64_SPECULATION_VECTOR
)
558 VCPU(vcpu
, iim
) = iim
;
560 set_ifa_itir_iha(vcpu
, ifa
, 1, 1, 1);
562 inject_guest_interruption(vcpu
, vector
);
565 static void set_pal_call_data(struct kvm_vcpu
*vcpu
)
567 struct exit_ctl_data
*p
= &vcpu
->arch
.exit_data
;
569 /*FIXME:For static and stacked convention, firmware
570 * has put the parameters in gr28-gr31 before
573 p
->u
.pal_data
.gr28
= vcpu_get_gr(vcpu
, 28);
574 p
->u
.pal_data
.gr29
= vcpu_get_gr(vcpu
, 29);
575 p
->u
.pal_data
.gr30
= vcpu_get_gr(vcpu
, 30);
576 p
->u
.pal_data
.gr31
= vcpu_get_gr(vcpu
, 31);
577 p
->exit_reason
= EXIT_REASON_PAL_CALL
;
580 static void set_pal_call_result(struct kvm_vcpu
*vcpu
)
582 struct exit_ctl_data
*p
= &vcpu
->arch
.exit_data
;
584 if (p
->exit_reason
== EXIT_REASON_PAL_CALL
) {
585 vcpu_set_gr(vcpu
, 8, p
->u
.pal_data
.ret
.status
, 0);
586 vcpu_set_gr(vcpu
, 9, p
->u
.pal_data
.ret
.v0
, 0);
587 vcpu_set_gr(vcpu
, 10, p
->u
.pal_data
.ret
.v1
, 0);
588 vcpu_set_gr(vcpu
, 11, p
->u
.pal_data
.ret
.v2
, 0);
590 panic_vm(vcpu
, "Mis-set for exit reason!\n");
593 static void set_sal_call_data(struct kvm_vcpu
*vcpu
)
595 struct exit_ctl_data
*p
= &vcpu
->arch
.exit_data
;
597 p
->u
.sal_data
.in0
= vcpu_get_gr(vcpu
, 32);
598 p
->u
.sal_data
.in1
= vcpu_get_gr(vcpu
, 33);
599 p
->u
.sal_data
.in2
= vcpu_get_gr(vcpu
, 34);
600 p
->u
.sal_data
.in3
= vcpu_get_gr(vcpu
, 35);
601 p
->u
.sal_data
.in4
= vcpu_get_gr(vcpu
, 36);
602 p
->u
.sal_data
.in5
= vcpu_get_gr(vcpu
, 37);
603 p
->u
.sal_data
.in6
= vcpu_get_gr(vcpu
, 38);
604 p
->u
.sal_data
.in7
= vcpu_get_gr(vcpu
, 39);
605 p
->exit_reason
= EXIT_REASON_SAL_CALL
;
608 static void set_sal_call_result(struct kvm_vcpu
*vcpu
)
610 struct exit_ctl_data
*p
= &vcpu
->arch
.exit_data
;
612 if (p
->exit_reason
== EXIT_REASON_SAL_CALL
) {
613 vcpu_set_gr(vcpu
, 8, p
->u
.sal_data
.ret
.r8
, 0);
614 vcpu_set_gr(vcpu
, 9, p
->u
.sal_data
.ret
.r9
, 0);
615 vcpu_set_gr(vcpu
, 10, p
->u
.sal_data
.ret
.r10
, 0);
616 vcpu_set_gr(vcpu
, 11, p
->u
.sal_data
.ret
.r11
, 0);
618 panic_vm(vcpu
, "Mis-set for exit reason!\n");
621 void kvm_ia64_handle_break(unsigned long ifa
, struct kvm_pt_regs
*regs
,
622 unsigned long isr
, unsigned long iim
)
624 struct kvm_vcpu
*v
= current_vcpu
;
626 if (ia64_psr(regs
)->cpl
== 0) {
627 /* Allow hypercalls only when cpl = 0. */
628 if (iim
== DOMN_PAL_REQUEST
) {
629 set_pal_call_data(v
);
631 set_pal_call_result(v
);
632 vcpu_increment_iip(v
);
634 } else if (iim
== DOMN_SAL_REQUEST
) {
635 set_sal_call_data(v
);
637 set_sal_call_result(v
);
638 vcpu_increment_iip(v
);
642 reflect_interruption(ifa
, isr
, iim
, 11, regs
);
645 void check_pending_irq(struct kvm_vcpu
*vcpu
)
647 int mask
, h_pending
, h_inservice
;
650 struct kvm_pt_regs
*regs
= vcpu_regs(vcpu
);
652 h_pending
= highest_pending_irq(vcpu
);
653 if (h_pending
== NULL_VECTOR
) {
654 update_vhpi(vcpu
, NULL_VECTOR
);
657 h_inservice
= highest_inservice_irq(vcpu
);
659 vpsr
= VCPU(vcpu
, vpsr
);
660 mask
= irq_masked(vcpu
, h_pending
, h_inservice
);
661 if ((vpsr
& IA64_PSR_I
) && IRQ_NO_MASKED
== mask
) {
662 isr
= vpsr
& IA64_PSR_RI
;
663 update_vhpi(vcpu
, h_pending
);
664 reflect_interruption(0, isr
, 0, 12, regs
); /* EXT IRQ */
665 } else if (mask
== IRQ_MASKED_BY_INSVC
) {
666 if (VCPU(vcpu
, vhpi
))
667 update_vhpi(vcpu
, NULL_VECTOR
);
669 /* masked by vpsr.i or vtpr.*/
670 update_vhpi(vcpu
, h_pending
);
674 static void generate_exirq(struct kvm_vcpu
*vcpu
)
679 struct kvm_pt_regs
*regs
= vcpu_regs(vcpu
);
681 vpsr
= VCPU(vcpu
, vpsr
);
682 isr
= vpsr
& IA64_PSR_RI
;
683 if (!(vpsr
& IA64_PSR_IC
))
684 panic_vm(vcpu
, "Trying to inject one IRQ with psr.ic=0\n");
685 reflect_interruption(0, isr
, 0, 12, regs
); /* EXT IRQ */
688 void vhpi_detection(struct kvm_vcpu
*vcpu
)
690 uint64_t threshold
, vhpi
;
692 struct ia64_psr vpsr
;
694 vpsr
= *(struct ia64_psr
*)&VCPU(vcpu
, vpsr
);
695 vtpr
.val
= VCPU(vcpu
, tpr
);
697 threshold
= ((!vpsr
.i
) << 5) | (vtpr
.mmi
<< 4) | vtpr
.mic
;
698 vhpi
= VCPU(vcpu
, vhpi
);
699 if (vhpi
> threshold
) {
700 /* interrupt actived*/
701 generate_exirq(vcpu
);
706 void leave_hypervisor_tail(void)
708 struct kvm_vcpu
*v
= current_vcpu
;
710 if (VMX(v
, timer_check
)) {
711 VMX(v
, timer_check
) = 0;
712 if (VMX(v
, itc_check
)) {
713 if (vcpu_get_itc(v
) > VCPU(v
, itm
)) {
714 if (!(VCPU(v
, itv
) & (1 << 16))) {
715 vcpu_pend_interrupt(v
, VCPU(v
, itv
)
717 VMX(v
, itc_check
) = 0;
719 v
->arch
.timer_pending
= 1;
721 VMX(v
, last_itc
) = VCPU(v
, itm
) + 1;
727 if (v
->arch
.irq_new_pending
) {
728 v
->arch
.irq_new_pending
= 0;
729 VMX(v
, irq_check
) = 0;
730 check_pending_irq(v
);
733 if (VMX(v
, irq_check
)) {
734 VMX(v
, irq_check
) = 0;
740 static inline void handle_lds(struct kvm_pt_regs
*regs
)
742 regs
->cr_ipsr
|= IA64_PSR_ED
;
745 void physical_tlb_miss(struct kvm_vcpu
*vcpu
, unsigned long vadr
, int type
)
750 rr
.val
= ia64_get_rr(vadr
);
751 pte
= vadr
& _PAGE_PPN_MASK
;
752 pte
= pte
| PHY_PAGE_WB
;
753 thash_vhpt_insert(vcpu
, pte
, (u64
)(rr
.ps
<< 2), vadr
, type
);
757 void kvm_page_fault(u64 vadr
, u64 vec
, struct kvm_pt_regs
*regs
)
762 u64 vhpt_adr
, gppa
, pteval
, rr
, itir
;
765 struct thash_data
*data
;
766 struct kvm_vcpu
*v
= current_vcpu
;
768 vpsr
= VCPU(v
, vpsr
);
769 misr
.val
= VMX(v
, cr_isr
);
773 if (is_physical_mode(v
) && (!(vadr
<< 1 >> 62))) {
775 if (__gpfn_is_io((vadr
<< 1) >> (PAGE_SHIFT
+ 1))) {
776 emulate_io_inst(v
, ((vadr
<< 1) >> 1), 4);
780 physical_tlb_miss(v
, vadr
, type
);
783 data
= vtlb_lookup(v
, vadr
, type
);
786 gppa
= (vadr
& ((1UL << data
->ps
) - 1))
787 + (data
->ppn
>> (data
->ps
- 12) << data
->ps
);
788 if (__gpfn_is_io(gppa
>> PAGE_SHIFT
)) {
789 if (data
->pl
>= ((regs
->cr_ipsr
>>
790 IA64_PSR_CPL0_BIT
) & 3))
791 emulate_io_inst(v
, gppa
, data
->ma
);
793 vcpu_set_isr(v
, misr
.val
);
794 data_access_rights(v
, vadr
);
799 thash_vhpt_insert(v
, data
->page_flags
, data
->itir
, vadr
, type
);
801 } else if (type
== D_TLB
) {
807 rr
= vcpu_get_rr(v
, vadr
);
808 itir
= rr
& (RR_RID_MASK
| RR_PS_MASK
);
810 if (!vhpt_enabled(v
, vadr
, misr
.rs
? RSE_REF
: DATA_REF
)) {
811 if (vpsr
& IA64_PSR_IC
) {
812 vcpu_set_isr(v
, misr
.val
);
820 vpta
.val
= vcpu_get_pta(v
);
821 /* avoid recursively walking (short format) VHPT */
823 vhpt_adr
= vcpu_thash(v
, vadr
);
824 if (!guest_vhpt_lookup(vhpt_adr
, &pteval
)) {
825 /* VHPT successfully read. */
826 if (!(pteval
& _PAGE_P
)) {
827 if (vpsr
& IA64_PSR_IC
) {
828 vcpu_set_isr(v
, misr
.val
);
833 } else if ((pteval
& _PAGE_MA_MASK
) != _PAGE_MA_ST
) {
834 thash_purge_and_insert(v
, pteval
, itir
,
836 } else if (vpsr
& IA64_PSR_IC
) {
837 vcpu_set_isr(v
, misr
.val
);
843 /* Can't read VHPT. */
844 if (vpsr
& IA64_PSR_IC
) {
845 vcpu_set_isr(v
, misr
.val
);
846 dvhpt_fault(v
, vadr
);
851 } else if (type
== I_TLB
) {
852 if (!(vpsr
& IA64_PSR_IC
))
854 if (!vhpt_enabled(v
, vadr
, INST_REF
)) {
855 vcpu_set_isr(v
, misr
.val
);
860 vpta
.val
= vcpu_get_pta(v
);
862 vhpt_adr
= vcpu_thash(v
, vadr
);
863 if (!guest_vhpt_lookup(vhpt_adr
, &pteval
)) {
864 /* VHPT successfully read. */
865 if (pteval
& _PAGE_P
) {
866 if ((pteval
& _PAGE_MA_MASK
) == _PAGE_MA_ST
) {
867 vcpu_set_isr(v
, misr
.val
);
871 rr
= vcpu_get_rr(v
, vadr
);
872 itir
= rr
& (RR_RID_MASK
| RR_PS_MASK
);
873 thash_purge_and_insert(v
, pteval
, itir
,
876 vcpu_set_isr(v
, misr
.val
);
877 inst_page_not_present(v
, vadr
);
880 vcpu_set_isr(v
, misr
.val
);
881 ivhpt_fault(v
, vadr
);
886 void kvm_vexirq(struct kvm_vcpu
*vcpu
)
889 struct kvm_pt_regs
*regs
;
891 regs
= vcpu_regs(vcpu
);
892 vpsr
= VCPU(vcpu
, vpsr
);
893 isr
= vpsr
& IA64_PSR_RI
;
894 reflect_interruption(0, isr
, 0, 12, regs
); /*EXT IRQ*/
897 void kvm_ia64_handle_irq(struct kvm_vcpu
*v
)
899 struct exit_ctl_data
*p
= &v
->arch
.exit_data
;
903 p
->exit_reason
= EXIT_REASON_EXTERNAL_INTERRUPT
;
905 local_irq_restore(psr
);
907 VMX(v
, timer_check
) = 1;
911 static void ptc_ga_remote_func(struct kvm_vcpu
*v
, int pos
)
913 u64 oldrid
, moldrid
, oldpsbits
, vaddr
;
914 struct kvm_ptc_g
*p
= &v
->arch
.ptc_g_data
[pos
];
917 oldrid
= VMX(v
, vrr
[0]);
918 VMX(v
, vrr
[0]) = p
->rr
;
919 oldpsbits
= VMX(v
, psbits
[0]);
920 VMX(v
, psbits
[0]) = VMX(v
, psbits
[REGION_NUMBER(vaddr
)]);
921 moldrid
= ia64_get_rr(0x0);
922 ia64_set_rr(0x0, vrrtomrr(p
->rr
));
925 vaddr
= PAGEALIGN(vaddr
, p
->ps
);
926 thash_purge_entries_remote(v
, vaddr
, p
->ps
);
928 VMX(v
, vrr
[0]) = oldrid
;
929 VMX(v
, psbits
[0]) = oldpsbits
;
930 ia64_set_rr(0x0, moldrid
);
931 ia64_dv_serialize_data();
934 static void vcpu_do_resume(struct kvm_vcpu
*vcpu
)
936 /*Re-init VHPT and VTLB once from resume*/
937 vcpu
->arch
.vhpt
.num
= VHPT_NUM_ENTRIES
;
938 thash_init(&vcpu
->arch
.vhpt
, VHPT_SHIFT
);
939 vcpu
->arch
.vtlb
.num
= VTLB_NUM_ENTRIES
;
940 thash_init(&vcpu
->arch
.vtlb
, VTLB_SHIFT
);
942 ia64_set_pta(vcpu
->arch
.vhpt
.pta
.val
);
945 static void vmm_sanity_check(struct kvm_vcpu
*vcpu
)
947 struct exit_ctl_data
*p
= &vcpu
->arch
.exit_data
;
949 if (!vmm_sanity
&& p
->exit_reason
!= EXIT_REASON_DEBUG
) {
950 panic_vm(vcpu
, "Failed to do vmm sanity check,"
951 "it maybe caused by crashed vmm!!\n\n");
955 static void kvm_do_resume_op(struct kvm_vcpu
*vcpu
)
957 vmm_sanity_check(vcpu
); /*Guarantee vcpu runing on healthy vmm!*/
959 if (test_and_clear_bit(KVM_REQ_RESUME
, &vcpu
->requests
)) {
960 vcpu_do_resume(vcpu
);
964 if (unlikely(test_and_clear_bit(KVM_REQ_TLB_FLUSH
, &vcpu
->requests
))) {
965 thash_purge_all(vcpu
);
969 if (test_and_clear_bit(KVM_REQ_PTC_G
, &vcpu
->requests
)) {
970 while (vcpu
->arch
.ptc_g_count
> 0)
971 ptc_ga_remote_func(vcpu
, --vcpu
->arch
.ptc_g_count
);
975 void vmm_transition(struct kvm_vcpu
*vcpu
)
977 ia64_call_vsa(PAL_VPS_SAVE
, (unsigned long)vcpu
->arch
.vpd
,
979 vmm_trampoline(&vcpu
->arch
.guest
, &vcpu
->arch
.host
);
980 ia64_call_vsa(PAL_VPS_RESTORE
, (unsigned long)vcpu
->arch
.vpd
,
982 kvm_do_resume_op(vcpu
);
985 void vmm_panic_handler(u64 vec
)
987 struct kvm_vcpu
*vcpu
= current_vcpu
;
989 panic_vm(vcpu
, "Unexpected interruption occurs in VMM, vector:0x%lx\n",