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b43: Add firmware information to modinfo
[linux-2.6/sactl.git] / drivers / net / forcedeth.c
blobd4843d014bc90752483711708b414cc0b804dd5d
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Changelog:
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41 * irq mask updated
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56 * open.
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60 * the tx length.
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * on close.
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
82 * capabilities.
83 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86 * 0.35: 26 Jun 2005: Support for MCP55 added.
87 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90 * per-packet flags.
91 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94 * of nv_remove
95 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
96 * in the second (and later) nv_open call
97 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100 * 0.46: 20 Oct 2005: Add irq optimization modes.
101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
113 * 0.59: 30 Oct 2006: Added support for recoverable error.
114 * 0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
115 *
116 * Known bugs:
117 * We suspect that on some hardware no TX done interrupts are generated.
118 * This means recovery from netif_stop_queue only happens if the hw timer
119 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
120 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
121 * If your hardware reliably generates tx done interrupts, then you can remove
122 * DEV_NEED_TIMERIRQ from the driver_data flags.
123 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
124 * superfluous timer interrupts from the nic.
125 */
126 #ifdef CONFIG_FORCEDETH_NAPI
127 #define DRIVERNAPI "-NAPI"
128 #else
129 #define DRIVERNAPI
130 #endif
131 #define FORCEDETH_VERSION "0.61"
132 #define DRV_NAME "forcedeth"
133
134 #include <linux/module.h>
135 #include <linux/types.h>
136 #include <linux/pci.h>
137 #include <linux/interrupt.h>
138 #include <linux/netdevice.h>
139 #include <linux/etherdevice.h>
140 #include <linux/delay.h>
141 #include <linux/spinlock.h>
142 #include <linux/ethtool.h>
143 #include <linux/timer.h>
144 #include <linux/skbuff.h>
145 #include <linux/mii.h>
146 #include <linux/random.h>
147 #include <linux/init.h>
148 #include <linux/if_vlan.h>
149 #include <linux/dma-mapping.h>
150
151 #include <asm/irq.h>
152 #include <asm/io.h>
153 #include <asm/uaccess.h>
154 #include <asm/system.h>
155
156 #if 0
157 #define dprintk printk
158 #else
159 #define dprintk(x...) do { } while (0)
160 #endif
161
162 #define TX_WORK_PER_LOOP 64
163 #define RX_WORK_PER_LOOP 64
164
165 /*
166 * Hardware access:
167 */
168
169 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
170 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
171 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
172 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
173 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
174 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
175 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
176 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
177 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
178 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
179 #define DEV_HAS_STATISTICS_V1 0x0400 /* device supports hw statistics version 1 */
180 #define DEV_HAS_STATISTICS_V2 0x0800 /* device supports hw statistics version 2 */
181 #define DEV_HAS_TEST_EXTENDED 0x1000 /* device supports extended diagnostic test */
182 #define DEV_HAS_MGMT_UNIT 0x2000 /* device supports management unit */
183 #define DEV_HAS_CORRECT_MACADDR 0x4000 /* device supports correct mac address order */
184
185 enum {
186 NvRegIrqStatus = 0x000,
187 #define NVREG_IRQSTAT_MIIEVENT 0x040
188 #define NVREG_IRQSTAT_MASK 0x81ff
189 NvRegIrqMask = 0x004,
190 #define NVREG_IRQ_RX_ERROR 0x0001
191 #define NVREG_IRQ_RX 0x0002
192 #define NVREG_IRQ_RX_NOBUF 0x0004
193 #define NVREG_IRQ_TX_ERR 0x0008
194 #define NVREG_IRQ_TX_OK 0x0010
195 #define NVREG_IRQ_TIMER 0x0020
196 #define NVREG_IRQ_LINK 0x0040
197 #define NVREG_IRQ_RX_FORCED 0x0080
198 #define NVREG_IRQ_TX_FORCED 0x0100
199 #define NVREG_IRQ_RECOVER_ERROR 0x8000
200 #define NVREG_IRQMASK_THROUGHPUT 0x00df
201 #define NVREG_IRQMASK_CPU 0x0060
202 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
203 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
204 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
205
206 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
207 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
208 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
209
210 NvRegUnknownSetupReg6 = 0x008,
211 #define NVREG_UNKSETUP6_VAL 3
212
213 /*
214 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
215 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
216 */
217 NvRegPollingInterval = 0x00c,
218 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
219 #define NVREG_POLL_DEFAULT_CPU 13
220 NvRegMSIMap0 = 0x020,
221 NvRegMSIMap1 = 0x024,
222 NvRegMSIIrqMask = 0x030,
223 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
224 NvRegMisc1 = 0x080,
225 #define NVREG_MISC1_PAUSE_TX 0x01
226 #define NVREG_MISC1_HD 0x02
227 #define NVREG_MISC1_FORCE 0x3b0f3c
228
229 NvRegMacReset = 0x34,
230 #define NVREG_MAC_RESET_ASSERT 0x0F3
231 NvRegTransmitterControl = 0x084,
232 #define NVREG_XMITCTL_START 0x01
233 #define NVREG_XMITCTL_MGMT_ST 0x40000000
234 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
235 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
236 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
237 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
238 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
239 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
240 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
241 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
242 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
243 NvRegTransmitterStatus = 0x088,
244 #define NVREG_XMITSTAT_BUSY 0x01
245
246 NvRegPacketFilterFlags = 0x8c,
247 #define NVREG_PFF_PAUSE_RX 0x08
248 #define NVREG_PFF_ALWAYS 0x7F0000
249 #define NVREG_PFF_PROMISC 0x80
250 #define NVREG_PFF_MYADDR 0x20
251 #define NVREG_PFF_LOOPBACK 0x10
252
253 NvRegOffloadConfig = 0x90,
254 #define NVREG_OFFLOAD_HOMEPHY 0x601
255 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
256 NvRegReceiverControl = 0x094,
257 #define NVREG_RCVCTL_START 0x01
258 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
259 NvRegReceiverStatus = 0x98,
260 #define NVREG_RCVSTAT_BUSY 0x01
261
262 NvRegRandomSeed = 0x9c,
263 #define NVREG_RNDSEED_MASK 0x00ff
264 #define NVREG_RNDSEED_FORCE 0x7f00
265 #define NVREG_RNDSEED_FORCE2 0x2d00
266 #define NVREG_RNDSEED_FORCE3 0x7400
267
268 NvRegTxDeferral = 0xA0,
269 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
270 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
271 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
272 NvRegRxDeferral = 0xA4,
273 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
274 NvRegMacAddrA = 0xA8,
275 NvRegMacAddrB = 0xAC,
276 NvRegMulticastAddrA = 0xB0,
277 #define NVREG_MCASTADDRA_FORCE 0x01
278 NvRegMulticastAddrB = 0xB4,
279 NvRegMulticastMaskA = 0xB8,
280 #define NVREG_MCASTMASKA_NONE 0xffffffff
281 NvRegMulticastMaskB = 0xBC,
282 #define NVREG_MCASTMASKB_NONE 0xffff
283
284 NvRegPhyInterface = 0xC0,
285 #define PHY_RGMII 0x10000000
286
287 NvRegTxRingPhysAddr = 0x100,
288 NvRegRxRingPhysAddr = 0x104,
289 NvRegRingSizes = 0x108,
290 #define NVREG_RINGSZ_TXSHIFT 0
291 #define NVREG_RINGSZ_RXSHIFT 16
292 NvRegTransmitPoll = 0x10c,
293 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
294 NvRegLinkSpeed = 0x110,
295 #define NVREG_LINKSPEED_FORCE 0x10000
296 #define NVREG_LINKSPEED_10 1000
297 #define NVREG_LINKSPEED_100 100
298 #define NVREG_LINKSPEED_1000 50
299 #define NVREG_LINKSPEED_MASK (0xFFF)
300 NvRegUnknownSetupReg5 = 0x130,
301 #define NVREG_UNKSETUP5_BIT31 (1<<31)
302 NvRegTxWatermark = 0x13c,
303 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
304 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
305 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
306 NvRegTxRxControl = 0x144,
307 #define NVREG_TXRXCTL_KICK 0x0001
308 #define NVREG_TXRXCTL_BIT1 0x0002
309 #define NVREG_TXRXCTL_BIT2 0x0004
310 #define NVREG_TXRXCTL_IDLE 0x0008
311 #define NVREG_TXRXCTL_RESET 0x0010
312 #define NVREG_TXRXCTL_RXCHECK 0x0400
313 #define NVREG_TXRXCTL_DESC_1 0
314 #define NVREG_TXRXCTL_DESC_2 0x002100
315 #define NVREG_TXRXCTL_DESC_3 0xc02200
316 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
317 #define NVREG_TXRXCTL_VLANINS 0x00080
318 NvRegTxRingPhysAddrHigh = 0x148,
319 NvRegRxRingPhysAddrHigh = 0x14C,
320 NvRegTxPauseFrame = 0x170,
321 #define NVREG_TX_PAUSEFRAME_DISABLE 0x01ff0080
322 #define NVREG_TX_PAUSEFRAME_ENABLE 0x01800010
323 NvRegMIIStatus = 0x180,
324 #define NVREG_MIISTAT_ERROR 0x0001
325 #define NVREG_MIISTAT_LINKCHANGE 0x0008
326 #define NVREG_MIISTAT_MASK_RW 0x0007
327 #define NVREG_MIISTAT_MASK_ALL 0x000f
328 NvRegMIIMask = 0x184,
329 #define NVREG_MII_LINKCHANGE 0x0008
330
331 NvRegAdapterControl = 0x188,
332 #define NVREG_ADAPTCTL_START 0x02
333 #define NVREG_ADAPTCTL_LINKUP 0x04
334 #define NVREG_ADAPTCTL_PHYVALID 0x40000
335 #define NVREG_ADAPTCTL_RUNNING 0x100000
336 #define NVREG_ADAPTCTL_PHYSHIFT 24
337 NvRegMIISpeed = 0x18c,
338 #define NVREG_MIISPEED_BIT8 (1<<8)
339 #define NVREG_MIIDELAY 5
340 NvRegMIIControl = 0x190,
341 #define NVREG_MIICTL_INUSE 0x08000
342 #define NVREG_MIICTL_WRITE 0x00400
343 #define NVREG_MIICTL_ADDRSHIFT 5
344 NvRegMIIData = 0x194,
345 NvRegWakeUpFlags = 0x200,
346 #define NVREG_WAKEUPFLAGS_VAL 0x7770
347 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
348 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
349 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
350 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
351 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
352 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
353 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
354 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
355 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
356 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
357
358 NvRegPatternCRC = 0x204,
359 NvRegPatternMask = 0x208,
360 NvRegPowerCap = 0x268,
361 #define NVREG_POWERCAP_D3SUPP (1<<30)
362 #define NVREG_POWERCAP_D2SUPP (1<<26)
363 #define NVREG_POWERCAP_D1SUPP (1<<25)
364 NvRegPowerState = 0x26c,
365 #define NVREG_POWERSTATE_POWEREDUP 0x8000
366 #define NVREG_POWERSTATE_VALID 0x0100
367 #define NVREG_POWERSTATE_MASK 0x0003
368 #define NVREG_POWERSTATE_D0 0x0000
369 #define NVREG_POWERSTATE_D1 0x0001
370 #define NVREG_POWERSTATE_D2 0x0002
371 #define NVREG_POWERSTATE_D3 0x0003
372 NvRegTxCnt = 0x280,
373 NvRegTxZeroReXmt = 0x284,
374 NvRegTxOneReXmt = 0x288,
375 NvRegTxManyReXmt = 0x28c,
376 NvRegTxLateCol = 0x290,
377 NvRegTxUnderflow = 0x294,
378 NvRegTxLossCarrier = 0x298,
379 NvRegTxExcessDef = 0x29c,
380 NvRegTxRetryErr = 0x2a0,
381 NvRegRxFrameErr = 0x2a4,
382 NvRegRxExtraByte = 0x2a8,
383 NvRegRxLateCol = 0x2ac,
384 NvRegRxRunt = 0x2b0,
385 NvRegRxFrameTooLong = 0x2b4,
386 NvRegRxOverflow = 0x2b8,
387 NvRegRxFCSErr = 0x2bc,
388 NvRegRxFrameAlignErr = 0x2c0,
389 NvRegRxLenErr = 0x2c4,
390 NvRegRxUnicast = 0x2c8,
391 NvRegRxMulticast = 0x2cc,
392 NvRegRxBroadcast = 0x2d0,
393 NvRegTxDef = 0x2d4,
394 NvRegTxFrame = 0x2d8,
395 NvRegRxCnt = 0x2dc,
396 NvRegTxPause = 0x2e0,
397 NvRegRxPause = 0x2e4,
398 NvRegRxDropFrame = 0x2e8,
399 NvRegVlanControl = 0x300,
400 #define NVREG_VLANCONTROL_ENABLE 0x2000
401 NvRegMSIXMap0 = 0x3e0,
402 NvRegMSIXMap1 = 0x3e4,
403 NvRegMSIXIrqStatus = 0x3f0,
404
405 NvRegPowerState2 = 0x600,
406 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
407 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
408 };
409
410 /* Big endian: should work, but is untested */
411 struct ring_desc {
412 __le32 buf;
413 __le32 flaglen;
414 };
415
416 struct ring_desc_ex {
417 __le32 bufhigh;
418 __le32 buflow;
419 __le32 txvlan;
420 __le32 flaglen;
421 };
422
423 union ring_type {
424 struct ring_desc* orig;
425 struct ring_desc_ex* ex;
426 };
427
428 #define FLAG_MASK_V1 0xffff0000
429 #define FLAG_MASK_V2 0xffffc000
430 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
431 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
432
433 #define NV_TX_LASTPACKET (1<<16)
434 #define NV_TX_RETRYERROR (1<<19)
435 #define NV_TX_FORCED_INTERRUPT (1<<24)
436 #define NV_TX_DEFERRED (1<<26)
437 #define NV_TX_CARRIERLOST (1<<27)
438 #define NV_TX_LATECOLLISION (1<<28)
439 #define NV_TX_UNDERFLOW (1<<29)
440 #define NV_TX_ERROR (1<<30)
441 #define NV_TX_VALID (1<<31)
442
443 #define NV_TX2_LASTPACKET (1<<29)
444 #define NV_TX2_RETRYERROR (1<<18)
445 #define NV_TX2_FORCED_INTERRUPT (1<<30)
446 #define NV_TX2_DEFERRED (1<<25)
447 #define NV_TX2_CARRIERLOST (1<<26)
448 #define NV_TX2_LATECOLLISION (1<<27)
449 #define NV_TX2_UNDERFLOW (1<<28)
450 /* error and valid are the same for both */
451 #define NV_TX2_ERROR (1<<30)
452 #define NV_TX2_VALID (1<<31)
453 #define NV_TX2_TSO (1<<28)
454 #define NV_TX2_TSO_SHIFT 14
455 #define NV_TX2_TSO_MAX_SHIFT 14
456 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
457 #define NV_TX2_CHECKSUM_L3 (1<<27)
458 #define NV_TX2_CHECKSUM_L4 (1<<26)
459
460 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
461
462 #define NV_RX_DESCRIPTORVALID (1<<16)
463 #define NV_RX_MISSEDFRAME (1<<17)
464 #define NV_RX_SUBSTRACT1 (1<<18)
465 #define NV_RX_ERROR1 (1<<23)
466 #define NV_RX_ERROR2 (1<<24)
467 #define NV_RX_ERROR3 (1<<25)
468 #define NV_RX_ERROR4 (1<<26)
469 #define NV_RX_CRCERR (1<<27)
470 #define NV_RX_OVERFLOW (1<<28)
471 #define NV_RX_FRAMINGERR (1<<29)
472 #define NV_RX_ERROR (1<<30)
473 #define NV_RX_AVAIL (1<<31)
474
475 #define NV_RX2_CHECKSUMMASK (0x1C000000)
476 #define NV_RX2_CHECKSUM_IP (0x10000000)
477 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
478 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
479 #define NV_RX2_DESCRIPTORVALID (1<<29)
480 #define NV_RX2_SUBSTRACT1 (1<<25)
481 #define NV_RX2_ERROR1 (1<<18)
482 #define NV_RX2_ERROR2 (1<<19)
483 #define NV_RX2_ERROR3 (1<<20)
484 #define NV_RX2_ERROR4 (1<<21)
485 #define NV_RX2_CRCERR (1<<22)
486 #define NV_RX2_OVERFLOW (1<<23)
487 #define NV_RX2_FRAMINGERR (1<<24)
488 /* error and avail are the same for both */
489 #define NV_RX2_ERROR (1<<30)
490 #define NV_RX2_AVAIL (1<<31)
491
492 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
493 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
494
495 /* Miscelaneous hardware related defines: */
496 #define NV_PCI_REGSZ_VER1 0x270
497 #define NV_PCI_REGSZ_VER2 0x2d4
498 #define NV_PCI_REGSZ_VER3 0x604
499
500 /* various timeout delays: all in usec */
501 #define NV_TXRX_RESET_DELAY 4
502 #define NV_TXSTOP_DELAY1 10
503 #define NV_TXSTOP_DELAY1MAX 500000
504 #define NV_TXSTOP_DELAY2 100
505 #define NV_RXSTOP_DELAY1 10
506 #define NV_RXSTOP_DELAY1MAX 500000
507 #define NV_RXSTOP_DELAY2 100
508 #define NV_SETUP5_DELAY 5
509 #define NV_SETUP5_DELAYMAX 50000
510 #define NV_POWERUP_DELAY 5
511 #define NV_POWERUP_DELAYMAX 5000
512 #define NV_MIIBUSY_DELAY 50
513 #define NV_MIIPHY_DELAY 10
514 #define NV_MIIPHY_DELAYMAX 10000
515 #define NV_MAC_RESET_DELAY 64
516
517 #define NV_WAKEUPPATTERNS 5
518 #define NV_WAKEUPMASKENTRIES 4
519
520 /* General driver defaults */
521 #define NV_WATCHDOG_TIMEO (5*HZ)
522
523 #define RX_RING_DEFAULT 128
524 #define TX_RING_DEFAULT 256
525 #define RX_RING_MIN 128
526 #define TX_RING_MIN 64
527 #define RING_MAX_DESC_VER_1 1024
528 #define RING_MAX_DESC_VER_2_3 16384
529
530 /* rx/tx mac addr + type + vlan + align + slack*/
531 #define NV_RX_HEADERS (64)
532 /* even more slack. */
533 #define NV_RX_ALLOC_PAD (64)
534
535 /* maximum mtu size */
536 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
537 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
538
539 #define OOM_REFILL (1+HZ/20)
540 #define POLL_WAIT (1+HZ/100)
541 #define LINK_TIMEOUT (3*HZ)
542 #define STATS_INTERVAL (10*HZ)
543
544 /*
545 * desc_ver values:
546 * The nic supports three different descriptor types:
547 * - DESC_VER_1: Original
548 * - DESC_VER_2: support for jumbo frames.
549 * - DESC_VER_3: 64-bit format.
550 */
551 #define DESC_VER_1 1
552 #define DESC_VER_2 2
553 #define DESC_VER_3 3
554
555 /* PHY defines */
556 #define PHY_OUI_MARVELL 0x5043
557 #define PHY_OUI_CICADA 0x03f1
558 #define PHY_OUI_VITESSE 0x01c1
559 #define PHY_OUI_REALTEK 0x0732
560 #define PHYID1_OUI_MASK 0x03ff
561 #define PHYID1_OUI_SHFT 6
562 #define PHYID2_OUI_MASK 0xfc00
563 #define PHYID2_OUI_SHFT 10
564 #define PHYID2_MODEL_MASK 0x03f0
565 #define PHY_MODEL_MARVELL_E3016 0x220
566 #define PHY_MARVELL_E3016_INITMASK 0x0300
567 #define PHY_CICADA_INIT1 0x0f000
568 #define PHY_CICADA_INIT2 0x0e00
569 #define PHY_CICADA_INIT3 0x01000
570 #define PHY_CICADA_INIT4 0x0200
571 #define PHY_CICADA_INIT5 0x0004
572 #define PHY_CICADA_INIT6 0x02000
573 #define PHY_VITESSE_INIT_REG1 0x1f
574 #define PHY_VITESSE_INIT_REG2 0x10
575 #define PHY_VITESSE_INIT_REG3 0x11
576 #define PHY_VITESSE_INIT_REG4 0x12
577 #define PHY_VITESSE_INIT_MSK1 0xc
578 #define PHY_VITESSE_INIT_MSK2 0x0180
579 #define PHY_VITESSE_INIT1 0x52b5
580 #define PHY_VITESSE_INIT2 0xaf8a
581 #define PHY_VITESSE_INIT3 0x8
582 #define PHY_VITESSE_INIT4 0x8f8a
583 #define PHY_VITESSE_INIT5 0xaf86
584 #define PHY_VITESSE_INIT6 0x8f86
585 #define PHY_VITESSE_INIT7 0xaf82
586 #define PHY_VITESSE_INIT8 0x0100
587 #define PHY_VITESSE_INIT9 0x8f82
588 #define PHY_VITESSE_INIT10 0x0
589 #define PHY_REALTEK_INIT_REG1 0x1f
590 #define PHY_REALTEK_INIT_REG2 0x19
591 #define PHY_REALTEK_INIT_REG3 0x13
592 #define PHY_REALTEK_INIT1 0x0000
593 #define PHY_REALTEK_INIT2 0x8e00
594 #define PHY_REALTEK_INIT3 0x0001
595 #define PHY_REALTEK_INIT4 0xad17
596
597 #define PHY_GIGABIT 0x0100
598
599 #define PHY_TIMEOUT 0x1
600 #define PHY_ERROR 0x2
601
602 #define PHY_100 0x1
603 #define PHY_1000 0x2
604 #define PHY_HALF 0x100
605
606 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
607 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
608 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
609 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
610 #define NV_PAUSEFRAME_RX_REQ 0x0010
611 #define NV_PAUSEFRAME_TX_REQ 0x0020
612 #define NV_PAUSEFRAME_AUTONEG 0x0040
613
614 /* MSI/MSI-X defines */
615 #define NV_MSI_X_MAX_VECTORS 8
616 #define NV_MSI_X_VECTORS_MASK 0x000f
617 #define NV_MSI_CAPABLE 0x0010
618 #define NV_MSI_X_CAPABLE 0x0020
619 #define NV_MSI_ENABLED 0x0040
620 #define NV_MSI_X_ENABLED 0x0080
621
622 #define NV_MSI_X_VECTOR_ALL 0x0
623 #define NV_MSI_X_VECTOR_RX 0x0
624 #define NV_MSI_X_VECTOR_TX 0x1
625 #define NV_MSI_X_VECTOR_OTHER 0x2
626
627 #define NV_RESTART_TX 0x1
628 #define NV_RESTART_RX 0x2
629
630 /* statistics */
631 struct nv_ethtool_str {
632 char name[ETH_GSTRING_LEN];
633 };
634
635 static const struct nv_ethtool_str nv_estats_str[] = {
636 { "tx_bytes" },
637 { "tx_zero_rexmt" },
638 { "tx_one_rexmt" },
639 { "tx_many_rexmt" },
640 { "tx_late_collision" },
641 { "tx_fifo_errors" },
642 { "tx_carrier_errors" },
643 { "tx_excess_deferral" },
644 { "tx_retry_error" },
645 { "rx_frame_error" },
646 { "rx_extra_byte" },
647 { "rx_late_collision" },
648 { "rx_runt" },
649 { "rx_frame_too_long" },
650 { "rx_over_errors" },
651 { "rx_crc_errors" },
652 { "rx_frame_align_error" },
653 { "rx_length_error" },
654 { "rx_unicast" },
655 { "rx_multicast" },
656 { "rx_broadcast" },
657 { "rx_packets" },
658 { "rx_errors_total" },
659 { "tx_errors_total" },
660
661 /* version 2 stats */
662 { "tx_deferral" },
663 { "tx_packets" },
664 { "rx_bytes" },
665 { "tx_pause" },
666 { "rx_pause" },
667 { "rx_drop_frame" }
668 };
669
670 struct nv_ethtool_stats {
671 u64 tx_bytes;
672 u64 tx_zero_rexmt;
673 u64 tx_one_rexmt;
674 u64 tx_many_rexmt;
675 u64 tx_late_collision;
676 u64 tx_fifo_errors;
677 u64 tx_carrier_errors;
678 u64 tx_excess_deferral;
679 u64 tx_retry_error;
680 u64 rx_frame_error;
681 u64 rx_extra_byte;
682 u64 rx_late_collision;
683 u64 rx_runt;
684 u64 rx_frame_too_long;
685 u64 rx_over_errors;
686 u64 rx_crc_errors;
687 u64 rx_frame_align_error;
688 u64 rx_length_error;
689 u64 rx_unicast;
690 u64 rx_multicast;
691 u64 rx_broadcast;
692 u64 rx_packets;
693 u64 rx_errors_total;
694 u64 tx_errors_total;
695
696 /* version 2 stats */
697 u64 tx_deferral;
698 u64 tx_packets;
699 u64 rx_bytes;
700 u64 tx_pause;
701 u64 rx_pause;
702 u64 rx_drop_frame;
703 };
704
705 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
706 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
707
708 /* diagnostics */
709 #define NV_TEST_COUNT_BASE 3
710 #define NV_TEST_COUNT_EXTENDED 4
711
712 static const struct nv_ethtool_str nv_etests_str[] = {
713 { "link (online/offline)" },
714 { "register (offline) " },
715 { "interrupt (offline) " },
716 { "loopback (offline) " }
717 };
718
719 struct register_test {
720 __u32 reg;
721 __u32 mask;
722 };
723
724 static const struct register_test nv_registers_test[] = {
725 { NvRegUnknownSetupReg6, 0x01 },
726 { NvRegMisc1, 0x03c },
727 { NvRegOffloadConfig, 0x03ff },
728 { NvRegMulticastAddrA, 0xffffffff },
729 { NvRegTxWatermark, 0x0ff },
730 { NvRegWakeUpFlags, 0x07777 },
731 { 0,0 }
732 };
733
734 struct nv_skb_map {
735 struct sk_buff *skb;
736 dma_addr_t dma;
737 unsigned int dma_len;
738 };
739
740 /*
741 * SMP locking:
742 * All hardware access under dev->priv->lock, except the performance
743 * critical parts:
744 * - rx is (pseudo-) lockless: it relies on the single-threading provided
745 * by the arch code for interrupts.
746 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
747 * needs dev->priv->lock :-(
748 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
749 */
750
751 /* in dev: base, irq */
752 struct fe_priv {
753 spinlock_t lock;
754
755 struct net_device *dev;
756 struct napi_struct napi;
757
758 /* General data:
759 * Locking: spin_lock(&np->lock); */
760 struct nv_ethtool_stats estats;
761 int in_shutdown;
762 u32 linkspeed;
763 int duplex;
764 int autoneg;
765 int fixed_mode;
766 int phyaddr;
767 int wolenabled;
768 unsigned int phy_oui;
769 unsigned int phy_model;
770 u16 gigabit;
771 int intr_test;
772 int recover_error;
773
774 /* General data: RO fields */
775 dma_addr_t ring_addr;
776 struct pci_dev *pci_dev;
777 u32 orig_mac[2];
778 u32 irqmask;
779 u32 desc_ver;
780 u32 txrxctl_bits;
781 u32 vlanctl_bits;
782 u32 driver_data;
783 u32 register_size;
784 int rx_csum;
785 u32 mac_in_use;
786
787 void __iomem *base;
788
789 /* rx specific fields.
790 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
791 */
792 union ring_type get_rx, put_rx, first_rx, last_rx;
793 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
794 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
795 struct nv_skb_map *rx_skb;
796
797 union ring_type rx_ring;
798 unsigned int rx_buf_sz;
799 unsigned int pkt_limit;
800 struct timer_list oom_kick;
801 struct timer_list nic_poll;
802 struct timer_list stats_poll;
803 u32 nic_poll_irq;
804 int rx_ring_size;
805
806 /* media detection workaround.
807 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
808 */
809 int need_linktimer;
810 unsigned long link_timeout;
811 /*
812 * tx specific fields.
813 */
814 union ring_type get_tx, put_tx, first_tx, last_tx;
815 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
816 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
817 struct nv_skb_map *tx_skb;
818
819 union ring_type tx_ring;
820 u32 tx_flags;
821 int tx_ring_size;
822 int tx_stop;
823
824 /* vlan fields */
825 struct vlan_group *vlangrp;
826
827 /* msi/msi-x fields */
828 u32 msi_flags;
829 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
830
831 /* flow control */
832 u32 pause_flags;
833 };
834
835 /*
836 * Maximum number of loops until we assume that a bit in the irq mask
837 * is stuck. Overridable with module param.
838 */
839 static int max_interrupt_work = 5;
840
841 /*
842 * Optimization can be either throuput mode or cpu mode
843 *
844 * Throughput Mode: Every tx and rx packet will generate an interrupt.
845 * CPU Mode: Interrupts are controlled by a timer.
846 */
847 enum {
848 NV_OPTIMIZATION_MODE_THROUGHPUT,
849 NV_OPTIMIZATION_MODE_CPU
850 };
851 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
852
853 /*
854 * Poll interval for timer irq
855 *
856 * This interval determines how frequent an interrupt is generated.
857 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
858 * Min = 0, and Max = 65535
859 */
860 static int poll_interval = -1;
861
862 /*
863 * MSI interrupts
864 */
865 enum {
866 NV_MSI_INT_DISABLED,
867 NV_MSI_INT_ENABLED
868 };
869 static int msi = NV_MSI_INT_ENABLED;
870
871 /*
872 * MSIX interrupts
873 */
874 enum {
875 NV_MSIX_INT_DISABLED,
876 NV_MSIX_INT_ENABLED
877 };
878 static int msix = NV_MSIX_INT_DISABLED;
879
880 /*
881 * DMA 64bit
882 */
883 enum {
884 NV_DMA_64BIT_DISABLED,
885 NV_DMA_64BIT_ENABLED
886 };
887 static int dma_64bit = NV_DMA_64BIT_ENABLED;
888
889 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
890 {
891 return netdev_priv(dev);
892 }
893
894 static inline u8 __iomem *get_hwbase(struct net_device *dev)
895 {
896 return ((struct fe_priv *)netdev_priv(dev))->base;
897 }
898
899 static inline void pci_push(u8 __iomem *base)
900 {
901 /* force out pending posted writes */
902 readl(base);
903 }
904
905 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
906 {
907 return le32_to_cpu(prd->flaglen)
908 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
909 }
910
911 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
912 {
913 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
914 }
915
916 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
917 int delay, int delaymax, const char *msg)
918 {
919 u8 __iomem *base = get_hwbase(dev);
920
921 pci_push(base);
922 do {
923 udelay(delay);
924 delaymax -= delay;
925 if (delaymax < 0) {
926 if (msg)
927 printk(msg);
928 return 1;
929 }
930 } while ((readl(base + offset) & mask) != target);
931 return 0;
932 }
933
934 #define NV_SETUP_RX_RING 0x01
935 #define NV_SETUP_TX_RING 0x02
936
937 static inline u32 dma_low(dma_addr_t addr)
938 {
939 return addr;
940 }
941
942 static inline u32 dma_high(dma_addr_t addr)
943 {
944 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
945 }
946
947 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
948 {
949 struct fe_priv *np = get_nvpriv(dev);
950 u8 __iomem *base = get_hwbase(dev);
951
952 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
953 if (rxtx_flags & NV_SETUP_RX_RING) {
954 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
955 }
956 if (rxtx_flags & NV_SETUP_TX_RING) {
957 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
958 }
959 } else {
960 if (rxtx_flags & NV_SETUP_RX_RING) {
961 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
962 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
963 }
964 if (rxtx_flags & NV_SETUP_TX_RING) {
965 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
966 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
967 }
968 }
969 }
970
971 static void free_rings(struct net_device *dev)
972 {
973 struct fe_priv *np = get_nvpriv(dev);
974
975 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
976 if (np->rx_ring.orig)
977 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
978 np->rx_ring.orig, np->ring_addr);
979 } else {
980 if (np->rx_ring.ex)
981 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
982 np->rx_ring.ex, np->ring_addr);
983 }
984 if (np->rx_skb)
985 kfree(np->rx_skb);
986 if (np->tx_skb)
987 kfree(np->tx_skb);
988 }
989
990 static int using_multi_irqs(struct net_device *dev)
991 {
992 struct fe_priv *np = get_nvpriv(dev);
993
994 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
995 ((np->msi_flags & NV_MSI_X_ENABLED) &&
996 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
997 return 0;
998 else
999 return 1;
1000 }
1001
1002 static void nv_enable_irq(struct net_device *dev)
1003 {
1004 struct fe_priv *np = get_nvpriv(dev);
1005
1006 if (!using_multi_irqs(dev)) {
1007 if (np->msi_flags & NV_MSI_X_ENABLED)
1008 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1009 else
1010 enable_irq(np->pci_dev->irq);
1011 } else {
1012 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1013 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1014 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1015 }
1016 }
1017
1018 static void nv_disable_irq(struct net_device *dev)
1019 {
1020 struct fe_priv *np = get_nvpriv(dev);
1021
1022 if (!using_multi_irqs(dev)) {
1023 if (np->msi_flags & NV_MSI_X_ENABLED)
1024 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1025 else
1026 disable_irq(np->pci_dev->irq);
1027 } else {
1028 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1029 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1030 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1031 }
1032 }
1033
1034 /* In MSIX mode, a write to irqmask behaves as XOR */
1035 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1036 {
1037 u8 __iomem *base = get_hwbase(dev);
1038
1039 writel(mask, base + NvRegIrqMask);
1040 }
1041
1042 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1043 {
1044 struct fe_priv *np = get_nvpriv(dev);
1045 u8 __iomem *base = get_hwbase(dev);
1046
1047 if (np->msi_flags & NV_MSI_X_ENABLED) {
1048 writel(mask, base + NvRegIrqMask);
1049 } else {
1050 if (np->msi_flags & NV_MSI_ENABLED)
1051 writel(0, base + NvRegMSIIrqMask);
1052 writel(0, base + NvRegIrqMask);
1053 }
1054 }
1055
1056 #define MII_READ (-1)
1057 /* mii_rw: read/write a register on the PHY.
1058 *
1059 * Caller must guarantee serialization
1060 */
1061 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1062 {
1063 u8 __iomem *base = get_hwbase(dev);
1064 u32 reg;
1065 int retval;
1066
1067 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1068
1069 reg = readl(base + NvRegMIIControl);
1070 if (reg & NVREG_MIICTL_INUSE) {
1071 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1072 udelay(NV_MIIBUSY_DELAY);
1073 }
1074
1075 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1076 if (value != MII_READ) {
1077 writel(value, base + NvRegMIIData);
1078 reg |= NVREG_MIICTL_WRITE;
1079 }
1080 writel(reg, base + NvRegMIIControl);
1081
1082 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1083 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1084 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1085 dev->name, miireg, addr);
1086 retval = -1;
1087 } else if (value != MII_READ) {
1088 /* it was a write operation - fewer failures are detectable */
1089 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1090 dev->name, value, miireg, addr);
1091 retval = 0;
1092 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1093 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1094 dev->name, miireg, addr);
1095 retval = -1;
1096 } else {
1097 retval = readl(base + NvRegMIIData);
1098 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1099 dev->name, miireg, addr, retval);
1100 }
1101
1102 return retval;
1103 }
1104
1105 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1106 {
1107 struct fe_priv *np = netdev_priv(dev);
1108 u32 miicontrol;
1109 unsigned int tries = 0;
1110
1111 miicontrol = BMCR_RESET | bmcr_setup;
1112 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1113 return -1;
1114 }
1115
1116 /* wait for 500ms */
1117 msleep(500);
1118
1119 /* must wait till reset is deasserted */
1120 while (miicontrol & BMCR_RESET) {
1121 msleep(10);
1122 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1123 /* FIXME: 100 tries seem excessive */
1124 if (tries++ > 100)
1125 return -1;
1126 }
1127 return 0;
1128 }
1129
1130 static int phy_init(struct net_device *dev)
1131 {
1132 struct fe_priv *np = get_nvpriv(dev);
1133 u8 __iomem *base = get_hwbase(dev);
1134 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1135
1136 /* phy errata for E3016 phy */
1137 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1138 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1139 reg &= ~PHY_MARVELL_E3016_INITMASK;
1140 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1141 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1142 return PHY_ERROR;
1143 }
1144 }
1145 if (np->phy_oui == PHY_OUI_REALTEK) {
1146 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1147 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1148 return PHY_ERROR;
1149 }
1150 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1151 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1152 return PHY_ERROR;
1153 }
1154 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1155 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1156 return PHY_ERROR;
1157 }
1158 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1159 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1160 return PHY_ERROR;
1161 }
1162 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1163 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1164 return PHY_ERROR;
1165 }
1166 }
1167
1168 /* set advertise register */
1169 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1170 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1171 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1172 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1173 return PHY_ERROR;
1174 }
1175
1176 /* get phy interface type */
1177 phyinterface = readl(base + NvRegPhyInterface);
1178
1179 /* see if gigabit phy */
1180 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1181 if (mii_status & PHY_GIGABIT) {
1182 np->gigabit = PHY_GIGABIT;
1183 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1184 mii_control_1000 &= ~ADVERTISE_1000HALF;
1185 if (phyinterface & PHY_RGMII)
1186 mii_control_1000 |= ADVERTISE_1000FULL;
1187 else
1188 mii_control_1000 &= ~ADVERTISE_1000FULL;
1189
1190 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1191 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1192 return PHY_ERROR;
1193 }
1194 }
1195 else
1196 np->gigabit = 0;
1197
1198 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1199 mii_control |= BMCR_ANENABLE;
1200
1201 /* reset the phy
1202 * (certain phys need bmcr to be setup with reset)
1203 */
1204 if (phy_reset(dev, mii_control)) {
1205 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1206 return PHY_ERROR;
1207 }
1208
1209 /* phy vendor specific configuration */
1210 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1211 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1212 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1213 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1214 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1215 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1216 return PHY_ERROR;
1217 }
1218 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1219 phy_reserved |= PHY_CICADA_INIT5;
1220 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1221 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1222 return PHY_ERROR;
1223 }
1224 }
1225 if (np->phy_oui == PHY_OUI_CICADA) {
1226 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1227 phy_reserved |= PHY_CICADA_INIT6;
1228 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1229 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1230 return PHY_ERROR;
1231 }
1232 }
1233 if (np->phy_oui == PHY_OUI_VITESSE) {
1234 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1235 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1236 return PHY_ERROR;
1237 }
1238 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1239 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1240 return PHY_ERROR;
1241 }
1242 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1243 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1244 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1245 return PHY_ERROR;
1246 }
1247 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1248 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1249 phy_reserved |= PHY_VITESSE_INIT3;
1250 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1251 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1252 return PHY_ERROR;
1253 }
1254 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1255 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1256 return PHY_ERROR;
1257 }
1258 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1259 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1260 return PHY_ERROR;
1261 }
1262 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1263 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1264 phy_reserved |= PHY_VITESSE_INIT3;
1265 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1266 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1267 return PHY_ERROR;
1268 }
1269 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1270 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1271 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1272 return PHY_ERROR;
1273 }
1274 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1275 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1276 return PHY_ERROR;
1277 }
1278 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1279 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1280 return PHY_ERROR;
1281 }
1282 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1283 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1284 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1285 return PHY_ERROR;
1286 }
1287 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1288 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1289 phy_reserved |= PHY_VITESSE_INIT8;
1290 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1291 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1292 return PHY_ERROR;
1293 }
1294 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1295 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1296 return PHY_ERROR;
1297 }
1298 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1299 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1300 return PHY_ERROR;
1301 }
1302 }
1303 if (np->phy_oui == PHY_OUI_REALTEK) {
1304 /* reset could have cleared these out, set them back */
1305 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1306 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1307 return PHY_ERROR;
1308 }
1309 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1310 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1311 return PHY_ERROR;
1312 }
1313 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1314 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1315 return PHY_ERROR;
1316 }
1317 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1318 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1319 return PHY_ERROR;
1320 }
1321 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1322 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1323 return PHY_ERROR;
1324 }
1325 }
1326
1327 /* some phys clear out pause advertisment on reset, set it back */
1328 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1329
1330 /* restart auto negotiation */
1331 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1332 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1333 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1334 return PHY_ERROR;
1335 }
1336
1337 return 0;
1338 }
1339
1340 static void nv_start_rx(struct net_device *dev)
1341 {
1342 struct fe_priv *np = netdev_priv(dev);
1343 u8 __iomem *base = get_hwbase(dev);
1344 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1345
1346 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1347 /* Already running? Stop it. */
1348 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1349 rx_ctrl &= ~NVREG_RCVCTL_START;
1350 writel(rx_ctrl, base + NvRegReceiverControl);
1351 pci_push(base);
1352 }
1353 writel(np->linkspeed, base + NvRegLinkSpeed);
1354 pci_push(base);
1355 rx_ctrl |= NVREG_RCVCTL_START;
1356 if (np->mac_in_use)
1357 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1358 writel(rx_ctrl, base + NvRegReceiverControl);
1359 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1360 dev->name, np->duplex, np->linkspeed);
1361 pci_push(base);
1362 }
1363
1364 static void nv_stop_rx(struct net_device *dev)
1365 {
1366 struct fe_priv *np = netdev_priv(dev);
1367 u8 __iomem *base = get_hwbase(dev);
1368 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1369
1370 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1371 if (!np->mac_in_use)
1372 rx_ctrl &= ~NVREG_RCVCTL_START;
1373 else
1374 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1375 writel(rx_ctrl, base + NvRegReceiverControl);
1376 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1377 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1378 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1379
1380 udelay(NV_RXSTOP_DELAY2);
1381 if (!np->mac_in_use)
1382 writel(0, base + NvRegLinkSpeed);
1383 }
1384
1385 static void nv_start_tx(struct net_device *dev)
1386 {
1387 struct fe_priv *np = netdev_priv(dev);
1388 u8 __iomem *base = get_hwbase(dev);
1389 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1390
1391 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1392 tx_ctrl |= NVREG_XMITCTL_START;
1393 if (np->mac_in_use)
1394 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1395 writel(tx_ctrl, base + NvRegTransmitterControl);
1396 pci_push(base);
1397 }
1398
1399 static void nv_stop_tx(struct net_device *dev)
1400 {
1401 struct fe_priv *np = netdev_priv(dev);
1402 u8 __iomem *base = get_hwbase(dev);
1403 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1404
1405 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1406 if (!np->mac_in_use)
1407 tx_ctrl &= ~NVREG_XMITCTL_START;
1408 else
1409 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1410 writel(tx_ctrl, base + NvRegTransmitterControl);
1411 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1412 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1413 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1414
1415 udelay(NV_TXSTOP_DELAY2);
1416 if (!np->mac_in_use)
1417 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1418 base + NvRegTransmitPoll);
1419 }
1420
1421 static void nv_txrx_reset(struct net_device *dev)
1422 {
1423 struct fe_priv *np = netdev_priv(dev);
1424 u8 __iomem *base = get_hwbase(dev);
1425
1426 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1427 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1428 pci_push(base);
1429 udelay(NV_TXRX_RESET_DELAY);
1430 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1431 pci_push(base);
1432 }
1433
1434 static void nv_mac_reset(struct net_device *dev)
1435 {
1436 struct fe_priv *np = netdev_priv(dev);
1437 u8 __iomem *base = get_hwbase(dev);
1438 u32 temp1, temp2, temp3;
1439
1440 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1441
1442 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1443 pci_push(base);
1444
1445 /* save registers since they will be cleared on reset */
1446 temp1 = readl(base + NvRegMacAddrA);
1447 temp2 = readl(base + NvRegMacAddrB);
1448 temp3 = readl(base + NvRegTransmitPoll);
1449
1450 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1451 pci_push(base);
1452 udelay(NV_MAC_RESET_DELAY);
1453 writel(0, base + NvRegMacReset);
1454 pci_push(base);
1455 udelay(NV_MAC_RESET_DELAY);
1456
1457 /* restore saved registers */
1458 writel(temp1, base + NvRegMacAddrA);
1459 writel(temp2, base + NvRegMacAddrB);
1460 writel(temp3, base + NvRegTransmitPoll);
1461
1462 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1463 pci_push(base);
1464 }
1465
1466 static void nv_get_hw_stats(struct net_device *dev)
1467 {
1468 struct fe_priv *np = netdev_priv(dev);
1469 u8 __iomem *base = get_hwbase(dev);
1470
1471 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1472 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1473 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1474 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1475 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1476 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1477 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1478 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1479 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1480 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1481 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1482 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1483 np->estats.rx_runt += readl(base + NvRegRxRunt);
1484 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1485 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1486 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1487 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1488 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1489 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1490 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1491 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1492 np->estats.rx_packets =
1493 np->estats.rx_unicast +
1494 np->estats.rx_multicast +
1495 np->estats.rx_broadcast;
1496 np->estats.rx_errors_total =
1497 np->estats.rx_crc_errors +
1498 np->estats.rx_over_errors +
1499 np->estats.rx_frame_error +
1500 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1501 np->estats.rx_late_collision +
1502 np->estats.rx_runt +
1503 np->estats.rx_frame_too_long;
1504 np->estats.tx_errors_total =
1505 np->estats.tx_late_collision +
1506 np->estats.tx_fifo_errors +
1507 np->estats.tx_carrier_errors +
1508 np->estats.tx_excess_deferral +
1509 np->estats.tx_retry_error;
1510
1511 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1512 np->estats.tx_deferral += readl(base + NvRegTxDef);
1513 np->estats.tx_packets += readl(base + NvRegTxFrame);
1514 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1515 np->estats.tx_pause += readl(base + NvRegTxPause);
1516 np->estats.rx_pause += readl(base + NvRegRxPause);
1517 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1518 }
1519 }
1520
1521 /*
1522 * nv_get_stats: dev->get_stats function
1523 * Get latest stats value from the nic.
1524 * Called with read_lock(&dev_base_lock) held for read -
1525 * only synchronized against unregister_netdevice.
1526 */
1527 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1528 {
1529 struct fe_priv *np = netdev_priv(dev);
1530
1531 /* If the nic supports hw counters then retrieve latest values */
1532 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1533 nv_get_hw_stats(dev);
1534
1535 /* copy to net_device stats */
1536 dev->stats.tx_bytes = np->estats.tx_bytes;
1537 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1538 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1539 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1540 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1541 dev->stats.rx_errors = np->estats.rx_errors_total;
1542 dev->stats.tx_errors = np->estats.tx_errors_total;
1543 }
1544
1545 return &dev->stats;
1546 }
1547
1548 /*
1549 * nv_alloc_rx: fill rx ring entries.
1550 * Return 1 if the allocations for the skbs failed and the
1551 * rx engine is without Available descriptors
1552 */
1553 static int nv_alloc_rx(struct net_device *dev)
1554 {
1555 struct fe_priv *np = netdev_priv(dev);
1556 struct ring_desc* less_rx;
1557
1558 less_rx = np->get_rx.orig;
1559 if (less_rx-- == np->first_rx.orig)
1560 less_rx = np->last_rx.orig;
1561
1562 while (np->put_rx.orig != less_rx) {
1563 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1564 if (skb) {
1565 np->put_rx_ctx->skb = skb;
1566 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1567 skb->data,
1568 skb_tailroom(skb),
1569 PCI_DMA_FROMDEVICE);
1570 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1571 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1572 wmb();
1573 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1574 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1575 np->put_rx.orig = np->first_rx.orig;
1576 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1577 np->put_rx_ctx = np->first_rx_ctx;
1578 } else {
1579 return 1;
1580 }
1581 }
1582 return 0;
1583 }
1584
1585 static int nv_alloc_rx_optimized(struct net_device *dev)
1586 {
1587 struct fe_priv *np = netdev_priv(dev);
1588 struct ring_desc_ex* less_rx;
1589
1590 less_rx = np->get_rx.ex;
1591 if (less_rx-- == np->first_rx.ex)
1592 less_rx = np->last_rx.ex;
1593
1594 while (np->put_rx.ex != less_rx) {
1595 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1596 if (skb) {
1597 np->put_rx_ctx->skb = skb;
1598 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1599 skb->data,
1600 skb_tailroom(skb),
1601 PCI_DMA_FROMDEVICE);
1602 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1603 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1604 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1605 wmb();
1606 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1607 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1608 np->put_rx.ex = np->first_rx.ex;
1609 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1610 np->put_rx_ctx = np->first_rx_ctx;
1611 } else {
1612 return 1;
1613 }
1614 }
1615 return 0;
1616 }
1617
1618 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1619 #ifdef CONFIG_FORCEDETH_NAPI
1620 static void nv_do_rx_refill(unsigned long data)
1621 {
1622 struct net_device *dev = (struct net_device *) data;
1623 struct fe_priv *np = netdev_priv(dev);
1624
1625 /* Just reschedule NAPI rx processing */
1626 netif_rx_schedule(dev, &np->napi);
1627 }
1628 #else
1629 static void nv_do_rx_refill(unsigned long data)
1630 {
1631 struct net_device *dev = (struct net_device *) data;
1632 struct fe_priv *np = netdev_priv(dev);
1633 int retcode;
1634
1635 if (!using_multi_irqs(dev)) {
1636 if (np->msi_flags & NV_MSI_X_ENABLED)
1637 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1638 else
1639 disable_irq(np->pci_dev->irq);
1640 } else {
1641 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1642 }
1643 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1644 retcode = nv_alloc_rx(dev);
1645 else
1646 retcode = nv_alloc_rx_optimized(dev);
1647 if (retcode) {
1648 spin_lock_irq(&np->lock);
1649 if (!np->in_shutdown)
1650 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1651 spin_unlock_irq(&np->lock);
1652 }
1653 if (!using_multi_irqs(dev)) {
1654 if (np->msi_flags & NV_MSI_X_ENABLED)
1655 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1656 else
1657 enable_irq(np->pci_dev->irq);
1658 } else {
1659 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1660 }
1661 }
1662 #endif
1663
1664 static void nv_init_rx(struct net_device *dev)
1665 {
1666 struct fe_priv *np = netdev_priv(dev);
1667 int i;
1668 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1669 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1670 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1671 else
1672 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1673 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1674 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1675
1676 for (i = 0; i < np->rx_ring_size; i++) {
1677 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1678 np->rx_ring.orig[i].flaglen = 0;
1679 np->rx_ring.orig[i].buf = 0;
1680 } else {
1681 np->rx_ring.ex[i].flaglen = 0;
1682 np->rx_ring.ex[i].txvlan = 0;
1683 np->rx_ring.ex[i].bufhigh = 0;
1684 np->rx_ring.ex[i].buflow = 0;
1685 }
1686 np->rx_skb[i].skb = NULL;
1687 np->rx_skb[i].dma = 0;
1688 }
1689 }
1690
1691 static void nv_init_tx(struct net_device *dev)
1692 {
1693 struct fe_priv *np = netdev_priv(dev);
1694 int i;
1695 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1696 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1697 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1698 else
1699 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1700 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1701 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1702
1703 for (i = 0; i < np->tx_ring_size; i++) {
1704 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1705 np->tx_ring.orig[i].flaglen = 0;
1706 np->tx_ring.orig[i].buf = 0;
1707 } else {
1708 np->tx_ring.ex[i].flaglen = 0;
1709 np->tx_ring.ex[i].txvlan = 0;
1710 np->tx_ring.ex[i].bufhigh = 0;
1711 np->tx_ring.ex[i].buflow = 0;
1712 }
1713 np->tx_skb[i].skb = NULL;
1714 np->tx_skb[i].dma = 0;
1715 }
1716 }
1717
1718 static int nv_init_ring(struct net_device *dev)
1719 {
1720 struct fe_priv *np = netdev_priv(dev);
1721
1722 nv_init_tx(dev);
1723 nv_init_rx(dev);
1724 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1725 return nv_alloc_rx(dev);
1726 else
1727 return nv_alloc_rx_optimized(dev);
1728 }
1729
1730 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1731 {
1732 struct fe_priv *np = netdev_priv(dev);
1733
1734 if (tx_skb->dma) {
1735 pci_unmap_page(np->pci_dev, tx_skb->dma,
1736 tx_skb->dma_len,
1737 PCI_DMA_TODEVICE);
1738 tx_skb->dma = 0;
1739 }
1740 if (tx_skb->skb) {
1741 dev_kfree_skb_any(tx_skb->skb);
1742 tx_skb->skb = NULL;
1743 return 1;
1744 } else {
1745 return 0;
1746 }
1747 }
1748
1749 static void nv_drain_tx(struct net_device *dev)
1750 {
1751 struct fe_priv *np = netdev_priv(dev);
1752 unsigned int i;
1753
1754 for (i = 0; i < np->tx_ring_size; i++) {
1755 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1756 np->tx_ring.orig[i].flaglen = 0;
1757 np->tx_ring.orig[i].buf = 0;
1758 } else {
1759 np->tx_ring.ex[i].flaglen = 0;
1760 np->tx_ring.ex[i].txvlan = 0;
1761 np->tx_ring.ex[i].bufhigh = 0;
1762 np->tx_ring.ex[i].buflow = 0;
1763 }
1764 if (nv_release_txskb(dev, &np->tx_skb[i]))
1765 dev->stats.tx_dropped++;
1766 }
1767 }
1768
1769 static void nv_drain_rx(struct net_device *dev)
1770 {
1771 struct fe_priv *np = netdev_priv(dev);
1772 int i;
1773
1774 for (i = 0; i < np->rx_ring_size; i++) {
1775 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1776 np->rx_ring.orig[i].flaglen = 0;
1777 np->rx_ring.orig[i].buf = 0;
1778 } else {
1779 np->rx_ring.ex[i].flaglen = 0;
1780 np->rx_ring.ex[i].txvlan = 0;
1781 np->rx_ring.ex[i].bufhigh = 0;
1782 np->rx_ring.ex[i].buflow = 0;
1783 }
1784 wmb();
1785 if (np->rx_skb[i].skb) {
1786 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1787 (skb_end_pointer(np->rx_skb[i].skb) -
1788 np->rx_skb[i].skb->data),
1789 PCI_DMA_FROMDEVICE);
1790 dev_kfree_skb(np->rx_skb[i].skb);
1791 np->rx_skb[i].skb = NULL;
1792 }
1793 }
1794 }
1795
1796 static void drain_ring(struct net_device *dev)
1797 {
1798 nv_drain_tx(dev);
1799 nv_drain_rx(dev);
1800 }
1801
1802 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1803 {
1804 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1805 }
1806
1807 /*
1808 * nv_start_xmit: dev->hard_start_xmit function
1809 * Called with netif_tx_lock held.
1810 */
1811 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1812 {
1813 struct fe_priv *np = netdev_priv(dev);
1814 u32 tx_flags = 0;
1815 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1816 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1817 unsigned int i;
1818 u32 offset = 0;
1819 u32 bcnt;
1820 u32 size = skb->len-skb->data_len;
1821 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1822 u32 empty_slots;
1823 struct ring_desc* put_tx;
1824 struct ring_desc* start_tx;
1825 struct ring_desc* prev_tx;
1826 struct nv_skb_map* prev_tx_ctx;
1827
1828 /* add fragments to entries count */
1829 for (i = 0; i < fragments; i++) {
1830 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1831 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1832 }
1833
1834 empty_slots = nv_get_empty_tx_slots(np);
1835 if (unlikely(empty_slots <= entries)) {
1836 spin_lock_irq(&np->lock);
1837 netif_stop_queue(dev);
1838 np->tx_stop = 1;
1839 spin_unlock_irq(&np->lock);
1840 return NETDEV_TX_BUSY;
1841 }
1842
1843 start_tx = put_tx = np->put_tx.orig;
1844
1845 /* setup the header buffer */
1846 do {
1847 prev_tx = put_tx;
1848 prev_tx_ctx = np->put_tx_ctx;
1849 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1850 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1851 PCI_DMA_TODEVICE);
1852 np->put_tx_ctx->dma_len = bcnt;
1853 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1854 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1855
1856 tx_flags = np->tx_flags;
1857 offset += bcnt;
1858 size -= bcnt;
1859 if (unlikely(put_tx++ == np->last_tx.orig))
1860 put_tx = np->first_tx.orig;
1861 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1862 np->put_tx_ctx = np->first_tx_ctx;
1863 } while (size);
1864
1865 /* setup the fragments */
1866 for (i = 0; i < fragments; i++) {
1867 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1868 u32 size = frag->size;
1869 offset = 0;
1870
1871 do {
1872 prev_tx = put_tx;
1873 prev_tx_ctx = np->put_tx_ctx;
1874 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1875 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1876 PCI_DMA_TODEVICE);
1877 np->put_tx_ctx->dma_len = bcnt;
1878 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1879 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1880
1881 offset += bcnt;
1882 size -= bcnt;
1883 if (unlikely(put_tx++ == np->last_tx.orig))
1884 put_tx = np->first_tx.orig;
1885 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1886 np->put_tx_ctx = np->first_tx_ctx;
1887 } while (size);
1888 }
1889
1890 /* set last fragment flag */
1891 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1892
1893 /* save skb in this slot's context area */
1894 prev_tx_ctx->skb = skb;
1895
1896 if (skb_is_gso(skb))
1897 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1898 else
1899 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1900 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1901
1902 spin_lock_irq(&np->lock);
1903
1904 /* set tx flags */
1905 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1906 np->put_tx.orig = put_tx;
1907
1908 spin_unlock_irq(&np->lock);
1909
1910 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1911 dev->name, entries, tx_flags_extra);
1912 {
1913 int j;
1914 for (j=0; j<64; j++) {
1915 if ((j%16) == 0)
1916 dprintk("\n%03x:", j);
1917 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1918 }
1919 dprintk("\n");
1920 }
1921
1922 dev->trans_start = jiffies;
1923 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1924 return NETDEV_TX_OK;
1925 }
1926
1927 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1928 {
1929 struct fe_priv *np = netdev_priv(dev);
1930 u32 tx_flags = 0;
1931 u32 tx_flags_extra;
1932 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1933 unsigned int i;
1934 u32 offset = 0;
1935 u32 bcnt;
1936 u32 size = skb->len-skb->data_len;
1937 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1938 u32 empty_slots;
1939 struct ring_desc_ex* put_tx;
1940 struct ring_desc_ex* start_tx;
1941 struct ring_desc_ex* prev_tx;
1942 struct nv_skb_map* prev_tx_ctx;
1943
1944 /* add fragments to entries count */
1945 for (i = 0; i < fragments; i++) {
1946 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1947 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1948 }
1949
1950 empty_slots = nv_get_empty_tx_slots(np);
1951 if (unlikely(empty_slots <= entries)) {
1952 spin_lock_irq(&np->lock);
1953 netif_stop_queue(dev);
1954 np->tx_stop = 1;
1955 spin_unlock_irq(&np->lock);
1956 return NETDEV_TX_BUSY;
1957 }
1958
1959 start_tx = put_tx = np->put_tx.ex;
1960
1961 /* setup the header buffer */
1962 do {
1963 prev_tx = put_tx;
1964 prev_tx_ctx = np->put_tx_ctx;
1965 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1966 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1967 PCI_DMA_TODEVICE);
1968 np->put_tx_ctx->dma_len = bcnt;
1969 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
1970 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
1971 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1972
1973 tx_flags = NV_TX2_VALID;
1974 offset += bcnt;
1975 size -= bcnt;
1976 if (unlikely(put_tx++ == np->last_tx.ex))
1977 put_tx = np->first_tx.ex;
1978 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1979 np->put_tx_ctx = np->first_tx_ctx;
1980 } while (size);
1981
1982 /* setup the fragments */
1983 for (i = 0; i < fragments; i++) {
1984 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1985 u32 size = frag->size;
1986 offset = 0;
1987
1988 do {
1989 prev_tx = put_tx;
1990 prev_tx_ctx = np->put_tx_ctx;
1991 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1992 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1993 PCI_DMA_TODEVICE);
1994 np->put_tx_ctx->dma_len = bcnt;
1995 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
1996 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
1997 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1998
1999 offset += bcnt;
2000 size -= bcnt;
2001 if (unlikely(put_tx++ == np->last_tx.ex))
2002 put_tx = np->first_tx.ex;
2003 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2004 np->put_tx_ctx = np->first_tx_ctx;
2005 } while (size);
2006 }
2007
2008 /* set last fragment flag */
2009 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2010
2011 /* save skb in this slot's context area */
2012 prev_tx_ctx->skb = skb;
2013
2014 if (skb_is_gso(skb))
2015 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2016 else
2017 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2018 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2019
2020 /* vlan tag */
2021 if (likely(!np->vlangrp)) {
2022 start_tx->txvlan = 0;
2023 } else {
2024 if (vlan_tx_tag_present(skb))
2025 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2026 else
2027 start_tx->txvlan = 0;
2028 }
2029
2030 spin_lock_irq(&np->lock);
2031
2032 /* set tx flags */
2033 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2034 np->put_tx.ex = put_tx;
2035
2036 spin_unlock_irq(&np->lock);
2037
2038 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2039 dev->name, entries, tx_flags_extra);
2040 {
2041 int j;
2042 for (j=0; j<64; j++) {
2043 if ((j%16) == 0)
2044 dprintk("\n%03x:", j);
2045 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2046 }
2047 dprintk("\n");
2048 }
2049
2050 dev->trans_start = jiffies;
2051 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2052 return NETDEV_TX_OK;
2053 }
2054
2055 /*
2056 * nv_tx_done: check for completed packets, release the skbs.
2057 *
2058 * Caller must own np->lock.
2059 */
2060 static void nv_tx_done(struct net_device *dev)
2061 {
2062 struct fe_priv *np = netdev_priv(dev);
2063 u32 flags;
2064 struct ring_desc* orig_get_tx = np->get_tx.orig;
2065
2066 while ((np->get_tx.orig != np->put_tx.orig) &&
2067 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2068
2069 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2070 dev->name, flags);
2071
2072 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2073 np->get_tx_ctx->dma_len,
2074 PCI_DMA_TODEVICE);
2075 np->get_tx_ctx->dma = 0;
2076
2077 if (np->desc_ver == DESC_VER_1) {
2078 if (flags & NV_TX_LASTPACKET) {
2079 if (flags & NV_TX_ERROR) {
2080 if (flags & NV_TX_UNDERFLOW)
2081 dev->stats.tx_fifo_errors++;
2082 if (flags & NV_TX_CARRIERLOST)
2083 dev->stats.tx_carrier_errors++;
2084 dev->stats.tx_errors++;
2085 } else {
2086 dev->stats.tx_packets++;
2087 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2088 }
2089 dev_kfree_skb_any(np->get_tx_ctx->skb);
2090 np->get_tx_ctx->skb = NULL;
2091 }
2092 } else {
2093 if (flags & NV_TX2_LASTPACKET) {
2094 if (flags & NV_TX2_ERROR) {
2095 if (flags & NV_TX2_UNDERFLOW)
2096 dev->stats.tx_fifo_errors++;
2097 if (flags & NV_TX2_CARRIERLOST)
2098 dev->stats.tx_carrier_errors++;
2099 dev->stats.tx_errors++;
2100 } else {
2101 dev->stats.tx_packets++;
2102 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2103 }
2104 dev_kfree_skb_any(np->get_tx_ctx->skb);
2105 np->get_tx_ctx->skb = NULL;
2106 }
2107 }
2108 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2109 np->get_tx.orig = np->first_tx.orig;
2110 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2111 np->get_tx_ctx = np->first_tx_ctx;
2112 }
2113 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2114 np->tx_stop = 0;
2115 netif_wake_queue(dev);
2116 }
2117 }
2118
2119 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2120 {
2121 struct fe_priv *np = netdev_priv(dev);
2122 u32 flags;
2123 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2124
2125 while ((np->get_tx.ex != np->put_tx.ex) &&
2126 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2127 (limit-- > 0)) {
2128
2129 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2130 dev->name, flags);
2131
2132 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2133 np->get_tx_ctx->dma_len,
2134 PCI_DMA_TODEVICE);
2135 np->get_tx_ctx->dma = 0;
2136
2137 if (flags & NV_TX2_LASTPACKET) {
2138 if (!(flags & NV_TX2_ERROR))
2139 dev->stats.tx_packets++;
2140 dev_kfree_skb_any(np->get_tx_ctx->skb);
2141 np->get_tx_ctx->skb = NULL;
2142 }
2143 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2144 np->get_tx.ex = np->first_tx.ex;
2145 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2146 np->get_tx_ctx = np->first_tx_ctx;
2147 }
2148 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2149 np->tx_stop = 0;
2150 netif_wake_queue(dev);
2151 }
2152 }
2153
2154 /*
2155 * nv_tx_timeout: dev->tx_timeout function
2156 * Called with netif_tx_lock held.
2157 */
2158 static void nv_tx_timeout(struct net_device *dev)
2159 {
2160 struct fe_priv *np = netdev_priv(dev);
2161 u8 __iomem *base = get_hwbase(dev);
2162 u32 status;
2163
2164 if (np->msi_flags & NV_MSI_X_ENABLED)
2165 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2166 else
2167 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2168
2169 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2170
2171 {
2172 int i;
2173
2174 printk(KERN_INFO "%s: Ring at %lx\n",
2175 dev->name, (unsigned long)np->ring_addr);
2176 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2177 for (i=0;i<=np->register_size;i+= 32) {
2178 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2179 i,
2180 readl(base + i + 0), readl(base + i + 4),
2181 readl(base + i + 8), readl(base + i + 12),
2182 readl(base + i + 16), readl(base + i + 20),
2183 readl(base + i + 24), readl(base + i + 28));
2184 }
2185 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2186 for (i=0;i<np->tx_ring_size;i+= 4) {
2187 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2188 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2189 i,
2190 le32_to_cpu(np->tx_ring.orig[i].buf),
2191 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2192 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2193 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2194 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2195 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2196 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2197 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2198 } else {
2199 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2200 i,
2201 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2202 le32_to_cpu(np->tx_ring.ex[i].buflow),
2203 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2204 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2205 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2206 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2207 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2208 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2209 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2210 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2211 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2212 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2213 }
2214 }
2215 }
2216
2217 spin_lock_irq(&np->lock);
2218
2219 /* 1) stop tx engine */
2220 nv_stop_tx(dev);
2221
2222 /* 2) check that the packets were not sent already: */
2223 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2224 nv_tx_done(dev);
2225 else
2226 nv_tx_done_optimized(dev, np->tx_ring_size);
2227
2228 /* 3) if there are dead entries: clear everything */
2229 if (np->get_tx_ctx != np->put_tx_ctx) {
2230 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2231 nv_drain_tx(dev);
2232 nv_init_tx(dev);
2233 setup_hw_rings(dev, NV_SETUP_TX_RING);
2234 }
2235
2236 netif_wake_queue(dev);
2237
2238 /* 4) restart tx engine */
2239 nv_start_tx(dev);
2240 spin_unlock_irq(&np->lock);
2241 }
2242
2243 /*
2244 * Called when the nic notices a mismatch between the actual data len on the
2245 * wire and the len indicated in the 802 header
2246 */
2247 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2248 {
2249 int hdrlen; /* length of the 802 header */
2250 int protolen; /* length as stored in the proto field */
2251
2252 /* 1) calculate len according to header */
2253 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2254 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2255 hdrlen = VLAN_HLEN;
2256 } else {
2257 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2258 hdrlen = ETH_HLEN;
2259 }
2260 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2261 dev->name, datalen, protolen, hdrlen);
2262 if (protolen > ETH_DATA_LEN)
2263 return datalen; /* Value in proto field not a len, no checks possible */
2264
2265 protolen += hdrlen;
2266 /* consistency checks: */
2267 if (datalen > ETH_ZLEN) {
2268 if (datalen >= protolen) {
2269 /* more data on wire than in 802 header, trim of
2270 * additional data.
2271 */
2272 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2273 dev->name, protolen);
2274 return protolen;
2275 } else {
2276 /* less data on wire than mentioned in header.
2277 * Discard the packet.
2278 */
2279 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2280 dev->name);
2281 return -1;
2282 }
2283 } else {
2284 /* short packet. Accept only if 802 values are also short */
2285 if (protolen > ETH_ZLEN) {
2286 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2287 dev->name);
2288 return -1;
2289 }
2290 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2291 dev->name, datalen);
2292 return datalen;
2293 }
2294 }
2295
2296 static int nv_rx_process(struct net_device *dev, int limit)
2297 {
2298 struct fe_priv *np = netdev_priv(dev);
2299 u32 flags;
2300 int rx_work = 0;
2301 struct sk_buff *skb;
2302 int len;
2303
2304 while((np->get_rx.orig != np->put_rx.orig) &&
2305 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2306 (rx_work < limit)) {
2307
2308 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2309 dev->name, flags);
2310
2311 /*
2312 * the packet is for us - immediately tear down the pci mapping.
2313 * TODO: check if a prefetch of the first cacheline improves
2314 * the performance.
2315 */
2316 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2317 np->get_rx_ctx->dma_len,
2318 PCI_DMA_FROMDEVICE);
2319 skb = np->get_rx_ctx->skb;
2320 np->get_rx_ctx->skb = NULL;
2321
2322 {
2323 int j;
2324 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2325 for (j=0; j<64; j++) {
2326 if ((j%16) == 0)
2327 dprintk("\n%03x:", j);
2328 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2329 }
2330 dprintk("\n");
2331 }
2332 /* look at what we actually got: */
2333 if (np->desc_ver == DESC_VER_1) {
2334 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2335 len = flags & LEN_MASK_V1;
2336 if (unlikely(flags & NV_RX_ERROR)) {
2337 if (flags & NV_RX_ERROR4) {
2338 len = nv_getlen(dev, skb->data, len);
2339 if (len < 0) {
2340 dev->stats.rx_errors++;
2341 dev_kfree_skb(skb);
2342 goto next_pkt;
2343 }
2344 }
2345 /* framing errors are soft errors */
2346 else if (flags & NV_RX_FRAMINGERR) {
2347 if (flags & NV_RX_SUBSTRACT1) {
2348 len--;
2349 }
2350 }
2351 /* the rest are hard errors */
2352 else {
2353 if (flags & NV_RX_MISSEDFRAME)
2354 dev->stats.rx_missed_errors++;
2355 if (flags & NV_RX_CRCERR)
2356 dev->stats.rx_crc_errors++;
2357 if (flags & NV_RX_OVERFLOW)
2358 dev->stats.rx_over_errors++;
2359 dev->stats.rx_errors++;
2360 dev_kfree_skb(skb);
2361 goto next_pkt;
2362 }
2363 }
2364 } else {
2365 dev_kfree_skb(skb);
2366 goto next_pkt;
2367 }
2368 } else {
2369 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2370 len = flags & LEN_MASK_V2;
2371 if (unlikely(flags & NV_RX2_ERROR)) {
2372 if (flags & NV_RX2_ERROR4) {
2373 len = nv_getlen(dev, skb->data, len);
2374 if (len < 0) {
2375 dev->stats.rx_errors++;
2376 dev_kfree_skb(skb);
2377 goto next_pkt;
2378 }
2379 }
2380 /* framing errors are soft errors */
2381 else if (flags & NV_RX2_FRAMINGERR) {
2382 if (flags & NV_RX2_SUBSTRACT1) {
2383 len--;
2384 }
2385 }
2386 /* the rest are hard errors */
2387 else {
2388 if (flags & NV_RX2_CRCERR)
2389 dev->stats.rx_crc_errors++;
2390 if (flags & NV_RX2_OVERFLOW)
2391 dev->stats.rx_over_errors++;
2392 dev->stats.rx_errors++;
2393 dev_kfree_skb(skb);
2394 goto next_pkt;
2395 }
2396 }
2397 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2398 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2399 skb->ip_summed = CHECKSUM_UNNECESSARY;
2400 } else {
2401 dev_kfree_skb(skb);
2402 goto next_pkt;
2403 }
2404 }
2405 /* got a valid packet - forward it to the network core */
2406 skb_put(skb, len);
2407 skb->protocol = eth_type_trans(skb, dev);
2408 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2409 dev->name, len, skb->protocol);
2410 #ifdef CONFIG_FORCEDETH_NAPI
2411 netif_receive_skb(skb);
2412 #else
2413 netif_rx(skb);
2414 #endif
2415 dev->last_rx = jiffies;
2416 dev->stats.rx_packets++;
2417 dev->stats.rx_bytes += len;
2418 next_pkt:
2419 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2420 np->get_rx.orig = np->first_rx.orig;
2421 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2422 np->get_rx_ctx = np->first_rx_ctx;
2423
2424 rx_work++;
2425 }
2426
2427 return rx_work;
2428 }
2429
2430 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2431 {
2432 struct fe_priv *np = netdev_priv(dev);
2433 u32 flags;
2434 u32 vlanflags = 0;
2435 int rx_work = 0;
2436 struct sk_buff *skb;
2437 int len;
2438
2439 while((np->get_rx.ex != np->put_rx.ex) &&
2440 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2441 (rx_work < limit)) {
2442
2443 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2444 dev->name, flags);
2445
2446 /*
2447 * the packet is for us - immediately tear down the pci mapping.
2448 * TODO: check if a prefetch of the first cacheline improves
2449 * the performance.
2450 */
2451 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2452 np->get_rx_ctx->dma_len,
2453 PCI_DMA_FROMDEVICE);
2454 skb = np->get_rx_ctx->skb;
2455 np->get_rx_ctx->skb = NULL;
2456
2457 {
2458 int j;
2459 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2460 for (j=0; j<64; j++) {
2461 if ((j%16) == 0)
2462 dprintk("\n%03x:", j);
2463 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2464 }
2465 dprintk("\n");
2466 }
2467 /* look at what we actually got: */
2468 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2469 len = flags & LEN_MASK_V2;
2470 if (unlikely(flags & NV_RX2_ERROR)) {
2471 if (flags & NV_RX2_ERROR4) {
2472 len = nv_getlen(dev, skb->data, len);
2473 if (len < 0) {
2474 dev_kfree_skb(skb);
2475 goto next_pkt;
2476 }
2477 }
2478 /* framing errors are soft errors */
2479 else if (flags & NV_RX2_FRAMINGERR) {
2480 if (flags & NV_RX2_SUBSTRACT1) {
2481 len--;
2482 }
2483 }
2484 /* the rest are hard errors */
2485 else {
2486 dev_kfree_skb(skb);
2487 goto next_pkt;
2488 }
2489 }
2490
2491 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2492 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2493 skb->ip_summed = CHECKSUM_UNNECESSARY;
2494
2495 /* got a valid packet - forward it to the network core */
2496 skb_put(skb, len);
2497 skb->protocol = eth_type_trans(skb, dev);
2498 prefetch(skb->data);
2499
2500 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2501 dev->name, len, skb->protocol);
2502
2503 if (likely(!np->vlangrp)) {
2504 #ifdef CONFIG_FORCEDETH_NAPI
2505 netif_receive_skb(skb);
2506 #else
2507 netif_rx(skb);
2508 #endif
2509 } else {
2510 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2511 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2512 #ifdef CONFIG_FORCEDETH_NAPI
2513 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2514 vlanflags & NV_RX3_VLAN_TAG_MASK);
2515 #else
2516 vlan_hwaccel_rx(skb, np->vlangrp,
2517 vlanflags & NV_RX3_VLAN_TAG_MASK);
2518 #endif
2519 } else {
2520 #ifdef CONFIG_FORCEDETH_NAPI
2521 netif_receive_skb(skb);
2522 #else
2523 netif_rx(skb);
2524 #endif
2525 }
2526 }
2527
2528 dev->last_rx = jiffies;
2529 dev->stats.rx_packets++;
2530 dev->stats.rx_bytes += len;
2531 } else {
2532 dev_kfree_skb(skb);
2533 }
2534 next_pkt:
2535 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2536 np->get_rx.ex = np->first_rx.ex;
2537 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2538 np->get_rx_ctx = np->first_rx_ctx;
2539
2540 rx_work++;
2541 }
2542
2543 return rx_work;
2544 }
2545
2546 static void set_bufsize(struct net_device *dev)
2547 {
2548 struct fe_priv *np = netdev_priv(dev);
2549
2550 if (dev->mtu <= ETH_DATA_LEN)
2551 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2552 else
2553 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2554 }
2555
2556 /*
2557 * nv_change_mtu: dev->change_mtu function
2558 * Called with dev_base_lock held for read.
2559 */
2560 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2561 {
2562 struct fe_priv *np = netdev_priv(dev);
2563 int old_mtu;
2564
2565 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2566 return -EINVAL;
2567
2568 old_mtu = dev->mtu;
2569 dev->mtu = new_mtu;
2570
2571 /* return early if the buffer sizes will not change */
2572 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2573 return 0;
2574 if (old_mtu == new_mtu)
2575 return 0;
2576
2577 /* synchronized against open : rtnl_lock() held by caller */
2578 if (netif_running(dev)) {
2579 u8 __iomem *base = get_hwbase(dev);
2580 /*
2581 * It seems that the nic preloads valid ring entries into an
2582 * internal buffer. The procedure for flushing everything is
2583 * guessed, there is probably a simpler approach.
2584 * Changing the MTU is a rare event, it shouldn't matter.
2585 */
2586 nv_disable_irq(dev);
2587 netif_tx_lock_bh(dev);
2588 spin_lock(&np->lock);
2589 /* stop engines */
2590 nv_stop_rx(dev);
2591 nv_stop_tx(dev);
2592 nv_txrx_reset(dev);
2593 /* drain rx queue */
2594 nv_drain_rx(dev);
2595 nv_drain_tx(dev);
2596 /* reinit driver view of the rx queue */
2597 set_bufsize(dev);
2598 if (nv_init_ring(dev)) {
2599 if (!np->in_shutdown)
2600 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2601 }
2602 /* reinit nic view of the rx queue */
2603 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2604 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2605 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2606 base + NvRegRingSizes);
2607 pci_push(base);
2608 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2609 pci_push(base);
2610
2611 /* restart rx engine */
2612 nv_start_rx(dev);
2613 nv_start_tx(dev);
2614 spin_unlock(&np->lock);
2615 netif_tx_unlock_bh(dev);
2616 nv_enable_irq(dev);
2617 }
2618 return 0;
2619 }
2620
2621 static void nv_copy_mac_to_hw(struct net_device *dev)
2622 {
2623 u8 __iomem *base = get_hwbase(dev);
2624 u32 mac[2];
2625
2626 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2627 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2628 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2629
2630 writel(mac[0], base + NvRegMacAddrA);
2631 writel(mac[1], base + NvRegMacAddrB);
2632 }
2633
2634 /*
2635 * nv_set_mac_address: dev->set_mac_address function
2636 * Called with rtnl_lock() held.
2637 */
2638 static int nv_set_mac_address(struct net_device *dev, void *addr)
2639 {
2640 struct fe_priv *np = netdev_priv(dev);
2641 struct sockaddr *macaddr = (struct sockaddr*)addr;
2642
2643 if (!is_valid_ether_addr(macaddr->sa_data))
2644 return -EADDRNOTAVAIL;
2645
2646 /* synchronized against open : rtnl_lock() held by caller */
2647 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2648
2649 if (netif_running(dev)) {
2650 netif_tx_lock_bh(dev);
2651 spin_lock_irq(&np->lock);
2652
2653 /* stop rx engine */
2654 nv_stop_rx(dev);
2655
2656 /* set mac address */
2657 nv_copy_mac_to_hw(dev);
2658
2659 /* restart rx engine */
2660 nv_start_rx(dev);
2661 spin_unlock_irq(&np->lock);
2662 netif_tx_unlock_bh(dev);
2663 } else {
2664 nv_copy_mac_to_hw(dev);
2665 }
2666 return 0;
2667 }
2668
2669 /*
2670 * nv_set_multicast: dev->set_multicast function
2671 * Called with netif_tx_lock held.
2672 */
2673 static void nv_set_multicast(struct net_device *dev)
2674 {
2675 struct fe_priv *np = netdev_priv(dev);
2676 u8 __iomem *base = get_hwbase(dev);
2677 u32 addr[2];
2678 u32 mask[2];
2679 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2680
2681 memset(addr, 0, sizeof(addr));
2682 memset(mask, 0, sizeof(mask));
2683
2684 if (dev->flags & IFF_PROMISC) {
2685 pff |= NVREG_PFF_PROMISC;
2686 } else {
2687 pff |= NVREG_PFF_MYADDR;
2688
2689 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2690 u32 alwaysOff[2];
2691 u32 alwaysOn[2];
2692
2693 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2694 if (dev->flags & IFF_ALLMULTI) {
2695 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2696 } else {
2697 struct dev_mc_list *walk;
2698
2699 walk = dev->mc_list;
2700 while (walk != NULL) {
2701 u32 a, b;
2702 a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2703 b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
2704 alwaysOn[0] &= a;
2705 alwaysOff[0] &= ~a;
2706 alwaysOn[1] &= b;
2707 alwaysOff[1] &= ~b;
2708 walk = walk->next;
2709 }
2710 }
2711 addr[0] = alwaysOn[0];
2712 addr[1] = alwaysOn[1];
2713 mask[0] = alwaysOn[0] | alwaysOff[0];
2714 mask[1] = alwaysOn[1] | alwaysOff[1];
2715 } else {
2716 mask[0] = NVREG_MCASTMASKA_NONE;
2717 mask[1] = NVREG_MCASTMASKB_NONE;
2718 }
2719 }
2720 addr[0] |= NVREG_MCASTADDRA_FORCE;
2721 pff |= NVREG_PFF_ALWAYS;
2722 spin_lock_irq(&np->lock);
2723 nv_stop_rx(dev);
2724 writel(addr[0], base + NvRegMulticastAddrA);
2725 writel(addr[1], base + NvRegMulticastAddrB);
2726 writel(mask[0], base + NvRegMulticastMaskA);
2727 writel(mask[1], base + NvRegMulticastMaskB);
2728 writel(pff, base + NvRegPacketFilterFlags);
2729 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2730 dev->name);
2731 nv_start_rx(dev);
2732 spin_unlock_irq(&np->lock);
2733 }
2734
2735 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2736 {
2737 struct fe_priv *np = netdev_priv(dev);
2738 u8 __iomem *base = get_hwbase(dev);
2739
2740 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2741
2742 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2743 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2744 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2745 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2746 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2747 } else {
2748 writel(pff, base + NvRegPacketFilterFlags);
2749 }
2750 }
2751 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2752 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2753 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2754 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
2755 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2756 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2757 } else {
2758 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2759 writel(regmisc, base + NvRegMisc1);
2760 }
2761 }
2762 }
2763
2764 /**
2765 * nv_update_linkspeed: Setup the MAC according to the link partner
2766 * @dev: Network device to be configured
2767 *
2768 * The function queries the PHY and checks if there is a link partner.
2769 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2770 * set to 10 MBit HD.
2771 *
2772 * The function returns 0 if there is no link partner and 1 if there is
2773 * a good link partner.
2774 */
2775 static int nv_update_linkspeed(struct net_device *dev)
2776 {
2777 struct fe_priv *np = netdev_priv(dev);
2778 u8 __iomem *base = get_hwbase(dev);
2779 int adv = 0;
2780 int lpa = 0;
2781 int adv_lpa, adv_pause, lpa_pause;
2782 int newls = np->linkspeed;
2783 int newdup = np->duplex;
2784 int mii_status;
2785 int retval = 0;
2786 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2787 u32 txrxFlags = 0;
2788
2789 /* BMSR_LSTATUS is latched, read it twice:
2790 * we want the current value.
2791 */
2792 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2793 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2794
2795 if (!(mii_status & BMSR_LSTATUS)) {
2796 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2797 dev->name);
2798 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2799 newdup = 0;
2800 retval = 0;
2801 goto set_speed;
2802 }
2803
2804 if (np->autoneg == 0) {
2805 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2806 dev->name, np->fixed_mode);
2807 if (np->fixed_mode & LPA_100FULL) {
2808 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2809 newdup = 1;
2810 } else if (np->fixed_mode & LPA_100HALF) {
2811 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2812 newdup = 0;
2813 } else if (np->fixed_mode & LPA_10FULL) {
2814 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2815 newdup = 1;
2816 } else {
2817 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2818 newdup = 0;
2819 }
2820 retval = 1;
2821 goto set_speed;
2822 }
2823 /* check auto negotiation is complete */
2824 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2825 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2826 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2827 newdup = 0;
2828 retval = 0;
2829 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2830 goto set_speed;
2831 }
2832
2833 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2834 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2835 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2836 dev->name, adv, lpa);
2837
2838 retval = 1;
2839 if (np->gigabit == PHY_GIGABIT) {
2840 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2841 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2842
2843 if ((control_1000 & ADVERTISE_1000FULL) &&
2844 (status_1000 & LPA_1000FULL)) {
2845 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2846 dev->name);
2847 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2848 newdup = 1;
2849 goto set_speed;
2850 }
2851 }
2852
2853 /* FIXME: handle parallel detection properly */
2854 adv_lpa = lpa & adv;
2855 if (adv_lpa & LPA_100FULL) {
2856 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2857 newdup = 1;
2858 } else if (adv_lpa & LPA_100HALF) {
2859 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2860 newdup = 0;
2861 } else if (adv_lpa & LPA_10FULL) {
2862 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2863 newdup = 1;
2864 } else if (adv_lpa & LPA_10HALF) {
2865 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2866 newdup = 0;
2867 } else {
2868 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2869 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2870 newdup = 0;
2871 }
2872
2873 set_speed:
2874 if (np->duplex == newdup && np->linkspeed == newls)
2875 return retval;
2876
2877 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2878 dev->name, np->linkspeed, np->duplex, newls, newdup);
2879
2880 np->duplex = newdup;
2881 np->linkspeed = newls;
2882
2883 /* The transmitter and receiver must be restarted for safe update */
2884 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
2885 txrxFlags |= NV_RESTART_TX;
2886 nv_stop_tx(dev);
2887 }
2888 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
2889 txrxFlags |= NV_RESTART_RX;
2890 nv_stop_rx(dev);
2891 }
2892
2893 if (np->gigabit == PHY_GIGABIT) {
2894 phyreg = readl(base + NvRegRandomSeed);
2895 phyreg &= ~(0x3FF00);
2896 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2897 phyreg |= NVREG_RNDSEED_FORCE3;
2898 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2899 phyreg |= NVREG_RNDSEED_FORCE2;
2900 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2901 phyreg |= NVREG_RNDSEED_FORCE;
2902 writel(phyreg, base + NvRegRandomSeed);
2903 }
2904
2905 phyreg = readl(base + NvRegPhyInterface);
2906 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2907 if (np->duplex == 0)
2908 phyreg |= PHY_HALF;
2909 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2910 phyreg |= PHY_100;
2911 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2912 phyreg |= PHY_1000;
2913 writel(phyreg, base + NvRegPhyInterface);
2914
2915 if (phyreg & PHY_RGMII) {
2916 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2917 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2918 else
2919 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2920 } else {
2921 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2922 }
2923 writel(txreg, base + NvRegTxDeferral);
2924
2925 if (np->desc_ver == DESC_VER_1) {
2926 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2927 } else {
2928 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2929 txreg = NVREG_TX_WM_DESC2_3_1000;
2930 else
2931 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2932 }
2933 writel(txreg, base + NvRegTxWatermark);
2934
2935 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2936 base + NvRegMisc1);
2937 pci_push(base);
2938 writel(np->linkspeed, base + NvRegLinkSpeed);
2939 pci_push(base);
2940
2941 pause_flags = 0;
2942 /* setup pause frame */
2943 if (np->duplex != 0) {
2944 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2945 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2946 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2947
2948 switch (adv_pause) {
2949 case ADVERTISE_PAUSE_CAP:
2950 if (lpa_pause & LPA_PAUSE_CAP) {
2951 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2952 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2953 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2954 }
2955 break;
2956 case ADVERTISE_PAUSE_ASYM:
2957 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2958 {
2959 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2960 }
2961 break;
2962 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2963 if (lpa_pause & LPA_PAUSE_CAP)
2964 {
2965 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2966 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2967 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2968 }
2969 if (lpa_pause == LPA_PAUSE_ASYM)
2970 {
2971 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2972 }
2973 break;
2974 }
2975 } else {
2976 pause_flags = np->pause_flags;
2977 }
2978 }
2979 nv_update_pause(dev, pause_flags);
2980
2981 if (txrxFlags & NV_RESTART_TX)
2982 nv_start_tx(dev);
2983 if (txrxFlags & NV_RESTART_RX)
2984 nv_start_rx(dev);
2985
2986 return retval;
2987 }
2988
2989 static void nv_linkchange(struct net_device *dev)
2990 {
2991 if (nv_update_linkspeed(dev)) {
2992 if (!netif_carrier_ok(dev)) {
2993 netif_carrier_on(dev);
2994 printk(KERN_INFO "%s: link up.\n", dev->name);
2995 nv_start_rx(dev);
2996 }
2997 } else {
2998 if (netif_carrier_ok(dev)) {
2999 netif_carrier_off(dev);
3000 printk(KERN_INFO "%s: link down.\n", dev->name);
3001 nv_stop_rx(dev);
3002 }
3003 }
3004 }
3005
3006 static void nv_link_irq(struct net_device *dev)
3007 {
3008 u8 __iomem *base = get_hwbase(dev);
3009 u32 miistat;
3010
3011 miistat = readl(base + NvRegMIIStatus);
3012 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3013 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3014
3015 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3016 nv_linkchange(dev);
3017 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3018 }
3019
3020 static irqreturn_t nv_nic_irq(int foo, void *data)
3021 {
3022 struct net_device *dev = (struct net_device *) data;
3023 struct fe_priv *np = netdev_priv(dev);
3024 u8 __iomem *base = get_hwbase(dev);
3025 u32 events;
3026 int i;
3027
3028 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3029
3030 for (i=0; ; i++) {
3031 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3032 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3033 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3034 } else {
3035 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3036 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3037 }
3038 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3039 if (!(events & np->irqmask))
3040 break;
3041
3042 spin_lock(&np->lock);
3043 nv_tx_done(dev);
3044 spin_unlock(&np->lock);
3045
3046 #ifdef CONFIG_FORCEDETH_NAPI
3047 if (events & NVREG_IRQ_RX_ALL) {
3048 netif_rx_schedule(dev, &np->napi);
3049
3050 /* Disable furthur receive irq's */
3051 spin_lock(&np->lock);
3052 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3053
3054 if (np->msi_flags & NV_MSI_X_ENABLED)
3055 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3056 else
3057 writel(np->irqmask, base + NvRegIrqMask);
3058 spin_unlock(&np->lock);
3059 }
3060 #else
3061 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3062 if (unlikely(nv_alloc_rx(dev))) {
3063 spin_lock(&np->lock);
3064 if (!np->in_shutdown)
3065 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3066 spin_unlock(&np->lock);
3067 }
3068 }
3069 #endif
3070 if (unlikely(events & NVREG_IRQ_LINK)) {
3071 spin_lock(&np->lock);
3072 nv_link_irq(dev);
3073 spin_unlock(&np->lock);
3074 }
3075 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3076 spin_lock(&np->lock);
3077 nv_linkchange(dev);
3078 spin_unlock(&np->lock);
3079 np->link_timeout = jiffies + LINK_TIMEOUT;
3080 }
3081 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3082 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3083 dev->name, events);
3084 }
3085 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3086 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3087 dev->name, events);
3088 }
3089 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3090 spin_lock(&np->lock);
3091 /* disable interrupts on the nic */
3092 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3093 writel(0, base + NvRegIrqMask);
3094 else
3095 writel(np->irqmask, base + NvRegIrqMask);
3096 pci_push(base);
3097
3098 if (!np->in_shutdown) {
3099 np->nic_poll_irq = np->irqmask;
3100 np->recover_error = 1;
3101 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3102 }
3103 spin_unlock(&np->lock);
3104 break;
3105 }
3106 if (unlikely(i > max_interrupt_work)) {
3107 spin_lock(&np->lock);
3108 /* disable interrupts on the nic */
3109 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3110 writel(0, base + NvRegIrqMask);
3111 else
3112 writel(np->irqmask, base + NvRegIrqMask);
3113 pci_push(base);
3114
3115 if (!np->in_shutdown) {
3116 np->nic_poll_irq = np->irqmask;
3117 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3118 }
3119 spin_unlock(&np->lock);
3120 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3121 break;
3122 }
3123
3124 }
3125 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3126
3127 return IRQ_RETVAL(i);
3128 }
3129
3130 /**
3131 * All _optimized functions are used to help increase performance
3132 * (reduce CPU and increase throughput). They use descripter version 3,
3133 * compiler directives, and reduce memory accesses.
3134 */
3135 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3136 {
3137 struct net_device *dev = (struct net_device *) data;
3138 struct fe_priv *np = netdev_priv(dev);
3139 u8 __iomem *base = get_hwbase(dev);
3140 u32 events;
3141 int i;
3142
3143 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3144
3145 for (i=0; ; i++) {
3146 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3147 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3148 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3149 } else {
3150 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3151 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3152 }
3153 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3154 if (!(events & np->irqmask))
3155 break;
3156
3157 spin_lock(&np->lock);
3158 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3159 spin_unlock(&np->lock);
3160
3161 #ifdef CONFIG_FORCEDETH_NAPI
3162 if (events & NVREG_IRQ_RX_ALL) {
3163 netif_rx_schedule(dev, &np->napi);
3164
3165 /* Disable furthur receive irq's */
3166 spin_lock(&np->lock);
3167 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3168
3169 if (np->msi_flags & NV_MSI_X_ENABLED)
3170 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3171 else
3172 writel(np->irqmask, base + NvRegIrqMask);
3173 spin_unlock(&np->lock);
3174 }
3175 #else
3176 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3177 if (unlikely(nv_alloc_rx_optimized(dev))) {
3178 spin_lock(&np->lock);
3179 if (!np->in_shutdown)
3180 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3181 spin_unlock(&np->lock);
3182 }
3183 }
3184 #endif
3185 if (unlikely(events & NVREG_IRQ_LINK)) {
3186 spin_lock(&np->lock);
3187 nv_link_irq(dev);
3188 spin_unlock(&np->lock);
3189 }
3190 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3191 spin_lock(&np->lock);
3192 nv_linkchange(dev);
3193 spin_unlock(&np->lock);
3194 np->link_timeout = jiffies + LINK_TIMEOUT;
3195 }
3196 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3197 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3198 dev->name, events);
3199 }
3200 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3201 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3202 dev->name, events);
3203 }
3204 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3205 spin_lock(&np->lock);
3206 /* disable interrupts on the nic */
3207 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3208 writel(0, base + NvRegIrqMask);
3209 else
3210 writel(np->irqmask, base + NvRegIrqMask);
3211 pci_push(base);
3212
3213 if (!np->in_shutdown) {
3214 np->nic_poll_irq = np->irqmask;
3215 np->recover_error = 1;
3216 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3217 }
3218 spin_unlock(&np->lock);
3219 break;
3220 }
3221
3222 if (unlikely(i > max_interrupt_work)) {
3223 spin_lock(&np->lock);
3224 /* disable interrupts on the nic */
3225 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3226 writel(0, base + NvRegIrqMask);
3227 else
3228 writel(np->irqmask, base + NvRegIrqMask);
3229 pci_push(base);
3230
3231 if (!np->in_shutdown) {
3232 np->nic_poll_irq = np->irqmask;
3233 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3234 }
3235 spin_unlock(&np->lock);
3236 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3237 break;
3238 }
3239
3240 }
3241 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3242
3243 return IRQ_RETVAL(i);
3244 }
3245
3246 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3247 {
3248 struct net_device *dev = (struct net_device *) data;
3249 struct fe_priv *np = netdev_priv(dev);
3250 u8 __iomem *base = get_hwbase(dev);
3251 u32 events;
3252 int i;
3253 unsigned long flags;
3254
3255 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3256
3257 for (i=0; ; i++) {
3258 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3259 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3260 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3261 if (!(events & np->irqmask))
3262 break;
3263
3264 spin_lock_irqsave(&np->lock, flags);
3265 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3266 spin_unlock_irqrestore(&np->lock, flags);
3267
3268 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3269 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3270 dev->name, events);
3271 }
3272 if (unlikely(i > max_interrupt_work)) {
3273 spin_lock_irqsave(&np->lock, flags);
3274 /* disable interrupts on the nic */
3275 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3276 pci_push(base);
3277
3278 if (!np->in_shutdown) {
3279 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3280 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3281 }
3282 spin_unlock_irqrestore(&np->lock, flags);
3283 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3284 break;
3285 }
3286
3287 }
3288 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3289
3290 return IRQ_RETVAL(i);
3291 }
3292
3293 #ifdef CONFIG_FORCEDETH_NAPI
3294 static int nv_napi_poll(struct napi_struct *napi, int budget)
3295 {
3296 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3297 struct net_device *dev = np->dev;
3298 u8 __iomem *base = get_hwbase(dev);
3299 unsigned long flags;
3300 int pkts, retcode;
3301
3302 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3303 pkts = nv_rx_process(dev, budget);
3304 retcode = nv_alloc_rx(dev);
3305 } else {
3306 pkts = nv_rx_process_optimized(dev, budget);
3307 retcode = nv_alloc_rx_optimized(dev);
3308 }
3309
3310 if (retcode) {
3311 spin_lock_irqsave(&np->lock, flags);
3312 if (!np->in_shutdown)
3313 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3314 spin_unlock_irqrestore(&np->lock, flags);
3315 }
3316
3317 if (pkts < budget) {
3318 /* re-enable receive interrupts */
3319 spin_lock_irqsave(&np->lock, flags);
3320
3321 __netif_rx_complete(dev, napi);
3322
3323 np->irqmask |= NVREG_IRQ_RX_ALL;
3324 if (np->msi_flags & NV_MSI_X_ENABLED)
3325 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3326 else
3327 writel(np->irqmask, base + NvRegIrqMask);
3328
3329 spin_unlock_irqrestore(&np->lock, flags);
3330 }
3331 return pkts;
3332 }
3333 #endif
3334
3335 #ifdef CONFIG_FORCEDETH_NAPI
3336 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3337 {
3338 struct net_device *dev = (struct net_device *) data;
3339 struct fe_priv *np = netdev_priv(dev);
3340 u8 __iomem *base = get_hwbase(dev);
3341 u32 events;
3342
3343 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3344 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3345
3346 if (events) {
3347 netif_rx_schedule(dev, &np->napi);
3348 /* disable receive interrupts on the nic */
3349 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3350 pci_push(base);
3351 }
3352 return IRQ_HANDLED;
3353 }
3354 #else
3355 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3356 {
3357 struct net_device *dev = (struct net_device *) data;
3358 struct fe_priv *np = netdev_priv(dev);
3359 u8 __iomem *base = get_hwbase(dev);
3360 u32 events;
3361 int i;
3362 unsigned long flags;
3363
3364 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3365
3366 for (i=0; ; i++) {
3367 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3368 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3369 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3370 if (!(events & np->irqmask))
3371 break;
3372
3373 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3374 if (unlikely(nv_alloc_rx_optimized(dev))) {
3375 spin_lock_irqsave(&np->lock, flags);
3376 if (!np->in_shutdown)
3377 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3378 spin_unlock_irqrestore(&np->lock, flags);
3379 }
3380 }
3381
3382 if (unlikely(i > max_interrupt_work)) {
3383 spin_lock_irqsave(&np->lock, flags);
3384 /* disable interrupts on the nic */
3385 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3386 pci_push(base);
3387
3388 if (!np->in_shutdown) {
3389 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3390 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3391 }
3392 spin_unlock_irqrestore(&np->lock, flags);
3393 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3394 break;
3395 }
3396 }
3397 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3398
3399 return IRQ_RETVAL(i);
3400 }
3401 #endif
3402
3403 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3404 {
3405 struct net_device *dev = (struct net_device *) data;
3406 struct fe_priv *np = netdev_priv(dev);
3407 u8 __iomem *base = get_hwbase(dev);
3408 u32 events;
3409 int i;
3410 unsigned long flags;
3411
3412 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3413
3414 for (i=0; ; i++) {
3415 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3416 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3417 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3418 if (!(events & np->irqmask))
3419 break;
3420
3421 /* check tx in case we reached max loop limit in tx isr */
3422 spin_lock_irqsave(&np->lock, flags);
3423 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3424 spin_unlock_irqrestore(&np->lock, flags);
3425
3426 if (events & NVREG_IRQ_LINK) {
3427 spin_lock_irqsave(&np->lock, flags);
3428 nv_link_irq(dev);
3429 spin_unlock_irqrestore(&np->lock, flags);
3430 }
3431 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3432 spin_lock_irqsave(&np->lock, flags);
3433 nv_linkchange(dev);
3434 spin_unlock_irqrestore(&np->lock, flags);
3435 np->link_timeout = jiffies + LINK_TIMEOUT;
3436 }
3437 if (events & NVREG_IRQ_RECOVER_ERROR) {
3438 spin_lock_irq(&np->lock);
3439 /* disable interrupts on the nic */
3440 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3441 pci_push(base);
3442
3443 if (!np->in_shutdown) {
3444 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3445 np->recover_error = 1;
3446 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3447 }
3448 spin_unlock_irq(&np->lock);
3449 break;
3450 }
3451 if (events & (NVREG_IRQ_UNKNOWN)) {
3452 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3453 dev->name, events);
3454 }
3455 if (unlikely(i > max_interrupt_work)) {
3456 spin_lock_irqsave(&np->lock, flags);
3457 /* disable interrupts on the nic */
3458 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3459 pci_push(base);
3460
3461 if (!np->in_shutdown) {
3462 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3463 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3464 }
3465 spin_unlock_irqrestore(&np->lock, flags);
3466 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3467 break;
3468 }
3469
3470 }
3471 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3472
3473 return IRQ_RETVAL(i);
3474 }
3475
3476 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3477 {
3478 struct net_device *dev = (struct net_device *) data;
3479 struct fe_priv *np = netdev_priv(dev);
3480 u8 __iomem *base = get_hwbase(dev);
3481 u32 events;
3482
3483 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3484
3485 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3486 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3487 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3488 } else {
3489 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3490 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3491 }
3492 pci_push(base);
3493 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3494 if (!(events & NVREG_IRQ_TIMER))
3495 return IRQ_RETVAL(0);
3496
3497 spin_lock(&np->lock);
3498 np->intr_test = 1;
3499 spin_unlock(&np->lock);
3500
3501 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3502
3503 return IRQ_RETVAL(1);
3504 }
3505
3506 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3507 {
3508 u8 __iomem *base = get_hwbase(dev);
3509 int i;
3510 u32 msixmap = 0;
3511
3512 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3513 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3514 * the remaining 8 interrupts.
3515 */
3516 for (i = 0; i < 8; i++) {
3517 if ((irqmask >> i) & 0x1) {
3518 msixmap |= vector << (i << 2);
3519 }
3520 }
3521 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3522
3523 msixmap = 0;
3524 for (i = 0; i < 8; i++) {
3525 if ((irqmask >> (i + 8)) & 0x1) {
3526 msixmap |= vector << (i << 2);
3527 }
3528 }
3529 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3530 }
3531
3532 static int nv_request_irq(struct net_device *dev, int intr_test)
3533 {
3534 struct fe_priv *np = get_nvpriv(dev);
3535 u8 __iomem *base = get_hwbase(dev);
3536 int ret = 1;
3537 int i;
3538 irqreturn_t (*handler)(int foo, void *data);
3539
3540 if (intr_test) {
3541 handler = nv_nic_irq_test;
3542 } else {
3543 if (np->desc_ver == DESC_VER_3)
3544 handler = nv_nic_irq_optimized;
3545 else
3546 handler = nv_nic_irq;
3547 }
3548
3549 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3550 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3551 np->msi_x_entry[i].entry = i;
3552 }
3553 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3554 np->msi_flags |= NV_MSI_X_ENABLED;
3555 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3556 /* Request irq for rx handling */
3557 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3558 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3559 pci_disable_msix(np->pci_dev);
3560 np->msi_flags &= ~NV_MSI_X_ENABLED;
3561 goto out_err;
3562 }
3563 /* Request irq for tx handling */
3564 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3565 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3566 pci_disable_msix(np->pci_dev);
3567 np->msi_flags &= ~NV_MSI_X_ENABLED;
3568 goto out_free_rx;
3569 }
3570 /* Request irq for link and timer handling */
3571 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3572 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3573 pci_disable_msix(np->pci_dev);
3574 np->msi_flags &= ~NV_MSI_X_ENABLED;
3575 goto out_free_tx;
3576 }
3577 /* map interrupts to their respective vector */
3578 writel(0, base + NvRegMSIXMap0);
3579 writel(0, base + NvRegMSIXMap1);
3580 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3581 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3582 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3583 } else {
3584 /* Request irq for all interrupts */
3585 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3586 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3587 pci_disable_msix(np->pci_dev);
3588 np->msi_flags &= ~NV_MSI_X_ENABLED;
3589 goto out_err;
3590 }
3591
3592 /* map interrupts to vector 0 */
3593 writel(0, base + NvRegMSIXMap0);
3594 writel(0, base + NvRegMSIXMap1);
3595 }
3596 }
3597 }
3598 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3599 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3600 np->msi_flags |= NV_MSI_ENABLED;
3601 dev->irq = np->pci_dev->irq;
3602 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3603 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3604 pci_disable_msi(np->pci_dev);
3605 np->msi_flags &= ~NV_MSI_ENABLED;
3606 dev->irq = np->pci_dev->irq;
3607 goto out_err;
3608 }
3609
3610 /* map interrupts to vector 0 */
3611 writel(0, base + NvRegMSIMap0);
3612 writel(0, base + NvRegMSIMap1);
3613 /* enable msi vector 0 */
3614 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3615 }
3616 }
3617 if (ret != 0) {
3618 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3619 goto out_err;
3620
3621 }
3622
3623 return 0;
3624 out_free_tx:
3625 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3626 out_free_rx:
3627 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3628 out_err:
3629 return 1;
3630 }
3631
3632 static void nv_free_irq(struct net_device *dev)
3633 {
3634 struct fe_priv *np = get_nvpriv(dev);
3635 int i;
3636
3637 if (np->msi_flags & NV_MSI_X_ENABLED) {
3638 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3639 free_irq(np->msi_x_entry[i].vector, dev);
3640 }
3641 pci_disable_msix(np->pci_dev);
3642 np->msi_flags &= ~NV_MSI_X_ENABLED;
3643 } else {
3644 free_irq(np->pci_dev->irq, dev);
3645 if (np->msi_flags & NV_MSI_ENABLED) {
3646 pci_disable_msi(np->pci_dev);
3647 np->msi_flags &= ~NV_MSI_ENABLED;
3648 }
3649 }
3650 }
3651
3652 static void nv_do_nic_poll(unsigned long data)
3653 {
3654 struct net_device *dev = (struct net_device *) data;
3655 struct fe_priv *np = netdev_priv(dev);
3656 u8 __iomem *base = get_hwbase(dev);
3657 u32 mask = 0;
3658
3659 /*
3660 * First disable irq(s) and then
3661 * reenable interrupts on the nic, we have to do this before calling
3662 * nv_nic_irq because that may decide to do otherwise
3663 */
3664
3665 if (!using_multi_irqs(dev)) {
3666 if (np->msi_flags & NV_MSI_X_ENABLED)
3667 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3668 else
3669 disable_irq_lockdep(np->pci_dev->irq);
3670 mask = np->irqmask;
3671 } else {
3672 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3673 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3674 mask |= NVREG_IRQ_RX_ALL;
3675 }
3676 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3677 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3678 mask |= NVREG_IRQ_TX_ALL;
3679 }
3680 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3681 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3682 mask |= NVREG_IRQ_OTHER;
3683 }
3684 }
3685 np->nic_poll_irq = 0;
3686
3687 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3688
3689 if (np->recover_error) {
3690 np->recover_error = 0;
3691 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3692 if (netif_running(dev)) {
3693 netif_tx_lock_bh(dev);
3694 spin_lock(&np->lock);
3695 /* stop engines */
3696 nv_stop_rx(dev);
3697 nv_stop_tx(dev);
3698 nv_txrx_reset(dev);
3699 /* drain rx queue */
3700 nv_drain_rx(dev);
3701 nv_drain_tx(dev);
3702 /* reinit driver view of the rx queue */
3703 set_bufsize(dev);
3704 if (nv_init_ring(dev)) {
3705 if (!np->in_shutdown)
3706 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3707 }
3708 /* reinit nic view of the rx queue */
3709 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3710 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3711 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3712 base + NvRegRingSizes);
3713 pci_push(base);
3714 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3715 pci_push(base);
3716
3717 /* restart rx engine */
3718 nv_start_rx(dev);
3719 nv_start_tx(dev);
3720 spin_unlock(&np->lock);
3721 netif_tx_unlock_bh(dev);
3722 }
3723 }
3724
3725
3726 writel(mask, base + NvRegIrqMask);
3727 pci_push(base);
3728
3729 if (!using_multi_irqs(dev)) {
3730 if (np->desc_ver == DESC_VER_3)
3731 nv_nic_irq_optimized(0, dev);
3732 else
3733 nv_nic_irq(0, dev);
3734 if (np->msi_flags & NV_MSI_X_ENABLED)
3735 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3736 else
3737 enable_irq_lockdep(np->pci_dev->irq);
3738 } else {
3739 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3740 nv_nic_irq_rx(0, dev);
3741 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3742 }
3743 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3744 nv_nic_irq_tx(0, dev);
3745 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3746 }
3747 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3748 nv_nic_irq_other(0, dev);
3749 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3750 }
3751 }
3752 }
3753
3754 #ifdef CONFIG_NET_POLL_CONTROLLER
3755 static void nv_poll_controller(struct net_device *dev)
3756 {
3757 nv_do_nic_poll((unsigned long) dev);
3758 }
3759 #endif
3760
3761 static void nv_do_stats_poll(unsigned long data)
3762 {
3763 struct net_device *dev = (struct net_device *) data;
3764 struct fe_priv *np = netdev_priv(dev);
3765
3766 nv_get_hw_stats(dev);
3767
3768 if (!np->in_shutdown)
3769 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3770 }
3771
3772 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3773 {
3774 struct fe_priv *np = netdev_priv(dev);
3775 strcpy(info->driver, DRV_NAME);
3776 strcpy(info->version, FORCEDETH_VERSION);
3777 strcpy(info->bus_info, pci_name(np->pci_dev));
3778 }
3779
3780 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3781 {
3782 struct fe_priv *np = netdev_priv(dev);
3783 wolinfo->supported = WAKE_MAGIC;
3784
3785 spin_lock_irq(&np->lock);
3786 if (np->wolenabled)
3787 wolinfo->wolopts = WAKE_MAGIC;
3788 spin_unlock_irq(&np->lock);
3789 }
3790
3791 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3792 {
3793 struct fe_priv *np = netdev_priv(dev);
3794 u8 __iomem *base = get_hwbase(dev);
3795 u32 flags = 0;
3796
3797 if (wolinfo->wolopts == 0) {
3798 np->wolenabled = 0;
3799 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3800 np->wolenabled = 1;
3801 flags = NVREG_WAKEUPFLAGS_ENABLE;
3802 }
3803 if (netif_running(dev)) {
3804 spin_lock_irq(&np->lock);
3805 writel(flags, base + NvRegWakeUpFlags);
3806 spin_unlock_irq(&np->lock);
3807 }
3808 return 0;
3809 }
3810
3811 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3812 {
3813 struct fe_priv *np = netdev_priv(dev);
3814 int adv;
3815
3816 spin_lock_irq(&np->lock);
3817 ecmd->port = PORT_MII;
3818 if (!netif_running(dev)) {
3819 /* We do not track link speed / duplex setting if the
3820 * interface is disabled. Force a link check */
3821 if (nv_update_linkspeed(dev)) {
3822 if (!netif_carrier_ok(dev))
3823 netif_carrier_on(dev);
3824 } else {
3825 if (netif_carrier_ok(dev))
3826 netif_carrier_off(dev);
3827 }
3828 }
3829
3830 if (netif_carrier_ok(dev)) {
3831 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3832 case NVREG_LINKSPEED_10:
3833 ecmd->speed = SPEED_10;
3834 break;
3835 case NVREG_LINKSPEED_100:
3836 ecmd->speed = SPEED_100;
3837 break;
3838 case NVREG_LINKSPEED_1000:
3839 ecmd->speed = SPEED_1000;
3840 break;
3841 }
3842 ecmd->duplex = DUPLEX_HALF;
3843 if (np->duplex)
3844 ecmd->duplex = DUPLEX_FULL;
3845 } else {
3846 ecmd->speed = -1;
3847 ecmd->duplex = -1;
3848 }
3849
3850 ecmd->autoneg = np->autoneg;
3851
3852 ecmd->advertising = ADVERTISED_MII;
3853 if (np->autoneg) {
3854 ecmd->advertising |= ADVERTISED_Autoneg;
3855 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3856 if (adv & ADVERTISE_10HALF)
3857 ecmd->advertising |= ADVERTISED_10baseT_Half;
3858 if (adv & ADVERTISE_10FULL)
3859 ecmd->advertising |= ADVERTISED_10baseT_Full;
3860 if (adv & ADVERTISE_100HALF)
3861 ecmd->advertising |= ADVERTISED_100baseT_Half;
3862 if (adv & ADVERTISE_100FULL)
3863 ecmd->advertising |= ADVERTISED_100baseT_Full;
3864 if (np->gigabit == PHY_GIGABIT) {
3865 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3866 if (adv & ADVERTISE_1000FULL)
3867 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3868 }
3869 }
3870 ecmd->supported = (SUPPORTED_Autoneg |
3871 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3872 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3873 SUPPORTED_MII);
3874 if (np->gigabit == PHY_GIGABIT)
3875 ecmd->supported |= SUPPORTED_1000baseT_Full;
3876
3877 ecmd->phy_address = np->phyaddr;
3878 ecmd->transceiver = XCVR_EXTERNAL;
3879
3880 /* ignore maxtxpkt, maxrxpkt for now */
3881 spin_unlock_irq(&np->lock);
3882 return 0;
3883 }
3884
3885 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3886 {
3887 struct fe_priv *np = netdev_priv(dev);
3888
3889 if (ecmd->port != PORT_MII)
3890 return -EINVAL;
3891 if (ecmd->transceiver != XCVR_EXTERNAL)
3892 return -EINVAL;
3893 if (ecmd->phy_address != np->phyaddr) {
3894 /* TODO: support switching between multiple phys. Should be
3895 * trivial, but not enabled due to lack of test hardware. */
3896 return -EINVAL;
3897 }
3898 if (ecmd->autoneg == AUTONEG_ENABLE) {
3899 u32 mask;
3900
3901 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3902 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3903 if (np->gigabit == PHY_GIGABIT)
3904 mask |= ADVERTISED_1000baseT_Full;
3905
3906 if ((ecmd->advertising & mask) == 0)
3907 return -EINVAL;
3908
3909 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3910 /* Note: autonegotiation disable, speed 1000 intentionally
3911 * forbidden - noone should need that. */
3912
3913 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3914 return -EINVAL;
3915 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3916 return -EINVAL;
3917 } else {
3918 return -EINVAL;
3919 }
3920
3921 netif_carrier_off(dev);
3922 if (netif_running(dev)) {
3923 nv_disable_irq(dev);
3924 netif_tx_lock_bh(dev);
3925 spin_lock(&np->lock);
3926 /* stop engines */
3927 nv_stop_rx(dev);
3928 nv_stop_tx(dev);
3929 spin_unlock(&np->lock);
3930 netif_tx_unlock_bh(dev);
3931 }
3932
3933 if (ecmd->autoneg == AUTONEG_ENABLE) {
3934 int adv, bmcr;
3935
3936 np->autoneg = 1;
3937
3938 /* advertise only what has been requested */
3939 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3940 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3941 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3942 adv |= ADVERTISE_10HALF;
3943 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3944 adv |= ADVERTISE_10FULL;
3945 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3946 adv |= ADVERTISE_100HALF;
3947 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3948 adv |= ADVERTISE_100FULL;
3949 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3950 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3951 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3952 adv |= ADVERTISE_PAUSE_ASYM;
3953 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3954
3955 if (np->gigabit == PHY_GIGABIT) {
3956 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3957 adv &= ~ADVERTISE_1000FULL;
3958 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3959 adv |= ADVERTISE_1000FULL;
3960 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3961 }
3962
3963 if (netif_running(dev))
3964 printk(KERN_INFO "%s: link down.\n", dev->name);
3965 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3966 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3967 bmcr |= BMCR_ANENABLE;
3968 /* reset the phy in order for settings to stick,
3969 * and cause autoneg to start */
3970 if (phy_reset(dev, bmcr)) {
3971 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3972 return -EINVAL;
3973 }
3974 } else {
3975 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3976 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3977 }
3978 } else {
3979 int adv, bmcr;
3980
3981 np->autoneg = 0;
3982
3983 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3984 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3985 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3986 adv |= ADVERTISE_10HALF;
3987 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3988 adv |= ADVERTISE_10FULL;
3989 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3990 adv |= ADVERTISE_100HALF;
3991 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3992 adv |= ADVERTISE_100FULL;
3993 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3994 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3995 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3996 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3997 }
3998 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3999 adv |= ADVERTISE_PAUSE_ASYM;
4000 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4001 }
4002 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4003 np->fixed_mode = adv;
4004
4005 if (np->gigabit == PHY_GIGABIT) {
4006 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4007 adv &= ~ADVERTISE_1000FULL;
4008 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4009 }
4010
4011 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4012 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4013 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4014 bmcr |= BMCR_FULLDPLX;
4015 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4016 bmcr |= BMCR_SPEED100;
4017 if (np->phy_oui == PHY_OUI_MARVELL) {
4018 /* reset the phy in order for forced mode settings to stick */
4019 if (phy_reset(dev, bmcr)) {
4020 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4021 return -EINVAL;
4022 }
4023 } else {
4024 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4025 if (netif_running(dev)) {
4026 /* Wait a bit and then reconfigure the nic. */
4027 udelay(10);
4028 nv_linkchange(dev);
4029 }
4030 }
4031 }
4032
4033 if (netif_running(dev)) {
4034 nv_start_rx(dev);
4035 nv_start_tx(dev);
4036 nv_enable_irq(dev);
4037 }
4038
4039 return 0;
4040 }
4041
4042 #define FORCEDETH_REGS_VER 1
4043
4044 static int nv_get_regs_len(struct net_device *dev)
4045 {
4046 struct fe_priv *np = netdev_priv(dev);
4047 return np->register_size;
4048 }
4049
4050 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4051 {
4052 struct fe_priv *np = netdev_priv(dev);
4053 u8 __iomem *base = get_hwbase(dev);
4054 u32 *rbuf = buf;
4055 int i;
4056
4057 regs->version = FORCEDETH_REGS_VER;
4058 spin_lock_irq(&np->lock);
4059 for (i = 0;i <= np->register_size/sizeof(u32); i++)
4060 rbuf[i] = readl(base + i*sizeof(u32));
4061 spin_unlock_irq(&np->lock);
4062 }
4063
4064 static int nv_nway_reset(struct net_device *dev)
4065 {
4066 struct fe_priv *np = netdev_priv(dev);
4067 int ret;
4068
4069 if (np->autoneg) {
4070 int bmcr;
4071
4072 netif_carrier_off(dev);
4073 if (netif_running(dev)) {
4074 nv_disable_irq(dev);
4075 netif_tx_lock_bh(dev);
4076 spin_lock(&np->lock);
4077 /* stop engines */
4078 nv_stop_rx(dev);
4079 nv_stop_tx(dev);
4080 spin_unlock(&np->lock);
4081 netif_tx_unlock_bh(dev);
4082 printk(KERN_INFO "%s: link down.\n", dev->name);
4083 }
4084
4085 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4086 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4087 bmcr |= BMCR_ANENABLE;
4088 /* reset the phy in order for settings to stick*/
4089 if (phy_reset(dev, bmcr)) {
4090 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4091 return -EINVAL;
4092 }
4093 } else {
4094 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4095 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4096 }
4097
4098 if (netif_running(dev)) {
4099 nv_start_rx(dev);
4100 nv_start_tx(dev);
4101 nv_enable_irq(dev);
4102 }
4103 ret = 0;
4104 } else {
4105 ret = -EINVAL;
4106 }
4107
4108 return ret;
4109 }
4110
4111 static int nv_set_tso(struct net_device *dev, u32 value)
4112 {
4113 struct fe_priv *np = netdev_priv(dev);
4114
4115 if ((np->driver_data & DEV_HAS_CHECKSUM))
4116 return ethtool_op_set_tso(dev, value);
4117 else
4118 return -EOPNOTSUPP;
4119 }
4120
4121 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4122 {
4123 struct fe_priv *np = netdev_priv(dev);
4124
4125 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4126 ring->rx_mini_max_pending = 0;
4127 ring->rx_jumbo_max_pending = 0;
4128 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4129
4130 ring->rx_pending = np->rx_ring_size;
4131 ring->rx_mini_pending = 0;
4132 ring->rx_jumbo_pending = 0;
4133 ring->tx_pending = np->tx_ring_size;
4134 }
4135
4136 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4137 {
4138 struct fe_priv *np = netdev_priv(dev);
4139 u8 __iomem *base = get_hwbase(dev);
4140 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4141 dma_addr_t ring_addr;
4142
4143 if (ring->rx_pending < RX_RING_MIN ||
4144 ring->tx_pending < TX_RING_MIN ||
4145 ring->rx_mini_pending != 0 ||
4146 ring->rx_jumbo_pending != 0 ||
4147 (np->desc_ver == DESC_VER_1 &&
4148 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4149 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4150 (np->desc_ver != DESC_VER_1 &&
4151 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4152 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4153 return -EINVAL;
4154 }
4155
4156 /* allocate new rings */
4157 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4158 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4159 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4160 &ring_addr);
4161 } else {
4162 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4163 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4164 &ring_addr);
4165 }
4166 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4167 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4168 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4169 /* fall back to old rings */
4170 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4171 if (rxtx_ring)
4172 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4173 rxtx_ring, ring_addr);
4174 } else {
4175 if (rxtx_ring)
4176 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4177 rxtx_ring, ring_addr);
4178 }
4179 if (rx_skbuff)
4180 kfree(rx_skbuff);
4181 if (tx_skbuff)
4182 kfree(tx_skbuff);
4183 goto exit;
4184 }
4185
4186 if (netif_running(dev)) {
4187 nv_disable_irq(dev);
4188 netif_tx_lock_bh(dev);
4189 spin_lock(&np->lock);
4190 /* stop engines */
4191 nv_stop_rx(dev);
4192 nv_stop_tx(dev);
4193 nv_txrx_reset(dev);
4194 /* drain queues */
4195 nv_drain_rx(dev);
4196 nv_drain_tx(dev);
4197 /* delete queues */
4198 free_rings(dev);
4199 }
4200
4201 /* set new values */
4202 np->rx_ring_size = ring->rx_pending;
4203 np->tx_ring_size = ring->tx_pending;
4204 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4205 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4206 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4207 } else {
4208 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4209 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4210 }
4211 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4212 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4213 np->ring_addr = ring_addr;
4214
4215 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4216 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4217
4218 if (netif_running(dev)) {
4219 /* reinit driver view of the queues */
4220 set_bufsize(dev);
4221 if (nv_init_ring(dev)) {
4222 if (!np->in_shutdown)
4223 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4224 }
4225
4226 /* reinit nic view of the queues */
4227 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4228 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4229 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4230 base + NvRegRingSizes);
4231 pci_push(base);
4232 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4233 pci_push(base);
4234
4235 /* restart engines */
4236 nv_start_rx(dev);
4237 nv_start_tx(dev);
4238 spin_unlock(&np->lock);
4239 netif_tx_unlock_bh(dev);
4240 nv_enable_irq(dev);
4241 }
4242 return 0;
4243 exit:
4244 return -ENOMEM;
4245 }
4246
4247 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4248 {
4249 struct fe_priv *np = netdev_priv(dev);
4250
4251 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4252 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4253 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4254 }
4255
4256 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4257 {
4258 struct fe_priv *np = netdev_priv(dev);
4259 int adv, bmcr;
4260
4261 if ((!np->autoneg && np->duplex == 0) ||
4262 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4263 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4264 dev->name);
4265 return -EINVAL;
4266 }
4267 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4268 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4269 return -EINVAL;
4270 }
4271
4272 netif_carrier_off(dev);
4273 if (netif_running(dev)) {
4274 nv_disable_irq(dev);
4275 netif_tx_lock_bh(dev);
4276 spin_lock(&np->lock);
4277 /* stop engines */
4278 nv_stop_rx(dev);
4279 nv_stop_tx(dev);
4280 spin_unlock(&np->lock);
4281 netif_tx_unlock_bh(dev);
4282 }
4283
4284 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4285 if (pause->rx_pause)
4286 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4287 if (pause->tx_pause)
4288 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4289
4290 if (np->autoneg && pause->autoneg) {
4291 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4292
4293 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4294 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4295 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4296 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4297 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4298 adv |= ADVERTISE_PAUSE_ASYM;
4299 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4300
4301 if (netif_running(dev))
4302 printk(KERN_INFO "%s: link down.\n", dev->name);
4303 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4304 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4305 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4306 } else {
4307 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4308 if (pause->rx_pause)
4309 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4310 if (pause->tx_pause)
4311 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4312
4313 if (!netif_running(dev))
4314 nv_update_linkspeed(dev);
4315 else
4316 nv_update_pause(dev, np->pause_flags);
4317 }
4318
4319 if (netif_running(dev)) {
4320 nv_start_rx(dev);
4321 nv_start_tx(dev);
4322 nv_enable_irq(dev);
4323 }
4324 return 0;
4325 }
4326
4327 static u32 nv_get_rx_csum(struct net_device *dev)
4328 {
4329 struct fe_priv *np = netdev_priv(dev);
4330 return (np->rx_csum) != 0;
4331 }
4332
4333 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4334 {
4335 struct fe_priv *np = netdev_priv(dev);
4336 u8 __iomem *base = get_hwbase(dev);
4337 int retcode = 0;
4338
4339 if (np->driver_data & DEV_HAS_CHECKSUM) {
4340 if (data) {
4341 np->rx_csum = 1;
4342 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4343 } else {
4344 np->rx_csum = 0;
4345 /* vlan is dependent on rx checksum offload */
4346 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4347 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4348 }
4349 if (netif_running(dev)) {
4350 spin_lock_irq(&np->lock);
4351 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4352 spin_unlock_irq(&np->lock);
4353 }
4354 } else {
4355 return -EINVAL;
4356 }
4357
4358 return retcode;
4359 }
4360
4361 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4362 {
4363 struct fe_priv *np = netdev_priv(dev);
4364
4365 if (np->driver_data & DEV_HAS_CHECKSUM)
4366 return ethtool_op_set_tx_hw_csum(dev, data);
4367 else
4368 return -EOPNOTSUPP;
4369 }
4370
4371 static int nv_set_sg(struct net_device *dev, u32 data)
4372 {
4373 struct fe_priv *np = netdev_priv(dev);
4374
4375 if (np->driver_data & DEV_HAS_CHECKSUM)
4376 return ethtool_op_set_sg(dev, data);
4377 else
4378 return -EOPNOTSUPP;
4379 }
4380
4381 static int nv_get_sset_count(struct net_device *dev, int sset)
4382 {
4383 struct fe_priv *np = netdev_priv(dev);
4384
4385 switch (sset) {
4386 case ETH_SS_TEST:
4387 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4388 return NV_TEST_COUNT_EXTENDED;
4389 else
4390 return NV_TEST_COUNT_BASE;
4391 case ETH_SS_STATS:
4392 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4393 return NV_DEV_STATISTICS_V1_COUNT;
4394 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4395 return NV_DEV_STATISTICS_V2_COUNT;
4396 else
4397 return 0;
4398 default:
4399 return -EOPNOTSUPP;
4400 }
4401 }
4402
4403 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4404 {
4405 struct fe_priv *np = netdev_priv(dev);
4406
4407 /* update stats */
4408 nv_do_stats_poll((unsigned long)dev);
4409
4410 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4411 }
4412
4413 static int nv_link_test(struct net_device *dev)
4414 {
4415 struct fe_priv *np = netdev_priv(dev);
4416 int mii_status;
4417
4418 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4419 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4420
4421 /* check phy link status */
4422 if (!(mii_status & BMSR_LSTATUS))
4423 return 0;
4424 else
4425 return 1;
4426 }
4427
4428 static int nv_register_test(struct net_device *dev)
4429 {
4430 u8 __iomem *base = get_hwbase(dev);
4431 int i = 0;
4432 u32 orig_read, new_read;
4433
4434 do {
4435 orig_read = readl(base + nv_registers_test[i].reg);
4436
4437 /* xor with mask to toggle bits */
4438 orig_read ^= nv_registers_test[i].mask;
4439
4440 writel(orig_read, base + nv_registers_test[i].reg);
4441
4442 new_read = readl(base + nv_registers_test[i].reg);
4443
4444 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4445 return 0;
4446
4447 /* restore original value */
4448 orig_read ^= nv_registers_test[i].mask;
4449 writel(orig_read, base + nv_registers_test[i].reg);
4450
4451 } while (nv_registers_test[++i].reg != 0);
4452
4453 return 1;
4454 }
4455
4456 static int nv_interrupt_test(struct net_device *dev)
4457 {
4458 struct fe_priv *np = netdev_priv(dev);
4459 u8 __iomem *base = get_hwbase(dev);
4460 int ret = 1;
4461 int testcnt;
4462 u32 save_msi_flags, save_poll_interval = 0;
4463
4464 if (netif_running(dev)) {
4465 /* free current irq */
4466 nv_free_irq(dev);
4467 save_poll_interval = readl(base+NvRegPollingInterval);
4468 }
4469
4470 /* flag to test interrupt handler */
4471 np->intr_test = 0;
4472
4473 /* setup test irq */
4474 save_msi_flags = np->msi_flags;
4475 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4476 np->msi_flags |= 0x001; /* setup 1 vector */
4477 if (nv_request_irq(dev, 1))
4478 return 0;
4479
4480 /* setup timer interrupt */
4481 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4482 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4483
4484 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4485
4486 /* wait for at least one interrupt */
4487 msleep(100);
4488
4489 spin_lock_irq(&np->lock);
4490
4491 /* flag should be set within ISR */
4492 testcnt = np->intr_test;
4493 if (!testcnt)
4494 ret = 2;
4495
4496 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4497 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4498 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4499 else
4500 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4501
4502 spin_unlock_irq(&np->lock);
4503
4504 nv_free_irq(dev);
4505
4506 np->msi_flags = save_msi_flags;
4507
4508 if (netif_running(dev)) {
4509 writel(save_poll_interval, base + NvRegPollingInterval);
4510 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4511 /* restore original irq */
4512 if (nv_request_irq(dev, 0))
4513 return 0;
4514 }
4515
4516 return ret;
4517 }
4518
4519 static int nv_loopback_test(struct net_device *dev)
4520 {
4521 struct fe_priv *np = netdev_priv(dev);
4522 u8 __iomem *base = get_hwbase(dev);
4523 struct sk_buff *tx_skb, *rx_skb;
4524 dma_addr_t test_dma_addr;
4525 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4526 u32 flags;
4527 int len, i, pkt_len;
4528 u8 *pkt_data;
4529 u32 filter_flags = 0;
4530 u32 misc1_flags = 0;
4531 int ret = 1;
4532
4533 if (netif_running(dev)) {
4534 nv_disable_irq(dev);
4535 filter_flags = readl(base + NvRegPacketFilterFlags);
4536 misc1_flags = readl(base + NvRegMisc1);
4537 } else {
4538 nv_txrx_reset(dev);
4539 }
4540
4541 /* reinit driver view of the rx queue */
4542 set_bufsize(dev);
4543 nv_init_ring(dev);
4544
4545 /* setup hardware for loopback */
4546 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4547 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4548
4549 /* reinit nic view of the rx queue */
4550 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4551 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4552 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4553 base + NvRegRingSizes);
4554 pci_push(base);
4555
4556 /* restart rx engine */
4557 nv_start_rx(dev);
4558 nv_start_tx(dev);
4559
4560 /* setup packet for tx */
4561 pkt_len = ETH_DATA_LEN;
4562 tx_skb = dev_alloc_skb(pkt_len);
4563 if (!tx_skb) {
4564 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4565 " of %s\n", dev->name);
4566 ret = 0;
4567 goto out;
4568 }
4569 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4570 skb_tailroom(tx_skb),
4571 PCI_DMA_FROMDEVICE);
4572 pkt_data = skb_put(tx_skb, pkt_len);
4573 for (i = 0; i < pkt_len; i++)
4574 pkt_data[i] = (u8)(i & 0xff);
4575
4576 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4577 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4578 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4579 } else {
4580 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4581 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4582 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4583 }
4584 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4585 pci_push(get_hwbase(dev));
4586
4587 msleep(500);
4588
4589 /* check for rx of the packet */
4590 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4591 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4592 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4593
4594 } else {
4595 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4596 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4597 }
4598
4599 if (flags & NV_RX_AVAIL) {
4600 ret = 0;
4601 } else if (np->desc_ver == DESC_VER_1) {
4602 if (flags & NV_RX_ERROR)
4603 ret = 0;
4604 } else {
4605 if (flags & NV_RX2_ERROR) {
4606 ret = 0;
4607 }
4608 }
4609
4610 if (ret) {
4611 if (len != pkt_len) {
4612 ret = 0;
4613 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4614 dev->name, len, pkt_len);
4615 } else {
4616 rx_skb = np->rx_skb[0].skb;
4617 for (i = 0; i < pkt_len; i++) {
4618 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4619 ret = 0;
4620 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4621 dev->name, i);
4622 break;
4623 }
4624 }
4625 }
4626 } else {
4627 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4628 }
4629
4630 pci_unmap_page(np->pci_dev, test_dma_addr,
4631 (skb_end_pointer(tx_skb) - tx_skb->data),
4632 PCI_DMA_TODEVICE);
4633 dev_kfree_skb_any(tx_skb);
4634 out:
4635 /* stop engines */
4636 nv_stop_rx(dev);
4637 nv_stop_tx(dev);
4638 nv_txrx_reset(dev);
4639 /* drain rx queue */
4640 nv_drain_rx(dev);
4641 nv_drain_tx(dev);
4642
4643 if (netif_running(dev)) {
4644 writel(misc1_flags, base + NvRegMisc1);
4645 writel(filter_flags, base + NvRegPacketFilterFlags);
4646 nv_enable_irq(dev);
4647 }
4648
4649 return ret;
4650 }
4651
4652 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4653 {
4654 struct fe_priv *np = netdev_priv(dev);
4655 u8 __iomem *base = get_hwbase(dev);
4656 int result;
4657 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4658
4659 if (!nv_link_test(dev)) {
4660 test->flags |= ETH_TEST_FL_FAILED;
4661 buffer[0] = 1;
4662 }
4663
4664 if (test->flags & ETH_TEST_FL_OFFLINE) {
4665 if (netif_running(dev)) {
4666 netif_stop_queue(dev);
4667 #ifdef CONFIG_FORCEDETH_NAPI
4668 napi_disable(&np->napi);
4669 #endif
4670 netif_tx_lock_bh(dev);
4671 spin_lock_irq(&np->lock);
4672 nv_disable_hw_interrupts(dev, np->irqmask);
4673 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4674 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4675 } else {
4676 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4677 }
4678 /* stop engines */
4679 nv_stop_rx(dev);
4680 nv_stop_tx(dev);
4681 nv_txrx_reset(dev);
4682 /* drain rx queue */
4683 nv_drain_rx(dev);
4684 nv_drain_tx(dev);
4685 spin_unlock_irq(&np->lock);
4686 netif_tx_unlock_bh(dev);
4687 }
4688
4689 if (!nv_register_test(dev)) {
4690 test->flags |= ETH_TEST_FL_FAILED;
4691 buffer[1] = 1;
4692 }
4693
4694 result = nv_interrupt_test(dev);
4695 if (result != 1) {
4696 test->flags |= ETH_TEST_FL_FAILED;
4697 buffer[2] = 1;
4698 }
4699 if (result == 0) {
4700 /* bail out */
4701 return;
4702 }
4703
4704 if (!nv_loopback_test(dev)) {
4705 test->flags |= ETH_TEST_FL_FAILED;
4706 buffer[3] = 1;
4707 }
4708
4709 if (netif_running(dev)) {
4710 /* reinit driver view of the rx queue */
4711 set_bufsize(dev);
4712 if (nv_init_ring(dev)) {
4713 if (!np->in_shutdown)
4714 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4715 }
4716 /* reinit nic view of the rx queue */
4717 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4718 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4719 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4720 base + NvRegRingSizes);
4721 pci_push(base);
4722 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4723 pci_push(base);
4724 /* restart rx engine */
4725 nv_start_rx(dev);
4726 nv_start_tx(dev);
4727 netif_start_queue(dev);
4728 #ifdef CONFIG_FORCEDETH_NAPI
4729 napi_enable(&np->napi);
4730 #endif
4731 nv_enable_hw_interrupts(dev, np->irqmask);
4732 }
4733 }
4734 }
4735
4736 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4737 {
4738 switch (stringset) {
4739 case ETH_SS_STATS:
4740 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4741 break;
4742 case ETH_SS_TEST:
4743 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4744 break;
4745 }
4746 }
4747
4748 static const struct ethtool_ops ops = {
4749 .get_drvinfo = nv_get_drvinfo,
4750 .get_link = ethtool_op_get_link,
4751 .get_wol = nv_get_wol,
4752 .set_wol = nv_set_wol,
4753 .get_settings = nv_get_settings,
4754 .set_settings = nv_set_settings,
4755 .get_regs_len = nv_get_regs_len,
4756 .get_regs = nv_get_regs,
4757 .nway_reset = nv_nway_reset,
4758 .set_tso = nv_set_tso,
4759 .get_ringparam = nv_get_ringparam,
4760 .set_ringparam = nv_set_ringparam,
4761 .get_pauseparam = nv_get_pauseparam,
4762 .set_pauseparam = nv_set_pauseparam,
4763 .get_rx_csum = nv_get_rx_csum,
4764 .set_rx_csum = nv_set_rx_csum,
4765 .set_tx_csum = nv_set_tx_csum,
4766 .set_sg = nv_set_sg,
4767 .get_strings = nv_get_strings,
4768 .get_ethtool_stats = nv_get_ethtool_stats,
4769 .get_sset_count = nv_get_sset_count,
4770 .self_test = nv_self_test,
4771 };
4772
4773 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4774 {
4775 struct fe_priv *np = get_nvpriv(dev);
4776
4777 spin_lock_irq(&np->lock);
4778
4779 /* save vlan group */
4780 np->vlangrp = grp;
4781
4782 if (grp) {
4783 /* enable vlan on MAC */
4784 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4785 } else {
4786 /* disable vlan on MAC */
4787 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4788 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4789 }
4790
4791 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4792
4793 spin_unlock_irq(&np->lock);
4794 }
4795
4796 /* The mgmt unit and driver use a semaphore to access the phy during init */
4797 static int nv_mgmt_acquire_sema(struct net_device *dev)
4798 {
4799 u8 __iomem *base = get_hwbase(dev);
4800 int i;
4801 u32 tx_ctrl, mgmt_sema;
4802
4803 for (i = 0; i < 10; i++) {
4804 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4805 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4806 break;
4807 msleep(500);
4808 }
4809
4810 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4811 return 0;
4812
4813 for (i = 0; i < 2; i++) {
4814 tx_ctrl = readl(base + NvRegTransmitterControl);
4815 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4816 writel(tx_ctrl, base + NvRegTransmitterControl);
4817
4818 /* verify that semaphore was acquired */
4819 tx_ctrl = readl(base + NvRegTransmitterControl);
4820 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4821 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4822 return 1;
4823 else
4824 udelay(50);
4825 }
4826
4827 return 0;
4828 }
4829
4830 static int nv_open(struct net_device *dev)
4831 {
4832 struct fe_priv *np = netdev_priv(dev);
4833 u8 __iomem *base = get_hwbase(dev);
4834 int ret = 1;
4835 int oom, i;
4836
4837 dprintk(KERN_DEBUG "nv_open: begin\n");
4838
4839 /* erase previous misconfiguration */
4840 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4841 nv_mac_reset(dev);
4842 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4843 writel(0, base + NvRegMulticastAddrB);
4844 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4845 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
4846 writel(0, base + NvRegPacketFilterFlags);
4847
4848 writel(0, base + NvRegTransmitterControl);
4849 writel(0, base + NvRegReceiverControl);
4850
4851 writel(0, base + NvRegAdapterControl);
4852
4853 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4854 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4855
4856 /* initialize descriptor rings */
4857 set_bufsize(dev);
4858 oom = nv_init_ring(dev);
4859
4860 writel(0, base + NvRegLinkSpeed);
4861 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4862 nv_txrx_reset(dev);
4863 writel(0, base + NvRegUnknownSetupReg6);
4864
4865 np->in_shutdown = 0;
4866
4867 /* give hw rings */
4868 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4869 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4870 base + NvRegRingSizes);
4871
4872 writel(np->linkspeed, base + NvRegLinkSpeed);
4873 if (np->desc_ver == DESC_VER_1)
4874 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4875 else
4876 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4877 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4878 writel(np->vlanctl_bits, base + NvRegVlanControl);
4879 pci_push(base);
4880 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4881 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4882 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4883 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4884
4885 writel(0, base + NvRegMIIMask);
4886 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4887 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
4888
4889 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4890 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4891 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4892 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4893
4894 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4895 get_random_bytes(&i, sizeof(i));
4896 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4897 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4898 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4899 if (poll_interval == -1) {
4900 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4901 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4902 else
4903 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4904 }
4905 else
4906 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4907 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4908 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4909 base + NvRegAdapterControl);
4910 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4911 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4912 if (np->wolenabled)
4913 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4914
4915 i = readl(base + NvRegPowerState);
4916 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4917 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4918
4919 pci_push(base);
4920 udelay(10);
4921 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4922
4923 nv_disable_hw_interrupts(dev, np->irqmask);
4924 pci_push(base);
4925 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
4926 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4927 pci_push(base);
4928
4929 if (nv_request_irq(dev, 0)) {
4930 goto out_drain;
4931 }
4932
4933 /* ask for interrupts */
4934 nv_enable_hw_interrupts(dev, np->irqmask);
4935
4936 spin_lock_irq(&np->lock);
4937 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4938 writel(0, base + NvRegMulticastAddrB);
4939 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4940 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
4941 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4942 /* One manual link speed update: Interrupts are enabled, future link
4943 * speed changes cause interrupts and are handled by nv_link_irq().
4944 */
4945 {
4946 u32 miistat;
4947 miistat = readl(base + NvRegMIIStatus);
4948 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
4949 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4950 }
4951 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4952 * to init hw */
4953 np->linkspeed = 0;
4954 ret = nv_update_linkspeed(dev);
4955 nv_start_rx(dev);
4956 nv_start_tx(dev);
4957 netif_start_queue(dev);
4958 #ifdef CONFIG_FORCEDETH_NAPI
4959 napi_enable(&np->napi);
4960 #endif
4961
4962 if (ret) {
4963 netif_carrier_on(dev);
4964 } else {
4965 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
4966 netif_carrier_off(dev);
4967 }
4968 if (oom)
4969 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4970
4971 /* start statistics timer */
4972 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
4973 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4974
4975 spin_unlock_irq(&np->lock);
4976
4977 return 0;
4978 out_drain:
4979 drain_ring(dev);
4980 return ret;
4981 }
4982
4983 static int nv_close(struct net_device *dev)
4984 {
4985 struct fe_priv *np = netdev_priv(dev);
4986 u8 __iomem *base;
4987
4988 spin_lock_irq(&np->lock);
4989 np->in_shutdown = 1;
4990 spin_unlock_irq(&np->lock);
4991 #ifdef CONFIG_FORCEDETH_NAPI
4992 napi_disable(&np->napi);
4993 #endif
4994 synchronize_irq(np->pci_dev->irq);
4995
4996 del_timer_sync(&np->oom_kick);
4997 del_timer_sync(&np->nic_poll);
4998 del_timer_sync(&np->stats_poll);
4999
5000 netif_stop_queue(dev);
5001 spin_lock_irq(&np->lock);
5002 nv_stop_tx(dev);
5003 nv_stop_rx(dev);
5004 nv_txrx_reset(dev);
5005
5006 /* disable interrupts on the nic or we will lock up */
5007 base = get_hwbase(dev);
5008 nv_disable_hw_interrupts(dev, np->irqmask);
5009 pci_push(base);
5010 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5011
5012 spin_unlock_irq(&np->lock);
5013
5014 nv_free_irq(dev);
5015
5016 drain_ring(dev);
5017
5018 if (np->wolenabled) {
5019 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5020 nv_start_rx(dev);
5021 }
5022
5023 /* FIXME: power down nic */
5024
5025 return 0;
5026 }
5027
5028 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5029 {
5030 struct net_device *dev;
5031 struct fe_priv *np;
5032 unsigned long addr;
5033 u8 __iomem *base;
5034 int err, i;
5035 u32 powerstate, txreg;
5036 u32 phystate_orig = 0, phystate;
5037 int phyinitialized = 0;
5038 DECLARE_MAC_BUF(mac);
5039 static int printed_version;
5040
5041 if (!printed_version++)
5042 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5043 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5044
5045 dev = alloc_etherdev(sizeof(struct fe_priv));
5046 err = -ENOMEM;
5047 if (!dev)
5048 goto out;
5049
5050 np = netdev_priv(dev);
5051 np->dev = dev;
5052 np->pci_dev = pci_dev;
5053 spin_lock_init(&np->lock);
5054 SET_NETDEV_DEV(dev, &pci_dev->dev);
5055
5056 init_timer(&np->oom_kick);
5057 np->oom_kick.data = (unsigned long) dev;
5058 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5059 init_timer(&np->nic_poll);
5060 np->nic_poll.data = (unsigned long) dev;
5061 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
5062 init_timer(&np->stats_poll);
5063 np->stats_poll.data = (unsigned long) dev;
5064 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
5065
5066 err = pci_enable_device(pci_dev);
5067 if (err)
5068 goto out_free;
5069
5070 pci_set_master(pci_dev);
5071
5072 err = pci_request_regions(pci_dev, DRV_NAME);
5073 if (err < 0)
5074 goto out_disable;
5075
5076 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5077 np->register_size = NV_PCI_REGSZ_VER3;
5078 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5079 np->register_size = NV_PCI_REGSZ_VER2;
5080 else
5081 np->register_size = NV_PCI_REGSZ_VER1;
5082
5083 err = -EINVAL;
5084 addr = 0;
5085 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5086 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5087 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5088 pci_resource_len(pci_dev, i),
5089 pci_resource_flags(pci_dev, i));
5090 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5091 pci_resource_len(pci_dev, i) >= np->register_size) {
5092 addr = pci_resource_start(pci_dev, i);
5093 break;
5094 }
5095 }
5096 if (i == DEVICE_COUNT_RESOURCE) {
5097 dev_printk(KERN_INFO, &pci_dev->dev,
5098 "Couldn't find register window\n");
5099 goto out_relreg;
5100 }
5101
5102 /* copy of driver data */
5103 np->driver_data = id->driver_data;
5104
5105 /* handle different descriptor versions */
5106 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5107 /* packet format 3: supports 40-bit addressing */
5108 np->desc_ver = DESC_VER_3;
5109 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5110 if (dma_64bit) {
5111 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5112 dev_printk(KERN_INFO, &pci_dev->dev,
5113 "64-bit DMA failed, using 32-bit addressing\n");
5114 else
5115 dev->features |= NETIF_F_HIGHDMA;
5116 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5117 dev_printk(KERN_INFO, &pci_dev->dev,
5118 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5119 }
5120 }
5121 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5122 /* packet format 2: supports jumbo frames */
5123 np->desc_ver = DESC_VER_2;
5124 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5125 } else {
5126 /* original packet format */
5127 np->desc_ver = DESC_VER_1;
5128 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5129 }
5130
5131 np->pkt_limit = NV_PKTLIMIT_1;
5132 if (id->driver_data & DEV_HAS_LARGEDESC)
5133 np->pkt_limit = NV_PKTLIMIT_2;
5134
5135 if (id->driver_data & DEV_HAS_CHECKSUM) {
5136 np->rx_csum = 1;
5137 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5138 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5139 dev->features |= NETIF_F_TSO;
5140 }
5141
5142 np->vlanctl_bits = 0;
5143 if (id->driver_data & DEV_HAS_VLAN) {
5144 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5145 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5146 dev->vlan_rx_register = nv_vlan_rx_register;
5147 }
5148
5149 np->msi_flags = 0;
5150 if ((id->driver_data & DEV_HAS_MSI) && msi) {
5151 np->msi_flags |= NV_MSI_CAPABLE;
5152 }
5153 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5154 np->msi_flags |= NV_MSI_X_CAPABLE;
5155 }
5156
5157 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5158 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
5159 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5160 }
5161
5162
5163 err = -ENOMEM;
5164 np->base = ioremap(addr, np->register_size);
5165 if (!np->base)
5166 goto out_relreg;
5167 dev->base_addr = (unsigned long)np->base;
5168
5169 dev->irq = pci_dev->irq;
5170
5171 np->rx_ring_size = RX_RING_DEFAULT;
5172 np->tx_ring_size = TX_RING_DEFAULT;
5173
5174 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
5175 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5176 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5177 &np->ring_addr);
5178 if (!np->rx_ring.orig)
5179 goto out_unmap;
5180 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5181 } else {
5182 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5183 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5184 &np->ring_addr);
5185 if (!np->rx_ring.ex)
5186 goto out_unmap;
5187 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5188 }
5189 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5190 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5191 if (!np->rx_skb || !np->tx_skb)
5192 goto out_freering;
5193
5194 dev->open = nv_open;
5195 dev->stop = nv_close;
5196 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5197 dev->hard_start_xmit = nv_start_xmit;
5198 else
5199 dev->hard_start_xmit = nv_start_xmit_optimized;
5200 dev->get_stats = nv_get_stats;
5201 dev->change_mtu = nv_change_mtu;
5202 dev->set_mac_address = nv_set_mac_address;
5203 dev->set_multicast_list = nv_set_multicast;
5204 #ifdef CONFIG_NET_POLL_CONTROLLER
5205 dev->poll_controller = nv_poll_controller;
5206 #endif
5207 #ifdef CONFIG_FORCEDETH_NAPI
5208 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5209 #endif
5210 SET_ETHTOOL_OPS(dev, &ops);
5211 dev->tx_timeout = nv_tx_timeout;
5212 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5213
5214 pci_set_drvdata(pci_dev, dev);
5215
5216 /* read the mac address */
5217 base = get_hwbase(dev);
5218 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5219 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5220
5221 /* check the workaround bit for correct mac address order */
5222 txreg = readl(base + NvRegTransmitPoll);
5223 if ((txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) ||
5224 (id->driver_data & DEV_HAS_CORRECT_MACADDR)) {
5225 /* mac address is already in correct order */
5226 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5227 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5228 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5229 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5230 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5231 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5232 } else {
5233 /* need to reverse mac address to correct order */
5234 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5235 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5236 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5237 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5238 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5239 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5240 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5241 }
5242 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5243
5244 if (!is_valid_ether_addr(dev->perm_addr)) {
5245 /*
5246 * Bad mac address. At least one bios sets the mac address
5247 * to 01:23:45:67:89:ab
5248 */
5249 dev_printk(KERN_ERR, &pci_dev->dev,
5250 "Invalid Mac address detected: %s\n",
5251 print_mac(mac, dev->dev_addr));
5252 dev_printk(KERN_ERR, &pci_dev->dev,
5253 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5254 dev->dev_addr[0] = 0x00;
5255 dev->dev_addr[1] = 0x00;
5256 dev->dev_addr[2] = 0x6c;
5257 get_random_bytes(&dev->dev_addr[3], 3);
5258 }
5259
5260 dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5261 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
5262
5263 /* set mac address */
5264 nv_copy_mac_to_hw(dev);
5265
5266 /* disable WOL */
5267 writel(0, base + NvRegWakeUpFlags);
5268 np->wolenabled = 0;
5269
5270 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5271
5272 /* take phy and nic out of low power mode */
5273 powerstate = readl(base + NvRegPowerState2);
5274 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5275 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5276 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5277 pci_dev->revision >= 0xA3)
5278 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5279 writel(powerstate, base + NvRegPowerState2);
5280 }
5281
5282 if (np->desc_ver == DESC_VER_1) {
5283 np->tx_flags = NV_TX_VALID;
5284 } else {
5285 np->tx_flags = NV_TX2_VALID;
5286 }
5287 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5288 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5289 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5290 np->msi_flags |= 0x0003;
5291 } else {
5292 np->irqmask = NVREG_IRQMASK_CPU;
5293 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5294 np->msi_flags |= 0x0001;
5295 }
5296
5297 if (id->driver_data & DEV_NEED_TIMERIRQ)
5298 np->irqmask |= NVREG_IRQ_TIMER;
5299 if (id->driver_data & DEV_NEED_LINKTIMER) {
5300 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5301 np->need_linktimer = 1;
5302 np->link_timeout = jiffies + LINK_TIMEOUT;
5303 } else {
5304 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5305 np->need_linktimer = 0;
5306 }
5307
5308 /* clear phy state and temporarily halt phy interrupts */
5309 writel(0, base + NvRegMIIMask);
5310 phystate = readl(base + NvRegAdapterControl);
5311 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5312 phystate_orig = 1;
5313 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5314 writel(phystate, base + NvRegAdapterControl);
5315 }
5316 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5317
5318 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5319 /* management unit running on the mac? */
5320 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5321 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5322 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5323 if (nv_mgmt_acquire_sema(dev)) {
5324 /* management unit setup the phy already? */
5325 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5326 NVREG_XMITCTL_SYNC_PHY_INIT) {
5327 /* phy is inited by mgmt unit */
5328 phyinitialized = 1;
5329 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5330 } else {
5331 /* we need to init the phy */
5332 }
5333 }
5334 }
5335 }
5336
5337 /* find a suitable phy */
5338 for (i = 1; i <= 32; i++) {
5339 int id1, id2;
5340 int phyaddr = i & 0x1F;
5341
5342 spin_lock_irq(&np->lock);
5343 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5344 spin_unlock_irq(&np->lock);
5345 if (id1 < 0 || id1 == 0xffff)
5346 continue;
5347 spin_lock_irq(&np->lock);
5348 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5349 spin_unlock_irq(&np->lock);
5350 if (id2 < 0 || id2 == 0xffff)
5351 continue;
5352
5353 np->phy_model = id2 & PHYID2_MODEL_MASK;
5354 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5355 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5356 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5357 pci_name(pci_dev), id1, id2, phyaddr);
5358 np->phyaddr = phyaddr;
5359 np->phy_oui = id1 | id2;
5360 break;
5361 }
5362 if (i == 33) {
5363 dev_printk(KERN_INFO, &pci_dev->dev,
5364 "open: Could not find a valid PHY.\n");
5365 goto out_error;
5366 }
5367
5368 if (!phyinitialized) {
5369 /* reset it */
5370 phy_init(dev);
5371 } else {
5372 /* see if it is a gigabit phy */
5373 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5374 if (mii_status & PHY_GIGABIT) {
5375 np->gigabit = PHY_GIGABIT;
5376 }
5377 }
5378
5379 /* set default link speed settings */
5380 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5381 np->duplex = 0;
5382 np->autoneg = 1;
5383
5384 err = register_netdev(dev);
5385 if (err) {
5386 dev_printk(KERN_INFO, &pci_dev->dev,
5387 "unable to register netdev: %d\n", err);
5388 goto out_error;
5389 }
5390
5391 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5392 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5393 dev->name,
5394 np->phy_oui,
5395 np->phyaddr,
5396 dev->dev_addr[0],
5397 dev->dev_addr[1],
5398 dev->dev_addr[2],
5399 dev->dev_addr[3],
5400 dev->dev_addr[4],
5401 dev->dev_addr[5]);
5402
5403 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5404 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5405 dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5406 "csum " : "",
5407 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5408 "vlan " : "",
5409 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5410 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5411 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5412 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5413 np->need_linktimer ? "lnktim " : "",
5414 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5415 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5416 np->desc_ver);
5417
5418 return 0;
5419
5420 out_error:
5421 if (phystate_orig)
5422 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5423 pci_set_drvdata(pci_dev, NULL);
5424 out_freering:
5425 free_rings(dev);
5426 out_unmap:
5427 iounmap(get_hwbase(dev));
5428 out_relreg:
5429 pci_release_regions(pci_dev);
5430 out_disable:
5431 pci_disable_device(pci_dev);
5432 out_free:
5433 free_netdev(dev);
5434 out:
5435 return err;
5436 }
5437
5438 static void __devexit nv_remove(struct pci_dev *pci_dev)
5439 {
5440 struct net_device *dev = pci_get_drvdata(pci_dev);
5441 struct fe_priv *np = netdev_priv(dev);
5442 u8 __iomem *base = get_hwbase(dev);
5443
5444 unregister_netdev(dev);
5445
5446 /* special op: write back the misordered MAC address - otherwise
5447 * the next nv_probe would see a wrong address.
5448 */
5449 writel(np->orig_mac[0], base + NvRegMacAddrA);
5450 writel(np->orig_mac[1], base + NvRegMacAddrB);
5451 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5452 base + NvRegTransmitPoll);
5453
5454 /* free all structures */
5455 free_rings(dev);
5456 iounmap(get_hwbase(dev));
5457 pci_release_regions(pci_dev);
5458 pci_disable_device(pci_dev);
5459 free_netdev(dev);
5460 pci_set_drvdata(pci_dev, NULL);
5461 }
5462
5463 #ifdef CONFIG_PM
5464 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5465 {
5466 struct net_device *dev = pci_get_drvdata(pdev);
5467 struct fe_priv *np = netdev_priv(dev);
5468
5469 if (!netif_running(dev))
5470 goto out;
5471
5472 netif_device_detach(dev);
5473
5474 // Gross.
5475 nv_close(dev);
5476
5477 pci_save_state(pdev);
5478 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5479 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5480 out:
5481 return 0;
5482 }
5483
5484 static int nv_resume(struct pci_dev *pdev)
5485 {
5486 struct net_device *dev = pci_get_drvdata(pdev);
5487 int rc = 0;
5488
5489 if (!netif_running(dev))
5490 goto out;
5491
5492 netif_device_attach(dev);
5493
5494 pci_set_power_state(pdev, PCI_D0);
5495 pci_restore_state(pdev);
5496 pci_enable_wake(pdev, PCI_D0, 0);
5497
5498 rc = nv_open(dev);
5499 out:
5500 return rc;
5501 }
5502 #else
5503 #define nv_suspend NULL
5504 #define nv_resume NULL
5505 #endif /* CONFIG_PM */
5506
5507 static struct pci_device_id pci_tbl[] = {
5508 { /* nForce Ethernet Controller */
5509 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5510 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5511 },
5512 { /* nForce2 Ethernet Controller */
5513 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5514 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5515 },
5516 { /* nForce3 Ethernet Controller */
5517 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5518 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5519 },
5520 { /* nForce3 Ethernet Controller */
5521 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5522 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5523 },
5524 { /* nForce3 Ethernet Controller */
5525 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5526 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5527 },
5528 { /* nForce3 Ethernet Controller */
5529 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5530 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5531 },
5532 { /* nForce3 Ethernet Controller */
5533 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5534 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5535 },
5536 { /* CK804 Ethernet Controller */
5537 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5538 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5539 },
5540 { /* CK804 Ethernet Controller */
5541 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5542 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5543 },
5544 { /* MCP04 Ethernet Controller */
5545 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5546 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5547 },
5548 { /* MCP04 Ethernet Controller */
5549 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5550 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5551 },
5552 { /* MCP51 Ethernet Controller */
5553 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5554 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5555 },
5556 { /* MCP51 Ethernet Controller */
5557 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5558 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5559 },
5560 { /* MCP55 Ethernet Controller */
5561 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5562 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5563 },
5564 { /* MCP55 Ethernet Controller */
5565 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5566 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5567 },
5568 { /* MCP61 Ethernet Controller */
5569 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5570 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5571 },
5572 { /* MCP61 Ethernet Controller */
5573 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5574 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5575 },
5576 { /* MCP61 Ethernet Controller */
5577 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5578 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5579 },
5580 { /* MCP61 Ethernet Controller */
5581 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5582 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5583 },
5584 { /* MCP65 Ethernet Controller */
5585 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5586 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5587 },
5588 { /* MCP65 Ethernet Controller */
5589 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5590 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5591 },
5592 { /* MCP65 Ethernet Controller */
5593 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5594 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5595 },
5596 { /* MCP65 Ethernet Controller */
5597 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5598 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5599 },
5600 { /* MCP67 Ethernet Controller */
5601 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5602 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5603 },
5604 { /* MCP67 Ethernet Controller */
5605 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5606 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5607 },
5608 { /* MCP67 Ethernet Controller */
5609 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5610 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5611 },
5612 { /* MCP67 Ethernet Controller */
5613 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5614 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5615 },
5616 { /* MCP73 Ethernet Controller */
5617 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
5618 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5619 },
5620 { /* MCP73 Ethernet Controller */
5621 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
5622 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5623 },
5624 { /* MCP73 Ethernet Controller */
5625 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
5626 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5627 },
5628 { /* MCP73 Ethernet Controller */
5629 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
5630 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5631 },
5632 { /* MCP77 Ethernet Controller */
5633 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
5634 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5635 },
5636 { /* MCP77 Ethernet Controller */
5637 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
5638 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5639 },
5640 { /* MCP77 Ethernet Controller */
5641 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
5642 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5643 },
5644 { /* MCP77 Ethernet Controller */
5645 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
5646 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5647 },
5648 { /* MCP79 Ethernet Controller */
5649 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
5650 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5651 },
5652 { /* MCP79 Ethernet Controller */
5653 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
5654 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5655 },
5656 { /* MCP79 Ethernet Controller */
5657 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
5658 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5659 },
5660 { /* MCP79 Ethernet Controller */
5661 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
5662 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5663 },
5664 {0,},
5665 };
5666
5667 static struct pci_driver driver = {
5668 .name = DRV_NAME,
5669 .id_table = pci_tbl,
5670 .probe = nv_probe,
5671 .remove = __devexit_p(nv_remove),
5672 .suspend = nv_suspend,
5673 .resume = nv_resume,
5674 };
5675
5676 static int __init init_nic(void)
5677 {
5678 return pci_register_driver(&driver);
5679 }
5680
5681 static void __exit exit_nic(void)
5682 {
5683 pci_unregister_driver(&driver);
5684 }
5685
5686 module_param(max_interrupt_work, int, 0);
5687 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5688 module_param(optimization_mode, int, 0);
5689 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5690 module_param(poll_interval, int, 0);
5691 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5692 module_param(msi, int, 0);
5693 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5694 module_param(msix, int, 0);
5695 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5696 module_param(dma_64bit, int, 0);
5697 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5698
5699 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5700 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5701 MODULE_LICENSE("GPL");
5702
5703 MODULE_DEVICE_TABLE(pci, pci_tbl);
5704
5705 module_init(init_nic);
5706 module_exit(exit_nic);
SocketAccessConTroL development