| blob | ea1137851a4adc4a6ae7adfcba8aa74ed303340c |
1 /*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * kexec bits:
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 *
17 */
19 #include <linux/sys.h>
20 #include <asm/unistd.h>
21 #include <asm/errno.h>
22 #include <asm/reg.h>
23 #include <asm/page.h>
24 #include <asm/cache.h>
25 #include <asm/cputable.h>
26 #include <asm/mmu.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/processor.h>
31 #include <asm/kexec.h>
33 .text
35 /*
36 * This returns the high 64 bits of the product of two 64-bit numbers.
37 */
38 _GLOBAL(mulhdu)
39 cmpwi r6,0
40 cmpwi cr1,r3,0
41 mr r10,r4
42 mulhwu r4,r4,r5
43 beq 1f
44 mulhwu r0,r10,r6
45 mullw r7,r10,r5
46 addc r7,r0,r7
47 addze r4,r4
48 1: beqlr cr1 /* all done if high part of A is 0 */
49 mr r10,r3
50 mullw r9,r3,r5
51 mulhwu r3,r3,r5
52 beq 2f
53 mullw r0,r10,r6
54 mulhwu r8,r10,r6
55 addc r7,r0,r7
56 adde r4,r4,r8
57 addze r3,r3
58 2: addc r4,r4,r9
59 addze r3,r3
60 blr
62 /*
63 * sub_reloc_offset(x) returns x - reloc_offset().
64 */
65 _GLOBAL(sub_reloc_offset)
66 mflr r0
67 bl 1f
68 1: mflr r5
69 lis r4,1b@ha
70 addi r4,r4,1b@l
71 subf r5,r4,r5
72 subf r3,r5,r3
73 mtlr r0
74 blr
76 /*
77 * reloc_got2 runs through the .got2 section adding an offset
78 * to each entry.
79 */
80 _GLOBAL(reloc_got2)
81 mflr r11
82 lis r7,__got2_start@ha
83 addi r7,r7,__got2_start@l
84 lis r8,__got2_end@ha
85 addi r8,r8,__got2_end@l
86 subf r8,r7,r8
87 srwi. r8,r8,2
88 beqlr
89 mtctr r8
90 bl 1f
91 1: mflr r0
92 lis r4,1b@ha
93 addi r4,r4,1b@l
94 subf r0,r4,r0
95 add r7,r0,r7
96 2: lwz r0,0(r7)
97 add r0,r0,r3
98 stw r0,0(r7)
99 addi r7,r7,4
100 bdnz 2b
101 mtlr r11
102 blr
104 /*
105 * call_setup_cpu - call the setup_cpu function for this cpu
106 * r3 = data offset, r24 = cpu number
107 *
108 * Setup function is called with:
109 * r3 = data offset
110 * r4 = ptr to CPU spec (relocated)
111 */
112 _GLOBAL(call_setup_cpu)
113 addis r4,r3,cur_cpu_spec@ha
114 addi r4,r4,cur_cpu_spec@l
115 lwz r4,0(r4)
116 add r4,r4,r3
117 lwz r5,CPU_SPEC_SETUP(r4)
118 cmpwi 0,r5,0
119 add r5,r5,r3
120 beqlr
121 mtctr r5
122 bctr
124 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
126 /* This gets called by via-pmu.c to switch the PLL selection
127 * on 750fx CPU. This function should really be moved to some
128 * other place (as most of the cpufreq code in via-pmu
129 */
130 _GLOBAL(low_choose_750fx_pll)
131 /* Clear MSR:EE */
132 mfmsr r7
133 rlwinm r0,r7,0,17,15
134 mtmsr r0
136 /* If switching to PLL1, disable HID0:BTIC */
137 cmplwi cr0,r3,0
138 beq 1f
139 mfspr r5,SPRN_HID0
140 rlwinm r5,r5,0,27,25
141 sync
142 mtspr SPRN_HID0,r5
143 isync
144 sync
146 1:
147 /* Calc new HID1 value */
148 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
149 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
150 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
151 or r4,r4,r5
152 mtspr SPRN_HID1,r4
154 /* Store new HID1 image */
155 rlwinm r6,r1,0,0,18
156 lwz r6,TI_CPU(r6)
157 slwi r6,r6,2
158 addis r6,r6,nap_save_hid1@ha
159 stw r4,nap_save_hid1@l(r6)
161 /* If switching to PLL0, enable HID0:BTIC */
162 cmplwi cr0,r3,0
163 bne 1f
164 mfspr r5,SPRN_HID0
165 ori r5,r5,HID0_BTIC
166 sync
167 mtspr SPRN_HID0,r5
168 isync
169 sync
171 1:
172 /* Return */
173 mtmsr r7
174 blr
176 _GLOBAL(low_choose_7447a_dfs)
177 /* Clear MSR:EE */
178 mfmsr r7
179 rlwinm r0,r7,0,17,15
180 mtmsr r0
182 /* Calc new HID1 value */
183 mfspr r4,SPRN_HID1
184 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
185 sync
186 mtspr SPRN_HID1,r4
187 sync
188 isync
190 /* Return */
191 mtmsr r7
192 blr
194 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
196 /*
197 * complement mask on the msr then "or" some values on.
198 * _nmask_and_or_msr(nmask, value_to_or)
199 */
200 _GLOBAL(_nmask_and_or_msr)
201 mfmsr r0 /* Get current msr */
202 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
203 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
204 SYNC /* Some chip revs have problems here... */
205 mtmsr r0 /* Update machine state */
206 isync
207 blr /* Done */
210 /*
211 * Flush MMU TLB
212 */
213 _GLOBAL(_tlbia)
214 #if defined(CONFIG_40x)
215 sync /* Flush to memory before changing mapping */
216 tlbia
217 isync /* Flush shadow TLB */
218 #elif defined(CONFIG_44x)
219 li r3,0
220 sync
222 /* Load high watermark */
223 lis r4,tlb_44x_hwater@ha
224 lwz r5,tlb_44x_hwater@l(r4)
226 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
227 addi r3,r3,1
228 cmpw 0,r3,r5
229 ble 1b
231 isync
232 #elif defined(CONFIG_FSL_BOOKE)
233 /* Invalidate all entries in TLB0 */
234 li r3, 0x04
235 tlbivax 0,3
236 /* Invalidate all entries in TLB1 */
237 li r3, 0x0c
238 tlbivax 0,3
239 /* Invalidate all entries in TLB2 */
240 li r3, 0x14
241 tlbivax 0,3
242 /* Invalidate all entries in TLB3 */
243 li r3, 0x1c
244 tlbivax 0,3
245 msync
246 #ifdef CONFIG_SMP
247 tlbsync
248 #endif /* CONFIG_SMP */
249 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
250 #if defined(CONFIG_SMP)
251 rlwinm r8,r1,0,0,18
252 lwz r8,TI_CPU(r8)
253 oris r8,r8,10
254 mfmsr r10
255 SYNC
256 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
257 rlwinm r0,r0,0,28,26 /* clear DR */
258 mtmsr r0
259 SYNC_601
260 isync
261 lis r9,mmu_hash_lock@h
262 ori r9,r9,mmu_hash_lock@l
263 tophys(r9,r9)
264 10: lwarx r7,0,r9
265 cmpwi 0,r7,0
266 bne- 10b
267 stwcx. r8,0,r9
268 bne- 10b
269 sync
270 tlbia
271 sync
272 TLBSYNC
273 li r0,0
274 stw r0,0(r9) /* clear mmu_hash_lock */
275 mtmsr r10
276 SYNC_601
277 isync
278 #else /* CONFIG_SMP */
279 sync
280 tlbia
281 sync
282 #endif /* CONFIG_SMP */
283 #endif /* ! defined(CONFIG_40x) */
284 blr
286 /*
287 * Flush MMU TLB for a particular address
288 */
289 _GLOBAL(_tlbie)
290 #if defined(CONFIG_40x)
291 /* We run the search with interrupts disabled because we have to change
292 * the PID and I don't want to preempt when that happens.
293 */
294 mfmsr r5
295 mfspr r6,SPRN_PID
296 wrteei 0
297 mtspr SPRN_PID,r4
298 tlbsx. r3, 0, r3
299 mtspr SPRN_PID,r6
300 wrtee r5
301 bne 10f
302 sync
303 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
304 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
305 * the TLB entry. */
306 tlbwe r3, r3, TLB_TAG
307 isync
308 10:
310 #elif defined(CONFIG_44x)
311 mfspr r5,SPRN_MMUCR
312 rlwimi r5,r4,0,24,31 /* Set TID */
314 /* We have to run the search with interrupts disabled, even critical
315 * and debug interrupts (in fact the only critical exceptions we have
316 * are debug and machine check). Otherwise an interrupt which causes
317 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
318 mfmsr r4
319 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
320 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
321 andc r6,r4,r6
322 mtmsr r6
323 mtspr SPRN_MMUCR,r5
324 tlbsx. r3, 0, r3
325 mtmsr r4
326 bne 10f
327 sync
328 /* There are only 64 TLB entries, so r3 < 64,
329 * which means bit 22, is clear. Since 22 is
330 * the V bit in the TLB_PAGEID, loading this
331 * value will invalidate the TLB entry.
332 */
333 tlbwe r3, r3, PPC44x_TLB_PAGEID
334 isync
335 10:
336 #elif defined(CONFIG_FSL_BOOKE)
337 rlwinm r4, r3, 0, 0, 19
338 ori r5, r4, 0x08 /* TLBSEL = 1 */
339 ori r6, r4, 0x10 /* TLBSEL = 2 */
340 ori r7, r4, 0x18 /* TLBSEL = 3 */
341 tlbivax 0, r4
342 tlbivax 0, r5
343 tlbivax 0, r6
344 tlbivax 0, r7
345 msync
346 #if defined(CONFIG_SMP)
347 tlbsync
348 #endif /* CONFIG_SMP */
349 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
350 #if defined(CONFIG_SMP)
351 rlwinm r8,r1,0,0,18
352 lwz r8,TI_CPU(r8)
353 oris r8,r8,11
354 mfmsr r10
355 SYNC
356 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
357 rlwinm r0,r0,0,28,26 /* clear DR */
358 mtmsr r0
359 SYNC_601
360 isync
361 lis r9,mmu_hash_lock@h
362 ori r9,r9,mmu_hash_lock@l
363 tophys(r9,r9)
364 10: lwarx r7,0,r9
365 cmpwi 0,r7,0
366 bne- 10b
367 stwcx. r8,0,r9
368 bne- 10b
369 eieio
370 tlbie r3
371 sync
372 TLBSYNC
373 li r0,0
374 stw r0,0(r9) /* clear mmu_hash_lock */
375 mtmsr r10
376 SYNC_601
377 isync
378 #else /* CONFIG_SMP */
379 tlbie r3
380 sync
381 #endif /* CONFIG_SMP */
382 #endif /* ! CONFIG_40x */
383 blr
385 /*
386 * Flush instruction cache.
387 * This is a no-op on the 601.
388 */
389 _GLOBAL(flush_instruction_cache)
390 #if defined(CONFIG_8xx)
391 isync
392 lis r5, IDC_INVALL@h
393 mtspr SPRN_IC_CST, r5
394 #elif defined(CONFIG_4xx)
395 #ifdef CONFIG_403GCX
396 li r3, 512
397 mtctr r3
398 lis r4, KERNELBASE@h
399 1: iccci 0, r4
400 addi r4, r4, 16
401 bdnz 1b
402 #else
403 lis r3, KERNELBASE@h
404 iccci 0,r3
405 #endif
406 #elif CONFIG_FSL_BOOKE
407 BEGIN_FTR_SECTION
408 mfspr r3,SPRN_L1CSR0
409 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
410 /* msync; isync recommended here */
411 mtspr SPRN_L1CSR0,r3
412 isync
413 blr
414 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
415 mfspr r3,SPRN_L1CSR1
416 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
417 mtspr SPRN_L1CSR1,r3
418 #else
419 mfspr r3,SPRN_PVR
420 rlwinm r3,r3,16,16,31
421 cmpwi 0,r3,1
422 beqlr /* for 601, do nothing */
423 /* 603/604 processor - use invalidate-all bit in HID0 */
424 mfspr r3,SPRN_HID0
425 ori r3,r3,HID0_ICFI
426 mtspr SPRN_HID0,r3
427 #endif /* CONFIG_8xx/4xx */
428 isync
429 blr
431 /*
432 * Write any modified data cache blocks out to memory
433 * and invalidate the corresponding instruction cache blocks.
434 * This is a no-op on the 601.
435 *
436 * flush_icache_range(unsigned long start, unsigned long stop)
437 */
438 _GLOBAL(__flush_icache_range)
439 BEGIN_FTR_SECTION
440 blr /* for 601, do nothing */
441 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
442 li r5,L1_CACHE_BYTES-1
443 andc r3,r3,r5
444 subf r4,r3,r4
445 add r4,r4,r5
446 srwi. r4,r4,L1_CACHE_SHIFT
447 beqlr
448 mtctr r4
449 mr r6,r3
450 1: dcbst 0,r3
451 addi r3,r3,L1_CACHE_BYTES
452 bdnz 1b
453 sync /* wait for dcbst's to get to ram */
454 mtctr r4
455 2: icbi 0,r6
456 addi r6,r6,L1_CACHE_BYTES
457 bdnz 2b
458 sync /* additional sync needed on g4 */
459 isync
460 blr
461 /*
462 * Write any modified data cache blocks out to memory.
463 * Does not invalidate the corresponding cache lines (especially for
464 * any corresponding instruction cache).
465 *
466 * clean_dcache_range(unsigned long start, unsigned long stop)
467 */
468 _GLOBAL(clean_dcache_range)
469 li r5,L1_CACHE_BYTES-1
470 andc r3,r3,r5
471 subf r4,r3,r4
472 add r4,r4,r5
473 srwi. r4,r4,L1_CACHE_SHIFT
474 beqlr
475 mtctr r4
477 1: dcbst 0,r3
478 addi r3,r3,L1_CACHE_BYTES
479 bdnz 1b
480 sync /* wait for dcbst's to get to ram */
481 blr
483 /*
484 * Write any modified data cache blocks out to memory and invalidate them.
485 * Does not invalidate the corresponding instruction cache blocks.
486 *
487 * flush_dcache_range(unsigned long start, unsigned long stop)
488 */
489 _GLOBAL(flush_dcache_range)
490 li r5,L1_CACHE_BYTES-1
491 andc r3,r3,r5
492 subf r4,r3,r4
493 add r4,r4,r5
494 srwi. r4,r4,L1_CACHE_SHIFT
495 beqlr
496 mtctr r4
498 1: dcbf 0,r3
499 addi r3,r3,L1_CACHE_BYTES
500 bdnz 1b
501 sync /* wait for dcbst's to get to ram */
502 blr
504 /*
505 * Like above, but invalidate the D-cache. This is used by the 8xx
506 * to invalidate the cache so the PPC core doesn't get stale data
507 * from the CPM (no cache snooping here :-).
508 *
509 * invalidate_dcache_range(unsigned long start, unsigned long stop)
510 */
511 _GLOBAL(invalidate_dcache_range)
512 li r5,L1_CACHE_BYTES-1
513 andc r3,r3,r5
514 subf r4,r3,r4
515 add r4,r4,r5
516 srwi. r4,r4,L1_CACHE_SHIFT
517 beqlr
518 mtctr r4
520 1: dcbi 0,r3
521 addi r3,r3,L1_CACHE_BYTES
522 bdnz 1b
523 sync /* wait for dcbi's to get to ram */
524 blr
526 /*
527 * Flush a particular page from the data cache to RAM.
528 * Note: this is necessary because the instruction cache does *not*
529 * snoop from the data cache.
530 * This is a no-op on the 601 which has a unified cache.
531 *
532 * void __flush_dcache_icache(void *page)
533 */
534 _GLOBAL(__flush_dcache_icache)
535 BEGIN_FTR_SECTION
536 blr
537 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
538 rlwinm r3,r3,0,0,19 /* Get page base address */
539 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
540 mtctr r4
541 mr r6,r3
542 0: dcbst 0,r3 /* Write line to ram */
543 addi r3,r3,L1_CACHE_BYTES
544 bdnz 0b
545 sync
546 #ifndef CONFIG_44x
547 /* We don't flush the icache on 44x. Those have a virtual icache
548 * and we don't have access to the virtual address here (it's
549 * not the page vaddr but where it's mapped in user space). The
550 * flushing of the icache on these is handled elsewhere, when
551 * a change in the address space occurs, before returning to
552 * user space
553 */
554 mtctr r4
555 1: icbi 0,r6
556 addi r6,r6,L1_CACHE_BYTES
557 bdnz 1b
558 sync
559 isync
560 #endif /* CONFIG_44x */
561 blr
563 /*
564 * Flush a particular page from the data cache to RAM, identified
565 * by its physical address. We turn off the MMU so we can just use
566 * the physical address (this may be a highmem page without a kernel
567 * mapping).
568 *
569 * void __flush_dcache_icache_phys(unsigned long physaddr)
570 */
571 _GLOBAL(__flush_dcache_icache_phys)
572 BEGIN_FTR_SECTION
573 blr /* for 601, do nothing */
574 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
575 mfmsr r10
576 rlwinm r0,r10,0,28,26 /* clear DR */
577 mtmsr r0
578 isync
579 rlwinm r3,r3,0,0,19 /* Get page base address */
580 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
581 mtctr r4
582 mr r6,r3
583 0: dcbst 0,r3 /* Write line to ram */
584 addi r3,r3,L1_CACHE_BYTES
585 bdnz 0b
586 sync
587 mtctr r4
588 1: icbi 0,r6
589 addi r6,r6,L1_CACHE_BYTES
590 bdnz 1b
591 sync
592 mtmsr r10 /* restore DR */
593 isync
594 blr
596 /*
597 * Clear pages using the dcbz instruction, which doesn't cause any
598 * memory traffic (except to write out any cache lines which get
599 * displaced). This only works on cacheable memory.
600 *
601 * void clear_pages(void *page, int order) ;
602 */
603 _GLOBAL(clear_pages)
604 li r0,4096/L1_CACHE_BYTES
605 slw r0,r0,r4
606 mtctr r0
607 #ifdef CONFIG_8xx
608 li r4, 0
609 1: stw r4, 0(r3)
610 stw r4, 4(r3)
611 stw r4, 8(r3)
612 stw r4, 12(r3)
613 #else
614 1: dcbz 0,r3
615 #endif
616 addi r3,r3,L1_CACHE_BYTES
617 bdnz 1b
618 blr
620 /*
621 * Copy a whole page. We use the dcbz instruction on the destination
622 * to reduce memory traffic (it eliminates the unnecessary reads of
623 * the destination into cache). This requires that the destination
624 * is cacheable.
625 */
626 #define COPY_16_BYTES \
627 lwz r6,4(r4); \
628 lwz r7,8(r4); \
629 lwz r8,12(r4); \
630 lwzu r9,16(r4); \
631 stw r6,4(r3); \
632 stw r7,8(r3); \
633 stw r8,12(r3); \
634 stwu r9,16(r3)
636 _GLOBAL(copy_page)
637 addi r3,r3,-4
638 addi r4,r4,-4
640 #ifdef CONFIG_8xx
641 /* don't use prefetch on 8xx */
642 li r0,4096/L1_CACHE_BYTES
643 mtctr r0
644 1: COPY_16_BYTES
645 bdnz 1b
646 blr
648 #else /* not 8xx, we can prefetch */
649 li r5,4
651 #if MAX_COPY_PREFETCH > 1
652 li r0,MAX_COPY_PREFETCH
653 li r11,4
654 mtctr r0
655 11: dcbt r11,r4
656 addi r11,r11,L1_CACHE_BYTES
657 bdnz 11b
658 #else /* MAX_COPY_PREFETCH == 1 */
659 dcbt r5,r4
660 li r11,L1_CACHE_BYTES+4
661 #endif /* MAX_COPY_PREFETCH */
662 li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
663 crclr 4*cr0+eq
664 2:
665 mtctr r0
666 1:
667 dcbt r11,r4
668 dcbz r5,r3
669 COPY_16_BYTES
670 #if L1_CACHE_BYTES >= 32
671 COPY_16_BYTES
672 #if L1_CACHE_BYTES >= 64
673 COPY_16_BYTES
674 COPY_16_BYTES
675 #if L1_CACHE_BYTES >= 128
676 COPY_16_BYTES
677 COPY_16_BYTES
678 COPY_16_BYTES
679 COPY_16_BYTES
680 #endif
681 #endif
682 #endif
683 bdnz 1b
684 beqlr
685 crnot 4*cr0+eq,4*cr0+eq
686 li r0,MAX_COPY_PREFETCH
687 li r11,4
688 b 2b
689 #endif /* CONFIG_8xx */
691 /*
692 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
693 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
694 */
695 _GLOBAL(atomic_clear_mask)
696 10: lwarx r5,0,r4
697 andc r5,r5,r3
698 PPC405_ERR77(0,r4)
699 stwcx. r5,0,r4
700 bne- 10b
701 blr
702 _GLOBAL(atomic_set_mask)
703 10: lwarx r5,0,r4
704 or r5,r5,r3
705 PPC405_ERR77(0,r4)
706 stwcx. r5,0,r4
707 bne- 10b
708 blr
710 /*
711 * Extended precision shifts.
712 *
713 * Updated to be valid for shift counts from 0 to 63 inclusive.
714 * -- Gabriel
715 *
716 * R3/R4 has 64 bit value
717 * R5 has shift count
718 * result in R3/R4
719 *
720 * ashrdi3: arithmetic right shift (sign propagation)
721 * lshrdi3: logical right shift
722 * ashldi3: left shift
723 */
724 _GLOBAL(__ashrdi3)
725 subfic r6,r5,32
726 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
727 addi r7,r5,32 # could be xori, or addi with -32
728 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
729 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
730 sraw r7,r3,r7 # t2 = MSW >> (count-32)
731 or r4,r4,r6 # LSW |= t1
732 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
733 sraw r3,r3,r5 # MSW = MSW >> count
734 or r4,r4,r7 # LSW |= t2
735 blr
737 _GLOBAL(__ashldi3)
738 subfic r6,r5,32
739 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
740 addi r7,r5,32 # could be xori, or addi with -32
741 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
742 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
743 or r3,r3,r6 # MSW |= t1
744 slw r4,r4,r5 # LSW = LSW << count
745 or r3,r3,r7 # MSW |= t2
746 blr
748 _GLOBAL(__lshrdi3)
749 subfic r6,r5,32
750 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
751 addi r7,r5,32 # could be xori, or addi with -32
752 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
753 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
754 or r4,r4,r6 # LSW |= t1
755 srw r3,r3,r5 # MSW = MSW >> count
756 or r4,r4,r7 # LSW |= t2
757 blr
759 _GLOBAL(abs)
760 srawi r4,r3,31
761 xor r3,r3,r4
762 sub r3,r3,r4
763 blr
765 /*
766 * Create a kernel thread
767 * kernel_thread(fn, arg, flags)
768 */
769 _GLOBAL(kernel_thread)
770 stwu r1,-16(r1)
771 stw r30,8(r1)
772 stw r31,12(r1)
773 mr r30,r3 /* function */
774 mr r31,r4 /* argument */
775 ori r3,r5,CLONE_VM /* flags */
776 oris r3,r3,CLONE_UNTRACED>>16
777 li r4,0 /* new sp (unused) */
778 li r0,__NR_clone
779 sc
780 cmpwi 0,r3,0 /* parent or child? */
781 bne 1f /* return if parent */
782 li r0,0 /* make top-level stack frame */
783 stwu r0,-16(r1)
784 mtlr r30 /* fn addr in lr */
785 mr r3,r31 /* load arg and call fn */
786 PPC440EP_ERR42
787 blrl
788 li r0,__NR_exit /* exit if function returns */
789 li r3,0
790 sc
791 1: lwz r30,8(r1)
792 lwz r31,12(r1)
793 addi r1,r1,16
794 blr
796 /*
797 * This routine is just here to keep GCC happy - sigh...
798 */
799 _GLOBAL(__main)
800 blr
802 #ifdef CONFIG_KEXEC
803 /*
804 * Must be relocatable PIC code callable as a C function.
805 */
806 .globl relocate_new_kernel
807 relocate_new_kernel:
808 /* r3 = page_list */
809 /* r4 = reboot_code_buffer */
810 /* r5 = start_address */
812 li r0, 0
814 /*
815 * Set Machine Status Register to a known status,
816 * switch the MMU off and jump to 1: in a single step.
817 */
819 mr r8, r0
820 ori r8, r8, MSR_RI|MSR_ME
821 mtspr SPRN_SRR1, r8
822 addi r8, r4, 1f - relocate_new_kernel
823 mtspr SPRN_SRR0, r8
824 sync
825 rfi
827 1:
828 /* from this point address translation is turned off */
829 /* and interrupts are disabled */
831 /* set a new stack at the bottom of our page... */
832 /* (not really needed now) */
833 addi r1, r4, KEXEC_CONTROL_CODE_SIZE - 8 /* for LR Save+Back Chain */
834 stw r0, 0(r1)
836 /* Do the copies */
837 li r6, 0 /* checksum */
838 mr r0, r3
839 b 1f
841 0: /* top, read another word for the indirection page */
842 lwzu r0, 4(r3)
844 1:
845 /* is it a destination page? (r8) */
846 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
847 beq 2f
849 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
850 b 0b
852 2: /* is it an indirection page? (r3) */
853 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
854 beq 2f
856 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
857 subi r3, r3, 4
858 b 0b
860 2: /* are we done? */
861 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
862 beq 2f
863 b 3f
865 2: /* is it a source page? (r9) */
866 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
867 beq 0b
869 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
871 li r7, PAGE_SIZE / 4
872 mtctr r7
873 subi r9, r9, 4
874 subi r8, r8, 4
875 9:
876 lwzu r0, 4(r9) /* do the copy */
877 xor r6, r6, r0
878 stwu r0, 4(r8)
879 dcbst 0, r8
880 sync
881 icbi 0, r8
882 bdnz 9b
884 addi r9, r9, 4
885 addi r8, r8, 4
886 b 0b
888 3:
890 /* To be certain of avoiding problems with self-modifying code
891 * execute a serializing instruction here.
892 */
893 isync
894 sync
896 /* jump to the entry point, usually the setup routine */
897 mtlr r5
898 blrl
900 1: b 1b
902 relocate_new_kernel_end:
904 .globl relocate_new_kernel_size
905 relocate_new_kernel_size:
906 .long relocate_new_kernel_end - relocate_new_kernel
907 #endif