2 * Sound driver for Silicon Graphics 320 and 540 Visual Workstations'
3 * onboard audio. See notes in Documentation/sound/oss/vwsnd .
5 * Copyright 1999 Silicon Graphics, Inc. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #undef VWSND_DEBUG /* define for debugging */
28 * Rename swbuf, hwbuf, u&i, hwptr&swptr to something rational.
29 * Bug - if select() called before read(), pcm_setup() not called.
30 * Bug - output doesn't stop soon enough if process killed.
36 * Will readv/writev work? Write a test.
38 * insmod/rmmod 100 million times.
40 * Run I/O until int ptrs wrap around (roughly 6.2 hours @ DAT
43 * Concurrent threads banging on mixer simultaneously, both UP
44 * and SMP kernels. Especially, watch for thread A changing
45 * OUTSRC while thread B changes gain -- both write to the same
48 * What happens if a client opens /dev/audio then forks?
49 * Do two procs have /dev/audio open? Test.
51 * Pump audio through the CD, MIC and line inputs and verify that
52 * they mix/mute into the output.
61 * need more input apps
63 * Run tests while bombarding with signals. setitimer(2) will do it... */
66 * This driver is organized in nine sections.
67 * The nine sections are:
70 * low level lithium access
71 * high level lithium access
77 * initialization and loadable kernel module interface
79 * That is roughly the order of increasing abstraction, so forward
80 * dependencies are minimal.
86 * INC_USE_COUNT and DEC_USE_COUNT keep track of the number of
87 * open descriptors to this driver. They store it in vwsnd_use_count.
88 * The global device list, vwsnd_dev_list, is immutable when the IN_USE
91 * devc->open_lock is a semaphore that is used to enforce the
92 * single reader/single writer rule for /dev/audio. The rule is
93 * that each device may have at most one reader and one writer.
94 * Open will block until the previous client has closed the
95 * device, unless O_NONBLOCK is specified.
97 * The semaphore devc->io_mutex serializes PCM I/O syscalls. This
98 * is unnecessary in Linux 2.2, because the kernel lock
99 * serializes read, write, and ioctl globally, but it's there,
100 * ready for the brave, new post-kernel-lock world.
102 * Locking between interrupt and baselevel is handled by the
103 * "lock" spinlock in vwsnd_port (one lock each for read and
104 * write). Each half holds the lock just long enough to see what
105 * area it owns and update its pointers. See pcm_output() and
106 * pcm_input() for most of the gory stuff.
108 * devc->mix_mutex serializes all mixer ioctls. This is also
109 * redundant because of the kernel lock.
111 * The lowest level lock is lith->lithium_lock. It is a
112 * spinlock which is held during the two-register tango of
113 * reading/writing an AD1843 register. See
114 * li_{read,write}_ad1843_reg().
118 * Sample Format Notes
120 * Lithium's DMA engine has two formats: 16-bit 2's complement
121 * and 8-bit unsigned . 16-bit transfers the data unmodified, 2
122 * bytes per sample. 8-bit unsigned transfers 1 byte per sample
123 * and XORs each byte with 0x80. Lithium can input or output
124 * either mono or stereo in either format.
126 * The AD1843 has four formats: 16-bit 2's complement, 8-bit
127 * unsigned, 8-bit mu-Law and 8-bit A-Law.
129 * This driver supports five formats: AFMT_S8, AFMT_U8,
130 * AFMT_MU_LAW, AFMT_A_LAW, and AFMT_S16_LE.
132 * For AFMT_U8 output, we keep the AD1843 in 16-bit mode, and
133 * rely on Lithium's XOR to translate between U8 and S8.
135 * For AFMT_S8, AFMT_MU_LAW and AFMT_A_LAW output, we have to XOR
136 * the 0x80 bit in software to compensate for Lithium's XOR.
137 * This happens in pcm_copy_{in,out}().
140 * 11-10-2000 Bartlomiej Zolnierkiewicz <bkz@linux-ide.org>
141 * Added some __init/__exit
144 #include <linux/module.h>
145 #include <linux/init.h>
147 #include <linux/spinlock.h>
148 #include <linux/smp_lock.h>
149 #include <linux/wait.h>
150 #include <linux/interrupt.h>
151 #include <linux/mutex.h>
153 #include <asm/mach-visws/cobalt.h>
155 #include "sound_config.h"
157 /*****************************************************************************/
162 static int shut_up
= 1;
165 * dbgassert - called when an assertion fails.
168 static void dbgassert(const char *fcn
, int line
, const char *expr
)
171 panic("ASSERTION FAILED IN INTERRUPT, %s:%s:%d %s\n",
172 __FILE__
, fcn
, line
, expr
);
175 printk(KERN_ERR
"ASSERTION FAILED, %s:%s:%d %s\n",
176 __FILE__
, fcn
, line
, expr
);
177 x
= * (volatile int *) 0; /* force proc to exit */
182 * Bunch of useful debug macros:
184 * ASSERT - print unless e nonzero (panic if in interrupt)
185 * DBGDO - include arbitrary code if debugging
186 * DBGX - debug print raw (w/o function name)
187 * DBGP - debug print w/ function name
188 * DBGE - debug print function entry
189 * DBGC - debug print function call
190 * DBGR - debug print function return
191 * DBGXV - debug print raw when verbose
192 * DBGPV - debug print when verbose
193 * DBGEV - debug print function entry when verbose
194 * DBGRV - debug print function return when verbose
197 #define ASSERT(e) ((e) ? (void) 0 : dbgassert(__FUNCTION__, __LINE__, #e))
199 #define DBGX(fmt, args...) (in_interrupt() ? 0 : printk(KERN_ERR fmt, ##args))
200 #define DBGP(fmt, args...) (DBGX("%s: " fmt, __FUNCTION__ , ##args))
201 #define DBGE(fmt, args...) (DBGX("%s" fmt, __FUNCTION__ , ##args))
202 #define DBGC(rtn) (DBGP("calling %s\n", rtn))
203 #define DBGR() (DBGP("returning\n"))
204 #define DBGXV(fmt, args...) (shut_up ? 0 : DBGX(fmt, ##args))
205 #define DBGPV(fmt, args...) (shut_up ? 0 : DBGP(fmt, ##args))
206 #define DBGEV(fmt, args...) (shut_up ? 0 : DBGE(fmt, ##args))
207 #define DBGCV(rtn) (shut_up ? 0 : DBGC(rtn))
208 #define DBGRV() (shut_up ? 0 : DBGR())
210 #else /* !VWSND_DEBUG */
212 #define ASSERT(e) ((void) 0)
213 #define DBGDO(x) /* don't */
214 #define DBGX(fmt, args...) ((void) 0)
215 #define DBGP(fmt, args...) ((void) 0)
216 #define DBGE(fmt, args...) ((void) 0)
217 #define DBGC(rtn) ((void) 0)
218 #define DBGR() ((void) 0)
219 #define DBGPV(fmt, args...) ((void) 0)
220 #define DBGXV(fmt, args...) ((void) 0)
221 #define DBGEV(fmt, args...) ((void) 0)
222 #define DBGCV(rtn) ((void) 0)
223 #define DBGRV() ((void) 0)
225 #endif /* !VWSND_DEBUG */
227 /*****************************************************************************/
228 /* low level lithium access */
231 * We need to talk to Lithium registers on three pages. Here are
232 * the pages' offsets from the base address (0xFF001000).
236 LI_PAGE0_OFFSET
= 0x01000 - 0x1000, /* FF001000 */
237 LI_PAGE1_OFFSET
= 0x0F000 - 0x1000, /* FF00F000 */
238 LI_PAGE2_OFFSET
= 0x10000 - 0x1000, /* FF010000 */
241 /* low-level lithium data */
243 typedef struct lithium
{
244 void * page0
; /* virtual addresses */
247 spinlock_t lock
; /* protects codec and UST/MSC access */
251 * li_create initializes the lithium_t structure and sets up vm mappings
252 * to access the registers.
253 * Returns 0 on success, -errno on failure.
256 static int __init
li_create(lithium_t
*lith
, unsigned long baseaddr
)
258 static void li_destroy(lithium_t
*);
260 spin_lock_init(&lith
->lock
);
261 lith
->page0
= ioremap_nocache(baseaddr
+ LI_PAGE0_OFFSET
, PAGE_SIZE
);
262 lith
->page1
= ioremap_nocache(baseaddr
+ LI_PAGE1_OFFSET
, PAGE_SIZE
);
263 lith
->page2
= ioremap_nocache(baseaddr
+ LI_PAGE2_OFFSET
, PAGE_SIZE
);
264 if (!lith
->page0
|| !lith
->page1
|| !lith
->page2
) {
272 * li_destroy destroys the lithium_t structure and vm mappings.
275 static void li_destroy(lithium_t
*lith
)
278 iounmap(lith
->page0
);
282 iounmap(lith
->page1
);
286 iounmap(lith
->page2
);
292 * basic register accessors - read/write long/byte
295 static __inline__
unsigned long li_readl(lithium_t
*lith
, int off
)
297 return * (volatile unsigned long *) (lith
->page0
+ off
);
300 static __inline__
unsigned char li_readb(lithium_t
*lith
, int off
)
302 return * (volatile unsigned char *) (lith
->page0
+ off
);
305 static __inline__
void li_writel(lithium_t
*lith
, int off
, unsigned long val
)
307 * (volatile unsigned long *) (lith
->page0
+ off
) = val
;
310 static __inline__
void li_writeb(lithium_t
*lith
, int off
, unsigned char val
)
312 * (volatile unsigned char *) (lith
->page0
+ off
) = val
;
315 /*****************************************************************************/
316 /* High Level Lithium Access */
321 * Lithium has two dedicated DMA channels for audio. They are known
322 * as comm1 and comm2 (communication areas 1 and 2). Comm1 is for
323 * input, and comm2 is for output. Each is controlled by three
324 * registers: BASE (base address), CFG (config) and CCTL
327 * Each DMA channel points to a physically contiguous ring buffer in
328 * main memory of up to 8 Kbytes. (This driver always uses 8 Kb.)
329 * There are three pointers into the ring buffer: read, write, and
330 * trigger. The pointers are 8 bits each. Each pointer points to
331 * 32-byte "chunks" of data. The DMA engine moves 32 bytes at a time,
332 * so there is no finer-granularity control.
334 * In comm1, the hardware updates the write ptr, and software updates
335 * the read ptr. In comm2, it's the opposite: hardware updates the
336 * read ptr, and software updates the write ptr. I designate the
337 * hardware-updated ptr as the hwptr, and the software-updated ptr as
340 * The trigger ptr and trigger mask are used to trigger interrupts.
341 * From the Lithium spec, section 5.6.8, revision of 12/15/1998:
345 * A three bit wide field that represents a power of two mask
346 * that is used whenever the trigger pointer is compared to its
347 * respective read or write pointer. A value of zero here
348 * implies a mask of 0xFF and a value of seven implies a mask
349 * 0x01. This value can be used to sub-divide the ring buffer
350 * into pie sections so that interrupts monitor the progress of
351 * hardware from section to section.
353 * My interpretation of that is, whenever the hw ptr is updated, it is
354 * compared with the trigger ptr, and the result is masked by the
355 * trigger mask. (Actually, by the complement of the trigger mask.)
356 * If the result is zero, an interrupt is triggered. I.e., interrupt
357 * if ((hwptr & ~mask) == (trptr & ~mask)). The mask is formed from
358 * the trigger register value as mask = (1 << (8 - tmreg)) - 1.
360 * In yet different words, setting tmreg to 0 causes an interrupt after
361 * every 256 DMA chunks (8192 bytes) or once per traversal of the
362 * ring buffer. Setting it to 7 caues an interrupt every 2 DMA chunks
363 * (64 bytes) or 128 times per traversal of the ring buffer.
366 /* Lithium register offsets and bit definitions */
368 #define LI_HOST_CONTROLLER 0x000
369 # define LI_HC_RESET 0x00008000
370 # define LI_HC_LINK_ENABLE 0x00004000
371 # define LI_HC_LINK_FAILURE 0x00000004
372 # define LI_HC_LINK_CODEC 0x00000002
373 # define LI_HC_LINK_READY 0x00000001
375 #define LI_INTR_STATUS 0x010
376 #define LI_INTR_MASK 0x014
377 # define LI_INTR_LINK_ERR 0x00008000
378 # define LI_INTR_COMM2_TRIG 0x00000008
379 # define LI_INTR_COMM2_UNDERFLOW 0x00000004
380 # define LI_INTR_COMM1_TRIG 0x00000002
381 # define LI_INTR_COMM1_OVERFLOW 0x00000001
383 #define LI_CODEC_COMMAND 0x018
384 # define LI_CC_BUSY 0x00008000
385 # define LI_CC_DIR 0x00000080
386 # define LI_CC_DIR_RD LI_CC_DIR
387 # define LI_CC_DIR_WR (!LI_CC_DIR)
388 # define LI_CC_ADDR_MASK 0x0000007F
390 #define LI_CODEC_DATA 0x01C
392 #define LI_COMM1_BASE 0x100
393 #define LI_COMM1_CTL 0x104
394 # define LI_CCTL_RESET 0x80000000
395 # define LI_CCTL_SIZE 0x70000000
396 # define LI_CCTL_DMA_ENABLE 0x08000000
397 # define LI_CCTL_TMASK 0x07000000 /* trigger mask */
398 # define LI_CCTL_TPTR 0x00FF0000 /* trigger pointer */
399 # define LI_CCTL_RPTR 0x0000FF00
400 # define LI_CCTL_WPTR 0x000000FF
401 #define LI_COMM1_CFG 0x108
402 # define LI_CCFG_LOCK 0x00008000
403 # define LI_CCFG_SLOT 0x00000070
404 # define LI_CCFG_DIRECTION 0x00000008
405 # define LI_CCFG_DIR_IN (!LI_CCFG_DIRECTION)
406 # define LI_CCFG_DIR_OUT LI_CCFG_DIRECTION
407 # define LI_CCFG_MODE 0x00000004
408 # define LI_CCFG_MODE_MONO (!LI_CCFG_MODE)
409 # define LI_CCFG_MODE_STEREO LI_CCFG_MODE
410 # define LI_CCFG_FORMAT 0x00000003
411 # define LI_CCFG_FMT_8BIT 0x00000000
412 # define LI_CCFG_FMT_16BIT 0x00000001
413 #define LI_COMM2_BASE 0x10C
414 #define LI_COMM2_CTL 0x110
415 /* bit definitions are the same as LI_COMM1_CTL */
416 #define LI_COMM2_CFG 0x114
417 /* bit definitions are the same as LI_COMM1_CFG */
419 #define LI_UST_LOW 0x200 /* 64-bit Unadjusted System Time is */
420 #define LI_UST_HIGH 0x204 /* microseconds since boot */
422 #define LI_AUDIO1_UST 0x300 /* UST-MSC pairs */
423 #define LI_AUDIO1_MSC 0x304 /* MSC (Media Stream Counter) */
424 #define LI_AUDIO2_UST 0x308 /* counts samples actually */
425 #define LI_AUDIO2_MSC 0x30C /* processed as of time UST */
428 * Lithium's DMA engine operates on chunks of 32 bytes. We call that
432 #define DMACHUNK_SHIFT 5
433 #define DMACHUNK_SIZE (1 << DMACHUNK_SHIFT)
434 #define BYTES_TO_CHUNKS(bytes) ((bytes) >> DMACHUNK_SHIFT)
435 #define CHUNKS_TO_BYTES(chunks) ((chunks) << DMACHUNK_SHIFT)
438 * Two convenient macros to shift bitfields into/out of position.
440 * Observe that (mask & -mask) is (1 << low_set_bit_of(mask)).
441 * As long as mask is constant, we trust the compiler will change the
442 * multipy and divide into shifts.
445 #define SHIFT_FIELD(val, mask) (((val) * ((mask) & -(mask))) & (mask))
446 #define UNSHIFT_FIELD(val, mask) (((val) & (mask)) / ((mask) & -(mask)))
449 * dma_chan_desc is invariant information about a Lithium
450 * DMA channel. There are two instances, li_comm1 and li_comm2.
452 * Note that the CCTL register fields are write ptr and read ptr, but what
453 * we care about are which pointer is updated by software and which by
457 typedef struct dma_chan_desc
{
465 unsigned long swptrmask
;
467 int direction
; /* LI_CCTL_DIR_IN/OUT */
470 static const dma_chan_desc_t li_comm1
= {
471 LI_COMM1_BASE
, /* base register offset */
472 LI_COMM1_CFG
, /* config register offset */
473 LI_COMM1_CTL
, /* control register offset */
474 LI_COMM1_CTL
+ 0, /* hw ptr reg offset (write ptr) */
475 LI_COMM1_CTL
+ 1, /* sw ptr reg offset (read ptr) */
476 LI_AUDIO1_UST
, /* ust reg offset */
477 LI_AUDIO1_MSC
, /* msc reg offset */
478 LI_CCTL_RPTR
, /* sw ptr bitmask in ctlval */
479 2, /* ad1843 serial slot */
480 LI_CCFG_DIR_IN
/* direction */
483 static const dma_chan_desc_t li_comm2
= {
484 LI_COMM2_BASE
, /* base register offset */
485 LI_COMM2_CFG
, /* config register offset */
486 LI_COMM2_CTL
, /* control register offset */
487 LI_COMM2_CTL
+ 1, /* hw ptr reg offset (read ptr) */
488 LI_COMM2_CTL
+ 0, /* sw ptr reg offset (writr ptr) */
489 LI_AUDIO2_UST
, /* ust reg offset */
490 LI_AUDIO2_MSC
, /* msc reg offset */
491 LI_CCTL_WPTR
, /* sw ptr bitmask in ctlval */
492 2, /* ad1843 serial slot */
493 LI_CCFG_DIR_OUT
/* direction */
497 * dma_chan is variable information about a Lithium DMA channel.
499 * The desc field points to invariant information.
500 * The lith field points to a lithium_t which is passed
501 * to li_read* and li_write* to access the registers.
502 * The *val fields shadow the lithium registers' contents.
505 typedef struct dma_chan
{
506 const dma_chan_desc_t
*desc
;
508 unsigned long baseval
;
509 unsigned long cfgval
;
510 unsigned long ctlval
;
514 * ustmsc is a UST/MSC pair (Unadjusted System Time/Media Stream Counter).
515 * UST is time in microseconds since the system booted, and MSC is a
516 * counter that increments with every audio sample.
519 typedef struct ustmsc
{
520 unsigned long long ust
;
525 * li_ad1843_wait waits until lithium says the AD1843 register
526 * exchange is not busy. Returns 0 on success, -EBUSY on timeout.
528 * Locking: must be called with lithium_lock held.
531 static int li_ad1843_wait(lithium_t
*lith
)
533 unsigned long later
= jiffies
+ 2;
534 while (li_readl(lith
, LI_CODEC_COMMAND
) & LI_CC_BUSY
)
535 if (time_after_eq(jiffies
, later
))
541 * li_read_ad1843_reg returns the current contents of a 16 bit AD1843 register.
543 * Returns unsigned register value on success, -errno on failure.
546 static int li_read_ad1843_reg(lithium_t
*lith
, int reg
)
550 ASSERT(!in_interrupt());
551 spin_lock(&lith
->lock
);
553 val
= li_ad1843_wait(lith
);
555 li_writel(lith
, LI_CODEC_COMMAND
, LI_CC_DIR_RD
| reg
);
556 val
= li_ad1843_wait(lith
);
559 val
= li_readl(lith
, LI_CODEC_DATA
);
561 spin_unlock(&lith
->lock
);
563 DBGXV("li_read_ad1843_reg(lith=0x%p, reg=%d) returns 0x%04x\n",
570 * li_write_ad1843_reg writes the specified value to a 16 bit AD1843 register.
573 static void li_write_ad1843_reg(lithium_t
*lith
, int reg
, int newval
)
575 spin_lock(&lith
->lock
);
577 if (li_ad1843_wait(lith
) == 0) {
578 li_writel(lith
, LI_CODEC_DATA
, newval
);
579 li_writel(lith
, LI_CODEC_COMMAND
, LI_CC_DIR_WR
| reg
);
582 spin_unlock(&lith
->lock
);
586 * li_setup_dma calculates all the register settings for DMA in a particular
587 * mode. It takes too many arguments.
590 static void li_setup_dma(dma_chan_t
*chan
,
591 const dma_chan_desc_t
*desc
,
593 unsigned long buffer_paddr
,
599 unsigned long mode
, format
;
600 unsigned long size
, tmask
;
602 DBGEV("(chan=0x%p, desc=0x%p, lith=0x%p, buffer_paddr=0x%lx, "
603 "bufshift=%d, fragshift=%d, channels=%d, sampsize=%d)\n",
604 chan
, desc
, lith
, buffer_paddr
,
605 bufshift
, fragshift
, channels
, sampsize
);
607 /* Reset the channel first. */
609 li_writel(lith
, desc
->ctlreg
, LI_CCTL_RESET
);
611 ASSERT(channels
== 1 || channels
== 2);
613 mode
= LI_CCFG_MODE_STEREO
;
615 mode
= LI_CCFG_MODE_MONO
;
616 ASSERT(sampsize
== 1 || sampsize
== 2);
618 format
= LI_CCFG_FMT_16BIT
;
620 format
= LI_CCFG_FMT_8BIT
;
625 * Lithium DMA address register takes a 40-bit physical
626 * address, right-shifted by 8 so it fits in 32 bits. Bit 37
627 * must be set -- it enables cache coherence.
630 ASSERT(!(buffer_paddr
& 0xFF));
631 chan
->baseval
= (buffer_paddr
>> 8) | 1 << (37 - 8);
633 chan
->cfgval
= (!LI_CCFG_LOCK
|
634 SHIFT_FIELD(desc
->ad1843_slot
, LI_CCFG_SLOT
) |
640 tmask
= 13 - fragshift
; /* See Lithium DMA Notes above. */
641 ASSERT(size
>= 2 && size
<= 7);
642 ASSERT(tmask
>= 1 && tmask
<= 7);
643 chan
->ctlval
= (!LI_CCTL_RESET
|
644 SHIFT_FIELD(size
, LI_CCTL_SIZE
) |
645 !LI_CCTL_DMA_ENABLE
|
646 SHIFT_FIELD(tmask
, LI_CCTL_TMASK
) |
647 SHIFT_FIELD(0, LI_CCTL_TPTR
));
649 DBGPV("basereg 0x%x = 0x%lx\n", desc
->basereg
, chan
->baseval
);
650 DBGPV("cfgreg 0x%x = 0x%lx\n", desc
->cfgreg
, chan
->cfgval
);
651 DBGPV("ctlreg 0x%x = 0x%lx\n", desc
->ctlreg
, chan
->ctlval
);
653 li_writel(lith
, desc
->basereg
, chan
->baseval
);
654 li_writel(lith
, desc
->cfgreg
, chan
->cfgval
);
655 li_writel(lith
, desc
->ctlreg
, chan
->ctlval
);
660 static void li_shutdown_dma(dma_chan_t
*chan
)
662 lithium_t
*lith
= chan
->lith
;
663 void * lith1
= lith
->page1
;
665 DBGEV("(chan=0x%p)\n", chan
);
667 chan
->ctlval
&= ~LI_CCTL_DMA_ENABLE
;
668 DBGPV("ctlreg 0x%x = 0x%lx\n", chan
->desc
->ctlreg
, chan
->ctlval
);
669 li_writel(lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
672 * Offset 0x500 on Lithium page 1 is an undocumented,
673 * unsupported register that holds the zero sample value.
674 * Lithium is supposed to output zero samples when DMA is
675 * inactive, and repeat the last sample when DMA underflows.
676 * But it has a bug, where, after underflow occurs, the zero
677 * sample is not reset.
679 * I expect this to break in a future rev of Lithium.
682 if (lith1
&& chan
->desc
->direction
== LI_CCFG_DIR_OUT
)
683 * (volatile unsigned long *) (lith1
+ 0x500) = 0;
687 * li_activate_dma always starts dma at the beginning of the buffer.
689 * N.B., these may be called from interrupt.
692 static __inline__
void li_activate_dma(dma_chan_t
*chan
)
694 chan
->ctlval
|= LI_CCTL_DMA_ENABLE
;
695 DBGPV("ctlval = 0x%lx\n", chan
->ctlval
);
696 li_writel(chan
->lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
699 static void li_deactivate_dma(dma_chan_t
*chan
)
701 lithium_t
*lith
= chan
->lith
;
702 void * lith2
= lith
->page2
;
704 chan
->ctlval
&= ~(LI_CCTL_DMA_ENABLE
| LI_CCTL_RPTR
| LI_CCTL_WPTR
);
705 DBGPV("ctlval = 0x%lx\n", chan
->ctlval
);
706 DBGPV("ctlreg 0x%x = 0x%lx\n", chan
->desc
->ctlreg
, chan
->ctlval
);
707 li_writel(lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
710 * Offsets 0x98 and 0x9C on Lithium page 2 are undocumented,
711 * unsupported registers that are internal copies of the DMA
712 * read and write pointers. Because of a Lithium bug, these
713 * registers aren't zeroed correctly when DMA is shut off. So
714 * we whack them directly.
716 * I expect this to break in a future rev of Lithium.
719 if (lith2
&& chan
->desc
->direction
== LI_CCFG_DIR_OUT
) {
720 * (volatile unsigned long *) (lith2
+ 0x98) = 0;
721 * (volatile unsigned long *) (lith2
+ 0x9C) = 0;
726 * read/write the ring buffer pointers. These routines' arguments and results
727 * are byte offsets from the beginning of the ring buffer.
730 static __inline__
int li_read_swptr(dma_chan_t
*chan
)
732 const unsigned long mask
= chan
->desc
->swptrmask
;
734 return CHUNKS_TO_BYTES(UNSHIFT_FIELD(chan
->ctlval
, mask
));
737 static __inline__
int li_read_hwptr(dma_chan_t
*chan
)
739 return CHUNKS_TO_BYTES(li_readb(chan
->lith
, chan
->desc
->hwptrreg
));
742 static __inline__
void li_write_swptr(dma_chan_t
*chan
, int val
)
744 const unsigned long mask
= chan
->desc
->swptrmask
;
746 ASSERT(!(val
& ~CHUNKS_TO_BYTES(0xFF)));
747 val
= BYTES_TO_CHUNKS(val
);
748 chan
->ctlval
= (chan
->ctlval
& ~mask
) | SHIFT_FIELD(val
, mask
);
749 li_writeb(chan
->lith
, chan
->desc
->swptrreg
, val
);
752 /* li_read_USTMSC() returns a UST/MSC pair for the given channel. */
754 static void li_read_USTMSC(dma_chan_t
*chan
, ustmsc_t
*ustmsc
)
756 lithium_t
*lith
= chan
->lith
;
757 const dma_chan_desc_t
*desc
= chan
->desc
;
758 unsigned long now_low
, now_high0
, now_high1
, chan_ust
;
760 spin_lock(&lith
->lock
);
763 * retry until we do all five reads without the
764 * high word changing. (High word increments
765 * every 2^32 microseconds, i.e., not often)
768 now_high0
= li_readl(lith
, LI_UST_HIGH
);
769 now_low
= li_readl(lith
, LI_UST_LOW
);
772 * Lithium guarantees these two reads will be
773 * atomic -- ust will not increment after msc
777 ustmsc
->msc
= li_readl(lith
, desc
->mscreg
);
778 chan_ust
= li_readl(lith
, desc
->ustreg
);
780 now_high1
= li_readl(lith
, LI_UST_HIGH
);
781 } while (now_high0
!= now_high1
);
783 spin_unlock(&lith
->lock
);
784 ustmsc
->ust
= ((unsigned long long) now_high0
<< 32 | chan_ust
);
787 static void li_enable_interrupts(lithium_t
*lith
, unsigned int mask
)
789 DBGEV("(lith=0x%p, mask=0x%x)\n", lith
, mask
);
791 /* clear any already-pending interrupts. */
793 li_writel(lith
, LI_INTR_STATUS
, mask
);
795 /* enable the interrupts. */
797 mask
|= li_readl(lith
, LI_INTR_MASK
);
798 li_writel(lith
, LI_INTR_MASK
, mask
);
801 static void li_disable_interrupts(lithium_t
*lith
, unsigned int mask
)
803 unsigned int keepmask
;
805 DBGEV("(lith=0x%p, mask=0x%x)\n", lith
, mask
);
807 /* disable the interrupts */
809 keepmask
= li_readl(lith
, LI_INTR_MASK
) & ~mask
;
810 li_writel(lith
, LI_INTR_MASK
, keepmask
);
812 /* clear any pending interrupts. */
814 li_writel(lith
, LI_INTR_STATUS
, mask
);
817 /* Get the interrupt status and clear all pending interrupts. */
819 static unsigned int li_get_clear_intr_status(lithium_t
*lith
)
823 status
= li_readl(lith
, LI_INTR_STATUS
);
824 li_writel(lith
, LI_INTR_STATUS
, ~0);
825 return status
& li_readl(lith
, LI_INTR_MASK
);
828 static int li_init(lithium_t
*lith
)
830 /* 1. System power supplies stabilize. */
832 /* 2. Assert the ~RESET signal. */
834 li_writel(lith
, LI_HOST_CONTROLLER
, LI_HC_RESET
);
837 /* 3. Deassert the ~RESET signal and enter a wait period to allow
838 the AD1843 internal clocks and the external crystal oscillator
841 li_writel(lith
, LI_HOST_CONTROLLER
, LI_HC_LINK_ENABLE
);
847 /*****************************************************************************/
851 * AD1843 bitfield definitions. All are named as in the AD1843 data
852 * sheet, with ad1843_ prepended and individual bit numbers removed.
854 * E.g., bits LSS0 through LSS2 become ad1843_LSS.
856 * Only the bitfields we need are defined.
859 typedef struct ad1843_bitfield
{
865 static const ad1843_bitfield_t
866 ad1843_PDNO
= { 0, 14, 1 }, /* Converter Power-Down Flag */
867 ad1843_INIT
= { 0, 15, 1 }, /* Clock Initialization Flag */
868 ad1843_RIG
= { 2, 0, 4 }, /* Right ADC Input Gain */
869 ad1843_RMGE
= { 2, 4, 1 }, /* Right ADC Mic Gain Enable */
870 ad1843_RSS
= { 2, 5, 3 }, /* Right ADC Source Select */
871 ad1843_LIG
= { 2, 8, 4 }, /* Left ADC Input Gain */
872 ad1843_LMGE
= { 2, 12, 1 }, /* Left ADC Mic Gain Enable */
873 ad1843_LSS
= { 2, 13, 3 }, /* Left ADC Source Select */
874 ad1843_RX1M
= { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */
875 ad1843_RX1MM
= { 4, 7, 1 }, /* Right Aux 1 Mix Mute */
876 ad1843_LX1M
= { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */
877 ad1843_LX1MM
= { 4, 15, 1 }, /* Left Aux 1 Mix Mute */
878 ad1843_RX2M
= { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */
879 ad1843_RX2MM
= { 5, 7, 1 }, /* Right Aux 2 Mix Mute */
880 ad1843_LX2M
= { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */
881 ad1843_LX2MM
= { 5, 15, 1 }, /* Left Aux 2 Mix Mute */
882 ad1843_RMCM
= { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */
883 ad1843_RMCMM
= { 7, 7, 1 }, /* Right Mic Mix Mute */
884 ad1843_LMCM
= { 7, 8, 5 }, /* Left Mic Mix Gain/Atten */
885 ad1843_LMCMM
= { 7, 15, 1 }, /* Left Mic Mix Mute */
886 ad1843_HPOS
= { 8, 4, 1 }, /* Headphone Output Voltage Swing */
887 ad1843_HPOM
= { 8, 5, 1 }, /* Headphone Output Mute */
888 ad1843_RDA1G
= { 9, 0, 6 }, /* Right DAC1 Analog/Digital Gain */
889 ad1843_RDA1GM
= { 9, 7, 1 }, /* Right DAC1 Analog Mute */
890 ad1843_LDA1G
= { 9, 8, 6 }, /* Left DAC1 Analog/Digital Gain */
891 ad1843_LDA1GM
= { 9, 15, 1 }, /* Left DAC1 Analog Mute */
892 ad1843_RDA1AM
= { 11, 7, 1 }, /* Right DAC1 Digital Mute */
893 ad1843_LDA1AM
= { 11, 15, 1 }, /* Left DAC1 Digital Mute */
894 ad1843_ADLC
= { 15, 0, 2 }, /* ADC Left Sample Rate Source */
895 ad1843_ADRC
= { 15, 2, 2 }, /* ADC Right Sample Rate Source */
896 ad1843_DA1C
= { 15, 8, 2 }, /* DAC1 Sample Rate Source */
897 ad1843_C1C
= { 17, 0, 16 }, /* Clock 1 Sample Rate Select */
898 ad1843_C2C
= { 20, 0, 16 }, /* Clock 1 Sample Rate Select */
899 ad1843_DAADL
= { 25, 4, 2 }, /* Digital ADC Left Source Select */
900 ad1843_DAADR
= { 25, 6, 2 }, /* Digital ADC Right Source Select */
901 ad1843_DRSFLT
= { 25, 15, 1 }, /* Digital Reampler Filter Mode */
902 ad1843_ADLF
= { 26, 0, 2 }, /* ADC Left Channel Data Format */
903 ad1843_ADRF
= { 26, 2, 2 }, /* ADC Right Channel Data Format */
904 ad1843_ADTLK
= { 26, 4, 1 }, /* ADC Transmit Lock Mode Select */
905 ad1843_SCF
= { 26, 7, 1 }, /* SCLK Frequency Select */
906 ad1843_DA1F
= { 26, 8, 2 }, /* DAC1 Data Format Select */
907 ad1843_DA1SM
= { 26, 14, 1 }, /* DAC1 Stereo/Mono Mode Select */
908 ad1843_ADLEN
= { 27, 0, 1 }, /* ADC Left Channel Enable */
909 ad1843_ADREN
= { 27, 1, 1 }, /* ADC Right Channel Enable */
910 ad1843_AAMEN
= { 27, 4, 1 }, /* Analog to Analog Mix Enable */
911 ad1843_ANAEN
= { 27, 7, 1 }, /* Analog Channel Enable */
912 ad1843_DA1EN
= { 27, 8, 1 }, /* DAC1 Enable */
913 ad1843_DA2EN
= { 27, 9, 1 }, /* DAC2 Enable */
914 ad1843_C1EN
= { 28, 11, 1 }, /* Clock Generator 1 Enable */
915 ad1843_C2EN
= { 28, 12, 1 }, /* Clock Generator 2 Enable */
916 ad1843_PDNI
= { 28, 15, 1 }; /* Converter Power Down */
919 * The various registers of the AD1843 use three different formats for
920 * specifying gain. The ad1843_gain structure parameterizes the
924 typedef struct ad1843_gain
{
926 int negative
; /* nonzero if gain is negative. */
927 const ad1843_bitfield_t
*lfield
;
928 const ad1843_bitfield_t
*rfield
;
932 static const ad1843_gain_t ad1843_gain_RECLEV
933 = { 0, &ad1843_LIG
, &ad1843_RIG
};
934 static const ad1843_gain_t ad1843_gain_LINE
935 = { 1, &ad1843_LX1M
, &ad1843_RX1M
};
936 static const ad1843_gain_t ad1843_gain_CD
937 = { 1, &ad1843_LX2M
, &ad1843_RX2M
};
938 static const ad1843_gain_t ad1843_gain_MIC
939 = { 1, &ad1843_LMCM
, &ad1843_RMCM
};
940 static const ad1843_gain_t ad1843_gain_PCM
941 = { 1, &ad1843_LDA1G
, &ad1843_RDA1G
};
943 /* read the current value of an AD1843 bitfield. */
945 static int ad1843_read_bits(lithium_t
*lith
, const ad1843_bitfield_t
*field
)
947 int w
= li_read_ad1843_reg(lith
, field
->reg
);
948 int val
= w
>> field
->lo_bit
& ((1 << field
->nbits
) - 1);
950 DBGXV("ad1843_read_bits(lith=0x%p, field->{%d %d %d}) returns 0x%x\n",
951 lith
, field
->reg
, field
->lo_bit
, field
->nbits
, val
);
957 * write a new value to an AD1843 bitfield and return the old value.
960 static int ad1843_write_bits(lithium_t
*lith
,
961 const ad1843_bitfield_t
*field
,
964 int w
= li_read_ad1843_reg(lith
, field
->reg
);
965 int mask
= ((1 << field
->nbits
) - 1) << field
->lo_bit
;
966 int oldval
= (w
& mask
) >> field
->lo_bit
;
967 int newbits
= (newval
<< field
->lo_bit
) & mask
;
968 w
= (w
& ~mask
) | newbits
;
969 (void) li_write_ad1843_reg(lith
, field
->reg
, w
);
971 DBGXV("ad1843_write_bits(lith=0x%p, field->{%d %d %d}, val=0x%x) "
973 lith
, field
->reg
, field
->lo_bit
, field
->nbits
, newval
,
980 * ad1843_read_multi reads multiple bitfields from the same AD1843
981 * register. It uses a single read cycle to do it. (Reading the
982 * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20
987 * ad1843_read_multi(lith, nfields,
988 * &ad1843_FIELD1, &val1,
989 * &ad1843_FIELD2, &val2, ...);
992 static void ad1843_read_multi(lithium_t
*lith
, int argcount
, ...)
995 const ad1843_bitfield_t
*fp
;
996 int w
= 0, mask
, *value
, reg
= -1;
998 va_start(ap
, argcount
);
999 while (--argcount
>= 0) {
1000 fp
= va_arg(ap
, const ad1843_bitfield_t
*);
1001 value
= va_arg(ap
, int *);
1004 w
= li_read_ad1843_reg(lith
, reg
);
1006 ASSERT(reg
== fp
->reg
);
1007 mask
= (1 << fp
->nbits
) - 1;
1008 *value
= w
>> fp
->lo_bit
& mask
;
1014 * ad1843_write_multi stores multiple bitfields into the same AD1843
1015 * register. It uses one read and one write cycle to do it.
1019 * ad1843_write_multi(lith, nfields,
1020 * &ad1843_FIELD1, val1,
1021 * &ad1843_FIELF2, val2, ...);
1024 static void ad1843_write_multi(lithium_t
*lith
, int argcount
, ...)
1028 const ad1843_bitfield_t
*fp
;
1030 int w
, m
, mask
, bits
;
1036 va_start(ap
, argcount
);
1037 while (--argcount
>= 0) {
1038 fp
= va_arg(ap
, const ad1843_bitfield_t
*);
1039 value
= va_arg(ap
, int);
1042 ASSERT(fp
->reg
== reg
);
1043 m
= ((1 << fp
->nbits
) - 1) << fp
->lo_bit
;
1045 bits
|= (value
<< fp
->lo_bit
) & m
;
1048 ASSERT(!(bits
& ~mask
));
1050 w
= li_read_ad1843_reg(lith
, reg
);
1053 w
= (w
& ~mask
) | bits
;
1054 (void) li_write_ad1843_reg(lith
, reg
, w
);
1058 * ad1843_get_gain reads the specified register and extracts the gain value
1059 * using the supplied gain type. It returns the gain in OSS format.
1062 static int ad1843_get_gain(lithium_t
*lith
, const ad1843_gain_t
*gp
)
1065 unsigned short mask
= (1 << gp
->lfield
->nbits
) - 1;
1067 ad1843_read_multi(lith
, 2, gp
->lfield
, &lg
, gp
->rfield
, &rg
);
1072 lg
= (lg
* 100 + (mask
>> 1)) / mask
;
1073 rg
= (rg
* 100 + (mask
>> 1)) / mask
;
1074 return lg
<< 0 | rg
<< 8;
1078 * Set an audio channel's gain. Converts from OSS format to AD1843's
1081 * Returns the new gain, which may be lower than the old gain.
1084 static int ad1843_set_gain(lithium_t
*lith
,
1085 const ad1843_gain_t
*gp
,
1088 unsigned short mask
= (1 << gp
->lfield
->nbits
) - 1;
1090 int lg
= newval
>> 0 & 0xFF;
1091 int rg
= newval
>> 8;
1092 if (lg
< 0 || lg
> 100 || rg
< 0 || rg
> 100)
1094 lg
= (lg
* mask
+ (mask
>> 1)) / 100;
1095 rg
= (rg
* mask
+ (mask
>> 1)) / 100;
1100 ad1843_write_multi(lith
, 2, gp
->lfield
, lg
, gp
->rfield
, rg
);
1101 return ad1843_get_gain(lith
, gp
);
1104 /* Returns the current recording source, in OSS format. */
1106 static int ad1843_get_recsrc(lithium_t
*lith
)
1108 int ls
= ad1843_read_bits(lith
, &ad1843_LSS
);
1112 return SOUND_MASK_MIC
;
1114 return SOUND_MASK_LINE
;
1116 return SOUND_MASK_CD
;
1118 return SOUND_MASK_PCM
;
1126 * Enable/disable digital resample mode in the AD1843.
1128 * The AD1843 requires that ADL, ADR, DA1 and DA2 be powered down
1129 * while switching modes. So we save DA1's state (DA2's state is not
1130 * interesting), power them down, switch into/out of resample mode,
1131 * power them up, and restore state.
1133 * This will cause audible glitches if D/A or A/D is going on, so the
1134 * driver disallows that (in mixer_write_ioctl()).
1136 * The open question is, is this worth doing? I'm leaving it in,
1137 * because it's written, but...
1140 static void ad1843_set_resample_mode(lithium_t
*lith
, int onoff
)
1142 /* Save DA1 mute and gain (addr 9 is DA1 analog gain/attenuation) */
1143 int save_da1
= li_read_ad1843_reg(lith
, 9);
1145 /* Power down A/D and D/A. */
1146 ad1843_write_multi(lith
, 4,
1153 ASSERT(onoff
== 0 || onoff
== 1);
1154 ad1843_write_bits(lith
, &ad1843_DRSFLT
, onoff
);
1156 /* Power up A/D and D/A. */
1157 ad1843_write_multi(lith
, 3,
1162 /* Restore DA1 mute and gain. */
1163 li_write_ad1843_reg(lith
, 9, save_da1
);
1167 * Set recording source. Arg newsrc specifies an OSS channel mask.
1169 * The complication is that when we switch into/out of loopback mode
1170 * (i.e., src = SOUND_MASK_PCM), we change the AD1843 into/out of
1171 * digital resampling mode.
1173 * Returns newsrc on success, -errno on failure.
1176 static int ad1843_set_recsrc(lithium_t
*lith
, int newsrc
)
1182 case SOUND_MASK_PCM
:
1186 case SOUND_MASK_MIC
:
1190 case SOUND_MASK_LINE
:
1201 oldbits
= ad1843_read_bits(lith
, &ad1843_LSS
);
1202 if (newsrc
== SOUND_MASK_PCM
&& oldbits
!= 6) {
1203 DBGP("enabling digital resample mode\n");
1204 ad1843_set_resample_mode(lith
, 1);
1205 ad1843_write_multi(lith
, 2,
1208 } else if (newsrc
!= SOUND_MASK_PCM
&& oldbits
== 6) {
1209 DBGP("disabling digital resample mode\n");
1210 ad1843_set_resample_mode(lith
, 0);
1211 ad1843_write_multi(lith
, 2,
1215 ad1843_write_multi(lith
, 2, &ad1843_LSS
, bits
, &ad1843_RSS
, bits
);
1220 * Return current output sources, in OSS format.
1223 static int ad1843_get_outsrc(lithium_t
*lith
)
1225 int pcm
, line
, mic
, cd
;
1227 pcm
= ad1843_read_bits(lith
, &ad1843_LDA1GM
) ? 0 : SOUND_MASK_PCM
;
1228 line
= ad1843_read_bits(lith
, &ad1843_LX1MM
) ? 0 : SOUND_MASK_LINE
;
1229 cd
= ad1843_read_bits(lith
, &ad1843_LX2MM
) ? 0 : SOUND_MASK_CD
;
1230 mic
= ad1843_read_bits(lith
, &ad1843_LMCMM
) ? 0 : SOUND_MASK_MIC
;
1232 return pcm
| line
| cd
| mic
;
1236 * Set output sources. Arg is a mask of active sources in OSS format.
1238 * Returns source mask on success, -errno on failure.
1241 static int ad1843_set_outsrc(lithium_t
*lith
, int mask
)
1243 int pcm
, line
, mic
, cd
;
1245 if (mask
& ~(SOUND_MASK_PCM
| SOUND_MASK_LINE
|
1246 SOUND_MASK_CD
| SOUND_MASK_MIC
))
1248 pcm
= (mask
& SOUND_MASK_PCM
) ? 0 : 1;
1249 line
= (mask
& SOUND_MASK_LINE
) ? 0 : 1;
1250 mic
= (mask
& SOUND_MASK_MIC
) ? 0 : 1;
1251 cd
= (mask
& SOUND_MASK_CD
) ? 0 : 1;
1253 ad1843_write_multi(lith
, 2, &ad1843_LDA1GM
, pcm
, &ad1843_RDA1GM
, pcm
);
1254 ad1843_write_multi(lith
, 2, &ad1843_LX1MM
, line
, &ad1843_RX1MM
, line
);
1255 ad1843_write_multi(lith
, 2, &ad1843_LX2MM
, cd
, &ad1843_RX2MM
, cd
);
1256 ad1843_write_multi(lith
, 2, &ad1843_LMCMM
, mic
, &ad1843_RMCMM
, mic
);
1261 /* Setup ad1843 for D/A conversion. */
1263 static void ad1843_setup_dac(lithium_t
*lith
,
1268 int ad_fmt
= 0, ad_mode
= 0;
1270 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1271 lith
, framerate
, fmt
, channels
);
1274 case AFMT_S8
: ad_fmt
= 1; break;
1275 case AFMT_U8
: ad_fmt
= 1; break;
1276 case AFMT_S16_LE
: ad_fmt
= 1; break;
1277 case AFMT_MU_LAW
: ad_fmt
= 2; break;
1278 case AFMT_A_LAW
: ad_fmt
= 3; break;
1283 case 2: ad_mode
= 0; break;
1284 case 1: ad_mode
= 1; break;
1288 DBGPV("ad_mode = %d, ad_fmt = %d\n", ad_mode
, ad_fmt
);
1289 ASSERT(framerate
>= 4000 && framerate
<= 49000);
1290 ad1843_write_bits(lith
, &ad1843_C1C
, framerate
);
1291 ad1843_write_multi(lith
, 2,
1292 &ad1843_DA1SM
, ad_mode
, &ad1843_DA1F
, ad_fmt
);
1295 static void ad1843_shutdown_dac(lithium_t
*lith
)
1297 ad1843_write_bits(lith
, &ad1843_DA1F
, 1);
1300 static void ad1843_setup_adc(lithium_t
*lith
, int framerate
, int fmt
, int channels
)
1304 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1305 lith
, framerate
, fmt
, channels
);
1308 case AFMT_S8
: da_fmt
= 1; break;
1309 case AFMT_U8
: da_fmt
= 1; break;
1310 case AFMT_S16_LE
: da_fmt
= 1; break;
1311 case AFMT_MU_LAW
: da_fmt
= 2; break;
1312 case AFMT_A_LAW
: da_fmt
= 3; break;
1316 DBGPV("da_fmt = %d\n", da_fmt
);
1317 ASSERT(framerate
>= 4000 && framerate
<= 49000);
1318 ad1843_write_bits(lith
, &ad1843_C2C
, framerate
);
1319 ad1843_write_multi(lith
, 2,
1320 &ad1843_ADLF
, da_fmt
, &ad1843_ADRF
, da_fmt
);
1323 static void ad1843_shutdown_adc(lithium_t
*lith
)
1329 * Fully initialize the ad1843. As described in the AD1843 data
1330 * sheet, section "START-UP SEQUENCE". The numbered comments are
1331 * subsection headings from the data sheet. See the data sheet, pages
1332 * 52-54, for more info.
1334 * return 0 on success, -errno on failure. */
1336 static int __init
ad1843_init(lithium_t
*lith
)
1338 unsigned long later
;
1341 err
= li_init(lith
);
1345 if (ad1843_read_bits(lith
, &ad1843_INIT
) != 0) {
1346 printk(KERN_ERR
"vwsnd sound: AD1843 won't initialize\n");
1350 ad1843_write_bits(lith
, &ad1843_SCF
, 1);
1352 /* 4. Put the conversion resources into standby. */
1354 ad1843_write_bits(lith
, &ad1843_PDNI
, 0);
1355 later
= jiffies
+ HZ
/ 2; /* roughly half a second */
1357 while (ad1843_read_bits(lith
, &ad1843_PDNO
)) {
1358 if (time_after(jiffies
, later
)) {
1360 "vwsnd audio: AD1843 won't power up\n");
1367 /* 5. Power up the clock generators and enable clock output pins. */
1369 ad1843_write_multi(lith
, 2, &ad1843_C1EN
, 1, &ad1843_C2EN
, 1);
1371 /* 6. Configure conversion resources while they are in standby. */
1373 /* DAC1 uses clock 1 as source, ADC uses clock 2. Always. */
1375 ad1843_write_multi(lith
, 3,
1380 /* 7. Enable conversion resources. */
1382 ad1843_write_bits(lith
, &ad1843_ADTLK
, 1);
1383 ad1843_write_multi(lith
, 5,
1390 /* 8. Configure conversion resources while they are enabled. */
1392 ad1843_write_bits(lith
, &ad1843_DA1C
, 1);
1394 /* Unmute all channels. */
1396 ad1843_set_outsrc(lith
,
1397 (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
1398 SOUND_MASK_MIC
| SOUND_MASK_CD
));
1399 ad1843_write_multi(lith
, 2, &ad1843_LDA1AM
, 0, &ad1843_RDA1AM
, 0);
1401 /* Set default recording source to Line In and set
1402 * mic gain to +20 dB.
1405 ad1843_set_recsrc(lith
, SOUND_MASK_LINE
);
1406 ad1843_write_multi(lith
, 2, &ad1843_LMGE
, 1, &ad1843_RMGE
, 1);
1408 /* Set Speaker Out level to +/- 4V and unmute it. */
1410 ad1843_write_multi(lith
, 2, &ad1843_HPOS
, 1, &ad1843_HPOM
, 0);
1415 /*****************************************************************************/
1418 #define READ_INTR_MASK (LI_INTR_COMM1_TRIG | LI_INTR_COMM1_OVERFLOW)
1419 #define WRITE_INTR_MASK (LI_INTR_COMM2_TRIG | LI_INTR_COMM2_UNDERFLOW)
1421 typedef enum vwsnd_port_swstate
{ /* software state */
1426 } vwsnd_port_swstate_t
;
1428 typedef enum vwsnd_port_hwstate
{ /* hardware state */
1431 } vwsnd_port_hwstate_t
;
1434 * These flags are read by ISR, but only written at baseline.
1437 typedef enum vwsnd_port_flags
{
1439 ERFLOWN
= 1 << 1, /* overflown or underflown */
1441 } vwsnd_port_flags_t
;
1444 * vwsnd_port is the per-port data structure. Each device has two
1445 * ports, one for input and one for output.
1449 * port->lock protects: hwstate, flags, swb_[iu]_avail.
1451 * devc->io_mutex protects: swstate, sw_*, swb_[iu]_idx.
1453 * everything else is only written by open/release or
1454 * pcm_{setup,shutdown}(), which are serialized by a
1455 * combination of devc->open_mutex and devc->io_mutex.
1458 typedef struct vwsnd_port
{
1461 wait_queue_head_t queue
;
1462 vwsnd_port_swstate_t swstate
;
1463 vwsnd_port_hwstate_t hwstate
;
1464 vwsnd_port_flags_t flags
;
1471 unsigned int zero_word
; /* zero for the sample format */
1477 unsigned int hw_fragshift
;
1478 unsigned int hw_fragsize
;
1479 unsigned int hw_fragcount
;
1482 unsigned long hwbuf_paddr
;
1483 unsigned long hwbuf_vaddr
;
1484 void * hwbuf
; /* hwbuf == hwbuf_vaddr */
1485 int hwbuf_max
; /* max bytes to preload */
1488 unsigned int swbuf_size
; /* size in bytes */
1489 unsigned int swb_u_idx
; /* index of next user byte */
1490 unsigned int swb_i_idx
; /* index of next intr byte */
1491 unsigned int swb_u_avail
; /* # bytes avail to user */
1492 unsigned int swb_i_avail
; /* # bytes avail to intr */
1504 /* vwsnd_dev is the per-device data structure. */
1506 typedef struct vwsnd_dev
{
1507 struct vwsnd_dev
*next_dev
;
1508 int audio_minor
; /* minor number of audio device */
1509 int mixer_minor
; /* minor number of mixer device */
1511 struct mutex open_mutex
;
1512 struct mutex io_mutex
;
1513 struct mutex mix_mutex
;
1515 wait_queue_head_t open_wait
;
1523 static vwsnd_dev_t
*vwsnd_dev_list
; /* linked list of all devices */
1525 static atomic_t vwsnd_use_count
= ATOMIC_INIT(0);
1527 # define INC_USE_COUNT (atomic_inc(&vwsnd_use_count))
1528 # define DEC_USE_COUNT (atomic_dec(&vwsnd_use_count))
1529 # define IN_USE (atomic_read(&vwsnd_use_count) != 0)
1532 * Lithium can only DMA multiples of 32 bytes. Its DMA buffer may
1533 * be up to 8 Kb. This driver always uses 8 Kb.
1535 * Memory bug workaround -- I'm not sure what's going on here, but
1536 * somehow pcm_copy_out() was triggering segv's going on to the next
1537 * page of the hw buffer. So, I make the hw buffer one size bigger
1538 * than we actually use. That way, the following page is allocated
1539 * and mapped, and no error. I suspect that something is broken
1540 * in Cobalt, but haven't really investigated. HBO is the actual
1541 * size of the buffer, and HWBUF_ORDER is what we allocate.
1544 #define HWBUF_SHIFT 13
1545 #define HWBUF_SIZE (1 << HWBUF_SHIFT)
1546 # define HBO (HWBUF_SHIFT > PAGE_SHIFT ? HWBUF_SHIFT - PAGE_SHIFT : 0)
1547 # define HWBUF_ORDER (HBO + 1) /* next size bigger */
1548 #define MIN_SPEED 4000
1549 #define MAX_SPEED 49000
1551 #define MIN_FRAGSHIFT (DMACHUNK_SHIFT + 1)
1552 #define MAX_FRAGSHIFT (PAGE_SHIFT)
1553 #define MIN_FRAGSIZE (1 << MIN_FRAGSHIFT)
1554 #define MAX_FRAGSIZE (1 << MAX_FRAGSHIFT)
1555 #define MIN_FRAGCOUNT(fragsize) 3
1556 #define MAX_FRAGCOUNT(fragsize) (32 * PAGE_SIZE / (fragsize))
1557 #define DEFAULT_FRAGSHIFT 12
1558 #define DEFAULT_FRAGCOUNT 16
1559 #define DEFAULT_SUBDIVSHIFT 0
1562 * The software buffer (swbuf) is a ring buffer shared between user
1563 * level and interrupt level. Each level owns some of the bytes in
1564 * the buffer, and may give bytes away by calling swb_inc_{u,i}().
1565 * User level calls _u for user, and interrupt level calls _i for
1568 * port->swb_{u,i}_avail is the number of bytes available to that level.
1570 * port->swb_{u,i}_idx is the index of the first available byte in the
1573 * Each level calls swb_inc_{u,i}() to atomically increment its index,
1574 * recalculate the number of bytes available for both sides, and
1575 * return the number of bytes available. Since each side can only
1576 * give away bytes, the other side can only increase the number of
1577 * bytes available to this side. Each side updates its own index
1578 * variable, swb_{u,i}_idx, so no lock is needed to read it.
1580 * To query the number of bytes available, call swb_inc_{u,i} with an
1581 * increment of zero.
1584 static __inline__
unsigned int __swb_inc_u(vwsnd_port_t
*port
, int inc
)
1587 port
->swb_u_idx
+= inc
;
1588 port
->swb_u_idx
%= port
->swbuf_size
;
1589 port
->swb_u_avail
-= inc
;
1590 port
->swb_i_avail
+= inc
;
1592 return port
->swb_u_avail
;
1595 static __inline__
unsigned int swb_inc_u(vwsnd_port_t
*port
, int inc
)
1597 unsigned long flags
;
1600 spin_lock_irqsave(&port
->lock
, flags
);
1602 ret
= __swb_inc_u(port
, inc
);
1604 spin_unlock_irqrestore(&port
->lock
, flags
);
1608 static __inline__
unsigned int __swb_inc_i(vwsnd_port_t
*port
, int inc
)
1611 port
->swb_i_idx
+= inc
;
1612 port
->swb_i_idx
%= port
->swbuf_size
;
1613 port
->swb_i_avail
-= inc
;
1614 port
->swb_u_avail
+= inc
;
1616 return port
->swb_i_avail
;
1619 static __inline__
unsigned int swb_inc_i(vwsnd_port_t
*port
, int inc
)
1621 unsigned long flags
;
1624 spin_lock_irqsave(&port
->lock
, flags
);
1626 ret
= __swb_inc_i(port
, inc
);
1628 spin_unlock_irqrestore(&port
->lock
, flags
);
1633 * pcm_setup - this routine initializes all port state after
1634 * mode-setting ioctls have been done, but before the first I/O is
1637 * Locking: called with devc->io_mutex held.
1639 * Returns 0 on success, -errno on failure.
1642 static int pcm_setup(vwsnd_dev_t
*devc
,
1643 vwsnd_port_t
*rport
,
1644 vwsnd_port_t
*wport
)
1646 vwsnd_port_t
*aport
= rport
? rport
: wport
;
1648 unsigned int zero_word
;
1650 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc
, rport
, wport
);
1652 ASSERT(aport
!= NULL
);
1653 if (aport
->swbuf
!= NULL
)
1655 switch (aport
->sw_samplefmt
) {
1658 zero_word
= 0xFFFFFFFF ^ 0x80808080;
1663 zero_word
= 0xD5D5D5D5 ^ 0x80808080;
1668 zero_word
= 0x80808080;
1673 zero_word
= 0x00000000;
1678 zero_word
= 0x00000000;
1682 sample_size
= 0; /* prevent compiler warning */
1686 aport
->sample_size
= sample_size
;
1687 aport
->zero_word
= zero_word
;
1688 aport
->frame_size
= aport
->sw_channels
* aport
->sample_size
;
1689 aport
->hw_fragshift
= aport
->sw_fragshift
- aport
->sw_subdivshift
;
1690 aport
->hw_fragsize
= 1 << aport
->hw_fragshift
;
1691 aport
->hw_fragcount
= aport
->sw_fragcount
<< aport
->sw_subdivshift
;
1692 ASSERT(aport
->hw_fragsize
>= MIN_FRAGSIZE
);
1693 ASSERT(aport
->hw_fragsize
<= MAX_FRAGSIZE
);
1694 ASSERT(aport
->hw_fragcount
>= MIN_FRAGCOUNT(aport
->hw_fragsize
));
1695 ASSERT(aport
->hw_fragcount
<= MAX_FRAGCOUNT(aport
->hw_fragsize
));
1697 int hwfrags
, swfrags
;
1698 rport
->hwbuf_max
= aport
->hwbuf_size
- DMACHUNK_SIZE
;
1699 hwfrags
= rport
->hwbuf_max
>> aport
->hw_fragshift
;
1700 swfrags
= aport
->hw_fragcount
- hwfrags
;
1703 rport
->swbuf_size
= swfrags
* aport
->hw_fragsize
;
1704 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags
, swfrags
);
1705 DBGPV("read hwbuf_max = %d, swbuf_size = %d\n",
1706 rport
->hwbuf_max
, rport
->swbuf_size
);
1709 int hwfrags
, swfrags
;
1710 int total_bytes
= aport
->hw_fragcount
* aport
->hw_fragsize
;
1711 wport
->hwbuf_max
= aport
->hwbuf_size
- DMACHUNK_SIZE
;
1712 if (wport
->hwbuf_max
> total_bytes
)
1713 wport
->hwbuf_max
= total_bytes
;
1714 hwfrags
= wport
->hwbuf_max
>> aport
->hw_fragshift
;
1715 DBGPV("hwfrags = %d\n", hwfrags
);
1716 swfrags
= aport
->hw_fragcount
- hwfrags
;
1719 wport
->swbuf_size
= swfrags
* aport
->hw_fragsize
;
1720 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags
, swfrags
);
1721 DBGPV("write hwbuf_max = %d, swbuf_size = %d\n",
1722 wport
->hwbuf_max
, wport
->swbuf_size
);
1725 aport
->swb_u_idx
= 0;
1726 aport
->swb_i_idx
= 0;
1727 aport
->byte_count
= 0;
1730 * Is this a Cobalt bug? We need to make this buffer extend
1731 * one page further than we actually use -- somehow memcpy
1732 * causes an exceptoin otherwise. I suspect there's a bug in
1733 * Cobalt (or somewhere) where it's generating a fault on a
1734 * speculative load or something. Obviously, I haven't taken
1735 * the time to track it down.
1738 aport
->swbuf
= vmalloc(aport
->swbuf_size
+ PAGE_SIZE
);
1741 if (rport
&& wport
) {
1742 ASSERT(aport
== rport
);
1743 ASSERT(wport
->swbuf
== NULL
);
1744 /* One extra page - see comment above. */
1745 wport
->swbuf
= vmalloc(aport
->swbuf_size
+ PAGE_SIZE
);
1746 if (!wport
->swbuf
) {
1747 vfree(aport
->swbuf
);
1748 aport
->swbuf
= NULL
;
1751 wport
->sample_size
= rport
->sample_size
;
1752 wport
->zero_word
= rport
->zero_word
;
1753 wport
->frame_size
= rport
->frame_size
;
1754 wport
->hw_fragshift
= rport
->hw_fragshift
;
1755 wport
->hw_fragsize
= rport
->hw_fragsize
;
1756 wport
->hw_fragcount
= rport
->hw_fragcount
;
1757 wport
->swbuf_size
= rport
->swbuf_size
;
1758 wport
->hwbuf_max
= rport
->hwbuf_max
;
1759 wport
->swb_u_idx
= rport
->swb_u_idx
;
1760 wport
->swb_i_idx
= rport
->swb_i_idx
;
1761 wport
->byte_count
= rport
->byte_count
;
1764 rport
->swb_u_avail
= 0;
1765 rport
->swb_i_avail
= rport
->swbuf_size
;
1766 rport
->swstate
= SW_RUN
;
1767 li_setup_dma(&rport
->chan
,
1772 rport
->hw_fragshift
,
1774 rport
->sample_size
);
1775 ad1843_setup_adc(&devc
->lith
,
1776 rport
->sw_framerate
,
1777 rport
->sw_samplefmt
,
1778 rport
->sw_channels
);
1779 li_enable_interrupts(&devc
->lith
, READ_INTR_MASK
);
1780 if (!(rport
->flags
& DISABLED
)) {
1782 rport
->hwstate
= HW_RUNNING
;
1783 li_activate_dma(&rport
->chan
);
1784 li_read_USTMSC(&rport
->chan
, &ustmsc
);
1785 rport
->MSC_offset
= ustmsc
.msc
;
1789 if (wport
->hwbuf_max
> wport
->swbuf_size
)
1790 wport
->hwbuf_max
= wport
->swbuf_size
;
1791 wport
->flags
&= ~ERFLOWN
;
1792 wport
->swb_u_avail
= wport
->swbuf_size
;
1793 wport
->swb_i_avail
= 0;
1794 wport
->swstate
= SW_RUN
;
1795 li_setup_dma(&wport
->chan
,
1800 wport
->hw_fragshift
,
1802 wport
->sample_size
);
1803 ad1843_setup_dac(&devc
->lith
,
1804 wport
->sw_framerate
,
1805 wport
->sw_samplefmt
,
1806 wport
->sw_channels
);
1807 li_enable_interrupts(&devc
->lith
, WRITE_INTR_MASK
);
1814 * pcm_shutdown_port - shut down one port (direction) for PCM I/O.
1815 * Only called from pcm_shutdown.
1818 static void pcm_shutdown_port(vwsnd_dev_t
*devc
,
1819 vwsnd_port_t
*aport
,
1822 unsigned long flags
;
1823 vwsnd_port_hwstate_t hwstate
;
1824 DECLARE_WAITQUEUE(wait
, current
);
1826 aport
->swstate
= SW_INITIAL
;
1827 add_wait_queue(&aport
->queue
, &wait
);
1829 set_current_state(TASK_UNINTERRUPTIBLE
);
1830 spin_lock_irqsave(&aport
->lock
, flags
);
1832 hwstate
= aport
->hwstate
;
1834 spin_unlock_irqrestore(&aport
->lock
, flags
);
1835 if (hwstate
== HW_STOPPED
)
1839 current
->state
= TASK_RUNNING
;
1840 remove_wait_queue(&aport
->queue
, &wait
);
1841 li_disable_interrupts(&devc
->lith
, mask
);
1842 if (aport
== &devc
->rport
)
1843 ad1843_shutdown_adc(&devc
->lith
);
1844 else /* aport == &devc->wport) */
1845 ad1843_shutdown_dac(&devc
->lith
);
1846 li_shutdown_dma(&aport
->chan
);
1847 vfree(aport
->swbuf
);
1848 aport
->swbuf
= NULL
;
1849 aport
->byte_count
= 0;
1853 * pcm_shutdown undoes what pcm_setup did.
1854 * Also sets the ports' swstate to newstate.
1857 static void pcm_shutdown(vwsnd_dev_t
*devc
,
1858 vwsnd_port_t
*rport
,
1859 vwsnd_port_t
*wport
)
1861 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc
, rport
, wport
);
1863 if (rport
&& rport
->swbuf
) {
1864 DBGPV("shutting down rport\n");
1865 pcm_shutdown_port(devc
, rport
, READ_INTR_MASK
);
1867 if (wport
&& wport
->swbuf
) {
1868 DBGPV("shutting down wport\n");
1869 pcm_shutdown_port(devc
, wport
, WRITE_INTR_MASK
);
1874 static void pcm_copy_in(vwsnd_port_t
*rport
, int swidx
, int hwidx
, int nb
)
1876 char *src
= rport
->hwbuf
+ hwidx
;
1877 char *dst
= rport
->swbuf
+ swidx
;
1878 int fmt
= rport
->sw_samplefmt
;
1880 DBGPV("swidx = %d, hwidx = %d\n", swidx
, hwidx
);
1881 ASSERT(rport
->hwbuf
!= NULL
);
1882 ASSERT(rport
->swbuf
!= NULL
);
1883 ASSERT(nb
> 0 && (nb
% 32) == 0);
1884 ASSERT(swidx
% 32 == 0 && hwidx
% 32 == 0);
1885 ASSERT(swidx
>= 0 && swidx
+ nb
<= rport
->swbuf_size
);
1886 ASSERT(hwidx
>= 0 && hwidx
+ nb
<= rport
->hwbuf_size
);
1888 if (fmt
== AFMT_MU_LAW
|| fmt
== AFMT_A_LAW
|| fmt
== AFMT_S8
) {
1890 /* See Sample Format Notes above. */
1892 char *end
= src
+ nb
;
1894 *dst
++ = *src
++ ^ 0x80;
1896 memcpy(dst
, src
, nb
);
1899 static void pcm_copy_out(vwsnd_port_t
*wport
, int swidx
, int hwidx
, int nb
)
1901 char *src
= wport
->swbuf
+ swidx
;
1902 char *dst
= wport
->hwbuf
+ hwidx
;
1903 int fmt
= wport
->sw_samplefmt
;
1905 ASSERT(nb
> 0 && (nb
% 32) == 0);
1906 ASSERT(wport
->hwbuf
!= NULL
);
1907 ASSERT(wport
->swbuf
!= NULL
);
1908 ASSERT(swidx
% 32 == 0 && hwidx
% 32 == 0);
1909 ASSERT(swidx
>= 0 && swidx
+ nb
<= wport
->swbuf_size
);
1910 ASSERT(hwidx
>= 0 && hwidx
+ nb
<= wport
->hwbuf_size
);
1911 if (fmt
== AFMT_MU_LAW
|| fmt
== AFMT_A_LAW
|| fmt
== AFMT_S8
) {
1913 /* See Sample Format Notes above. */
1915 char *end
= src
+ nb
;
1917 *dst
++ = *src
++ ^ 0x80;
1919 memcpy(dst
, src
, nb
);
1923 * pcm_output() is called both from baselevel and from interrupt level.
1924 * This is where audio frames are copied into the hardware-accessible
1927 * Locking note: The part of this routine that figures out what to do
1928 * holds wport->lock. The longer part releases wport->lock, but sets
1929 * wport->flags & HW_BUSY. Afterward, it reacquires wport->lock, and
1930 * checks for more work to do.
1932 * If another thread calls pcm_output() while HW_BUSY is set, it
1933 * returns immediately, knowing that the thread that set HW_BUSY will
1934 * look for more work to do before returning.
1936 * This has the advantage that port->lock is held for several short
1937 * periods instead of one long period. Also, when pcm_output is
1938 * called from base level, it reenables interrupts.
1941 static void pcm_output(vwsnd_dev_t
*devc
, int erflown
, int nb
)
1943 vwsnd_port_t
*wport
= &devc
->wport
;
1944 const int hwmax
= wport
->hwbuf_max
;
1945 const int hwsize
= wport
->hwbuf_size
;
1946 const int swsize
= wport
->swbuf_size
;
1947 const int fragsize
= wport
->hw_fragsize
;
1948 unsigned long iflags
;
1950 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc
, erflown
, nb
);
1951 spin_lock_irqsave(&wport
->lock
, iflags
);
1953 wport
->flags
|= ERFLOWN
;
1954 (void) __swb_inc_u(wport
, nb
);
1955 if (wport
->flags
& HW_BUSY
) {
1956 spin_unlock_irqrestore(&wport
->lock
, iflags
);
1957 DBGPV("returning: HW BUSY\n");
1960 if (wport
->flags
& DISABLED
) {
1961 spin_unlock_irqrestore(&wport
->lock
, iflags
);
1962 DBGPV("returning: DISABLED\n");
1965 wport
->flags
|= HW_BUSY
;
1967 int swptr
, hwptr
, hw_avail
, sw_avail
, swidx
;
1968 vwsnd_port_hwstate_t hwstate
= wport
->hwstate
;
1969 vwsnd_port_swstate_t swstate
= wport
->swstate
;
1973 hwptr
= li_read_hwptr(&wport
->chan
);
1974 swptr
= li_read_swptr(&wport
->chan
);
1975 hw_unavail
= (swptr
- hwptr
+ hwsize
) % hwsize
;
1976 hw_avail
= (hwmax
- hw_unavail
) & -fragsize
;
1977 sw_avail
= wport
->swb_i_avail
& -fragsize
;
1978 if (sw_avail
&& swstate
== SW_RUN
) {
1979 if (wport
->flags
& ERFLOWN
) {
1980 wport
->flags
&= ~ERFLOWN
;
1982 } else if (swstate
== SW_INITIAL
||
1983 swstate
== SW_OFF
||
1984 (swstate
== SW_DRAIN
&&
1986 (wport
->flags
& ERFLOWN
))) {
1987 DBGP("stopping. hwstate = %d\n", hwstate
);
1988 if (hwstate
!= HW_STOPPED
) {
1989 li_deactivate_dma(&wport
->chan
);
1990 wport
->hwstate
= HW_STOPPED
;
1992 wake_up(&wport
->queue
);
1995 if (!sw_avail
|| !hw_avail
)
1997 spin_unlock_irqrestore(&wport
->lock
, iflags
);
2000 * We gave up the port lock, but we have the HW_BUSY flag.
2001 * Proceed without accessing any nonlocal state.
2002 * Do not exit the loop -- must check for more work.
2005 swidx
= wport
->swb_i_idx
;
2009 if (nb
> hwsize
- swptr
)
2010 nb
= hwsize
- swptr
; /* don't overflow hwbuf */
2011 if (nb
> swsize
- swidx
)
2012 nb
= swsize
- swidx
; /* don't overflow swbuf */
2014 if (nb
% fragsize
) {
2015 DBGP("nb = %d, fragsize = %d\n", nb
, fragsize
);
2016 DBGP("hw_avail = %d\n", hw_avail
);
2017 DBGP("sw_avail = %d\n", sw_avail
);
2018 DBGP("hwsize = %d, swptr = %d\n", hwsize
, swptr
);
2019 DBGP("swsize = %d, swidx = %d\n", swsize
, swidx
);
2021 ASSERT(!(nb
% fragsize
));
2022 DBGPV("copying swb[%d..%d] to hwb[%d..%d]\n",
2023 swidx
, swidx
+ nb
, swptr
, swptr
+ nb
);
2024 pcm_copy_out(wport
, swidx
, swptr
, nb
);
2025 li_write_swptr(&wport
->chan
, (swptr
+ nb
) % hwsize
);
2026 spin_lock_irqsave(&wport
->lock
, iflags
);
2027 if (hwstate
== HW_STOPPED
) {
2028 DBGPV("starting\n");
2029 li_activate_dma(&wport
->chan
);
2030 wport
->hwstate
= HW_RUNNING
;
2031 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2032 ASSERT(wport
->byte_count
% wport
->frame_size
== 0);
2033 wport
->MSC_offset
= ustmsc
.msc
- wport
->byte_count
/ wport
->frame_size
;
2035 __swb_inc_i(wport
, nb
);
2036 wport
->byte_count
+= nb
;
2037 wport
->frag_count
+= nb
/ fragsize
;
2038 ASSERT(nb
% fragsize
== 0);
2039 wake_up(&wport
->queue
);
2041 wport
->flags
&= ~HW_BUSY
;
2042 spin_unlock_irqrestore(&wport
->lock
, iflags
);
2047 * pcm_input() is called both from baselevel and from interrupt level.
2048 * This is where audio frames are copied out of the hardware-accessible
2051 * Locking note: The part of this routine that figures out what to do
2052 * holds rport->lock. The longer part releases rport->lock, but sets
2053 * rport->flags & HW_BUSY. Afterward, it reacquires rport->lock, and
2054 * checks for more work to do.
2056 * If another thread calls pcm_input() while HW_BUSY is set, it
2057 * returns immediately, knowing that the thread that set HW_BUSY will
2058 * look for more work to do before returning.
2060 * This has the advantage that port->lock is held for several short
2061 * periods instead of one long period. Also, when pcm_input is
2062 * called from base level, it reenables interrupts.
2065 static void pcm_input(vwsnd_dev_t
*devc
, int erflown
, int nb
)
2067 vwsnd_port_t
*rport
= &devc
->rport
;
2068 const int hwmax
= rport
->hwbuf_max
;
2069 const int hwsize
= rport
->hwbuf_size
;
2070 const int swsize
= rport
->swbuf_size
;
2071 const int fragsize
= rport
->hw_fragsize
;
2072 unsigned long iflags
;
2074 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc
, erflown
, nb
);
2076 spin_lock_irqsave(&rport
->lock
, iflags
);
2078 rport
->flags
|= ERFLOWN
;
2079 (void) __swb_inc_u(rport
, nb
);
2080 if (rport
->flags
& HW_BUSY
|| !rport
->swbuf
) {
2081 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2082 DBGPV("returning: HW BUSY or !swbuf\n");
2085 if (rport
->flags
& DISABLED
) {
2086 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2087 DBGPV("returning: DISABLED\n");
2090 rport
->flags
|= HW_BUSY
;
2092 int swptr
, hwptr
, hw_avail
, sw_avail
, swidx
;
2093 vwsnd_port_hwstate_t hwstate
= rport
->hwstate
;
2094 vwsnd_port_swstate_t swstate
= rport
->swstate
;
2096 hwptr
= li_read_hwptr(&rport
->chan
);
2097 swptr
= li_read_swptr(&rport
->chan
);
2098 hw_avail
= (hwptr
- swptr
+ hwsize
) % hwsize
& -fragsize
;
2099 if (hw_avail
> hwmax
)
2101 sw_avail
= rport
->swb_i_avail
& -fragsize
;
2102 if (swstate
!= SW_RUN
) {
2103 DBGP("stopping. hwstate = %d\n", hwstate
);
2104 if (hwstate
!= HW_STOPPED
) {
2105 li_deactivate_dma(&rport
->chan
);
2106 rport
->hwstate
= HW_STOPPED
;
2108 wake_up(&rport
->queue
);
2111 if (!sw_avail
|| !hw_avail
)
2113 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2116 * We gave up the port lock, but we have the HW_BUSY flag.
2117 * Proceed without accessing any nonlocal state.
2118 * Do not exit the loop -- must check for more work.
2121 swidx
= rport
->swb_i_idx
;
2125 if (nb
> hwsize
- swptr
)
2126 nb
= hwsize
- swptr
; /* don't overflow hwbuf */
2127 if (nb
> swsize
- swidx
)
2128 nb
= swsize
- swidx
; /* don't overflow swbuf */
2130 if (nb
% fragsize
) {
2131 DBGP("nb = %d, fragsize = %d\n", nb
, fragsize
);
2132 DBGP("hw_avail = %d\n", hw_avail
);
2133 DBGP("sw_avail = %d\n", sw_avail
);
2134 DBGP("hwsize = %d, swptr = %d\n", hwsize
, swptr
);
2135 DBGP("swsize = %d, swidx = %d\n", swsize
, swidx
);
2137 ASSERT(!(nb
% fragsize
));
2138 DBGPV("copying hwb[%d..%d] to swb[%d..%d]\n",
2139 swptr
, swptr
+ nb
, swidx
, swidx
+ nb
);
2140 pcm_copy_in(rport
, swidx
, swptr
, nb
);
2141 li_write_swptr(&rport
->chan
, (swptr
+ nb
) % hwsize
);
2142 spin_lock_irqsave(&rport
->lock
, iflags
);
2143 __swb_inc_i(rport
, nb
);
2144 rport
->byte_count
+= nb
;
2145 rport
->frag_count
+= nb
/ fragsize
;
2146 ASSERT(nb
% fragsize
== 0);
2147 wake_up(&rport
->queue
);
2149 rport
->flags
&= ~HW_BUSY
;
2150 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2155 * pcm_flush_frag() writes zero samples to fill the current fragment,
2156 * then flushes it to the hardware.
2158 * It is only meaningful to flush output, not input.
2161 static void pcm_flush_frag(vwsnd_dev_t
*devc
)
2163 vwsnd_port_t
*wport
= &devc
->wport
;
2165 DBGPV("swstate = %d\n", wport
->swstate
);
2166 if (wport
->swstate
== SW_RUN
) {
2167 int idx
= wport
->swb_u_idx
;
2168 int end
= (idx
+ wport
->hw_fragsize
- 1)
2169 >> wport
->hw_fragshift
2170 << wport
->hw_fragshift
;
2172 DBGPV("clearing %d bytes\n", nb
);
2174 memset(wport
->swbuf
+ idx
,
2175 (char) wport
->zero_word
,
2177 wport
->swstate
= SW_DRAIN
;
2178 pcm_output(devc
, 0, nb
);
2184 * Wait for output to drain. This sleeps uninterruptibly because
2185 * there is nothing intelligent we can do if interrupted. This
2186 * means the process will be delayed in responding to the signal.
2189 static void pcm_write_sync(vwsnd_dev_t
*devc
)
2191 vwsnd_port_t
*wport
= &devc
->wport
;
2192 DECLARE_WAITQUEUE(wait
, current
);
2193 unsigned long flags
;
2194 vwsnd_port_hwstate_t hwstate
;
2196 DBGEV("(devc=0x%p)\n", devc
);
2197 add_wait_queue(&wport
->queue
, &wait
);
2199 set_current_state(TASK_UNINTERRUPTIBLE
);
2200 spin_lock_irqsave(&wport
->lock
, flags
);
2202 hwstate
= wport
->hwstate
;
2204 spin_unlock_irqrestore(&wport
->lock
, flags
);
2205 if (hwstate
== HW_STOPPED
)
2209 current
->state
= TASK_RUNNING
;
2210 remove_wait_queue(&wport
->queue
, &wait
);
2211 DBGPV("swstate = %d, hwstate = %d\n", wport
->swstate
, wport
->hwstate
);
2215 /*****************************************************************************/
2219 * seek on an audio device always fails.
2222 static void vwsnd_audio_read_intr(vwsnd_dev_t
*devc
, unsigned int status
)
2224 int overflown
= status
& LI_INTR_COMM1_OVERFLOW
;
2226 if (status
& READ_INTR_MASK
)
2227 pcm_input(devc
, overflown
, 0);
2230 static void vwsnd_audio_write_intr(vwsnd_dev_t
*devc
, unsigned int status
)
2232 int underflown
= status
& LI_INTR_COMM2_UNDERFLOW
;
2234 if (status
& WRITE_INTR_MASK
)
2235 pcm_output(devc
, underflown
, 0);
2238 static irqreturn_t
vwsnd_audio_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2240 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) dev_id
;
2241 unsigned int status
;
2243 DBGEV("(irq=%d, dev_id=0x%p, regs=0x%p)\n", irq
, dev_id
, regs
);
2245 status
= li_get_clear_intr_status(&devc
->lith
);
2246 vwsnd_audio_read_intr(devc
, status
);
2247 vwsnd_audio_write_intr(devc
, status
);
2251 static ssize_t
vwsnd_audio_do_read(struct file
*file
,
2256 vwsnd_dev_t
*devc
= file
->private_data
;
2257 vwsnd_port_t
*rport
= ((file
->f_mode
& FMODE_READ
) ?
2258 &devc
->rport
: NULL
);
2261 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2262 file
, buffer
, count
, ppos
);
2267 if (rport
->swbuf
== NULL
) {
2268 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2269 &devc
->wport
: NULL
;
2270 ret
= pcm_setup(devc
, rport
, wport
);
2275 if (!access_ok(VERIFY_READ
, buffer
, count
))
2279 DECLARE_WAITQUEUE(wait
, current
);
2280 add_wait_queue(&rport
->queue
, &wait
);
2281 while ((nb
= swb_inc_u(rport
, 0)) == 0) {
2282 DBGPV("blocking\n");
2283 set_current_state(TASK_INTERRUPTIBLE
);
2284 if (rport
->flags
& DISABLED
||
2285 file
->f_flags
& O_NONBLOCK
) {
2286 current
->state
= TASK_RUNNING
;
2287 remove_wait_queue(&rport
->queue
, &wait
);
2288 return ret
? ret
: -EAGAIN
;
2291 if (signal_pending(current
)) {
2292 current
->state
= TASK_RUNNING
;
2293 remove_wait_queue(&rport
->queue
, &wait
);
2294 return ret
? ret
: -ERESTARTSYS
;
2297 current
->state
= TASK_RUNNING
;
2298 remove_wait_queue(&rport
->queue
, &wait
);
2299 pcm_input(devc
, 0, 0);
2300 /* nb bytes are available in userbuf. */
2303 DBGPV("nb = %d\n", nb
);
2304 if (copy_to_user(buffer
, rport
->swbuf
+ rport
->swb_u_idx
, nb
))
2306 (void) swb_inc_u(rport
, nb
);
2311 DBGPV("returning %d\n", ret
);
2315 static ssize_t
vwsnd_audio_read(struct file
*file
,
2320 vwsnd_dev_t
*devc
= file
->private_data
;
2323 mutex_lock(&devc
->io_mutex
);
2324 ret
= vwsnd_audio_do_read(file
, buffer
, count
, ppos
);
2325 mutex_unlock(&devc
->io_mutex
);
2329 static ssize_t
vwsnd_audio_do_write(struct file
*file
,
2334 vwsnd_dev_t
*devc
= file
->private_data
;
2335 vwsnd_port_t
*wport
= ((file
->f_mode
& FMODE_WRITE
) ?
2336 &devc
->wport
: NULL
);
2339 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2340 file
, buffer
, count
, ppos
);
2345 if (wport
->swbuf
== NULL
) {
2346 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2347 &devc
->rport
: NULL
;
2348 ret
= pcm_setup(devc
, rport
, wport
);
2352 if (!access_ok(VERIFY_WRITE
, buffer
, count
))
2356 DECLARE_WAITQUEUE(wait
, current
);
2357 add_wait_queue(&wport
->queue
, &wait
);
2358 while ((nb
= swb_inc_u(wport
, 0)) == 0) {
2359 set_current_state(TASK_INTERRUPTIBLE
);
2360 if (wport
->flags
& DISABLED
||
2361 file
->f_flags
& O_NONBLOCK
) {
2362 current
->state
= TASK_RUNNING
;
2363 remove_wait_queue(&wport
->queue
, &wait
);
2364 return ret
? ret
: -EAGAIN
;
2367 if (signal_pending(current
)) {
2368 current
->state
= TASK_RUNNING
;
2369 remove_wait_queue(&wport
->queue
, &wait
);
2370 return ret
? ret
: -ERESTARTSYS
;
2373 current
->state
= TASK_RUNNING
;
2374 remove_wait_queue(&wport
->queue
, &wait
);
2375 /* nb bytes are available in userbuf. */
2378 DBGPV("nb = %d\n", nb
);
2379 if (copy_from_user(wport
->swbuf
+ wport
->swb_u_idx
, buffer
, nb
))
2381 pcm_output(devc
, 0, nb
);
2386 DBGPV("returning %d\n", ret
);
2390 static ssize_t
vwsnd_audio_write(struct file
*file
,
2395 vwsnd_dev_t
*devc
= file
->private_data
;
2398 mutex_lock(&devc
->io_mutex
);
2399 ret
= vwsnd_audio_do_write(file
, buffer
, count
, ppos
);
2400 mutex_unlock(&devc
->io_mutex
);
2404 /* No kernel lock - fine */
2405 static unsigned int vwsnd_audio_poll(struct file
*file
,
2406 struct poll_table_struct
*wait
)
2408 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2409 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2410 &devc
->rport
: NULL
;
2411 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2412 &devc
->wport
: NULL
;
2413 unsigned int mask
= 0;
2415 DBGEV("(file=0x%p, wait=0x%p)\n", file
, wait
);
2417 ASSERT(rport
|| wport
);
2419 poll_wait(file
, &rport
->queue
, wait
);
2420 if (swb_inc_u(rport
, 0))
2421 mask
|= (POLLIN
| POLLRDNORM
);
2424 poll_wait(file
, &wport
->queue
, wait
);
2425 if (wport
->swbuf
== NULL
|| swb_inc_u(wport
, 0))
2426 mask
|= (POLLOUT
| POLLWRNORM
);
2429 DBGPV("returning 0x%x\n", mask
);
2433 static int vwsnd_audio_do_ioctl(struct inode
*inode
,
2438 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2439 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2440 &devc
->rport
: NULL
;
2441 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2442 &devc
->wport
: NULL
;
2443 vwsnd_port_t
*aport
= rport
? rport
: wport
;
2444 struct audio_buf_info buf_info
;
2445 struct count_info info
;
2446 unsigned long flags
;
2450 DBGEV("(inode=0x%p, file=0x%p, cmd=0x%x, arg=0x%lx)\n",
2451 inode
, file
, cmd
, arg
);
2453 case OSS_GETVERSION
: /* _SIOR ('M', 118, int) */
2454 DBGX("OSS_GETVERSION\n");
2455 ival
= SOUND_VERSION
;
2456 return put_user(ival
, (int *) arg
);
2458 case SNDCTL_DSP_GETCAPS
: /* _SIOR ('P',15, int) */
2459 DBGX("SNDCTL_DSP_GETCAPS\n");
2460 ival
= DSP_CAP_DUPLEX
| DSP_CAP_REALTIME
| DSP_CAP_TRIGGER
;
2461 return put_user(ival
, (int *) arg
);
2463 case SNDCTL_DSP_GETFMTS
: /* _SIOR ('P',11, int) */
2464 DBGX("SNDCTL_DSP_GETFMTS\n");
2465 ival
= (AFMT_S16_LE
| AFMT_MU_LAW
| AFMT_A_LAW
|
2467 return put_user(ival
, (int *) arg
);
2470 case SOUND_PCM_READ_RATE
: /* _SIOR ('P', 2, int) */
2471 DBGX("SOUND_PCM_READ_RATE\n");
2472 ival
= aport
->sw_framerate
;
2473 return put_user(ival
, (int *) arg
);
2475 case SOUND_PCM_READ_CHANNELS
: /* _SIOR ('P', 6, int) */
2476 DBGX("SOUND_PCM_READ_CHANNELS\n");
2477 ival
= aport
->sw_channels
;
2478 return put_user(ival
, (int *) arg
);
2480 case SNDCTL_DSP_SPEED
: /* _SIOWR('P', 2, int) */
2481 if (get_user(ival
, (int *) arg
))
2483 DBGX("SNDCTL_DSP_SPEED %d\n", ival
);
2485 if (aport
->swstate
!= SW_INITIAL
) {
2486 DBGX("SNDCTL_DSP_SPEED failed: swstate = %d\n",
2490 if (ival
< MIN_SPEED
)
2492 if (ival
> MAX_SPEED
)
2495 rport
->sw_framerate
= ival
;
2497 wport
->sw_framerate
= ival
;
2499 ival
= aport
->sw_framerate
;
2500 return put_user(ival
, (int *) arg
);
2502 case SNDCTL_DSP_STEREO
: /* _SIOWR('P', 3, int) */
2503 if (get_user(ival
, (int *) arg
))
2505 DBGX("SNDCTL_DSP_STEREO %d\n", ival
);
2506 if (ival
!= 0 && ival
!= 1)
2508 if (aport
->swstate
!= SW_INITIAL
)
2511 rport
->sw_channels
= ival
+ 1;
2513 wport
->sw_channels
= ival
+ 1;
2514 return put_user(ival
, (int *) arg
);
2516 case SNDCTL_DSP_CHANNELS
: /* _SIOWR('P', 6, int) */
2517 if (get_user(ival
, (int *) arg
))
2519 DBGX("SNDCTL_DSP_CHANNELS %d\n", ival
);
2520 if (ival
!= 1 && ival
!= 2)
2522 if (aport
->swstate
!= SW_INITIAL
)
2525 rport
->sw_channels
= ival
;
2527 wport
->sw_channels
= ival
;
2528 return put_user(ival
, (int *) arg
);
2530 case SNDCTL_DSP_GETBLKSIZE
: /* _SIOWR('P', 4, int) */
2531 ival
= pcm_setup(devc
, rport
, wport
);
2533 DBGX("SNDCTL_DSP_GETBLKSIZE failed, errno %d\n", ival
);
2536 ival
= 1 << aport
->sw_fragshift
;
2537 DBGX("SNDCTL_DSP_GETBLKSIZE returning %d\n", ival
);
2538 return put_user(ival
, (int *) arg
);
2540 case SNDCTL_DSP_SETFRAGMENT
: /* _SIOWR('P',10, int) */
2541 if (get_user(ival
, (int *) arg
))
2543 DBGX("SNDCTL_DSP_SETFRAGMENT %d:%d\n",
2544 ival
>> 16, ival
& 0xFFFF);
2545 if (aport
->swstate
!= SW_INITIAL
)
2548 int sw_fragshift
= ival
& 0xFFFF;
2549 int sw_subdivshift
= aport
->sw_subdivshift
;
2550 int hw_fragshift
= sw_fragshift
- sw_subdivshift
;
2551 int sw_fragcount
= (ival
>> 16) & 0xFFFF;
2553 if (hw_fragshift
< MIN_FRAGSHIFT
)
2554 hw_fragshift
= MIN_FRAGSHIFT
;
2555 if (hw_fragshift
> MAX_FRAGSHIFT
)
2556 hw_fragshift
= MAX_FRAGSHIFT
;
2557 sw_fragshift
= hw_fragshift
+ aport
->sw_subdivshift
;
2558 hw_fragsize
= 1 << hw_fragshift
;
2559 if (sw_fragcount
< MIN_FRAGCOUNT(hw_fragsize
))
2560 sw_fragcount
= MIN_FRAGCOUNT(hw_fragsize
);
2561 if (sw_fragcount
> MAX_FRAGCOUNT(hw_fragsize
))
2562 sw_fragcount
= MAX_FRAGCOUNT(hw_fragsize
);
2563 DBGPV("sw_fragshift = %d\n", sw_fragshift
);
2564 DBGPV("rport = 0x%p, wport = 0x%p\n", rport
, wport
);
2566 rport
->sw_fragshift
= sw_fragshift
;
2567 rport
->sw_fragcount
= sw_fragcount
;
2570 wport
->sw_fragshift
= sw_fragshift
;
2571 wport
->sw_fragcount
= sw_fragcount
;
2573 ival
= sw_fragcount
<< 16 | sw_fragshift
;
2575 DBGX("SNDCTL_DSP_SETFRAGMENT returns %d:%d\n",
2576 ival
>> 16, ival
& 0xFFFF);
2577 return put_user(ival
, (int *) arg
);
2579 case SNDCTL_DSP_SUBDIVIDE
: /* _SIOWR('P', 9, int) */
2580 if (get_user(ival
, (int *) arg
))
2582 DBGX("SNDCTL_DSP_SUBDIVIDE %d\n", ival
);
2583 if (aport
->swstate
!= SW_INITIAL
)
2587 int hw_fragshift
, hw_fragsize
, hw_fragcount
;
2589 case 1: subdivshift
= 0; break;
2590 case 2: subdivshift
= 1; break;
2591 case 4: subdivshift
= 2; break;
2592 default: return -EINVAL
;
2594 hw_fragshift
= aport
->sw_fragshift
- subdivshift
;
2595 if (hw_fragshift
< MIN_FRAGSHIFT
||
2596 hw_fragshift
> MAX_FRAGSHIFT
)
2598 hw_fragsize
= 1 << hw_fragshift
;
2599 hw_fragcount
= aport
->sw_fragcount
>> subdivshift
;
2600 if (hw_fragcount
< MIN_FRAGCOUNT(hw_fragsize
) ||
2601 hw_fragcount
> MAX_FRAGCOUNT(hw_fragsize
))
2604 rport
->sw_subdivshift
= subdivshift
;
2606 wport
->sw_subdivshift
= subdivshift
;
2610 case SNDCTL_DSP_SETFMT
: /* _SIOWR('P',5, int) */
2611 if (get_user(ival
, (int *) arg
))
2613 DBGX("SNDCTL_DSP_SETFMT %d\n", ival
);
2614 if (ival
!= AFMT_QUERY
) {
2615 if (aport
->swstate
!= SW_INITIAL
) {
2616 DBGP("SETFMT failed, swstate = %d\n",
2627 rport
->sw_samplefmt
= ival
;
2629 wport
->sw_samplefmt
= ival
;
2635 ival
= aport
->sw_samplefmt
;
2636 return put_user(ival
, (int *) arg
);
2638 case SNDCTL_DSP_GETOSPACE
: /* _SIOR ('P',12, audio_buf_info) */
2639 DBGXV("SNDCTL_DSP_GETOSPACE\n");
2642 ival
= pcm_setup(devc
, rport
, wport
);
2645 ival
= swb_inc_u(wport
, 0);
2646 buf_info
.fragments
= ival
>> wport
->sw_fragshift
;
2647 buf_info
.fragstotal
= wport
->sw_fragcount
;
2648 buf_info
.fragsize
= 1 << wport
->sw_fragshift
;
2649 buf_info
.bytes
= ival
;
2650 DBGXV("SNDCTL_DSP_GETOSPACE returns { %d %d %d %d }\n",
2651 buf_info
.fragments
, buf_info
.fragstotal
,
2652 buf_info
.fragsize
, buf_info
.bytes
);
2653 if (copy_to_user((void *) arg
, &buf_info
, sizeof buf_info
))
2657 case SNDCTL_DSP_GETISPACE
: /* _SIOR ('P',13, audio_buf_info) */
2658 DBGX("SNDCTL_DSP_GETISPACE\n");
2661 ival
= pcm_setup(devc
, rport
, wport
);
2664 ival
= swb_inc_u(rport
, 0);
2665 buf_info
.fragments
= ival
>> rport
->sw_fragshift
;
2666 buf_info
.fragstotal
= rport
->sw_fragcount
;
2667 buf_info
.fragsize
= 1 << rport
->sw_fragshift
;
2668 buf_info
.bytes
= ival
;
2669 DBGX("SNDCTL_DSP_GETISPACE returns { %d %d %d %d }\n",
2670 buf_info
.fragments
, buf_info
.fragstotal
,
2671 buf_info
.fragsize
, buf_info
.bytes
);
2672 if (copy_to_user((void *) arg
, &buf_info
, sizeof buf_info
))
2676 case SNDCTL_DSP_NONBLOCK
: /* _SIO ('P',14) */
2677 DBGX("SNDCTL_DSP_NONBLOCK\n");
2678 file
->f_flags
|= O_NONBLOCK
;
2681 case SNDCTL_DSP_RESET
: /* _SIO ('P', 0) */
2682 DBGX("SNDCTL_DSP_RESET\n");
2684 * Nothing special needs to be done for input. Input
2685 * samples sit in swbuf, but it will be reinitialized
2686 * to empty when pcm_setup() is called.
2688 if (wport
&& wport
->swbuf
) {
2689 wport
->swstate
= SW_INITIAL
;
2690 pcm_output(devc
, 0, 0);
2691 pcm_write_sync(devc
);
2693 pcm_shutdown(devc
, rport
, wport
);
2696 case SNDCTL_DSP_SYNC
: /* _SIO ('P', 1) */
2697 DBGX("SNDCTL_DSP_SYNC\n");
2699 pcm_flush_frag(devc
);
2700 pcm_write_sync(devc
);
2702 pcm_shutdown(devc
, rport
, wport
);
2705 case SNDCTL_DSP_POST
: /* _SIO ('P', 8) */
2706 DBGX("SNDCTL_DSP_POST\n");
2709 pcm_flush_frag(devc
);
2712 case SNDCTL_DSP_GETIPTR
: /* _SIOR ('P', 17, count_info) */
2713 DBGX("SNDCTL_DSP_GETIPTR\n");
2716 spin_lock_irqsave(&rport
->lock
, flags
);
2719 if (rport
->hwstate
== HW_RUNNING
) {
2720 ASSERT(rport
->swstate
== SW_RUN
);
2721 li_read_USTMSC(&rport
->chan
, &ustmsc
);
2722 info
.bytes
= ustmsc
.msc
- rport
->MSC_offset
;
2723 info
.bytes
*= rport
->frame_size
;
2725 info
.bytes
= rport
->byte_count
;
2727 info
.blocks
= rport
->frag_count
;
2728 info
.ptr
= 0; /* not implemented */
2729 rport
->frag_count
= 0;
2731 spin_unlock_irqrestore(&rport
->lock
, flags
);
2732 if (copy_to_user((void *) arg
, &info
, sizeof info
))
2736 case SNDCTL_DSP_GETOPTR
: /* _SIOR ('P',18, count_info) */
2737 DBGX("SNDCTL_DSP_GETOPTR\n");
2740 spin_lock_irqsave(&wport
->lock
, flags
);
2743 if (wport
->hwstate
== HW_RUNNING
) {
2744 ASSERT(wport
->swstate
== SW_RUN
);
2745 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2746 info
.bytes
= ustmsc
.msc
- wport
->MSC_offset
;
2747 info
.bytes
*= wport
->frame_size
;
2749 info
.bytes
= wport
->byte_count
;
2751 info
.blocks
= wport
->frag_count
;
2752 info
.ptr
= 0; /* not implemented */
2753 wport
->frag_count
= 0;
2755 spin_unlock_irqrestore(&wport
->lock
, flags
);
2756 if (copy_to_user((void *) arg
, &info
, sizeof info
))
2760 case SNDCTL_DSP_GETODELAY
: /* _SIOR ('P', 23, int) */
2761 DBGX("SNDCTL_DSP_GETODELAY\n");
2764 spin_lock_irqsave(&wport
->lock
, flags
);
2766 int fsize
= wport
->frame_size
;
2767 ival
= wport
->swb_i_avail
/ fsize
;
2768 if (wport
->hwstate
== HW_RUNNING
) {
2769 int swptr
, hwptr
, hwframes
, hwbytes
, hwsize
;
2773 hwsize
= wport
->hwbuf_size
;
2774 swptr
= li_read_swptr(&wport
->chan
);
2775 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2776 hwframes
= ustmsc
.msc
- wport
->MSC_offset
;
2777 totalhwbytes
= hwframes
* fsize
;
2778 hwptr
= totalhwbytes
% hwsize
;
2779 hwbytes
= (swptr
- hwptr
+ hwsize
) % hwsize
;
2780 ival
+= hwbytes
/ fsize
;
2783 spin_unlock_irqrestore(&wport
->lock
, flags
);
2784 return put_user(ival
, (int *) arg
);
2786 case SNDCTL_DSP_PROFILE
: /* _SIOW ('P', 23, int) */
2787 DBGX("SNDCTL_DSP_PROFILE\n");
2790 * Thomas Sailer explains SNDCTL_DSP_PROFILE
2791 * (private email, March 24, 1999):
2793 * This gives the sound driver a hint on what it
2794 * should do with partial fragments
2795 * (i.e. fragments partially filled with write).
2796 * This can direct the driver to zero them or
2797 * leave them alone. But don't ask me what this
2798 * is good for, my driver just zeroes the last
2799 * fragment before the receiver stops, no idea
2800 * what good for any other behaviour could
2801 * be. Implementing it as NOP seems safe.
2806 case SNDCTL_DSP_GETTRIGGER
: /* _SIOR ('P',16, int) */
2807 DBGX("SNDCTL_DSP_GETTRIGGER\n");
2810 spin_lock_irqsave(&rport
->lock
, flags
);
2812 if (!(rport
->flags
& DISABLED
))
2813 ival
|= PCM_ENABLE_INPUT
;
2815 spin_unlock_irqrestore(&rport
->lock
, flags
);
2818 spin_lock_irqsave(&wport
->lock
, flags
);
2820 if (!(wport
->flags
& DISABLED
))
2821 ival
|= PCM_ENABLE_OUTPUT
;
2823 spin_unlock_irqrestore(&wport
->lock
, flags
);
2825 return put_user(ival
, (int *) arg
);
2827 case SNDCTL_DSP_SETTRIGGER
: /* _SIOW ('P',16, int) */
2828 if (get_user(ival
, (int *) arg
))
2830 DBGX("SNDCTL_DSP_SETTRIGGER %d\n", ival
);
2833 * If user is disabling I/O and port is not in initial
2834 * state, fail with EINVAL.
2837 if (((rport
&& !(ival
& PCM_ENABLE_INPUT
)) ||
2838 (wport
&& !(ival
& PCM_ENABLE_OUTPUT
))) &&
2839 aport
->swstate
!= SW_INITIAL
)
2843 vwsnd_port_hwstate_t hwstate
;
2844 spin_lock_irqsave(&rport
->lock
, flags
);
2846 hwstate
= rport
->hwstate
;
2847 if (ival
& PCM_ENABLE_INPUT
)
2848 rport
->flags
&= ~DISABLED
;
2850 rport
->flags
|= DISABLED
;
2852 spin_unlock_irqrestore(&rport
->lock
, flags
);
2853 if (hwstate
!= HW_RUNNING
&& ival
& PCM_ENABLE_INPUT
) {
2855 if (rport
->swstate
== SW_INITIAL
)
2856 pcm_setup(devc
, rport
, wport
);
2858 li_activate_dma(&rport
->chan
);
2862 vwsnd_port_flags_t pflags
;
2863 spin_lock_irqsave(&wport
->lock
, flags
);
2865 pflags
= wport
->flags
;
2866 if (ival
& PCM_ENABLE_OUTPUT
)
2867 wport
->flags
&= ~DISABLED
;
2869 wport
->flags
|= DISABLED
;
2871 spin_unlock_irqrestore(&wport
->lock
, flags
);
2872 if (pflags
& DISABLED
&& ival
& PCM_ENABLE_OUTPUT
) {
2873 if (wport
->swstate
== SW_RUN
)
2874 pcm_output(devc
, 0, 0);
2880 DBGP("unknown ioctl 0x%x\n", cmd
);
2883 DBGP("unimplemented ioctl 0x%x\n", cmd
);
2887 static int vwsnd_audio_ioctl(struct inode
*inode
,
2892 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2895 mutex_lock(&devc
->io_mutex
);
2896 ret
= vwsnd_audio_do_ioctl(inode
, file
, cmd
, arg
);
2897 mutex_unlock(&devc
->io_mutex
);
2903 static int vwsnd_audio_mmap(struct file
*file
, struct vm_area_struct
*vma
)
2905 DBGE("(file=0x%p, vma=0x%p)\n", file
, vma
);
2910 * Open the audio device for read and/or write.
2912 * Returns 0 on success, -errno on failure.
2915 static int vwsnd_audio_open(struct inode
*inode
, struct file
*file
)
2918 int minor
= iminor(inode
);
2921 DBGE("(inode=0x%p, file=0x%p)\n", inode
, file
);
2924 for (devc
= vwsnd_dev_list
; devc
; devc
= devc
->next_dev
)
2925 if ((devc
->audio_minor
& ~0x0F) == (minor
& ~0x0F))
2933 mutex_lock(&devc
->open_mutex
);
2934 while (devc
->open_mode
& file
->f_mode
) {
2935 mutex_unlock(&devc
->open_mutex
);
2936 if (file
->f_flags
& O_NONBLOCK
) {
2940 interruptible_sleep_on(&devc
->open_wait
);
2941 if (signal_pending(current
)) {
2943 return -ERESTARTSYS
;
2945 mutex_lock(&devc
->open_mutex
);
2947 devc
->open_mode
|= file
->f_mode
& (FMODE_READ
| FMODE_WRITE
);
2948 mutex_unlock(&devc
->open_mutex
);
2950 /* get default sample format from minor number. */
2953 if ((minor
& 0xF) == SND_DEV_DSP
)
2954 sw_samplefmt
= AFMT_U8
;
2955 else if ((minor
& 0xF) == SND_DEV_AUDIO
)
2956 sw_samplefmt
= AFMT_MU_LAW
;
2957 else if ((minor
& 0xF) == SND_DEV_DSP16
)
2958 sw_samplefmt
= AFMT_S16_LE
;
2962 /* Initialize vwsnd_ports. */
2964 mutex_lock(&devc
->io_mutex
);
2966 if (file
->f_mode
& FMODE_READ
) {
2967 devc
->rport
.swstate
= SW_INITIAL
;
2968 devc
->rport
.flags
= 0;
2969 devc
->rport
.sw_channels
= 1;
2970 devc
->rport
.sw_samplefmt
= sw_samplefmt
;
2971 devc
->rport
.sw_framerate
= 8000;
2972 devc
->rport
.sw_fragshift
= DEFAULT_FRAGSHIFT
;
2973 devc
->rport
.sw_fragcount
= DEFAULT_FRAGCOUNT
;
2974 devc
->rport
.sw_subdivshift
= DEFAULT_SUBDIVSHIFT
;
2975 devc
->rport
.byte_count
= 0;
2976 devc
->rport
.frag_count
= 0;
2978 if (file
->f_mode
& FMODE_WRITE
) {
2979 devc
->wport
.swstate
= SW_INITIAL
;
2980 devc
->wport
.flags
= 0;
2981 devc
->wport
.sw_channels
= 1;
2982 devc
->wport
.sw_samplefmt
= sw_samplefmt
;
2983 devc
->wport
.sw_framerate
= 8000;
2984 devc
->wport
.sw_fragshift
= DEFAULT_FRAGSHIFT
;
2985 devc
->wport
.sw_fragcount
= DEFAULT_FRAGCOUNT
;
2986 devc
->wport
.sw_subdivshift
= DEFAULT_SUBDIVSHIFT
;
2987 devc
->wport
.byte_count
= 0;
2988 devc
->wport
.frag_count
= 0;
2991 mutex_unlock(&devc
->io_mutex
);
2993 file
->private_data
= devc
;
2999 * Release (close) the audio device.
3002 static int vwsnd_audio_release(struct inode
*inode
, struct file
*file
)
3004 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
3005 vwsnd_port_t
*wport
= NULL
, *rport
= NULL
;
3009 mutex_lock(&devc
->io_mutex
);
3011 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3013 if (file
->f_mode
& FMODE_READ
)
3014 rport
= &devc
->rport
;
3015 if (file
->f_mode
& FMODE_WRITE
) {
3016 wport
= &devc
->wport
;
3017 pcm_flush_frag(devc
);
3018 pcm_write_sync(devc
);
3020 pcm_shutdown(devc
, rport
, wport
);
3022 rport
->swstate
= SW_OFF
;
3024 wport
->swstate
= SW_OFF
;
3026 mutex_unlock(&devc
->io_mutex
);
3028 mutex_lock(&devc
->open_mutex
);
3030 devc
->open_mode
&= ~file
->f_mode
;
3032 mutex_unlock(&devc
->open_mutex
);
3033 wake_up(&devc
->open_wait
);
3040 static struct file_operations vwsnd_audio_fops
= {
3041 .owner
= THIS_MODULE
,
3042 .llseek
= no_llseek
,
3043 .read
= vwsnd_audio_read
,
3044 .write
= vwsnd_audio_write
,
3045 .poll
= vwsnd_audio_poll
,
3046 .ioctl
= vwsnd_audio_ioctl
,
3047 .mmap
= vwsnd_audio_mmap
,
3048 .open
= vwsnd_audio_open
,
3049 .release
= vwsnd_audio_release
,
3052 /*****************************************************************************/
3055 /* open the mixer device. */
3057 static int vwsnd_mixer_open(struct inode
*inode
, struct file
*file
)
3061 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3064 for (devc
= vwsnd_dev_list
; devc
; devc
= devc
->next_dev
)
3065 if (devc
->mixer_minor
== iminor(inode
))
3072 file
->private_data
= devc
;
3076 /* release (close) the mixer device. */
3078 static int vwsnd_mixer_release(struct inode
*inode
, struct file
*file
)
3080 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3085 /* mixer_read_ioctl handles all read ioctls on the mixer device. */
3087 static int mixer_read_ioctl(vwsnd_dev_t
*devc
, unsigned int nr
, void __user
*arg
)
3091 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc
, nr
, arg
);
3094 case SOUND_MIXER_CAPS
:
3095 val
= SOUND_CAP_EXCL_INPUT
;
3098 case SOUND_MIXER_DEVMASK
:
3099 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3100 SOUND_MASK_MIC
| SOUND_MASK_CD
| SOUND_MASK_RECLEV
);
3103 case SOUND_MIXER_STEREODEVS
:
3104 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3105 SOUND_MASK_MIC
| SOUND_MASK_CD
| SOUND_MASK_RECLEV
);
3108 case SOUND_MIXER_OUTMASK
:
3109 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3110 SOUND_MASK_MIC
| SOUND_MASK_CD
);
3113 case SOUND_MIXER_RECMASK
:
3114 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3115 SOUND_MASK_MIC
| SOUND_MASK_CD
);
3118 case SOUND_MIXER_PCM
:
3119 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_PCM
);
3122 case SOUND_MIXER_LINE
:
3123 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_LINE
);
3126 case SOUND_MIXER_MIC
:
3127 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_MIC
);
3130 case SOUND_MIXER_CD
:
3131 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_CD
);
3134 case SOUND_MIXER_RECLEV
:
3135 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_RECLEV
);
3138 case SOUND_MIXER_RECSRC
:
3139 val
= ad1843_get_recsrc(&devc
->lith
);
3142 case SOUND_MIXER_OUTSRC
:
3143 val
= ad1843_get_outsrc(&devc
->lith
);
3149 return put_user(val
, (int __user
*) arg
);
3152 /* mixer_write_ioctl handles all write ioctls on the mixer device. */
3154 static int mixer_write_ioctl(vwsnd_dev_t
*devc
, unsigned int nr
, void __user
*arg
)
3159 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc
, nr
, arg
);
3161 err
= get_user(val
, (int __user
*) arg
);
3165 case SOUND_MIXER_PCM
:
3166 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_PCM
, val
);
3169 case SOUND_MIXER_LINE
:
3170 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_LINE
, val
);
3173 case SOUND_MIXER_MIC
:
3174 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_MIC
, val
);
3177 case SOUND_MIXER_CD
:
3178 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_CD
, val
);
3181 case SOUND_MIXER_RECLEV
:
3182 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_RECLEV
, val
);
3185 case SOUND_MIXER_RECSRC
:
3186 if (devc
->rport
.swbuf
|| devc
->wport
.swbuf
)
3187 return -EBUSY
; /* can't change recsrc while running */
3188 val
= ad1843_set_recsrc(&devc
->lith
, val
);
3191 case SOUND_MIXER_OUTSRC
:
3192 val
= ad1843_set_outsrc(&devc
->lith
, val
);
3200 return put_user(val
, (int __user
*) arg
);
3203 /* This is the ioctl entry to the mixer driver. */
3205 static int vwsnd_mixer_ioctl(struct inode
*ioctl
,
3210 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
3211 const unsigned int nrmask
= _IOC_NRMASK
<< _IOC_NRSHIFT
;
3212 const unsigned int nr
= (cmd
& nrmask
) >> _IOC_NRSHIFT
;
3215 DBGEV("(devc=0x%p, cmd=0x%x, arg=0x%lx)\n", devc
, cmd
, arg
);
3217 mutex_lock(&devc
->mix_mutex
);
3219 if ((cmd
& ~nrmask
) == MIXER_READ(0))
3220 retval
= mixer_read_ioctl(devc
, nr
, (void __user
*) arg
);
3221 else if ((cmd
& ~nrmask
) == MIXER_WRITE(0))
3222 retval
= mixer_write_ioctl(devc
, nr
, (void __user
*) arg
);
3226 mutex_unlock(&devc
->mix_mutex
);
3230 static struct file_operations vwsnd_mixer_fops
= {
3231 .owner
= THIS_MODULE
,
3232 .llseek
= no_llseek
,
3233 .ioctl
= vwsnd_mixer_ioctl
,
3234 .open
= vwsnd_mixer_open
,
3235 .release
= vwsnd_mixer_release
,
3238 /*****************************************************************************/
3239 /* probe/attach/unload */
3241 /* driver probe routine. Return nonzero if hardware is found. */
3243 static int __init
probe_vwsnd(struct address_info
*hw_config
)
3247 unsigned long later
;
3249 DBGEV("(hw_config=0x%p)\n", hw_config
);
3251 /* XXX verify lithium present (to prevent crash on non-vw) */
3253 if (li_create(&lith
, hw_config
->io_base
) != 0) {
3254 printk(KERN_WARNING
"probe_vwsnd: can't map lithium\n");
3257 later
= jiffies
+ 2;
3258 li_writel(&lith
, LI_HOST_CONTROLLER
, LI_HC_LINK_ENABLE
);
3260 w
= li_readl(&lith
, LI_HOST_CONTROLLER
);
3261 } while (w
== LI_HC_LINK_ENABLE
&& time_before(jiffies
, later
));
3265 DBGPV("HC = 0x%04x\n", w
);
3267 if ((w
== LI_HC_LINK_ENABLE
) || (w
& LI_HC_LINK_CODEC
)) {
3269 /* This may indicate a beta machine with no audio,
3270 * or a future machine with different audio.
3271 * On beta-release 320 w/ no audio, HC == 0x4000 */
3273 printk(KERN_WARNING
"probe_vwsnd: audio codec not found\n");
3277 if (w
& LI_HC_LINK_FAILURE
) {
3278 printk(KERN_WARNING
"probe_vwsnd: can't init audio codec\n");
3282 printk(KERN_INFO
"vwsnd: lithium audio at mmio %#x irq %d\n",
3283 hw_config
->io_base
, hw_config
->irq
);
3289 * driver attach routine. Initialize driver data structures and
3290 * initialize hardware. A new vwsnd_dev_t is allocated and put
3291 * onto the global list, vwsnd_dev_list.
3293 * Return +minor_dev on success, -errno on failure.
3296 static int __init
attach_vwsnd(struct address_info
*hw_config
)
3298 vwsnd_dev_t
*devc
= NULL
;
3301 DBGEV("(hw_config=0x%p)\n", hw_config
);
3303 devc
= kmalloc(sizeof (vwsnd_dev_t
), GFP_KERNEL
);
3307 err
= li_create(&devc
->lith
, hw_config
->io_base
);
3311 init_waitqueue_head(&devc
->open_wait
);
3313 devc
->rport
.hwbuf_size
= HWBUF_SIZE
;
3314 devc
->rport
.hwbuf_vaddr
= __get_free_pages(GFP_KERNEL
, HWBUF_ORDER
);
3315 if (!devc
->rport
.hwbuf_vaddr
)
3317 devc
->rport
.hwbuf
= (void *) devc
->rport
.hwbuf_vaddr
;
3318 devc
->rport
.hwbuf_paddr
= virt_to_phys(devc
->rport
.hwbuf
);
3321 * Quote from the NT driver:
3323 * // WARNING!!! HACK to setup output dma!!!
3324 * // This is required because even on output there is some data
3325 * // trickling into the input DMA channel. This is a bug in the
3326 * // Lithium microcode.
3329 * We set the input side's DMA base address here. It will remain
3330 * valid until the driver is unloaded.
3333 li_writel(&devc
->lith
, LI_COMM1_BASE
,
3334 devc
->rport
.hwbuf_paddr
>> 8 | 1 << (37 - 8));
3336 devc
->wport
.hwbuf_size
= HWBUF_SIZE
;
3337 devc
->wport
.hwbuf_vaddr
= __get_free_pages(GFP_KERNEL
, HWBUF_ORDER
);
3338 if (!devc
->wport
.hwbuf_vaddr
)
3340 devc
->wport
.hwbuf
= (void *) devc
->wport
.hwbuf_vaddr
;
3341 devc
->wport
.hwbuf_paddr
= virt_to_phys(devc
->wport
.hwbuf
);
3342 DBGP("wport hwbuf = 0x%p\n", devc
->wport
.hwbuf
);
3345 err
= ad1843_init(&devc
->lith
);
3350 /* install interrupt handler */
3352 err
= request_irq(hw_config
->irq
, vwsnd_audio_intr
, 0, "vwsnd", devc
);
3356 /* register this device's drivers. */
3358 devc
->audio_minor
= register_sound_dsp(&vwsnd_audio_fops
, -1);
3359 if ((err
= devc
->audio_minor
) < 0) {
3360 DBGDO(printk(KERN_WARNING
3361 "attach_vwsnd: register_sound_dsp error %d\n",
3365 devc
->mixer_minor
= register_sound_mixer(&vwsnd_mixer_fops
,
3366 devc
->audio_minor
>> 4);
3367 if ((err
= devc
->mixer_minor
) < 0) {
3368 DBGDO(printk(KERN_WARNING
3369 "attach_vwsnd: register_sound_mixer error %d\n",
3374 /* Squirrel away device indices for unload routine. */
3376 hw_config
->slots
[0] = devc
->audio_minor
;
3378 /* Initialize as much of *devc as possible */
3380 mutex_init(&devc
->open_mutex
);
3381 mutex_init(&devc
->io_mutex
);
3382 mutex_init(&devc
->mix_mutex
);
3383 devc
->open_mode
= 0;
3384 spin_lock_init(&devc
->rport
.lock
);
3385 init_waitqueue_head(&devc
->rport
.queue
);
3386 devc
->rport
.swstate
= SW_OFF
;
3387 devc
->rport
.hwstate
= HW_STOPPED
;
3388 devc
->rport
.flags
= 0;
3389 devc
->rport
.swbuf
= NULL
;
3390 spin_lock_init(&devc
->wport
.lock
);
3391 init_waitqueue_head(&devc
->wport
.queue
);
3392 devc
->wport
.swstate
= SW_OFF
;
3393 devc
->wport
.hwstate
= HW_STOPPED
;
3394 devc
->wport
.flags
= 0;
3395 devc
->wport
.swbuf
= NULL
;
3397 /* Success. Link us onto the local device list. */
3399 devc
->next_dev
= vwsnd_dev_list
;
3400 vwsnd_dev_list
= devc
;
3401 return devc
->audio_minor
;
3403 /* So many ways to fail. Undo what we did. */
3406 unregister_sound_dsp(devc
->audio_minor
);
3408 free_irq(hw_config
->irq
, devc
);
3411 free_pages(devc
->wport
.hwbuf_vaddr
, HWBUF_ORDER
);
3413 free_pages(devc
->rport
.hwbuf_vaddr
, HWBUF_ORDER
);
3415 li_destroy(&devc
->lith
);
3422 static int __exit
unload_vwsnd(struct address_info
*hw_config
)
3424 vwsnd_dev_t
*devc
, **devcp
;
3428 devcp
= &vwsnd_dev_list
;
3429 while ((devc
= *devcp
)) {
3430 if (devc
->audio_minor
== hw_config
->slots
[0]) {
3431 *devcp
= devc
->next_dev
;
3434 devcp
= &devc
->next_dev
;
3440 unregister_sound_mixer(devc
->mixer_minor
);
3441 unregister_sound_dsp(devc
->audio_minor
);
3442 free_irq(hw_config
->irq
, devc
);
3443 free_pages(devc
->wport
.hwbuf_vaddr
, HWBUF_ORDER
);
3444 free_pages(devc
->rport
.hwbuf_vaddr
, HWBUF_ORDER
);
3445 li_destroy(&devc
->lith
);
3451 /*****************************************************************************/
3452 /* initialization and loadable kernel module interface */
3454 static struct address_info the_hw_config
= {
3455 0xFF001000, /* lithium phys addr */
3456 CO_IRQ(CO_APIC_LI_AUDIO
) /* irq */
3459 MODULE_DESCRIPTION("SGI Visual Workstation sound module");
3460 MODULE_AUTHOR("Bob Miller <kbob@sgi.com>");
3461 MODULE_LICENSE("GPL");
3463 static int __init
init_vwsnd(void)
3468 DBGXV("sound::vwsnd::init_module()\n");
3470 if (!probe_vwsnd(&the_hw_config
))
3473 err
= attach_vwsnd(&the_hw_config
);
3479 static void __exit
cleanup_vwsnd(void)
3481 DBGX("sound::vwsnd::cleanup_module()\n");
3483 unload_vwsnd(&the_hw_config
);
3486 module_init(init_vwsnd
);
3487 module_exit(cleanup_vwsnd
);