1 /*****************************************************************************
5 * $Date: 2005/03/23 07:41:27 $ *
7 * Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
22 * http://www.chelsio.com *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
27 * Maintainers: maintainers@chelsio.com *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
38 ****************************************************************************/
51 * t1_wait_op_done - wait until an operation is completed
52 * @adapter: the adapter performing the operation
53 * @reg: the register to check for completion
54 * @mask: a single-bit field within @reg that indicates completion
55 * @polarity: the value of the field when the operation is completed
56 * @attempts: number of check iterations
57 * @delay: delay in usecs between iterations
59 * Wait until an operation is completed by checking a bit in a register
60 * up to @attempts times. Returns %0 if the operation completes and %1
63 static int t1_wait_op_done(adapter_t
*adapter
, int reg
, u32 mask
, int polarity
,
64 int attempts
, int delay
)
67 u32 val
= t1_read_reg_4(adapter
, reg
) & mask
;
69 if (!!val
== polarity
)
78 #define TPI_ATTEMPTS 50
81 * Write a register over the TPI interface (unlocked and locked versions).
83 static int __t1_tpi_write(adapter_t
*adapter
, u32 addr
, u32 value
)
87 t1_write_reg_4(adapter
, A_TPI_ADDR
, addr
);
88 t1_write_reg_4(adapter
, A_TPI_WR_DATA
, value
);
89 t1_write_reg_4(adapter
, A_TPI_CSR
, F_TPIWR
);
91 tpi_busy
= t1_wait_op_done(adapter
, A_TPI_CSR
, F_TPIRDY
, 1,
94 CH_ALERT("%s: TPI write to 0x%x failed\n",
99 int t1_tpi_write(adapter_t
*adapter
, u32 addr
, u32 value
)
104 ret
= __t1_tpi_write(adapter
, addr
, value
);
110 * Read a register over the TPI interface (unlocked and locked versions).
112 static int __t1_tpi_read(adapter_t
*adapter
, u32 addr
, u32
*valp
)
116 t1_write_reg_4(adapter
, A_TPI_ADDR
, addr
);
117 t1_write_reg_4(adapter
, A_TPI_CSR
, 0);
119 tpi_busy
= t1_wait_op_done(adapter
, A_TPI_CSR
, F_TPIRDY
, 1,
122 CH_ALERT("%s: TPI read from 0x%x failed\n",
123 adapter
->name
, addr
);
125 *valp
= t1_read_reg_4(adapter
, A_TPI_RD_DATA
);
129 int t1_tpi_read(adapter_t
*adapter
, u32 addr
, u32
*valp
)
134 ret
= __t1_tpi_read(adapter
, addr
, valp
);
140 * Set a TPI parameter.
142 static void t1_tpi_par(adapter_t
*adapter
, u32 value
)
144 t1_write_reg_4(adapter
, A_TPI_PAR
, V_TPIPAR(value
));
148 * Called when a port's link settings change to propagate the new values to the
149 * associated PHY and MAC. After performing the common tasks it invokes an
150 * OS-specific handler.
152 /* static */ void link_changed(adapter_t
*adapter
, int port_id
)
154 int link_ok
, speed
, duplex
, fc
;
155 struct cphy
*phy
= adapter
->port
[port_id
].phy
;
156 struct link_config
*lc
= &adapter
->port
[port_id
].link_config
;
158 phy
->ops
->get_link_status(phy
, &link_ok
, &speed
, &duplex
, &fc
);
160 lc
->speed
= speed
< 0 ? SPEED_INVALID
: speed
;
161 lc
->duplex
= duplex
< 0 ? DUPLEX_INVALID
: duplex
;
162 if (!(lc
->requested_fc
& PAUSE_AUTONEG
))
163 fc
= lc
->requested_fc
& (PAUSE_RX
| PAUSE_TX
);
165 if (link_ok
&& speed
>= 0 && lc
->autoneg
== AUTONEG_ENABLE
) {
166 /* Set MAC speed, duplex, and flow control to match PHY. */
167 struct cmac
*mac
= adapter
->port
[port_id
].mac
;
169 mac
->ops
->set_speed_duplex_fc(mac
, speed
, duplex
, fc
);
170 lc
->fc
= (unsigned char)fc
;
172 t1_link_changed(adapter
, port_id
, link_ok
, speed
, duplex
, fc
);
175 static int t1_pci_intr_handler(adapter_t
*adapter
)
179 pci_read_config_dword(adapter
->pdev
, A_PCICFG_INTR_CAUSE
, &pcix_cause
);
182 pci_write_config_dword(adapter
->pdev
, A_PCICFG_INTR_CAUSE
,
184 t1_fatal_err(adapter
); /* PCI errors are fatal */
191 * Wait until Elmer's MI1 interface is ready for new operations.
193 static int mi1_wait_until_ready(adapter_t
*adapter
, int mi1_reg
)
195 int attempts
= 100, busy
;
200 __t1_tpi_read(adapter
, mi1_reg
, &val
);
201 busy
= val
& F_MI1_OP_BUSY
;
204 } while (busy
&& --attempts
);
206 CH_ALERT("%s: MDIO operation timed out\n",
212 * MI1 MDIO initialization.
214 static void mi1_mdio_init(adapter_t
*adapter
, const struct board_info
*bi
)
216 u32 clkdiv
= bi
->clock_elmer0
/ (2 * bi
->mdio_mdc
) - 1;
217 u32 val
= F_MI1_PREAMBLE_ENABLE
| V_MI1_MDI_INVERT(bi
->mdio_mdiinv
) |
218 V_MI1_MDI_ENABLE(bi
->mdio_mdien
) | V_MI1_CLK_DIV(clkdiv
);
220 if (!(bi
->caps
& SUPPORTED_10000baseT_Full
))
222 t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_CFG
, val
);
225 static int mi1_mdio_ext_read(adapter_t
*adapter
, int phy_addr
, int mmd_addr
,
226 int reg_addr
, unsigned int *valp
)
228 u32 addr
= V_MI1_REG_ADDR(mmd_addr
) | V_MI1_PHY_ADDR(phy_addr
);
232 /* Write the address we want. */
233 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_ADDR
, addr
);
234 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_DATA
, reg_addr
);
235 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_OP
,
236 MI1_OP_INDIRECT_ADDRESS
);
237 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
239 /* Write the operation we want. */
240 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_OP
, MI1_OP_INDIRECT_READ
);
241 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
244 __t1_tpi_read(adapter
, A_ELMER0_PORT0_MI1_DATA
, valp
);
249 static int mi1_mdio_ext_write(adapter_t
*adapter
, int phy_addr
, int mmd_addr
,
250 int reg_addr
, unsigned int val
)
252 u32 addr
= V_MI1_REG_ADDR(mmd_addr
) | V_MI1_PHY_ADDR(phy_addr
);
256 /* Write the address we want. */
257 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_ADDR
, addr
);
258 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_DATA
, reg_addr
);
259 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_OP
,
260 MI1_OP_INDIRECT_ADDRESS
);
261 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
263 /* Write the data. */
264 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_DATA
, val
);
265 __t1_tpi_write(adapter
, A_ELMER0_PORT0_MI1_OP
, MI1_OP_INDIRECT_WRITE
);
266 mi1_wait_until_ready(adapter
, A_ELMER0_PORT0_MI1_OP
);
271 static struct mdio_ops mi1_mdio_ext_ops
= {
283 static struct board_info t1_board
[] = {
285 { CHBT_BOARD_N110
, 1/*ports#*/,
286 SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
/*caps*/, CHBT_TERM_T1
,
287 CHBT_MAC_PM3393
, CHBT_PHY_88X2010
,
288 125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
289 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
290 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops
,
291 &t1_mv88x201x_ops
, &mi1_mdio_ext_ops
,
292 "Chelsio N110 1x10GBaseX NIC" },
294 { CHBT_BOARD_N210
, 1/*ports#*/,
295 SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
/*caps*/, CHBT_TERM_T2
,
296 CHBT_MAC_PM3393
, CHBT_PHY_88X2010
,
297 125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
298 1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
299 0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops
,
300 &t1_mv88x201x_ops
, &mi1_mdio_ext_ops
,
301 "Chelsio N210 1x10GBaseX NIC" },
305 struct pci_device_id t1_pci_tbl
[] = {
306 CH_DEVICE(7, 0, CH_BRD_N110_1F
),
307 CH_DEVICE(10, 1, CH_BRD_N210_1F
),
312 * Return the board_info structure with a given index. Out-of-range indices
315 const struct board_info
*t1_get_board_info(unsigned int board_id
)
317 return board_id
< DIMOF(t1_board
) ? &t1_board
[board_id
] : NULL
;
320 struct chelsio_vpd_t
{
322 u8 serial_number
[16];
323 u8 mac_base_address
[6];
324 u8 pad
[2]; /* make multiple-of-4 size requirement explicit */
327 #define EEPROMSIZE (8 * 1024)
328 #define EEPROM_MAX_POLL 4
331 * Read SEEPROM. A zero is written to the flag register when the addres is
332 * written to the Control register. The hardware device will set the flag to a
333 * one when 4B have been transferred to the Data register.
335 int t1_seeprom_read(adapter_t
*adapter
, u32 addr
, u32
*data
)
337 int i
= EEPROM_MAX_POLL
;
340 if (addr
>= EEPROMSIZE
|| (addr
& 3))
343 pci_write_config_word(adapter
->pdev
, A_PCICFG_VPD_ADDR
, (u16
)addr
);
346 pci_read_config_word(adapter
->pdev
, A_PCICFG_VPD_ADDR
, &val
);
347 } while (!(val
& F_VPD_OP_FLAG
) && --i
);
349 if (!(val
& F_VPD_OP_FLAG
)) {
350 CH_ERR("%s: reading EEPROM address 0x%x failed\n",
351 adapter
->name
, addr
);
354 pci_read_config_dword(adapter
->pdev
, A_PCICFG_VPD_DATA
, data
);
355 *data
= le32_to_cpu(*data
);
359 static int t1_eeprom_vpd_get(adapter_t
*adapter
, struct chelsio_vpd_t
*vpd
)
363 for (addr
= 0; !ret
&& addr
< sizeof(*vpd
); addr
+= sizeof(u32
))
364 ret
= t1_seeprom_read(adapter
, addr
,
365 (u32
*)((u8
*)vpd
+ addr
));
371 * Read a port's MAC address from the VPD ROM.
373 static int vpd_macaddress_get(adapter_t
*adapter
, int index
, u8 mac_addr
[])
375 struct chelsio_vpd_t vpd
;
377 if (t1_eeprom_vpd_get(adapter
, &vpd
))
379 memcpy(mac_addr
, vpd
.mac_base_address
, 5);
380 mac_addr
[5] = vpd
.mac_base_address
[5] + index
;
385 * Set up the MAC/PHY according to the requested link settings.
387 * If the PHY can auto-negotiate first decide what to advertise, then
388 * enable/disable auto-negotiation as desired and reset.
390 * If the PHY does not auto-negotiate we just reset it.
392 * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
393 * otherwise do it later based on the outcome of auto-negotiation.
395 int t1_link_start(struct cphy
*phy
, struct cmac
*mac
, struct link_config
*lc
)
397 unsigned int fc
= lc
->requested_fc
& (PAUSE_RX
| PAUSE_TX
);
399 if (lc
->supported
& SUPPORTED_Autoneg
) {
400 lc
->advertising
&= ~(ADVERTISED_ASYM_PAUSE
| ADVERTISED_PAUSE
);
402 lc
->advertising
|= ADVERTISED_ASYM_PAUSE
;
403 if (fc
== (PAUSE_RX
| PAUSE_TX
))
404 lc
->advertising
|= ADVERTISED_PAUSE
;
406 phy
->ops
->advertise(phy
, lc
->advertising
);
408 if (lc
->autoneg
== AUTONEG_DISABLE
) {
409 lc
->speed
= lc
->requested_speed
;
410 lc
->duplex
= lc
->requested_duplex
;
411 lc
->fc
= (unsigned char)fc
;
412 mac
->ops
->set_speed_duplex_fc(mac
, lc
->speed
,
414 /* Also disables autoneg */
415 phy
->ops
->set_speed_duplex(phy
, lc
->speed
, lc
->duplex
);
416 phy
->ops
->reset(phy
, 0);
418 phy
->ops
->autoneg_enable(phy
); /* also resets PHY */
420 mac
->ops
->set_speed_duplex_fc(mac
, -1, -1, fc
);
421 lc
->fc
= (unsigned char)fc
;
422 phy
->ops
->reset(phy
, 0);
428 * External interrupt handler for boards using elmer0.
430 int elmer0_ext_intr_handler(adapter_t
*adapter
)
436 t1_tpi_read(adapter
, A_ELMER0_INT_CAUSE
, &cause
);
438 switch (board_info(adapter
)->board
) {
439 case CHBT_BOARD_CHT210
:
440 case CHBT_BOARD_N210
:
441 case CHBT_BOARD_N110
:
442 if (cause
& ELMER0_GP_BIT6
) { /* Marvell 88x2010 interrupt */
443 phy
= adapter
->port
[0].phy
;
444 phy_cause
= phy
->ops
->interrupt_handler(phy
);
445 if (phy_cause
& cphy_cause_link_change
)
446 link_changed(adapter
, 0);
449 case CHBT_BOARD_8000
:
450 case CHBT_BOARD_CHT110
:
451 CH_DBG(adapter
, INTR
, "External interrupt cause 0x%x\n",
453 if (cause
& ELMER0_GP_BIT1
) { /* PMC3393 INTB */
454 struct cmac
*mac
= adapter
->port
[0].mac
;
456 mac
->ops
->interrupt_handler(mac
);
458 if (cause
& ELMER0_GP_BIT5
) { /* XPAK MOD_DETECT */
461 t1_tpi_read(adapter
, A_ELMER0_GPI_STAT
, &mod_detect
);
462 CH_MSG(adapter
, INFO
, LINK
, "XPAK %s\n",
463 mod_detect
? "removed" : "inserted");
467 t1_tpi_write(adapter
, A_ELMER0_INT_CAUSE
, cause
);
471 /* Enables all interrupts. */
472 void t1_interrupts_enable(adapter_t
*adapter
)
476 adapter
->slow_intr_mask
= F_PL_INTR_SGE_ERR
| F_PL_INTR_TP
;
478 t1_sge_intr_enable(adapter
->sge
);
479 t1_tp_intr_enable(adapter
->tp
);
481 adapter
->slow_intr_mask
|= F_PL_INTR_ESPI
;
482 t1_espi_intr_enable(adapter
->espi
);
485 /* Enable MAC/PHY interrupts for each port. */
486 for_each_port(adapter
, i
) {
487 adapter
->port
[i
].mac
->ops
->interrupt_enable(adapter
->port
[i
].mac
);
488 adapter
->port
[i
].phy
->ops
->interrupt_enable(adapter
->port
[i
].phy
);
491 /* Enable PCIX & external chip interrupts on ASIC boards. */
492 if (t1_is_asic(adapter
)) {
493 u32 pl_intr
= t1_read_reg_4(adapter
, A_PL_ENABLE
);
495 /* PCI-X interrupts */
496 pci_write_config_dword(adapter
->pdev
, A_PCICFG_INTR_ENABLE
,
499 adapter
->slow_intr_mask
|= F_PL_INTR_EXT
| F_PL_INTR_PCIX
;
500 pl_intr
|= F_PL_INTR_EXT
| F_PL_INTR_PCIX
;
501 t1_write_reg_4(adapter
, A_PL_ENABLE
, pl_intr
);
505 /* Disables all interrupts. */
506 void t1_interrupts_disable(adapter_t
* adapter
)
510 t1_sge_intr_disable(adapter
->sge
);
511 t1_tp_intr_disable(adapter
->tp
);
513 t1_espi_intr_disable(adapter
->espi
);
515 /* Disable MAC/PHY interrupts for each port. */
516 for_each_port(adapter
, i
) {
517 adapter
->port
[i
].mac
->ops
->interrupt_disable(adapter
->port
[i
].mac
);
518 adapter
->port
[i
].phy
->ops
->interrupt_disable(adapter
->port
[i
].phy
);
521 /* Disable PCIX & external chip interrupts. */
522 if (t1_is_asic(adapter
))
523 t1_write_reg_4(adapter
, A_PL_ENABLE
, 0);
525 /* PCI-X interrupts */
526 pci_write_config_dword(adapter
->pdev
, A_PCICFG_INTR_ENABLE
, 0);
528 adapter
->slow_intr_mask
= 0;
531 /* Clears all interrupts */
532 void t1_interrupts_clear(adapter_t
* adapter
)
536 t1_sge_intr_clear(adapter
->sge
);
537 t1_tp_intr_clear(adapter
->tp
);
539 t1_espi_intr_clear(adapter
->espi
);
541 /* Clear MAC/PHY interrupts for each port. */
542 for_each_port(adapter
, i
) {
543 adapter
->port
[i
].mac
->ops
->interrupt_clear(adapter
->port
[i
].mac
);
544 adapter
->port
[i
].phy
->ops
->interrupt_clear(adapter
->port
[i
].phy
);
547 /* Enable interrupts for external devices. */
548 if (t1_is_asic(adapter
)) {
549 u32 pl_intr
= t1_read_reg_4(adapter
, A_PL_CAUSE
);
551 t1_write_reg_4(adapter
, A_PL_CAUSE
,
552 pl_intr
| F_PL_INTR_EXT
| F_PL_INTR_PCIX
);
555 /* PCI-X interrupts */
556 pci_write_config_dword(adapter
->pdev
, A_PCICFG_INTR_CAUSE
, 0xffffffff);
560 * Slow path interrupt handler for ASICs.
562 static int asic_slow_intr(adapter_t
*adapter
)
564 u32 cause
= t1_read_reg_4(adapter
, A_PL_CAUSE
);
566 cause
&= adapter
->slow_intr_mask
;
569 if (cause
& F_PL_INTR_SGE_ERR
)
570 t1_sge_intr_error_handler(adapter
->sge
);
571 if (cause
& F_PL_INTR_TP
)
572 t1_tp_intr_handler(adapter
->tp
);
573 if (cause
& F_PL_INTR_ESPI
)
574 t1_espi_intr_handler(adapter
->espi
);
575 if (cause
& F_PL_INTR_PCIX
)
576 t1_pci_intr_handler(adapter
);
577 if (cause
& F_PL_INTR_EXT
)
578 t1_elmer0_ext_intr(adapter
);
580 /* Clear the interrupts just processed. */
581 t1_write_reg_4(adapter
, A_PL_CAUSE
, cause
);
582 (void)t1_read_reg_4(adapter
, A_PL_CAUSE
); /* flush writes */
586 int t1_slow_intr_handler(adapter_t
*adapter
)
588 return asic_slow_intr(adapter
);
591 /* Power sequencing is a work-around for Intel's XPAKs. */
592 static void power_sequence_xpak(adapter_t
* adapter
)
598 t1_tpi_read(adapter
, A_ELMER0_GPI_STAT
, &mod_detect
);
599 if (!(ELMER0_GP_BIT5
& mod_detect
)) {
600 /* XPAK is present */
601 t1_tpi_read(adapter
, A_ELMER0_GPO
, &gpo
);
602 gpo
|= ELMER0_GP_BIT18
;
603 t1_tpi_write(adapter
, A_ELMER0_GPO
, gpo
);
607 int __devinit
t1_get_board_rev(adapter_t
*adapter
, const struct board_info
*bi
,
608 struct adapter_params
*p
)
610 p
->chip_version
= bi
->chip_term
;
611 p
->is_asic
= (p
->chip_version
!= CHBT_TERM_FPGA
);
612 if (p
->chip_version
== CHBT_TERM_T1
||
613 p
->chip_version
== CHBT_TERM_T2
||
614 p
->chip_version
== CHBT_TERM_FPGA
) {
615 u32 val
= t1_read_reg_4(adapter
, A_TP_PC_CONFIG
);
617 val
= G_TP_PC_REV(val
);
619 p
->chip_revision
= TERM_T1B
;
621 p
->chip_revision
= TERM_T2
;
630 * Enable board components other than the Chelsio chip, such as external MAC
633 static int board_init(adapter_t
*adapter
, const struct board_info
*bi
)
636 case CHBT_BOARD_8000
:
637 case CHBT_BOARD_N110
:
638 case CHBT_BOARD_N210
:
639 case CHBT_BOARD_CHT210
:
640 case CHBT_BOARD_COUGAR
:
641 t1_tpi_par(adapter
, 0xf);
642 t1_tpi_write(adapter
, A_ELMER0_GPO
, 0x800);
644 case CHBT_BOARD_CHT110
:
645 t1_tpi_par(adapter
, 0xf);
646 t1_tpi_write(adapter
, A_ELMER0_GPO
, 0x1800);
648 /* TBD XXX Might not need. This fixes a problem
649 * described in the Intel SR XPAK errata.
651 power_sequence_xpak(adapter
);
658 * Initialize and configure the Terminator HW modules. Note that external
659 * MAC and PHYs are initialized separately.
661 int t1_init_hw_modules(adapter_t
*adapter
)
664 const struct board_info
*bi
= board_info(adapter
);
667 u32 val
= t1_read_reg_4(adapter
, A_MC4_CFG
);
669 t1_write_reg_4(adapter
, A_MC4_CFG
, val
| F_READY
| F_MC4_SLOW
);
670 t1_write_reg_4(adapter
, A_MC5_CONFIG
,
671 F_M_BUS_ENABLE
| F_TCAM_RESET
);
674 if (adapter
->espi
&& t1_espi_init(adapter
->espi
, bi
->chip_mac
,
678 if (t1_tp_reset(adapter
->tp
, &adapter
->params
.tp
, bi
->clock_core
))
681 err
= t1_sge_configure(adapter
->sge
, &adapter
->params
.sge
);
691 * Determine a card's PCI mode.
693 static void __devinit
get_pci_mode(adapter_t
*adapter
, struct pci_params
*p
)
695 static unsigned short speed_map
[] = { 33, 66, 100, 133 };
698 pci_read_config_dword(adapter
->pdev
, A_PCICFG_MODE
, &pci_mode
);
699 p
->speed
= speed_map
[G_PCI_MODE_CLK(pci_mode
)];
700 p
->width
= (pci_mode
& F_PCI_MODE_64BIT
) ? 64 : 32;
701 p
->is_pcix
= (pci_mode
& F_PCI_MODE_PCIX
) != 0;
705 * Release the structures holding the SW per-Terminator-HW-module state.
707 void t1_free_sw_modules(adapter_t
*adapter
)
711 for_each_port(adapter
, i
) {
712 struct cmac
*mac
= adapter
->port
[i
].mac
;
713 struct cphy
*phy
= adapter
->port
[i
].phy
;
716 mac
->ops
->destroy(mac
);
718 phy
->ops
->destroy(phy
);
722 t1_sge_destroy(adapter
->sge
);
724 t1_tp_destroy(adapter
->tp
);
726 t1_espi_destroy(adapter
->espi
);
729 static void __devinit
init_link_config(struct link_config
*lc
,
730 const struct board_info
*bi
)
732 lc
->supported
= bi
->caps
;
733 lc
->requested_speed
= lc
->speed
= SPEED_INVALID
;
734 lc
->requested_duplex
= lc
->duplex
= DUPLEX_INVALID
;
735 lc
->requested_fc
= lc
->fc
= PAUSE_RX
| PAUSE_TX
;
736 if (lc
->supported
& SUPPORTED_Autoneg
) {
737 lc
->advertising
= lc
->supported
;
738 lc
->autoneg
= AUTONEG_ENABLE
;
739 lc
->requested_fc
|= PAUSE_AUTONEG
;
742 lc
->autoneg
= AUTONEG_DISABLE
;
748 * Allocate and initialize the data structures that hold the SW state of
749 * the Terminator HW modules.
751 int __devinit
t1_init_sw_modules(adapter_t
*adapter
,
752 const struct board_info
*bi
)
756 adapter
->params
.brd_info
= bi
;
757 adapter
->params
.nports
= bi
->port_number
;
758 adapter
->params
.stats_update_period
= bi
->gmac
->stats_update_period
;
760 adapter
->sge
= t1_sge_create(adapter
, &adapter
->params
.sge
);
762 CH_ERR("%s: SGE initialization failed\n",
769 if (bi
->espi_nports
&& !(adapter
->espi
= t1_espi_create(adapter
))) {
770 CH_ERR("%s: ESPI initialization failed\n",
775 adapter
->tp
= t1_tp_create(adapter
, &adapter
->params
.tp
);
777 CH_ERR("%s: TP initialization failed\n",
782 board_init(adapter
, bi
);
783 bi
->mdio_ops
->init(adapter
, bi
);
785 bi
->gphy
->reset(adapter
);
787 bi
->gmac
->reset(adapter
);
789 for_each_port(adapter
, i
) {
792 int phy_addr
= bi
->mdio_phybaseaddr
+ i
;
794 adapter
->port
[i
].phy
= bi
->gphy
->create(adapter
, phy_addr
,
796 if (!adapter
->port
[i
].phy
) {
797 CH_ERR("%s: PHY %d initialization failed\n",
802 adapter
->port
[i
].mac
= mac
= bi
->gmac
->create(adapter
, i
);
804 CH_ERR("%s: MAC %d initialization failed\n",
810 * Get the port's MAC addresses either from the EEPROM if one
811 * exists or the one hardcoded in the MAC.
813 if (!t1_is_asic(adapter
) || bi
->chip_mac
== CHBT_MAC_DUMMY
)
814 mac
->ops
->macaddress_get(mac
, hw_addr
);
815 else if (vpd_macaddress_get(adapter
, i
, hw_addr
)) {
816 CH_ERR("%s: could not read MAC address from VPD ROM\n",
817 port_name(adapter
, i
));
820 t1_set_hw_addr(adapter
, i
, hw_addr
);
821 init_link_config(&adapter
->port
[i
].link_config
, bi
);
824 get_pci_mode(adapter
, &adapter
->params
.pci
);
825 t1_interrupts_clear(adapter
);
829 t1_free_sw_modules(adapter
);