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Tidy up addresses in random drivers
[linux-2.6/sactl.git] / include / linux / intel-iommu.h
blob3d017cfd245b6a2ad690cd4579fd6413f6c22a42
1 /*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
20 */
21
22 #ifndef _INTEL_IOMMU_H_
23 #define _INTEL_IOMMU_H_
24
25 #include <linux/types.h>
26 #include <linux/msi.h>
27 #include <linux/sysdev.h>
28 #include <linux/iova.h>
29 #include <linux/io.h>
30 #include <linux/dma_remapping.h>
31 #include <asm/cacheflush.h>
32 #include <asm/iommu.h>
33
34 /*
35 * Intel IOMMU register specification per version 1.0 public spec.
36 */
37
38 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
39 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
40 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
41 #define DMAR_GCMD_REG 0x18 /* Global command register */
42 #define DMAR_GSTS_REG 0x1c /* Global status register */
43 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
44 #define DMAR_CCMD_REG 0x28 /* Context command reg */
45 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
46 #define DMAR_FECTL_REG 0x38 /* Fault control register */
47 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
48 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
49 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
50 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
51 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
52 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
53 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
54 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
55 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
56 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
57 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
58 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
59 #define DMAR_ICS_REG 0x98 /* Invalidation complete status register */
60 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
61
62 #define OFFSET_STRIDE (9)
63 /*
64 #define dmar_readl(dmar, reg) readl(dmar + reg)
65 #define dmar_readq(dmar, reg) ({ \
66 u32 lo, hi; \
67 lo = readl(dmar + reg); \
68 hi = readl(dmar + reg + 4); \
69 (((u64) hi) << 32) + lo; })
70 */
71 static inline u64 dmar_readq(void __iomem *addr)
72 {
73 u32 lo, hi;
74 lo = readl(addr);
75 hi = readl(addr + 4);
76 return (((u64) hi) << 32) + lo;
77 }
78
79 static inline void dmar_writeq(void __iomem *addr, u64 val)
80 {
81 writel((u32)val, addr);
82 writel((u32)(val >> 32), addr + 4);
83 }
84
85 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
86 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
87
88 /*
89 * Decoding Capability Register
90 */
91 #define cap_read_drain(c) (((c) >> 55) & 1)
92 #define cap_write_drain(c) (((c) >> 54) & 1)
93 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
94 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
95 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
96
97 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
98 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
99 * OFFSET_STRIDE) + 21)
100
101 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
102 #define cap_max_fault_reg_offset(c) \
103 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
104
105 #define cap_zlr(c) (((c) >> 22) & 1)
106 #define cap_isoch(c) (((c) >> 23) & 1)
107 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
108 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
109 #define cap_caching_mode(c) (((c) >> 7) & 1)
110 #define cap_phmr(c) (((c) >> 6) & 1)
111 #define cap_plmr(c) (((c) >> 5) & 1)
112 #define cap_rwbf(c) (((c) >> 4) & 1)
113 #define cap_afl(c) (((c) >> 3) & 1)
114 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
115 /*
116 * Extended Capability Register
117 */
118
119 #define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
120 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
121 #define ecap_max_iotlb_offset(e) \
122 (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
123 #define ecap_coherent(e) ((e) & 0x1)
124 #define ecap_qis(e) ((e) & 0x2)
125 #define ecap_eim_support(e) ((e >> 4) & 0x1)
126 #define ecap_ir_support(e) ((e >> 3) & 0x1)
127 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
128
129
130 /* IOTLB_REG */
131 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
132 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
133 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
134 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
135 #define DMA_TLB_IIRG(type) ((type >> 60) & 7)
136 #define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
137 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
138 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
139 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
140 #define DMA_TLB_IVT (((u64)1) << 63)
141 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
142 #define DMA_TLB_MAX_SIZE (0x3f)
143
144 /* INVALID_DESC */
145 #define DMA_CCMD_INVL_GRANU_OFFSET 61
146 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
147 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)
148 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)
149 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
150 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
151 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
152 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
153 #define DMA_ID_TLB_ADDR(addr) (addr)
154 #define DMA_ID_TLB_ADDR_MASK(mask) (mask)
155
156 /* PMEN_REG */
157 #define DMA_PMEN_EPM (((u32)1)<<31)
158 #define DMA_PMEN_PRS (((u32)1)<<0)
159
160 /* GCMD_REG */
161 #define DMA_GCMD_TE (((u32)1) << 31)
162 #define DMA_GCMD_SRTP (((u32)1) << 30)
163 #define DMA_GCMD_SFL (((u32)1) << 29)
164 #define DMA_GCMD_EAFL (((u32)1) << 28)
165 #define DMA_GCMD_WBF (((u32)1) << 27)
166 #define DMA_GCMD_QIE (((u32)1) << 26)
167 #define DMA_GCMD_SIRTP (((u32)1) << 24)
168 #define DMA_GCMD_IRE (((u32) 1) << 25)
169
170 /* GSTS_REG */
171 #define DMA_GSTS_TES (((u32)1) << 31)
172 #define DMA_GSTS_RTPS (((u32)1) << 30)
173 #define DMA_GSTS_FLS (((u32)1) << 29)
174 #define DMA_GSTS_AFLS (((u32)1) << 28)
175 #define DMA_GSTS_WBFS (((u32)1) << 27)
176 #define DMA_GSTS_QIES (((u32)1) << 26)
177 #define DMA_GSTS_IRTPS (((u32)1) << 24)
178 #define DMA_GSTS_IRES (((u32)1) << 25)
179
180 /* CCMD_REG */
181 #define DMA_CCMD_ICC (((u64)1) << 63)
182 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
183 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
184 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
185 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
186 #define DMA_CCMD_MASK_NOBIT 0
187 #define DMA_CCMD_MASK_1BIT 1
188 #define DMA_CCMD_MASK_2BIT 2
189 #define DMA_CCMD_MASK_3BIT 3
190 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
191 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
192
193 /* FECTL_REG */
194 #define DMA_FECTL_IM (((u32)1) << 31)
195
196 /* FSTS_REG */
197 #define DMA_FSTS_PPF ((u32)2)
198 #define DMA_FSTS_PFO ((u32)1)
199 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
200
201 /* FRCD_REG, 32 bits access */
202 #define DMA_FRCD_F (((u32)1) << 31)
203 #define dma_frcd_type(d) ((d >> 30) & 1)
204 #define dma_frcd_fault_reason(c) (c & 0xff)
205 #define dma_frcd_source_id(c) (c & 0xffff)
206 /* low 64 bit */
207 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
208
209 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
210 do { \
211 cycles_t start_time = get_cycles(); \
212 while (1) { \
213 sts = op(iommu->reg + offset); \
214 if (cond) \
215 break; \
216 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
217 panic("DMAR hardware is malfunctioning\n"); \
218 cpu_relax(); \
219 } \
220 } while (0)
221
222 #define QI_LENGTH 256 /* queue length */
223
224 enum {
225 QI_FREE,
226 QI_IN_USE,
227 QI_DONE
228 };
229
230 #define QI_CC_TYPE 0x1
231 #define QI_IOTLB_TYPE 0x2
232 #define QI_DIOTLB_TYPE 0x3
233 #define QI_IEC_TYPE 0x4
234 #define QI_IWD_TYPE 0x5
235
236 #define QI_IEC_SELECTIVE (((u64)1) << 4)
237 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
238 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
239
240 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
241 #define QI_IWD_STATUS_WRITE (((u64)1) << 5)
242
243 #define QI_IOTLB_DID(did) (((u64)did) << 16)
244 #define QI_IOTLB_DR(dr) (((u64)dr) << 7)
245 #define QI_IOTLB_DW(dw) (((u64)dw) << 6)
246 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
247 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
248 #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
249 #define QI_IOTLB_AM(am) (((u8)am))
250
251 #define QI_CC_FM(fm) (((u64)fm) << 48)
252 #define QI_CC_SID(sid) (((u64)sid) << 32)
253 #define QI_CC_DID(did) (((u64)did) << 16)
254 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
255
256 struct qi_desc {
257 u64 low, high;
258 };
259
260 struct q_inval {
261 spinlock_t q_lock;
262 struct qi_desc *desc; /* invalidation queue */
263 int *desc_status; /* desc status */
264 int free_head; /* first free entry */
265 int free_tail; /* last free entry */
266 int free_cnt;
267 };
268
269 #ifdef CONFIG_INTR_REMAP
270 /* 1MB - maximum possible interrupt remapping table size */
271 #define INTR_REMAP_PAGE_ORDER 8
272 #define INTR_REMAP_TABLE_REG_SIZE 0xf
273
274 #define INTR_REMAP_TABLE_ENTRIES 65536
275
276 struct ir_table {
277 struct irte *base;
278 };
279 #endif
280
281 struct iommu_flush {
282 int (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
283 u64 type, int non_present_entry_flush);
284 int (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
285 unsigned int size_order, u64 type, int non_present_entry_flush);
286 };
287
288 struct intel_iommu {
289 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
290 u64 cap;
291 u64 ecap;
292 int seg;
293 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
294 spinlock_t register_lock; /* protect register handling */
295 int seq_id; /* sequence id of the iommu */
296
297 #ifdef CONFIG_DMAR
298 unsigned long *domain_ids; /* bitmap of domains */
299 struct dmar_domain **domains; /* ptr to domains */
300 spinlock_t lock; /* protect context, domain ids */
301 struct root_entry *root_entry; /* virtual address */
302
303 unsigned int irq;
304 unsigned char name[7]; /* Device Name */
305 struct msi_msg saved_msg;
306 struct sys_device sysdev;
307 struct iommu_flush flush;
308 #endif
309 struct q_inval *qi; /* Queued invalidation info */
310 #ifdef CONFIG_INTR_REMAP
311 struct ir_table *ir_table; /* Interrupt remapping info */
312 #endif
313 };
314
315 static inline void __iommu_flush_cache(
316 struct intel_iommu *iommu, void *addr, int size)
317 {
318 if (!ecap_coherent(iommu->ecap))
319 clflush_cache_range(addr, size);
320 }
321
322 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
323
324 extern int alloc_iommu(struct dmar_drhd_unit *drhd);
325 extern void free_iommu(struct intel_iommu *iommu);
326 extern int dmar_enable_qi(struct intel_iommu *iommu);
327 extern void qi_global_iec(struct intel_iommu *iommu);
328
329 extern int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
330 u8 fm, u64 type, int non_present_entry_flush);
331 extern int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
332 unsigned int size_order, u64 type,
333 int non_present_entry_flush);
334
335 extern void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
336
337 void intel_iommu_domain_exit(struct dmar_domain *domain);
338 struct dmar_domain *intel_iommu_domain_alloc(struct pci_dev *pdev);
339 int intel_iommu_context_mapping(struct dmar_domain *domain,
340 struct pci_dev *pdev);
341 int intel_iommu_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
342 u64 hpa, size_t size, int prot);
343 void intel_iommu_detach_dev(struct dmar_domain *domain, u8 bus, u8 devfn);
344 struct dmar_domain *intel_iommu_find_domain(struct pci_dev *pdev);
345 u64 intel_iommu_iova_to_pfn(struct dmar_domain *domain, u64 iova);
346
347 #ifdef CONFIG_DMAR
348 int intel_iommu_found(void);
349 #else /* CONFIG_DMAR */
350 static inline int intel_iommu_found(void)
351 {
352 return 0;
353 }
354 #endif /* CONFIG_DMAR */
355
356 extern void *intel_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
357 extern void intel_free_coherent(struct device *, size_t, void *, dma_addr_t);
358 extern dma_addr_t intel_map_single(struct device *, phys_addr_t, size_t, int);
359 extern void intel_unmap_single(struct device *, dma_addr_t, size_t, int);
360 extern int intel_map_sg(struct device *, struct scatterlist *, int, int);
361 extern void intel_unmap_sg(struct device *, struct scatterlist *, int, int);
362
363 #endif
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