arch/i386/pci/irq.c

   1 /*
   2  *      Low-Level PCI Support for PC -- Routing of Interrupts
   3  *
   4  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   5  */
   6
   7 #include <linux/config.h>
   8 #include <linux/types.h>
   9 #include <linux/kernel.h>
  10 #include <linux/pci.h>
  11 #include <linux/init.h>
  12 #include <linux/slab.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/dmi.h>
  15 #include <asm/io.h>
  16 #include <asm/smp.h>
  17 #include <asm/io_apic.h>
  18 #include <linux/irq.h>
  19 #include <linux/acpi.h>
  20
  21 #include "pci.h"
  22
  23 #define PIRQ_SIGNATURE  (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
  24 #define PIRQ_VERSION 0x0100
  25
  26 static int broken_hp_bios_irq9;
  27 static int acer_tm360_irqrouting;
  28
  29 static struct irq_routing_table *pirq_table;
  30
  31 static int pirq_enable_irq(struct pci_dev *dev);
  32
  33 /*
  34  * Never use: 0, 1, 2 (timer, keyboard, and cascade)
  35  * Avoid using: 13, 14 and 15 (FP error and IDE).
  36  * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
  37  */
  38 unsigned int pcibios_irq_mask = 0xfff8;
  39
  40 static int pirq_penalty[16] = {
  41         1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
  42         0, 0, 0, 0, 1000, 100000, 100000, 100000
  43 };
  44
  45 struct irq_router {
  46         char *name;
  47         u16 vendor, device;
  48         int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
  49         int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
  50 };
  51
  52 struct irq_router_handler {
  53         u16 vendor;
  54         int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
  55 };
  56
  57 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
  58 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
  59
  60 /*
  61  *  Check passed address for the PCI IRQ Routing Table signature
  62  *  and perform checksum verification.
  63  */
  64
  65 static inline struct irq_routing_table * pirq_check_routing_table(u8 *addr)
  66 {
  67         struct irq_routing_table *rt;
  68         int i;
  69         u8 sum;
  70
  71         rt = (struct irq_routing_table *) addr;
  72         if (rt->signature != PIRQ_SIGNATURE ||
  73             rt->version != PIRQ_VERSION ||
  74             rt->size % 16 ||
  75             rt->size < sizeof(struct irq_routing_table))
  76                 return NULL;
  77         sum = 0;
  78         for (i=0; i < rt->size; i++)
  79                 sum += addr[i];
  80         if (!sum) {
  81                 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
  82                 return rt;
  83         }
  84         return NULL;
  85 }
  86
  87
  88
  89 /*
  90  *  Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
  91  */
  92
  93 static struct irq_routing_table * __init pirq_find_routing_table(void)
  94 {
  95         u8 *addr;
  96         struct irq_routing_table *rt;
  97
  98         if (pirq_table_addr) {
  99                 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
 100                 if (rt)
 101                         return rt;
 102                 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
 103         }
 104         for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
 105                 rt = pirq_check_routing_table(addr);
 106                 if (rt)
 107                         return rt;
 108         }
 109         return NULL;
 110 }
 111
 112 /*
 113  *  If we have a IRQ routing table, use it to search for peer host
 114  *  bridges.  It's a gross hack, but since there are no other known
 115  *  ways how to get a list of buses, we have to go this way.
 116  */
 117
 118 static void __init pirq_peer_trick(void)
 119 {
 120         struct irq_routing_table *rt = pirq_table;
 121         u8 busmap[256];
 122         int i;
 123         struct irq_info *e;
 124
 125         memset(busmap, 0, sizeof(busmap));
 126         for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
 127                 e = &rt->slots[i];
 128 #ifdef DEBUG
 129                 {
 130                         int j;
 131                         DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
 132                         for(j=0; j<4; j++)
 133                                 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
 134                         DBG("\n");
 135                 }
 136 #endif
 137                 busmap[e->bus] = 1;
 138         }
 139         for(i = 1; i < 256; i++) {
 140                 if (!busmap[i] || pci_find_bus(0, i))
 141                         continue;
 142                 if (pci_scan_bus(i, &pci_root_ops, NULL))
 143                         printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
 144         }
 145         pcibios_last_bus = -1;
 146 }
 147
 148 /*
 149  *  Code for querying and setting of IRQ routes on various interrupt routers.
 150  */
 151
 152 void eisa_set_level_irq(unsigned int irq)
 153 {
 154         unsigned char mask = 1 << (irq & 7);
 155         unsigned int port = 0x4d0 + (irq >> 3);
 156         unsigned char val;
 157         static u16 eisa_irq_mask;
 158
 159         if (irq >= 16 || (1 << irq) & eisa_irq_mask)
 160                 return;
 161
 162         eisa_irq_mask |= (1 << irq);
 163         printk("PCI: setting IRQ %u as level-triggered\n", irq);
 164         val = inb(port);
 165         if (!(val & mask)) {
 166                 DBG(" -> edge");
 167                 outb(val | mask, port);
 168         }
 169 }
 170
 171 /*
 172  * Common IRQ routing practice: nybbles in config space,
 173  * offset by some magic constant.
 174  */
 175 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
 176 {
 177         u8 x;
 178         unsigned reg = offset + (nr >> 1);
 179
 180         pci_read_config_byte(router, reg, &x);
 181         return (nr & 1) ? (x >> 4) : (x & 0xf);
 182 }
 183
 184 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
 185 {
 186         u8 x;
 187         unsigned reg = offset + (nr >> 1);
 188
 189         pci_read_config_byte(router, reg, &x);
 190         x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
 191         pci_write_config_byte(router, reg, x);
 192 }
 193
 194 /*
 195  * ALI pirq entries are damn ugly, and completely undocumented.
 196  * This has been figured out from pirq tables, and it's not a pretty
 197  * picture.
 198  */
 199 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 200 {
 201         static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
 202
 203         return irqmap[read_config_nybble(router, 0x48, pirq-1)];
 204 }
 205
 206 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 207 {
 208         static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
 209         unsigned int val = irqmap[irq];
 210
 211         if (val) {
 212                 write_config_nybble(router, 0x48, pirq-1, val);
 213                 return 1;
 214         }
 215         return 0;
 216 }
 217
 218 /*
 219  * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
 220  * just a pointer to the config space.
 221  */
 222 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 223 {
 224         u8 x;
 225
 226         pci_read_config_byte(router, pirq, &x);
 227         return (x < 16) ? x : 0;
 228 }
 229
 230 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 231 {
 232         pci_write_config_byte(router, pirq, irq);
 233         return 1;
 234 }
 235
 236 /*
 237  * The VIA pirq rules are nibble-based, like ALI,
 238  * but without the ugly irq number munging.
 239  * However, PIRQD is in the upper instead of lower 4 bits.
 240  */
 241 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 242 {
 243         return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
 244 }
 245
 246 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 247 {
 248         write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
 249         return 1;
 250 }
 251
 252 /*
 253  * The VIA pirq rules are nibble-based, like ALI,
 254  * but without the ugly irq number munging.
 255  * However, for 82C586, nibble map is different .
 256  */
 257 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 258 {
 259         static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
 260         return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
 261 }
 262
 263 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 264 {
 265         static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
 266         write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
 267         return 1;
 268 }
 269
 270 /*
 271  * ITE 8330G pirq rules are nibble-based
 272  * FIXME: pirqmap may be { 1, 0, 3, 2 },
 273  *        2+3 are both mapped to irq 9 on my system
 274  */
 275 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 276 {
 277         static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 278         return read_config_nybble(router,0x43, pirqmap[pirq-1]);
 279 }
 280
 281 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 282 {
 283         static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 284         write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
 285         return 1;
 286 }
 287
 288 /*
 289  * OPTI: high four bits are nibble pointer..
 290  * I wonder what the low bits do?
 291  */
 292 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 293 {
 294         return read_config_nybble(router, 0xb8, pirq >> 4);
 295 }
 296
 297 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 298 {
 299         write_config_nybble(router, 0xb8, pirq >> 4, irq);
 300         return 1;
 301 }
 302
 303 /*
 304  * Cyrix: nibble offset 0x5C
 305  * 0x5C bits 7:4 is INTB bits 3:0 is INTA
 306  * 0x5D bits 7:4 is INTD bits 3:0 is INTC
 307  */
 308 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 309 {
 310         return read_config_nybble(router, 0x5C, (pirq-1)^1);
 311 }
 312
 313 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 314 {
 315         write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
 316         return 1;
 317 }
 318
 319 /*
 320  *      PIRQ routing for SiS 85C503 router used in several SiS chipsets.
 321  *      We have to deal with the following issues here:
 322  *      - vendors have different ideas about the meaning of link values
 323  *      - some onboard devices (integrated in the chipset) have special
 324  *        links and are thus routed differently (i.e. not via PCI INTA-INTD)
 325  *      - different revision of the router have a different layout for
 326  *        the routing registers, particularly for the onchip devices
 327  *
 328  *      For all routing registers the common thing is we have one byte
 329  *      per routeable link which is defined as:
 330  *               bit 7      IRQ mapping enabled (0) or disabled (1)
 331  *               bits [6:4] reserved (sometimes used for onchip devices)
 332  *               bits [3:0] IRQ to map to
 333  *                   allowed: 3-7, 9-12, 14-15
 334  *                   reserved: 0, 1, 2, 8, 13
 335  *
 336  *      The config-space registers located at 0x41/0x42/0x43/0x44 are
 337  *      always used to route the normal PCI INT A/B/C/D respectively.
 338  *      Apparently there are systems implementing PCI routing table using
 339  *      link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
 340  *      We try our best to handle both link mappings.
 341  *
 342  *      Currently (2003-05-21) it appears most SiS chipsets follow the
 343  *      definition of routing registers from the SiS-5595 southbridge.
 344  *      According to the SiS 5595 datasheets the revision id's of the
 345  *      router (ISA-bridge) should be 0x01 or 0xb0.
 346  *
 347  *      Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
 348  *      Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
 349  *      They seem to work with the current routing code. However there is
 350  *      some concern because of the two USB-OHCI HCs (original SiS 5595
 351  *      had only one). YMMV.
 352  *
 353  *      Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
 354  *
 355  *      0x61:   IDEIRQ:
 356  *              bits [6:5] must be written 01
 357  *              bit 4 channel-select primary (0), secondary (1)
 358  *
 359  *      0x62:   USBIRQ:
 360  *              bit 6 OHCI function disabled (0), enabled (1)
 361  *
 362  *      0x6a:   ACPI/SCI IRQ: bits 4-6 reserved
 363  *
 364  *      0x7e:   Data Acq. Module IRQ - bits 4-6 reserved
 365  *
 366  *      We support USBIRQ (in addition to INTA-INTD) and keep the
 367  *      IDE, ACPI and DAQ routing untouched as set by the BIOS.
 368  *
 369  *      Currently the only reported exception is the new SiS 65x chipset
 370  *      which includes the SiS 69x southbridge. Here we have the 85C503
 371  *      router revision 0x04 and there are changes in the register layout
 372  *      mostly related to the different USB HCs with USB 2.0 support.
 373  *
 374  *      Onchip routing for router rev-id 0x04 (try-and-error observation)
 375  *
 376  *      0x60/0x61/0x62/0x63:    1xEHCI and 3xOHCI (companion) USB-HCs
 377  *                              bit 6-4 are probably unused, not like 5595
 378  */
 379
 380 #define PIRQ_SIS_IRQ_MASK       0x0f
 381 #define PIRQ_SIS_IRQ_DISABLE    0x80
 382 #define PIRQ_SIS_USB_ENABLE     0x40
 383
 384 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 385 {
 386         u8 x;
 387         int reg;
 388
 389         reg = pirq;
 390         if (reg >= 0x01 && reg <= 0x04)
 391                 reg += 0x40;
 392         pci_read_config_byte(router, reg, &x);
 393         return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
 394 }
 395
 396 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 397 {
 398         u8 x;
 399         int reg;
 400
 401         reg = pirq;
 402         if (reg >= 0x01 && reg <= 0x04)
 403                 reg += 0x40;
 404         pci_read_config_byte(router, reg, &x);
 405         x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
 406         x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
 407         pci_write_config_byte(router, reg, x);
 408         return 1;
 409 }
 410
 411
 412 /*
 413  * VLSI: nibble offset 0x74 - educated guess due to routing table and
 414  *       config space of VLSI 82C534 PCI-bridge/router (1004:0102)
 415  *       Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
 416  *       devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
 417  *       for the busbridge to the docking station.
 418  */
 419
 420 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 421 {
 422         if (pirq > 8) {
 423                 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
 424                 return 0;
 425         }
 426         return read_config_nybble(router, 0x74, pirq-1);
 427 }
 428
 429 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 430 {
 431         if (pirq > 8) {
 432                 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
 433                 return 0;
 434         }
 435         write_config_nybble(router, 0x74, pirq-1, irq);
 436         return 1;
 437 }
 438
 439 /*
 440  * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
 441  * and Redirect I/O registers (0x0c00 and 0x0c01).  The Index register
 442  * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a.  The Redirect
 443  * register is a straight binary coding of desired PIC IRQ (low nibble).
 444  *
 445  * The 'link' value in the PIRQ table is already in the correct format
 446  * for the Index register.  There are some special index values:
 447  * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
 448  * and 0x03 for SMBus.
 449  */
 450 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 451 {
 452         outb_p(pirq, 0xc00);
 453         return inb(0xc01) & 0xf;
 454 }
 455
 456 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 457 {
 458         outb_p(pirq, 0xc00);
 459         outb_p(irq, 0xc01);
 460         return 1;
 461 }
 462
 463 /* Support for AMD756 PCI IRQ Routing
 464  * Jhon H. Caicedo <jhcaiced@osso.org.co>
 465  * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
 466  * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
 467  * The AMD756 pirq rules are nibble-based
 468  * offset 0x56 0-3 PIRQA  4-7  PIRQB
 469  * offset 0x57 0-3 PIRQC  4-7  PIRQD
 470  */
 471 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 472 {
 473         u8 irq;
 474         irq = 0;
 475         if (pirq <= 4)
 476         {
 477                 irq = read_config_nybble(router, 0x56, pirq - 1);
 478         }
 479         printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
 480                 dev->vendor, dev->device, pirq, irq);
 481         return irq;
 482 }
 483
 484 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 485 {
 486         printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
 487                 dev->vendor, dev->device, pirq, irq);
 488         if (pirq <= 4)
 489         {
 490                 write_config_nybble(router, 0x56, pirq - 1, irq);
 491         }
 492         return 1;
 493 }
 494
 495 #ifdef CONFIG_PCI_BIOS
 496
 497 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 498 {
 499         struct pci_dev *bridge;
 500         int pin = pci_get_interrupt_pin(dev, &bridge);
 501         return pcibios_set_irq_routing(bridge, pin, irq);
 502 }
 503
 504 #endif
 505
 506 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 507 {
 508         static struct pci_device_id pirq_440gx[] = {
 509                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
 510                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
 511                 { },
 512         };
 513
 514         /* 440GX has a proprietary PIRQ router -- don't use it */
 515         if (pci_dev_present(pirq_440gx))
 516                 return 0;
 517
 518         switch(device)
 519         {
 520                 case PCI_DEVICE_ID_INTEL_82371FB_0:
 521                 case PCI_DEVICE_ID_INTEL_82371SB_0:
 522                 case PCI_DEVICE_ID_INTEL_82371AB_0:
 523                 case PCI_DEVICE_ID_INTEL_82371MX:
 524                 case PCI_DEVICE_ID_INTEL_82443MX_0:
 525                 case PCI_DEVICE_ID_INTEL_82801AA_0:
 526                 case PCI_DEVICE_ID_INTEL_82801AB_0:
 527                 case PCI_DEVICE_ID_INTEL_82801BA_0:
 528                 case PCI_DEVICE_ID_INTEL_82801BA_10:
 529                 case PCI_DEVICE_ID_INTEL_82801CA_0:
 530                 case PCI_DEVICE_ID_INTEL_82801CA_12:
 531                 case PCI_DEVICE_ID_INTEL_82801DB_0:
 532                 case PCI_DEVICE_ID_INTEL_82801E_0:
 533                 case PCI_DEVICE_ID_INTEL_82801EB_0:
 534                 case PCI_DEVICE_ID_INTEL_ESB_1:
 535                 case PCI_DEVICE_ID_INTEL_ICH6_0:
 536                 case PCI_DEVICE_ID_INTEL_ICH6_1:
 537                 case PCI_DEVICE_ID_INTEL_ICH7_0:
 538                 case PCI_DEVICE_ID_INTEL_ICH7_1:
 539                 case PCI_DEVICE_ID_INTEL_ICH7_30:
 540                 case PCI_DEVICE_ID_INTEL_ICH7_31:
 541                 case PCI_DEVICE_ID_INTEL_ESB2_0:
 542                         r->name = "PIIX/ICH";
 543                         r->get = pirq_piix_get;
 544                         r->set = pirq_piix_set;
 545                         return 1;
 546         }
 547         return 0;
 548 }
 549
 550 static __init int via_router_probe(struct irq_router *r,
 551                                 struct pci_dev *router, u16 device)
 552 {
 553         /* FIXME: We should move some of the quirk fixup stuff here */
 554
 555         /*
 556          * work arounds for some buggy BIOSes
 557          */
 558         if (device == PCI_DEVICE_ID_VIA_82C586_0) {
 559                 switch(router->device) {
 560                 case PCI_DEVICE_ID_VIA_82C686:
 561                         /*
 562                          * Asus k7m bios wrongly reports 82C686A
 563                          * as 586-compatible
 564                          */
 565                         device = PCI_DEVICE_ID_VIA_82C686;
 566                         break;
 567                 case PCI_DEVICE_ID_VIA_8235:
 568                         /**
 569                          * Asus a7v-x bios wrongly reports 8235
 570                          * as 586-compatible
 571                          */
 572                         device = PCI_DEVICE_ID_VIA_8235;
 573                         break;
 574                 }
 575         }
 576
 577         switch(device) {
 578         case PCI_DEVICE_ID_VIA_82C586_0:
 579                 r->name = "VIA";
 580                 r->get = pirq_via586_get;
 581                 r->set = pirq_via586_set;
 582                 return 1;
 583         case PCI_DEVICE_ID_VIA_82C596:
 584         case PCI_DEVICE_ID_VIA_82C686:
 585         case PCI_DEVICE_ID_VIA_8231:
 586         case PCI_DEVICE_ID_VIA_8235:
 587                 /* FIXME: add new ones for 8233/5 */
 588                 r->name = "VIA";
 589                 r->get = pirq_via_get;
 590                 r->set = pirq_via_set;
 591                 return 1;
 592         }
 593         return 0;
 594 }
 595
 596 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 597 {
 598         switch(device)
 599         {
 600                 case PCI_DEVICE_ID_VLSI_82C534:
 601                         r->name = "VLSI 82C534";
 602                         r->get = pirq_vlsi_get;
 603                         r->set = pirq_vlsi_set;
 604                         return 1;
 605         }
 606         return 0;
 607 }
 608
 609
 610 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 611 {
 612         switch(device)
 613         {
 614                 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
 615                 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
 616                         r->name = "ServerWorks";
 617                         r->get = pirq_serverworks_get;
 618                         r->set = pirq_serverworks_set;
 619                         return 1;
 620         }
 621         return 0;
 622 }
 623
 624 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 625 {
 626         if (device != PCI_DEVICE_ID_SI_503)
 627                 return 0;
 628
 629         r->name = "SIS";
 630         r->get = pirq_sis_get;
 631         r->set = pirq_sis_set;
 632         return 1;
 633 }
 634
 635 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 636 {
 637         switch(device)
 638         {
 639                 case PCI_DEVICE_ID_CYRIX_5520:
 640                         r->name = "NatSemi";
 641                         r->get = pirq_cyrix_get;
 642                         r->set = pirq_cyrix_set;
 643                         return 1;
 644         }
 645         return 0;
 646 }
 647
 648 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 649 {
 650         switch(device)
 651         {
 652                 case PCI_DEVICE_ID_OPTI_82C700:
 653                         r->name = "OPTI";
 654                         r->get = pirq_opti_get;
 655                         r->set = pirq_opti_set;
 656                         return 1;
 657         }
 658         return 0;
 659 }
 660
 661 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 662 {
 663         switch(device)
 664         {
 665                 case PCI_DEVICE_ID_ITE_IT8330G_0:
 666                         r->name = "ITE";
 667                         r->get = pirq_ite_get;
 668                         r->set = pirq_ite_set;
 669                         return 1;
 670         }
 671         return 0;
 672 }
 673
 674 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 675 {
 676         switch(device)
 677         {
 678         case PCI_DEVICE_ID_AL_M1533:
 679         case PCI_DEVICE_ID_AL_M1563:
 680                 printk("PCI: Using ALI IRQ Router\n");
 681                         r->name = "ALI";
 682                         r->get = pirq_ali_get;
 683                         r->set = pirq_ali_set;
 684                         return 1;
 685         }
 686         return 0;
 687 }
 688
 689 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 690 {
 691         switch(device)
 692         {
 693                 case PCI_DEVICE_ID_AMD_VIPER_740B:
 694                         r->name = "AMD756";
 695                         break;
 696                 case PCI_DEVICE_ID_AMD_VIPER_7413:
 697                         r->name = "AMD766";
 698                         break;
 699                 case PCI_DEVICE_ID_AMD_VIPER_7443:
 700                         r->name = "AMD768";
 701                         break;
 702                 default:
 703                         return 0;
 704         }
 705         r->get = pirq_amd756_get;
 706         r->set = pirq_amd756_set;
 707         return 1;
 708 }
 709
 710 static __initdata struct irq_router_handler pirq_routers[] = {
 711         { PCI_VENDOR_ID_INTEL, intel_router_probe },
 712         { PCI_VENDOR_ID_AL, ali_router_probe },
 713         { PCI_VENDOR_ID_ITE, ite_router_probe },
 714         { PCI_VENDOR_ID_VIA, via_router_probe },
 715         { PCI_VENDOR_ID_OPTI, opti_router_probe },
 716         { PCI_VENDOR_ID_SI, sis_router_probe },
 717         { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
 718         { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
 719         { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
 720         { PCI_VENDOR_ID_AMD, amd_router_probe },
 721         /* Someone with docs needs to add the ATI Radeon IGP */
 722         { 0, NULL }
 723 };
 724 static struct irq_router pirq_router;
 725 static struct pci_dev *pirq_router_dev;
 726
 727
 728 /*
 729  *      FIXME: should we have an option to say "generic for
 730  *      chipset" ?
 731  */
 732
 733 static void __init pirq_find_router(struct irq_router *r)
 734 {
 735         struct irq_routing_table *rt = pirq_table;
 736         struct irq_router_handler *h;
 737
 738 #ifdef CONFIG_PCI_BIOS
 739         if (!rt->signature) {
 740                 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
 741                 r->set = pirq_bios_set;
 742                 r->name = "BIOS";
 743                 return;
 744         }
 745 #endif
 746
 747         /* Default unless a driver reloads it */
 748         r->name = "default";
 749         r->get = NULL;
 750         r->set = NULL;
 751
 752         DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
 753             rt->rtr_vendor, rt->rtr_device);
 754
 755         pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
 756         if (!pirq_router_dev) {
 757                 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
 758                 return;
 759         }
 760
 761         for( h = pirq_routers; h->vendor; h++) {
 762                 /* First look for a router match */
 763                 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
 764                         break;
 765                 /* Fall back to a device match */
 766                 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
 767                         break;
 768         }
 769         printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
 770                 pirq_router.name,
 771                 pirq_router_dev->vendor,
 772                 pirq_router_dev->device,
 773                 pci_name(pirq_router_dev));
 774 }
 775
 776 static struct irq_info *pirq_get_info(struct pci_dev *dev)
 777 {
 778         struct irq_routing_table *rt = pirq_table;
 779         int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
 780         struct irq_info *info;
 781
 782         for (info = rt->slots; entries--; info++)
 783                 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
 784                         return info;
 785         return NULL;
 786 }
 787
 788 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
 789 {
 790         u8 pin;
 791         struct irq_info *info;
 792         int i, pirq, newirq;
 793         int irq = 0;
 794         u32 mask;
 795         struct irq_router *r = &pirq_router;
 796         struct pci_dev *dev2 = NULL;
 797         char *msg = NULL;
 798
 799         /* Find IRQ pin */
 800         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
 801         if (!pin) {
 802                 DBG(" -> no interrupt pin\n");
 803                 return 0;
 804         }
 805         pin = pin - 1;
 806
 807         /* Find IRQ routing entry */
 808
 809         if (!pirq_table)
 810                 return 0;
 811
 812         DBG("IRQ for %s[%c]", pci_name(dev), 'A' + pin);
 813         info = pirq_get_info(dev);
 814         if (!info) {
 815                 DBG(" -> not found in routing table\n");
 816                 return 0;
 817         }
 818         pirq = info->irq[pin].link;
 819         mask = info->irq[pin].bitmap;
 820         if (!pirq) {
 821                 DBG(" -> not routed\n");
 822                 return 0;
 823         }
 824         DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
 825         mask &= pcibios_irq_mask;
 826
 827         /* Work around broken HP Pavilion Notebooks which assign USB to
 828            IRQ 9 even though it is actually wired to IRQ 11 */
 829
 830         if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
 831                 dev->irq = 11;
 832                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
 833                 r->set(pirq_router_dev, dev, pirq, 11);
 834         }
 835
 836         /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
 837         if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
 838                 pirq = 0x68;
 839                 mask = 0x400;
 840                 dev->irq = r->get(pirq_router_dev, dev, pirq);
 841                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 842         }
 843
 844         /*
 845          * Find the best IRQ to assign: use the one
 846          * reported by the device if possible.
 847          */
 848         newirq = dev->irq;
 849         if (!((1 << newirq) & mask)) {
 850                 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
 851                 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev));
 852         }
 853         if (!newirq && assign) {
 854                 for (i = 0; i < 16; i++) {
 855                         if (!(mask & (1 << i)))
 856                                 continue;
 857                         if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
 858                                 newirq = i;
 859                 }
 860         }
 861         DBG(" -> newirq=%d", newirq);
 862
 863         /* Check if it is hardcoded */
 864         if ((pirq & 0xf0) == 0xf0) {
 865                 irq = pirq & 0xf;
 866                 DBG(" -> hardcoded IRQ %d\n", irq);
 867                 msg = "Hardcoded";
 868         } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
 869         ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
 870                 DBG(" -> got IRQ %d\n", irq);
 871                 msg = "Found";
 872         } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
 873                 DBG(" -> assigning IRQ %d", newirq);
 874                 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
 875                         eisa_set_level_irq(newirq);
 876                         DBG(" ... OK\n");
 877                         msg = "Assigned";
 878                         irq = newirq;
 879                 }
 880         }
 881
 882         if (!irq) {
 883                 DBG(" ... failed\n");
 884                 if (newirq && mask == (1 << newirq)) {
 885                         msg = "Guessed";
 886                         irq = newirq;
 887                 } else
 888                         return 0;
 889         }
 890         printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
 891
 892         /* Update IRQ for all devices with the same pirq value */
 893         while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
 894                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
 895                 if (!pin)
 896                         continue;
 897                 pin--;
 898                 info = pirq_get_info(dev2);
 899                 if (!info)
 900                         continue;
 901                 if (info->irq[pin].link == pirq) {
 902                         /* We refuse to override the dev->irq information. Give a warning! */
 903                         if ( dev2->irq && dev2->irq != irq && \
 904                         (!(pci_probe & PCI_USE_PIRQ_MASK) || \
 905                         ((1 << dev2->irq) & mask)) ) {
 906 #ifndef CONFIG_PCI_MSI
 907                                 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
 908                                        pci_name(dev2), dev2->irq, irq);
 909 #endif
 910                                 continue;
 911                         }
 912                         dev2->irq = irq;
 913                         pirq_penalty[irq]++;
 914                         if (dev != dev2)
 915                                 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
 916                 }
 917         }
 918         return 1;
 919 }
 920
 921 static void __init pcibios_fixup_irqs(void)
 922 {
 923         struct pci_dev *dev = NULL;
 924         u8 pin;
 925
 926         DBG("PCI: IRQ fixup\n");
 927         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
 928                 /*
 929                  * If the BIOS has set an out of range IRQ number, just ignore it.
 930                  * Also keep track of which IRQ's are already in use.
 931                  */
 932                 if (dev->irq >= 16) {
 933                         DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
 934                         dev->irq = 0;
 935                 }
 936                 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
 937                 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
 938                         pirq_penalty[dev->irq] = 0;
 939                 pirq_penalty[dev->irq]++;
 940         }
 941
 942         dev = NULL;
 943         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
 944                 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
 945 #ifdef CONFIG_X86_IO_APIC
 946                 /*
 947                  * Recalculate IRQ numbers if we use the I/O APIC.
 948                  */
 949                 if (io_apic_assign_pci_irqs)
 950                 {
 951                         int irq;
 952
 953                         if (pin) {
 954                                 pin--;          /* interrupt pins are numbered starting from 1 */
 955                                 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
 956         /*
 957          * Busses behind bridges are typically not listed in the MP-table.
 958          * In this case we have to look up the IRQ based on the parent bus,
 959          * parent slot, and pin number. The SMP code detects such bridged
 960          * busses itself so we should get into this branch reliably.
 961          */
 962                                 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
 963                                         struct pci_dev * bridge = dev->bus->self;
 964
 965                                         pin = (pin + PCI_SLOT(dev->devfn)) % 4;
 966                                         irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
 967                                                         PCI_SLOT(bridge->devfn), pin);
 968                                         if (irq >= 0)
 969                                                 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
 970                                                         pci_name(bridge), 'A' + pin, irq);
 971                                 }
 972                                 if (irq >= 0) {
 973                                         if (use_pci_vector() &&
 974                                                 !platform_legacy_irq(irq))
 975                                                 irq = IO_APIC_VECTOR(irq);
 976
 977                                         printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
 978                                                 pci_name(dev), 'A' + pin, irq);
 979                                         dev->irq = irq;
 980                                 }
 981                         }
 982                 }
 983 #endif
 984                 /*
 985                  * Still no IRQ? Try to lookup one...
 986                  */
 987                 if (pin && !dev->irq)
 988                         pcibios_lookup_irq(dev, 0);
 989         }
 990 }
 991
 992 /*
 993  * Work around broken HP Pavilion Notebooks which assign USB to
 994  * IRQ 9 even though it is actually wired to IRQ 11
 995  */
 996 static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
 997 {
 998         if (!broken_hp_bios_irq9) {
 999                 broken_hp_bios_irq9 = 1;
1000                 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
1001         }
1002         return 0;
1003 }
1004
1005 /*
1006  * Work around broken Acer TravelMate 360 Notebooks which assign
1007  * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1008  */
1009 static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
1010 {
1011         if (!acer_tm360_irqrouting) {
1012                 acer_tm360_irqrouting = 1;
1013                 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
1014         }
1015         return 0;
1016 }
1017
1018 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1019         {
1020                 .callback = fix_broken_hp_bios_irq9,
1021                 .ident = "HP Pavilion N5400 Series Laptop",
1022                 .matches = {
1023                         DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1024                         DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1025                         DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
1026                         DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1027                 },
1028         },
1029         {
1030                 .callback = fix_acer_tm360_irqrouting,
1031                 .ident = "Acer TravelMate 36x Laptop",
1032                 .matches = {
1033                         DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1034                         DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1035                 },
1036         },
1037         { }
1038 };
1039
1040 static int __init pcibios_irq_init(void)
1041 {
1042         DBG("PCI: IRQ init\n");
1043
1044         if (pcibios_enable_irq || raw_pci_ops == NULL)
1045                 return 0;
1046
1047         dmi_check_system(pciirq_dmi_table);
1048
1049         pirq_table = pirq_find_routing_table();
1050
1051 #ifdef CONFIG_PCI_BIOS
1052         if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1053                 pirq_table = pcibios_get_irq_routing_table();
1054 #endif
1055         if (pirq_table) {
1056                 pirq_peer_trick();
1057                 pirq_find_router(&pirq_router);
1058                 if (pirq_table->exclusive_irqs) {
1059                         int i;
1060                         for (i=0; i<16; i++)
1061                                 if (!(pirq_table->exclusive_irqs & (1 << i)))
1062                                         pirq_penalty[i] += 100;
1063                 }
1064                 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
1065                 if (io_apic_assign_pci_irqs)
1066                         pirq_table = NULL;
1067         }
1068
1069         pcibios_enable_irq = pirq_enable_irq;
1070
1071         pcibios_fixup_irqs();
1072         return 0;
1073 }
1074
1075 subsys_initcall(pcibios_irq_init);
1076
1077
1078 static void pirq_penalize_isa_irq(int irq, int active)
1079 {
1080         /*
1081          *  If any ISAPnP device reports an IRQ in its list of possible
1082          *  IRQ's, we try to avoid assigning it to PCI devices.
1083          */
1084         if (irq < 16) {
1085                 if (active)
1086                         pirq_penalty[irq] += 1000;
1087                 else
1088                         pirq_penalty[irq] += 100;
1089         }
1090 }
1091
1092 void pcibios_penalize_isa_irq(int irq, int active)
1093 {
1094 #ifdef CONFIG_ACPI
1095         if (!acpi_noirq)
1096                 acpi_penalize_isa_irq(irq, active);
1097         else
1098 #endif
1099                 pirq_penalize_isa_irq(irq, active);
1100 }
1101
1102 static int pirq_enable_irq(struct pci_dev *dev)
1103 {
1104         u8 pin;
1105         struct pci_dev *temp_dev;
1106
1107         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1108         if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1109                 char *msg = "";
1110
1111                 pin--;          /* interrupt pins are numbered starting from 1 */
1112
1113                 if (io_apic_assign_pci_irqs) {
1114                         int irq;
1115
1116                         irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1117                         /*
1118                          * Busses behind bridges are typically not listed in the MP-table.
1119                          * In this case we have to look up the IRQ based on the parent bus,
1120                          * parent slot, and pin number. The SMP code detects such bridged
1121                          * busses itself so we should get into this branch reliably.
1122                          */
1123                         temp_dev = dev;
1124                         while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1125                                 struct pci_dev * bridge = dev->bus->self;
1126
1127                                 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1128                                 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1129                                                 PCI_SLOT(bridge->devfn), pin);
1130                                 if (irq >= 0)
1131                                         printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
1132                                                 pci_name(bridge), 'A' + pin, irq);
1133                                 dev = bridge;
1134                         }
1135                         dev = temp_dev;
1136                         if (irq >= 0) {
1137 #ifdef CONFIG_PCI_MSI
1138                                 if (!platform_legacy_irq(irq))
1139                                         irq = IO_APIC_VECTOR(irq);
1140 #endif
1141                                 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
1142                                         pci_name(dev), 'A' + pin, irq);
1143                                 dev->irq = irq;
1144                                 return 0;
1145                         } else
1146                                 msg = " Probably buggy MP table.";
1147                 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1148                         msg = "";
1149                 else
1150                         msg = " Please try using pci=biosirq.";
1151
1152                 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1153                 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1154                         return 0;
1155
1156                 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1157                        'A' + pin, pci_name(dev), msg);
1158         }
1159         return 0;
1160 }
1161
1162 int pci_vector_resources(int last, int nr_released)
1163 {
1164         int count = nr_released;
1165
1166         int next = last;
1167         int offset = (last % 8);
1168
1169         while (next < FIRST_SYSTEM_VECTOR) {
1170                 next += 8;
1171 #ifdef CONFIG_X86_64
1172                 if (next == IA32_SYSCALL_VECTOR)
1173                         continue;
1174 #else
1175                 if (next == SYSCALL_VECTOR)
1176                         continue;
1177 #endif
1178                 count++;
1179                 if (next >= FIRST_SYSTEM_VECTOR) {
1180                         if (offset%8) {
1181                                 next = FIRST_DEVICE_VECTOR + offset;
1182                                 offset++;
1183                                 continue;
1184                         }
1185                         count--;
1186                 }
1187         }
1188
1189         return count;
1190 }