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[PATCH] README: add info about -stable to README and point at applying-patches.txt
[linux-2.6/sactl.git] / drivers / serial / serial_txx9.c
blobf10c86d60b647fb8dedad8423d7f507920d3b705
1 /*
2 * drivers/serial/serial_txx9.c
3 *
4 * Derived from many drivers using generic_serial interface,
5 * especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c
6 * (was in Linux/VR tree) by Jim Pick.
7 *
8 * Copyright (C) 1999 Harald Koerfgen
9 * Copyright (C) 2000 Jim Pick <jim@jimpick.com>
10 * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
11 * Copyright (C) 2000-2002 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller
18 *
19 * Revision History:
20 * 0.30 Initial revision. (Renamed from serial_txx927.c)
21 * 0.31 Use save_flags instead of local_irq_save.
22 * 0.32 Support SCLK.
23 * 0.33 Switch TXX9_TTY_NAME by CONFIG_SERIAL_TXX9_STDSERIAL.
24 * Support TIOCSERGETLSR.
25 * 0.34 Support slow baudrate.
26 * 0.40 Merge codes from mainstream kernel (2.4.22).
27 * 0.41 Fix console checking in rs_shutdown_port().
28 * Disable flow-control in serial_console_write().
29 * 0.42 Fix minor compiler warning.
30 * 1.00 Kernel 2.6. Converted to new serial core (based on 8250.c).
31 * 1.01 Set fifosize to make tx_empry called properly.
32 * Use standard uart_get_divisor.
33 * 1.02 Cleanup. (import 8250.c changes)
34 * 1.03 Fix low-latency mode. (import 8250.c changes)
35 * 1.04 Remove usage of deprecated functions, cleanup.
36 */
37 #include <linux/config.h>
38
39 #if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
40 #define SUPPORT_SYSRQ
41 #endif
42
43 #include <linux/module.h>
44 #include <linux/ioport.h>
45 #include <linux/init.h>
46 #include <linux/console.h>
47 #include <linux/sysrq.h>
48 #include <linux/delay.h>
49 #include <linux/device.h>
50 #include <linux/pci.h>
51 #include <linux/tty.h>
52 #include <linux/tty_flip.h>
53 #include <linux/serial_core.h>
54 #include <linux/serial.h>
55
56 #include <asm/io.h>
57 #include <asm/irq.h>
58
59 static char *serial_version = "1.04";
60 static char *serial_name = "TX39/49 Serial driver";
61
62 #define PASS_LIMIT 256
63
64 #if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
65 /* "ttyS" is used for standard serial driver */
66 #define TXX9_TTY_NAME "ttyTX"
67 #define TXX9_TTY_DEVFS_NAME "tttx/"
68 #define TXX9_TTY_MINOR_START (64 + 64) /* ttyTX0(128), ttyTX1(129) */
69 #else
70 /* acts like standard serial driver */
71 #define TXX9_TTY_NAME "ttyS"
72 #define TXX9_TTY_DEVFS_NAME "tts/"
73 #define TXX9_TTY_MINOR_START 64
74 #endif
75 #define TXX9_TTY_MAJOR TTY_MAJOR
76
77 /* flag aliases */
78 #define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
79 #define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
80
81 #ifdef CONFIG_PCI
82 /* support for Toshiba TC86C001 SIO */
83 #define ENABLE_SERIAL_TXX9_PCI
84 #endif
85
86 /*
87 * Number of serial ports
88 */
89 #ifdef ENABLE_SERIAL_TXX9_PCI
90 #define NR_PCI_BOARDS 4
91 #define UART_NR (4 + NR_PCI_BOARDS)
92 #else
93 #define UART_NR 4
94 #endif
95
96 struct uart_txx9_port {
97 struct uart_port port;
98
99 /*
100 * We provide a per-port pm hook.
101 */
102 void (*pm)(struct uart_port *port,
103 unsigned int state, unsigned int old);
104 };
105
106 #define TXX9_REGION_SIZE 0x24
107
108 /* TXX9 Serial Registers */
109 #define TXX9_SILCR 0x00
110 #define TXX9_SIDICR 0x04
111 #define TXX9_SIDISR 0x08
112 #define TXX9_SICISR 0x0c
113 #define TXX9_SIFCR 0x10
114 #define TXX9_SIFLCR 0x14
115 #define TXX9_SIBGR 0x18
116 #define TXX9_SITFIFO 0x1c
117 #define TXX9_SIRFIFO 0x20
118
119 /* SILCR : Line Control */
120 #define TXX9_SILCR_SCS_MASK 0x00000060
121 #define TXX9_SILCR_SCS_IMCLK 0x00000000
122 #define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
123 #define TXX9_SILCR_SCS_SCLK 0x00000040
124 #define TXX9_SILCR_SCS_SCLK_BG 0x00000060
125 #define TXX9_SILCR_UEPS 0x00000010
126 #define TXX9_SILCR_UPEN 0x00000008
127 #define TXX9_SILCR_USBL_MASK 0x00000004
128 #define TXX9_SILCR_USBL_1BIT 0x00000000
129 #define TXX9_SILCR_USBL_2BIT 0x00000004
130 #define TXX9_SILCR_UMODE_MASK 0x00000003
131 #define TXX9_SILCR_UMODE_8BIT 0x00000000
132 #define TXX9_SILCR_UMODE_7BIT 0x00000001
133
134 /* SIDICR : DMA/Int. Control */
135 #define TXX9_SIDICR_TDE 0x00008000
136 #define TXX9_SIDICR_RDE 0x00004000
137 #define TXX9_SIDICR_TIE 0x00002000
138 #define TXX9_SIDICR_RIE 0x00001000
139 #define TXX9_SIDICR_SPIE 0x00000800
140 #define TXX9_SIDICR_CTSAC 0x00000600
141 #define TXX9_SIDICR_STIE_MASK 0x0000003f
142 #define TXX9_SIDICR_STIE_OERS 0x00000020
143 #define TXX9_SIDICR_STIE_CTSS 0x00000010
144 #define TXX9_SIDICR_STIE_RBRKD 0x00000008
145 #define TXX9_SIDICR_STIE_TRDY 0x00000004
146 #define TXX9_SIDICR_STIE_TXALS 0x00000002
147 #define TXX9_SIDICR_STIE_UBRKD 0x00000001
148
149 /* SIDISR : DMA/Int. Status */
150 #define TXX9_SIDISR_UBRK 0x00008000
151 #define TXX9_SIDISR_UVALID 0x00004000
152 #define TXX9_SIDISR_UFER 0x00002000
153 #define TXX9_SIDISR_UPER 0x00001000
154 #define TXX9_SIDISR_UOER 0x00000800
155 #define TXX9_SIDISR_ERI 0x00000400
156 #define TXX9_SIDISR_TOUT 0x00000200
157 #define TXX9_SIDISR_TDIS 0x00000100
158 #define TXX9_SIDISR_RDIS 0x00000080
159 #define TXX9_SIDISR_STIS 0x00000040
160 #define TXX9_SIDISR_RFDN_MASK 0x0000001f
161
162 /* SICISR : Change Int. Status */
163 #define TXX9_SICISR_OERS 0x00000020
164 #define TXX9_SICISR_CTSS 0x00000010
165 #define TXX9_SICISR_RBRKD 0x00000008
166 #define TXX9_SICISR_TRDY 0x00000004
167 #define TXX9_SICISR_TXALS 0x00000002
168 #define TXX9_SICISR_UBRKD 0x00000001
169
170 /* SIFCR : FIFO Control */
171 #define TXX9_SIFCR_SWRST 0x00008000
172 #define TXX9_SIFCR_RDIL_MASK 0x00000180
173 #define TXX9_SIFCR_RDIL_1 0x00000000
174 #define TXX9_SIFCR_RDIL_4 0x00000080
175 #define TXX9_SIFCR_RDIL_8 0x00000100
176 #define TXX9_SIFCR_RDIL_12 0x00000180
177 #define TXX9_SIFCR_RDIL_MAX 0x00000180
178 #define TXX9_SIFCR_TDIL_MASK 0x00000018
179 #define TXX9_SIFCR_TDIL_MASK 0x00000018
180 #define TXX9_SIFCR_TDIL_1 0x00000000
181 #define TXX9_SIFCR_TDIL_4 0x00000001
182 #define TXX9_SIFCR_TDIL_8 0x00000010
183 #define TXX9_SIFCR_TDIL_MAX 0x00000010
184 #define TXX9_SIFCR_TFRST 0x00000004
185 #define TXX9_SIFCR_RFRST 0x00000002
186 #define TXX9_SIFCR_FRSTE 0x00000001
187 #define TXX9_SIO_TX_FIFO 8
188 #define TXX9_SIO_RX_FIFO 16
189
190 /* SIFLCR : Flow Control */
191 #define TXX9_SIFLCR_RCS 0x00001000
192 #define TXX9_SIFLCR_TES 0x00000800
193 #define TXX9_SIFLCR_RTSSC 0x00000200
194 #define TXX9_SIFLCR_RSDE 0x00000100
195 #define TXX9_SIFLCR_TSDE 0x00000080
196 #define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
197 #define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
198 #define TXX9_SIFLCR_TBRK 0x00000001
199
200 /* SIBGR : Baudrate Control */
201 #define TXX9_SIBGR_BCLK_MASK 0x00000300
202 #define TXX9_SIBGR_BCLK_T0 0x00000000
203 #define TXX9_SIBGR_BCLK_T2 0x00000100
204 #define TXX9_SIBGR_BCLK_T4 0x00000200
205 #define TXX9_SIBGR_BCLK_T6 0x00000300
206 #define TXX9_SIBGR_BRD_MASK 0x000000ff
207
208 static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
209 {
210 switch (up->port.iotype) {
211 default:
212 return *(volatile u32 *)(up->port.membase + offset);
213 case UPIO_PORT:
214 return inl(up->port.iobase + offset);
215 }
216 }
217
218 static inline void
219 sio_out(struct uart_txx9_port *up, int offset, int value)
220 {
221 switch (up->port.iotype) {
222 default:
223 *(volatile u32 *)(up->port.membase + offset) = value;
224 break;
225 case UPIO_PORT:
226 outl(value, up->port.iobase + offset);
227 break;
228 }
229 }
230
231 static inline void
232 sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
233 {
234 sio_out(up, offset, sio_in(up, offset) & ~value);
235 }
236 static inline void
237 sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
238 {
239 sio_out(up, offset, sio_in(up, offset) | value);
240 }
241
242 static inline void
243 sio_quot_set(struct uart_txx9_port *up, int quot)
244 {
245 quot >>= 1;
246 if (quot < 256)
247 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
248 else if (quot < (256 << 2))
249 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
250 else if (quot < (256 << 4))
251 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
252 else if (quot < (256 << 6))
253 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
254 else
255 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
256 }
257
258 static void serial_txx9_stop_tx(struct uart_port *port)
259 {
260 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
261 unsigned long flags;
262
263 spin_lock_irqsave(&up->port.lock, flags);
264 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
265 spin_unlock_irqrestore(&up->port.lock, flags);
266 }
267
268 static void serial_txx9_start_tx(struct uart_port *port)
269 {
270 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
271 unsigned long flags;
272
273 spin_lock_irqsave(&up->port.lock, flags);
274 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
275 spin_unlock_irqrestore(&up->port.lock, flags);
276 }
277
278 static void serial_txx9_stop_rx(struct uart_port *port)
279 {
280 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
281 unsigned long flags;
282
283 spin_lock_irqsave(&up->port.lock, flags);
284 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
285 #if 0
286 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
287 #endif
288 spin_unlock_irqrestore(&up->port.lock, flags);
289 }
290
291 static void serial_txx9_enable_ms(struct uart_port *port)
292 {
293 /* TXX9-SIO can not control DTR... */
294 }
295
296 static inline void
297 receive_chars(struct uart_txx9_port *up, unsigned int *status, struct pt_regs *regs)
298 {
299 struct tty_struct *tty = up->port.info->tty;
300 unsigned char ch;
301 unsigned int disr = *status;
302 int max_count = 256;
303 char flag;
304
305 do {
306 /* The following is not allowed by the tty layer and
307 unsafe. It should be fixed ASAP */
308 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
309 if (tty->low_latency) {
310 spin_unlock(&up->port.lock);
311 tty_flip_buffer_push(tty);
312 spin_lock(&up->port.lock);
313 }
314 /* If this failed then we will throw away the
315 bytes but must do so to clear interrupts */
316 }
317 ch = sio_in(up, TXX9_SIRFIFO);
318 flag = TTY_NORMAL;
319 up->port.icount.rx++;
320
321 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
322 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
323 /*
324 * For statistics only
325 */
326 if (disr & TXX9_SIDISR_UBRK) {
327 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
328 up->port.icount.brk++;
329 /*
330 * We do the SysRQ and SAK checking
331 * here because otherwise the break
332 * may get masked by ignore_status_mask
333 * or read_status_mask.
334 */
335 if (uart_handle_break(&up->port))
336 goto ignore_char;
337 } else if (disr & TXX9_SIDISR_UPER)
338 up->port.icount.parity++;
339 else if (disr & TXX9_SIDISR_UFER)
340 up->port.icount.frame++;
341 if (disr & TXX9_SIDISR_UOER)
342 up->port.icount.overrun++;
343
344 /*
345 * Mask off conditions which should be ingored.
346 */
347 disr &= up->port.read_status_mask;
348
349 if (disr & TXX9_SIDISR_UBRK) {
350 flag = TTY_BREAK;
351 } else if (disr & TXX9_SIDISR_UPER)
352 flag = TTY_PARITY;
353 else if (disr & TXX9_SIDISR_UFER)
354 flag = TTY_FRAME;
355 }
356 if (uart_handle_sysrq_char(&up->port, ch, regs))
357 goto ignore_char;
358
359 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
360
361 ignore_char:
362 disr = sio_in(up, TXX9_SIDISR);
363 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
364 spin_unlock(&up->port.lock);
365 tty_flip_buffer_push(tty);
366 spin_lock(&up->port.lock);
367 *status = disr;
368 }
369
370 static inline void transmit_chars(struct uart_txx9_port *up)
371 {
372 struct circ_buf *xmit = &up->port.info->xmit;
373 int count;
374
375 if (up->port.x_char) {
376 sio_out(up, TXX9_SITFIFO, up->port.x_char);
377 up->port.icount.tx++;
378 up->port.x_char = 0;
379 return;
380 }
381 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
382 serial_txx9_stop_tx(&up->port);
383 return;
384 }
385
386 count = TXX9_SIO_TX_FIFO;
387 do {
388 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
389 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
390 up->port.icount.tx++;
391 if (uart_circ_empty(xmit))
392 break;
393 } while (--count > 0);
394
395 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
396 uart_write_wakeup(&up->port);
397
398 if (uart_circ_empty(xmit))
399 serial_txx9_stop_tx(&up->port);
400 }
401
402 static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id, struct pt_regs *regs)
403 {
404 int pass_counter = 0;
405 struct uart_txx9_port *up = dev_id;
406 unsigned int status;
407
408 while (1) {
409 spin_lock(&up->port.lock);
410 status = sio_in(up, TXX9_SIDISR);
411 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
412 status &= ~TXX9_SIDISR_TDIS;
413 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
414 TXX9_SIDISR_TOUT))) {
415 spin_unlock(&up->port.lock);
416 break;
417 }
418
419 if (status & TXX9_SIDISR_RDIS)
420 receive_chars(up, &status, regs);
421 if (status & TXX9_SIDISR_TDIS)
422 transmit_chars(up);
423 /* Clear TX/RX Int. Status */
424 sio_mask(up, TXX9_SIDISR,
425 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
426 TXX9_SIDISR_TOUT);
427 spin_unlock(&up->port.lock);
428
429 if (pass_counter++ > PASS_LIMIT)
430 break;
431 }
432
433 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
434 }
435
436 static unsigned int serial_txx9_tx_empty(struct uart_port *port)
437 {
438 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
439 unsigned long flags;
440 unsigned int ret;
441
442 spin_lock_irqsave(&up->port.lock, flags);
443 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
444 spin_unlock_irqrestore(&up->port.lock, flags);
445
446 return ret;
447 }
448
449 static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
450 {
451 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
452 unsigned int ret;
453
454 ret = ((sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS)
455 | ((sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS);
456
457 return ret;
458 }
459
460 static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
461 {
462 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
463 unsigned long flags;
464
465 spin_lock_irqsave(&up->port.lock, flags);
466 if (mctrl & TIOCM_RTS)
467 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
468 else
469 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
470 spin_unlock_irqrestore(&up->port.lock, flags);
471 }
472
473 static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
474 {
475 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
476 unsigned long flags;
477
478 spin_lock_irqsave(&up->port.lock, flags);
479 if (break_state == -1)
480 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
481 else
482 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
483 spin_unlock_irqrestore(&up->port.lock, flags);
484 }
485
486 static int serial_txx9_startup(struct uart_port *port)
487 {
488 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
489 unsigned long flags;
490 int retval;
491
492 /*
493 * Clear the FIFO buffers and disable them.
494 * (they will be reeanbled in set_termios())
495 */
496 sio_set(up, TXX9_SIFCR,
497 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
498 /* clear reset */
499 sio_mask(up, TXX9_SIFCR,
500 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
501 sio_out(up, TXX9_SIDICR, 0);
502
503 /*
504 * Clear the interrupt registers.
505 */
506 sio_out(up, TXX9_SIDISR, 0);
507
508 retval = request_irq(up->port.irq, serial_txx9_interrupt,
509 SA_SHIRQ, "serial_txx9", up);
510 if (retval)
511 return retval;
512
513 /*
514 * Now, initialize the UART
515 */
516 spin_lock_irqsave(&up->port.lock, flags);
517 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
518 spin_unlock_irqrestore(&up->port.lock, flags);
519
520 /* Enable RX/TX */
521 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
522
523 /*
524 * Finally, enable interrupts.
525 */
526 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
527
528 return 0;
529 }
530
531 static void serial_txx9_shutdown(struct uart_port *port)
532 {
533 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
534 unsigned long flags;
535
536 /*
537 * Disable interrupts from this port
538 */
539 sio_out(up, TXX9_SIDICR, 0); /* disable all intrs */
540
541 spin_lock_irqsave(&up->port.lock, flags);
542 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
543 spin_unlock_irqrestore(&up->port.lock, flags);
544
545 /*
546 * Disable break condition
547 */
548 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
549
550 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
551 if (up->port.cons && up->port.line == up->port.cons->index) {
552 free_irq(up->port.irq, up);
553 return;
554 }
555 #endif
556 /* reset FIFOs */
557 sio_set(up, TXX9_SIFCR,
558 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
559 /* clear reset */
560 sio_mask(up, TXX9_SIFCR,
561 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
562
563 /* Disable RX/TX */
564 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
565
566 free_irq(up->port.irq, up);
567 }
568
569 static void
570 serial_txx9_set_termios(struct uart_port *port, struct termios *termios,
571 struct termios *old)
572 {
573 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
574 unsigned int cval, fcr = 0;
575 unsigned long flags;
576 unsigned int baud, quot;
577
578 cval = sio_in(up, TXX9_SILCR);
579 /* byte size and parity */
580 cval &= ~TXX9_SILCR_UMODE_MASK;
581 switch (termios->c_cflag & CSIZE) {
582 case CS7:
583 cval |= TXX9_SILCR_UMODE_7BIT;
584 break;
585 default:
586 case CS5: /* not supported */
587 case CS6: /* not supported */
588 case CS8:
589 cval |= TXX9_SILCR_UMODE_8BIT;
590 break;
591 }
592
593 cval &= ~TXX9_SILCR_USBL_MASK;
594 if (termios->c_cflag & CSTOPB)
595 cval |= TXX9_SILCR_USBL_2BIT;
596 else
597 cval |= TXX9_SILCR_USBL_1BIT;
598 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
599 if (termios->c_cflag & PARENB)
600 cval |= TXX9_SILCR_UPEN;
601 if (!(termios->c_cflag & PARODD))
602 cval |= TXX9_SILCR_UEPS;
603
604 /*
605 * Ask the core to calculate the divisor for us.
606 */
607 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
608 quot = uart_get_divisor(port, baud);
609
610 /* Set up FIFOs */
611 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
612 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
613
614 /*
615 * Ok, we're now changing the port state. Do it with
616 * interrupts disabled.
617 */
618 spin_lock_irqsave(&up->port.lock, flags);
619
620 /*
621 * Update the per-port timeout.
622 */
623 uart_update_timeout(port, termios->c_cflag, baud);
624
625 up->port.read_status_mask = TXX9_SIDISR_UOER |
626 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
627 if (termios->c_iflag & INPCK)
628 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
629 if (termios->c_iflag & (BRKINT | PARMRK))
630 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
631
632 /*
633 * Characteres to ignore
634 */
635 up->port.ignore_status_mask = 0;
636 if (termios->c_iflag & IGNPAR)
637 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
638 if (termios->c_iflag & IGNBRK) {
639 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
640 /*
641 * If we're ignoring parity and break indicators,
642 * ignore overruns too (for real raw support).
643 */
644 if (termios->c_iflag & IGNPAR)
645 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
646 }
647
648 /*
649 * ignore all characters if CREAD is not set
650 */
651 if ((termios->c_cflag & CREAD) == 0)
652 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
653
654 /* CTS flow control flag */
655 if ((termios->c_cflag & CRTSCTS) &&
656 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
657 sio_set(up, TXX9_SIFLCR,
658 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
659 } else {
660 sio_mask(up, TXX9_SIFLCR,
661 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
662 }
663
664 sio_out(up, TXX9_SILCR, cval);
665 sio_quot_set(up, quot);
666 sio_out(up, TXX9_SIFCR, fcr);
667
668 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
669 spin_unlock_irqrestore(&up->port.lock, flags);
670 }
671
672 static void
673 serial_txx9_pm(struct uart_port *port, unsigned int state,
674 unsigned int oldstate)
675 {
676 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
677 if (up->pm)
678 up->pm(port, state, oldstate);
679 }
680
681 static int serial_txx9_request_resource(struct uart_txx9_port *up)
682 {
683 unsigned int size = TXX9_REGION_SIZE;
684 int ret = 0;
685
686 switch (up->port.iotype) {
687 default:
688 if (!up->port.mapbase)
689 break;
690
691 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
692 ret = -EBUSY;
693 break;
694 }
695
696 if (up->port.flags & UPF_IOREMAP) {
697 up->port.membase = ioremap(up->port.mapbase, size);
698 if (!up->port.membase) {
699 release_mem_region(up->port.mapbase, size);
700 ret = -ENOMEM;
701 }
702 }
703 break;
704
705 case UPIO_PORT:
706 if (!request_region(up->port.iobase, size, "serial_txx9"))
707 ret = -EBUSY;
708 break;
709 }
710 return ret;
711 }
712
713 static void serial_txx9_release_resource(struct uart_txx9_port *up)
714 {
715 unsigned int size = TXX9_REGION_SIZE;
716
717 switch (up->port.iotype) {
718 default:
719 if (!up->port.mapbase)
720 break;
721
722 if (up->port.flags & UPF_IOREMAP) {
723 iounmap(up->port.membase);
724 up->port.membase = NULL;
725 }
726
727 release_mem_region(up->port.mapbase, size);
728 break;
729
730 case UPIO_PORT:
731 release_region(up->port.iobase, size);
732 break;
733 }
734 }
735
736 static void serial_txx9_release_port(struct uart_port *port)
737 {
738 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
739 serial_txx9_release_resource(up);
740 }
741
742 static int serial_txx9_request_port(struct uart_port *port)
743 {
744 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
745 return serial_txx9_request_resource(up);
746 }
747
748 static void serial_txx9_config_port(struct uart_port *port, int uflags)
749 {
750 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
751 unsigned long flags;
752 int ret;
753
754 /*
755 * Find the region that we can probe for. This in turn
756 * tells us whether we can probe for the type of port.
757 */
758 ret = serial_txx9_request_resource(up);
759 if (ret < 0)
760 return;
761 port->type = PORT_TXX9;
762 up->port.fifosize = TXX9_SIO_TX_FIFO;
763
764 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
765 if (up->port.line == up->port.cons->index)
766 return;
767 #endif
768 spin_lock_irqsave(&up->port.lock, flags);
769 /*
770 * Reset the UART.
771 */
772 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
773 #ifdef CONFIG_CPU_TX49XX
774 /* TX4925 BUG WORKAROUND. Accessing SIOC register
775 * immediately after soft reset causes bus error. */
776 iob();
777 udelay(1);
778 #endif
779 while (sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST)
780 ;
781 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
782 sio_set(up, TXX9_SIFCR,
783 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
784 /* initial settings */
785 sio_out(up, TXX9_SILCR,
786 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
787 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
788 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
789 sio_quot_set(up, uart_get_divisor(port, 9600));
790 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
791 spin_unlock_irqrestore(&up->port.lock, flags);
792 }
793
794 static int
795 serial_txx9_verify_port(struct uart_port *port, struct serial_struct *ser)
796 {
797 if (ser->irq < 0 ||
798 ser->baud_base < 9600 || ser->type != PORT_TXX9)
799 return -EINVAL;
800 return 0;
801 }
802
803 static const char *
804 serial_txx9_type(struct uart_port *port)
805 {
806 return "txx9";
807 }
808
809 static struct uart_ops serial_txx9_pops = {
810 .tx_empty = serial_txx9_tx_empty,
811 .set_mctrl = serial_txx9_set_mctrl,
812 .get_mctrl = serial_txx9_get_mctrl,
813 .stop_tx = serial_txx9_stop_tx,
814 .start_tx = serial_txx9_start_tx,
815 .stop_rx = serial_txx9_stop_rx,
816 .enable_ms = serial_txx9_enable_ms,
817 .break_ctl = serial_txx9_break_ctl,
818 .startup = serial_txx9_startup,
819 .shutdown = serial_txx9_shutdown,
820 .set_termios = serial_txx9_set_termios,
821 .pm = serial_txx9_pm,
822 .type = serial_txx9_type,
823 .release_port = serial_txx9_release_port,
824 .request_port = serial_txx9_request_port,
825 .config_port = serial_txx9_config_port,
826 .verify_port = serial_txx9_verify_port,
827 };
828
829 static struct uart_txx9_port serial_txx9_ports[UART_NR];
830
831 static void __init serial_txx9_register_ports(struct uart_driver *drv)
832 {
833 int i;
834
835 for (i = 0; i < UART_NR; i++) {
836 struct uart_txx9_port *up = &serial_txx9_ports[i];
837
838 up->port.line = i;
839 up->port.ops = &serial_txx9_pops;
840 uart_add_one_port(drv, &up->port);
841 }
842 }
843
844 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
845
846 /*
847 * Wait for transmitter & holding register to empty
848 */
849 static inline void wait_for_xmitr(struct uart_txx9_port *up)
850 {
851 unsigned int tmout = 10000;
852
853 /* Wait up to 10ms for the character(s) to be sent. */
854 while (--tmout &&
855 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
856 udelay(1);
857
858 /* Wait up to 1s for flow control if necessary */
859 if (up->port.flags & UPF_CONS_FLOW) {
860 tmout = 1000000;
861 while (--tmout &&
862 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
863 udelay(1);
864 }
865 }
866
867 /*
868 * Print a string to the serial port trying not to disturb
869 * any possible real use of the port...
870 *
871 * The console_lock must be held when we get here.
872 */
873 static void
874 serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
875 {
876 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
877 unsigned int ier, flcr;
878 int i;
879
880 /*
881 * First save the UER then disable the interrupts
882 */
883 ier = sio_in(up, TXX9_SIDICR);
884 sio_out(up, TXX9_SIDICR, 0);
885 /*
886 * Disable flow-control if enabled (and unnecessary)
887 */
888 flcr = sio_in(up, TXX9_SIFLCR);
889 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
890 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
891
892 /*
893 * Now, do each character
894 */
895 for (i = 0; i < count; i++, s++) {
896 wait_for_xmitr(up);
897
898 /*
899 * Send the character out.
900 * If a LF, also do CR...
901 */
902 sio_out(up, TXX9_SITFIFO, *s);
903 if (*s == 10) {
904 wait_for_xmitr(up);
905 sio_out(up, TXX9_SITFIFO, 13);
906 }
907 }
908
909 /*
910 * Finally, wait for transmitter to become empty
911 * and restore the IER
912 */
913 wait_for_xmitr(up);
914 sio_out(up, TXX9_SIFLCR, flcr);
915 sio_out(up, TXX9_SIDICR, ier);
916 }
917
918 static int serial_txx9_console_setup(struct console *co, char *options)
919 {
920 struct uart_port *port;
921 struct uart_txx9_port *up;
922 int baud = 9600;
923 int bits = 8;
924 int parity = 'n';
925 int flow = 'n';
926
927 /*
928 * Check whether an invalid uart number has been specified, and
929 * if so, search for the first available port that does have
930 * console support.
931 */
932 if (co->index >= UART_NR)
933 co->index = 0;
934 up = &serial_txx9_ports[co->index];
935 port = &up->port;
936 if (!port->ops)
937 return -ENODEV;
938
939 /*
940 * Temporary fix.
941 */
942 spin_lock_init(&port->lock);
943
944 /*
945 * Disable UART interrupts, set DTR and RTS high
946 * and set speed.
947 */
948 sio_out(up, TXX9_SIDICR, 0);
949 /* initial settings */
950 sio_out(up, TXX9_SILCR,
951 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
952 ((port->flags & UPF_TXX9_USE_SCLK) ?
953 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
954 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
955
956 if (options)
957 uart_parse_options(options, &baud, &parity, &bits, &flow);
958
959 return uart_set_options(port, co, baud, parity, bits, flow);
960 }
961
962 static struct uart_driver serial_txx9_reg;
963 static struct console serial_txx9_console = {
964 .name = TXX9_TTY_NAME,
965 .write = serial_txx9_console_write,
966 .device = uart_console_device,
967 .setup = serial_txx9_console_setup,
968 .flags = CON_PRINTBUFFER,
969 .index = -1,
970 .data = &serial_txx9_reg,
971 };
972
973 static int __init serial_txx9_console_init(void)
974 {
975 register_console(&serial_txx9_console);
976 return 0;
977 }
978 console_initcall(serial_txx9_console_init);
979
980 #define SERIAL_TXX9_CONSOLE &serial_txx9_console
981 #else
982 #define SERIAL_TXX9_CONSOLE NULL
983 #endif
984
985 static struct uart_driver serial_txx9_reg = {
986 .owner = THIS_MODULE,
987 .driver_name = "serial_txx9",
988 .devfs_name = TXX9_TTY_DEVFS_NAME,
989 .dev_name = TXX9_TTY_NAME,
990 .major = TXX9_TTY_MAJOR,
991 .minor = TXX9_TTY_MINOR_START,
992 .nr = UART_NR,
993 .cons = SERIAL_TXX9_CONSOLE,
994 };
995
996 int __init early_serial_txx9_setup(struct uart_port *port)
997 {
998 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
999 return -ENODEV;
1000
1001 serial_txx9_ports[port->line].port = *port;
1002 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
1003 serial_txx9_ports[port->line].port.flags |= UPF_BOOT_AUTOCONF;
1004 return 0;
1005 }
1006
1007 #ifdef ENABLE_SERIAL_TXX9_PCI
1008 /**
1009 * serial_txx9_suspend_port - suspend one serial port
1010 * @line: serial line number
1011 * @level: the level of port suspension, as per uart_suspend_port
1012 *
1013 * Suspend one serial port.
1014 */
1015 static void serial_txx9_suspend_port(int line)
1016 {
1017 uart_suspend_port(&serial_txx9_reg, &serial_txx9_ports[line].port);
1018 }
1019
1020 /**
1021 * serial_txx9_resume_port - resume one serial port
1022 * @line: serial line number
1023 * @level: the level of port resumption, as per uart_resume_port
1024 *
1025 * Resume one serial port.
1026 */
1027 static void serial_txx9_resume_port(int line)
1028 {
1029 uart_resume_port(&serial_txx9_reg, &serial_txx9_ports[line].port);
1030 }
1031
1032 static DECLARE_MUTEX(serial_txx9_sem);
1033
1034 /**
1035 * serial_txx9_register_port - register a serial port
1036 * @port: serial port template
1037 *
1038 * Configure the serial port specified by the request.
1039 *
1040 * The port is then probed and if necessary the IRQ is autodetected
1041 * If this fails an error is returned.
1042 *
1043 * On success the port is ready to use and the line number is returned.
1044 */
1045 static int __devinit serial_txx9_register_port(struct uart_port *port)
1046 {
1047 int i;
1048 struct uart_txx9_port *uart;
1049 int ret = -ENOSPC;
1050
1051 down(&serial_txx9_sem);
1052 for (i = 0; i < UART_NR; i++) {
1053 uart = &serial_txx9_ports[i];
1054 if (uart->port.type == PORT_UNKNOWN)
1055 break;
1056 }
1057 if (i < UART_NR) {
1058 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1059 uart->port.iobase = port->iobase;
1060 uart->port.membase = port->membase;
1061 uart->port.irq = port->irq;
1062 uart->port.uartclk = port->uartclk;
1063 uart->port.iotype = port->iotype;
1064 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
1065 uart->port.mapbase = port->mapbase;
1066 if (port->dev)
1067 uart->port.dev = port->dev;
1068 ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
1069 if (ret == 0)
1070 ret = uart->port.line;
1071 }
1072 up(&serial_txx9_sem);
1073 return ret;
1074 }
1075
1076 /**
1077 * serial_txx9_unregister_port - remove a txx9 serial port at runtime
1078 * @line: serial line number
1079 *
1080 * Remove one serial port. This may not be called from interrupt
1081 * context. We hand the port back to the our control.
1082 */
1083 static void __devexit serial_txx9_unregister_port(int line)
1084 {
1085 struct uart_txx9_port *uart = &serial_txx9_ports[line];
1086
1087 down(&serial_txx9_sem);
1088 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1089 uart->port.flags = 0;
1090 uart->port.type = PORT_UNKNOWN;
1091 uart->port.iobase = 0;
1092 uart->port.mapbase = 0;
1093 uart->port.membase = 0;
1094 uart->port.dev = NULL;
1095 uart_add_one_port(&serial_txx9_reg, &uart->port);
1096 up(&serial_txx9_sem);
1097 }
1098
1099 /*
1100 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1101 * to the arrangement of serial ports on a PCI card.
1102 */
1103 static int __devinit
1104 pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1105 {
1106 struct uart_port port;
1107 int line;
1108 int rc;
1109
1110 rc = pci_enable_device(dev);
1111 if (rc)
1112 return rc;
1113
1114 memset(&port, 0, sizeof(port));
1115 port.ops = &serial_txx9_pops;
1116 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1117 port.uartclk = 66670000;
1118 port.irq = dev->irq;
1119 port.iotype = UPIO_PORT;
1120 port.iobase = pci_resource_start(dev, 1);
1121 port.dev = &dev->dev;
1122 line = serial_txx9_register_port(&port);
1123 if (line < 0) {
1124 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1125 }
1126 pci_set_drvdata(dev, (void *)(long)line);
1127
1128 return 0;
1129 }
1130
1131 static void __devexit pciserial_txx9_remove_one(struct pci_dev *dev)
1132 {
1133 int line = (int)(long)pci_get_drvdata(dev);
1134
1135 pci_set_drvdata(dev, NULL);
1136
1137 if (line) {
1138 serial_txx9_unregister_port(line);
1139 pci_disable_device(dev);
1140 }
1141 }
1142
1143 static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1144 {
1145 int line = (int)(long)pci_get_drvdata(dev);
1146
1147 if (line)
1148 serial_txx9_suspend_port(line);
1149 pci_save_state(dev);
1150 pci_set_power_state(dev, pci_choose_state(dev, state));
1151 return 0;
1152 }
1153
1154 static int pciserial_txx9_resume_one(struct pci_dev *dev)
1155 {
1156 int line = (int)(long)pci_get_drvdata(dev);
1157
1158 pci_set_power_state(dev, PCI_D0);
1159 pci_restore_state(dev);
1160
1161 if (line) {
1162 pci_enable_device(dev);
1163 serial_txx9_resume_port(line);
1164 }
1165 return 0;
1166 }
1167
1168 static struct pci_device_id serial_txx9_pci_tbl[] = {
1169 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC,
1170 PCI_ANY_ID, PCI_ANY_ID,
1171 0, 0, 0 },
1172 { 0, }
1173 };
1174
1175 static struct pci_driver serial_txx9_pci_driver = {
1176 .name = "serial_txx9",
1177 .probe = pciserial_txx9_init_one,
1178 .remove = __devexit_p(pciserial_txx9_remove_one),
1179 .suspend = pciserial_txx9_suspend_one,
1180 .resume = pciserial_txx9_resume_one,
1181 .id_table = serial_txx9_pci_tbl,
1182 };
1183
1184 MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1185 #endif /* ENABLE_SERIAL_TXX9_PCI */
1186
1187 static int __init serial_txx9_init(void)
1188 {
1189 int ret;
1190
1191 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1192
1193 ret = uart_register_driver(&serial_txx9_reg);
1194 if (ret >= 0) {
1195 serial_txx9_register_ports(&serial_txx9_reg);
1196
1197 #ifdef ENABLE_SERIAL_TXX9_PCI
1198 ret = pci_module_init(&serial_txx9_pci_driver);
1199 #endif
1200 }
1201 return ret;
1202 }
1203
1204 static void __exit serial_txx9_exit(void)
1205 {
1206 int i;
1207
1208 #ifdef ENABLE_SERIAL_TXX9_PCI
1209 pci_unregister_driver(&serial_txx9_pci_driver);
1210 #endif
1211 for (i = 0; i < UART_NR; i++)
1212 uart_remove_one_port(&serial_txx9_reg, &serial_txx9_ports[i].port);
1213
1214 uart_unregister_driver(&serial_txx9_reg);
1215 }
1216
1217 module_init(serial_txx9_init);
1218 module_exit(serial_txx9_exit);
1219
1220 MODULE_LICENSE("GPL");
1221 MODULE_DESCRIPTION("TX39/49 serial driver");
1222
1223 MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
SocketAccessConTroL development