[PATCH] pcmcia: ide-cs id_table update
[linux-2.6/sactl.git] / include / asm-sh / dma.h
blob8e9436093ca826adb2bf7db5df254d8413c0f7cc
1 /*
2 * include/asm-sh/dma.h
4 * Copyright (C) 2003, 2004 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #ifndef __ASM_SH_DMA_H
11 #define __ASM_SH_DMA_H
12 #ifdef __KERNEL__
14 #include <linux/config.h>
15 #include <linux/spinlock.h>
16 #include <linux/wait.h>
17 #include <linux/sysdev.h>
18 #include <asm/cpu/dma.h>
19 #include <asm/semaphore.h>
21 /* The maximum address that we can perform a DMA transfer to on this platform */
22 /* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
23 occurrence should be flagged as an error. */
24 /* But... */
25 /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
26 #define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
28 #ifdef CONFIG_NR_DMA_CHANNELS
29 # define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
30 #else
31 # define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
32 #endif
35 * Read and write modes can mean drastically different things depending on the
36 * channel configuration. Consult your DMAC documentation and module
37 * implementation for further clues.
39 #define DMA_MODE_READ 0x00
40 #define DMA_MODE_WRITE 0x01
41 #define DMA_MODE_MASK 0x01
43 #define DMA_AUTOINIT 0x10
46 * DMAC (dma_info) flags
48 enum {
49 DMAC_CHANNELS_CONFIGURED = 0x00,
50 DMAC_CHANNELS_TEI_CAPABLE = 0x01,
54 * DMA channel capabilities / flags
56 enum {
57 DMA_CONFIGURED = 0x00,
58 DMA_TEI_CAPABLE = 0x01,
61 extern spinlock_t dma_spin_lock;
63 struct dma_channel;
65 struct dma_ops {
66 int (*request)(struct dma_channel *chan);
67 void (*free)(struct dma_channel *chan);
69 int (*get_residue)(struct dma_channel *chan);
70 int (*xfer)(struct dma_channel *chan);
71 void (*configure)(struct dma_channel *chan, unsigned long flags);
74 struct dma_channel {
75 char dev_id[16];
77 unsigned int chan;
78 unsigned int mode;
79 unsigned int count;
81 unsigned long sar;
82 unsigned long dar;
84 unsigned long flags;
85 atomic_t busy;
87 struct semaphore sem;
88 wait_queue_head_t wait_queue;
90 struct sys_device dev;
93 struct dma_info {
94 const char *name;
95 unsigned int nr_channels;
96 unsigned long flags;
98 struct dma_ops *ops;
99 struct dma_channel *channels;
101 struct list_head list;
104 #define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
106 /* arch/sh/drivers/dma/dma-api.c */
107 extern int dma_xfer(unsigned int chan, unsigned long from,
108 unsigned long to, size_t size, unsigned int mode);
110 #define dma_write(chan, from, to, size) \
111 dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
112 #define dma_write_page(chan, from, to) \
113 dma_write(chan, from, to, PAGE_SIZE)
115 #define dma_read(chan, from, to, size) \
116 dma_xfer(chan, from, to, size, DMA_MODE_READ)
117 #define dma_read_page(chan, from, to) \
118 dma_read(chan, from, to, PAGE_SIZE)
120 extern int request_dma(unsigned int chan, const char *dev_id);
121 extern void free_dma(unsigned int chan);
122 extern int get_dma_residue(unsigned int chan);
123 extern struct dma_info *get_dma_info(unsigned int chan);
124 extern struct dma_channel *get_dma_channel(unsigned int chan);
125 extern void dma_wait_for_completion(unsigned int chan);
126 extern void dma_configure_channel(unsigned int chan, unsigned long flags);
128 extern int register_dmac(struct dma_info *info);
129 extern void unregister_dmac(struct dma_info *info);
131 #ifdef CONFIG_SYSFS
132 /* arch/sh/drivers/dma/dma-sysfs.c */
133 extern int dma_create_sysfs_files(struct dma_channel *);
134 #endif
136 #ifdef CONFIG_PCI
137 extern int isa_dma_bridge_buggy;
138 #else
139 #define isa_dma_bridge_buggy (0)
140 #endif
142 #endif /* __KERNEL__ */
143 #endif /* __ASM_SH_DMA_H */