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docsrc: fix getdelays printk formats
[linux-2.6/sactl.git] / drivers / video / neofb.c
blob25172b2a2a941e15fe684e9130293c019467981d
1 /*
2 * linux/drivers/video/neofb.c -- NeoMagic Framebuffer Driver
3 *
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 *
6 *
7 * Card specific code is based on XFree86's neomagic driver.
8 * Framebuffer framework code is based on code of cyber2000fb.
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file COPYING in the main directory of this
12 * archive for more details.
13 *
14 *
15 * 0.4.1
16 * - Cosmetic changes (dok)
17 *
18 * 0.4
19 * - Toshiba Libretto support, allow modes larger than LCD size if
20 * LCD is disabled, keep BIOS settings if internal/external display
21 * haven't been enabled explicitly
22 * (Thomas J. Moore <dark@mama.indstate.edu>)
23 *
24 * 0.3.3
25 * - Porting over to new fbdev api. (jsimmons)
26 *
27 * 0.3.2
28 * - got rid of all floating point (dok)
29 *
30 * 0.3.1
31 * - added module license (dok)
32 *
33 * 0.3
34 * - hardware accelerated clear and move for 2200 and above (dok)
35 * - maximum allowed dotclock is handled now (dok)
36 *
37 * 0.2.1
38 * - correct panning after X usage (dok)
39 * - added module and kernel parameters (dok)
40 * - no stretching if external display is enabled (dok)
41 *
42 * 0.2
43 * - initial version (dok)
44 *
45 *
46 * TODO
47 * - ioctl for internal/external switching
48 * - blanking
49 * - 32bit depth support, maybe impossible
50 * - disable pan-on-sync, need specs
51 *
52 * BUGS
53 * - white margin on bootup like with tdfxfb (colormap problem?)
54 *
55 */
56
57 #include <linux/module.h>
58 #include <linux/kernel.h>
59 #include <linux/errno.h>
60 #include <linux/string.h>
61 #include <linux/mm.h>
62 #include <linux/slab.h>
63 #include <linux/delay.h>
64 #include <linux/fb.h>
65 #include <linux/pci.h>
66 #include <linux/init.h>
67 #ifdef CONFIG_TOSHIBA
68 #include <linux/toshiba.h>
69 #endif
70
71 #include <asm/io.h>
72 #include <asm/irq.h>
73 #include <asm/pgtable.h>
74 #include <asm/system.h>
75
76 #ifdef CONFIG_MTRR
77 #include <asm/mtrr.h>
78 #endif
79
80 #include <video/vga.h>
81 #include <video/neomagic.h>
82
83 #define NEOFB_VERSION "0.4.2"
84
85 /* --------------------------------------------------------------------- */
86
87 static int internal;
88 static int external;
89 static int libretto;
90 static int nostretch;
91 static int nopciburst;
92 static char *mode_option __devinitdata = NULL;
93
94 #ifdef MODULE
95
96 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@convergence.de>");
97 MODULE_LICENSE("GPL");
98 MODULE_DESCRIPTION("FBDev driver for NeoMagic PCI Chips");
99 module_param(internal, bool, 0);
100 MODULE_PARM_DESC(internal, "Enable output on internal LCD Display.");
101 module_param(external, bool, 0);
102 MODULE_PARM_DESC(external, "Enable output on external CRT.");
103 module_param(libretto, bool, 0);
104 MODULE_PARM_DESC(libretto, "Force Libretto 100/110 800x480 LCD.");
105 module_param(nostretch, bool, 0);
106 MODULE_PARM_DESC(nostretch,
107 "Disable stretching of modes smaller than LCD.");
108 module_param(nopciburst, bool, 0);
109 MODULE_PARM_DESC(nopciburst, "Disable PCI burst mode.");
110 module_param(mode_option, charp, 0);
111 MODULE_PARM_DESC(mode_option, "Preferred video mode ('640x480-8@60', etc)");
112
113 #endif
114
115
116 /* --------------------------------------------------------------------- */
117
118 static biosMode bios8[] = {
119 {320, 240, 0x40},
120 {300, 400, 0x42},
121 {640, 400, 0x20},
122 {640, 480, 0x21},
123 {800, 600, 0x23},
124 {1024, 768, 0x25},
125 };
126
127 static biosMode bios16[] = {
128 {320, 200, 0x2e},
129 {320, 240, 0x41},
130 {300, 400, 0x43},
131 {640, 480, 0x31},
132 {800, 600, 0x34},
133 {1024, 768, 0x37},
134 };
135
136 static biosMode bios24[] = {
137 {640, 480, 0x32},
138 {800, 600, 0x35},
139 {1024, 768, 0x38}
140 };
141
142 #ifdef NO_32BIT_SUPPORT_YET
143 /* FIXME: guessed values, wrong */
144 static biosMode bios32[] = {
145 {640, 480, 0x33},
146 {800, 600, 0x36},
147 {1024, 768, 0x39}
148 };
149 #endif
150
151 static inline void write_le32(int regindex, u32 val, const struct neofb_par *par)
152 {
153 writel(val, par->neo2200 + par->cursorOff + regindex);
154 }
155
156 static int neoFindMode(int xres, int yres, int depth)
157 {
158 int xres_s;
159 int i, size;
160 biosMode *mode;
161
162 switch (depth) {
163 case 8:
164 size = ARRAY_SIZE(bios8);
165 mode = bios8;
166 break;
167 case 16:
168 size = ARRAY_SIZE(bios16);
169 mode = bios16;
170 break;
171 case 24:
172 size = ARRAY_SIZE(bios24);
173 mode = bios24;
174 break;
175 #ifdef NO_32BIT_SUPPORT_YET
176 case 32:
177 size = ARRAY_SIZE(bios32);
178 mode = bios32;
179 break;
180 #endif
181 default:
182 return 0;
183 }
184
185 for (i = 0; i < size; i++) {
186 if (xres <= mode[i].x_res) {
187 xres_s = mode[i].x_res;
188 for (; i < size; i++) {
189 if (mode[i].x_res != xres_s)
190 return mode[i - 1].mode;
191 if (yres <= mode[i].y_res)
192 return mode[i].mode;
193 }
194 }
195 }
196 return mode[size - 1].mode;
197 }
198
199 /*
200 * neoCalcVCLK --
201 *
202 * Determine the closest clock frequency to the one requested.
203 */
204 #define MAX_N 127
205 #define MAX_D 31
206 #define MAX_F 1
207
208 static void neoCalcVCLK(const struct fb_info *info,
209 struct neofb_par *par, long freq)
210 {
211 int n, d, f;
212 int n_best = 0, d_best = 0, f_best = 0;
213 long f_best_diff = 0x7ffff;
214
215 for (f = 0; f <= MAX_F; f++)
216 for (d = 0; d <= MAX_D; d++)
217 for (n = 0; n <= MAX_N; n++) {
218 long f_out;
219 long f_diff;
220
221 f_out = ((14318 * (n + 1)) / (d + 1)) >> f;
222 f_diff = abs(f_out - freq);
223 if (f_diff <= f_best_diff) {
224 f_best_diff = f_diff;
225 n_best = n;
226 d_best = d;
227 f_best = f;
228 }
229 if (f_out > freq)
230 break;
231 }
232
233 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
234 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
235 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
236 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
237 /* NOT_DONE: We are trying the full range of the 2200 clock.
238 We should be able to try n up to 2047 */
239 par->VCLK3NumeratorLow = n_best;
240 par->VCLK3NumeratorHigh = (f_best << 7);
241 } else
242 par->VCLK3NumeratorLow = n_best | (f_best << 7);
243
244 par->VCLK3Denominator = d_best;
245
246 #ifdef NEOFB_DEBUG
247 printk(KERN_DEBUG "neoVCLK: f:%ld NumLow=%d NumHi=%d Den=%d Df=%ld\n",
248 freq,
249 par->VCLK3NumeratorLow,
250 par->VCLK3NumeratorHigh,
251 par->VCLK3Denominator, f_best_diff);
252 #endif
253 }
254
255 /*
256 * vgaHWInit --
257 * Handle the initialization, etc. of a screen.
258 * Return FALSE on failure.
259 */
260
261 static int vgaHWInit(const struct fb_var_screeninfo *var,
262 struct neofb_par *par)
263 {
264 int hsync_end = var->xres + var->right_margin + var->hsync_len;
265 int htotal = (hsync_end + var->left_margin) >> 3;
266 int vsync_start = var->yres + var->lower_margin;
267 int vsync_end = vsync_start + var->vsync_len;
268 int vtotal = vsync_end + var->upper_margin;
269
270 par->MiscOutReg = 0x23;
271
272 if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
273 par->MiscOutReg |= 0x40;
274
275 if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
276 par->MiscOutReg |= 0x80;
277
278 /*
279 * Time Sequencer
280 */
281 par->Sequencer[0] = 0x00;
282 par->Sequencer[1] = 0x01;
283 par->Sequencer[2] = 0x0F;
284 par->Sequencer[3] = 0x00; /* Font select */
285 par->Sequencer[4] = 0x0E; /* Misc */
286
287 /*
288 * CRTC Controller
289 */
290 par->CRTC[0] = htotal - 5;
291 par->CRTC[1] = (var->xres >> 3) - 1;
292 par->CRTC[2] = (var->xres >> 3) - 1;
293 par->CRTC[3] = ((htotal - 1) & 0x1F) | 0x80;
294 par->CRTC[4] = ((var->xres + var->right_margin) >> 3);
295 par->CRTC[5] = (((htotal - 1) & 0x20) << 2)
296 | (((hsync_end >> 3)) & 0x1F);
297 par->CRTC[6] = (vtotal - 2) & 0xFF;
298 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8)
299 | (((var->yres - 1) & 0x100) >> 7)
300 | ((vsync_start & 0x100) >> 6)
301 | (((var->yres - 1) & 0x100) >> 5)
302 | 0x10 | (((vtotal - 2) & 0x200) >> 4)
303 | (((var->yres - 1) & 0x200) >> 3)
304 | ((vsync_start & 0x200) >> 2);
305 par->CRTC[8] = 0x00;
306 par->CRTC[9] = (((var->yres - 1) & 0x200) >> 4) | 0x40;
307
308 if (var->vmode & FB_VMODE_DOUBLE)
309 par->CRTC[9] |= 0x80;
310
311 par->CRTC[10] = 0x00;
312 par->CRTC[11] = 0x00;
313 par->CRTC[12] = 0x00;
314 par->CRTC[13] = 0x00;
315 par->CRTC[14] = 0x00;
316 par->CRTC[15] = 0x00;
317 par->CRTC[16] = vsync_start & 0xFF;
318 par->CRTC[17] = (vsync_end & 0x0F) | 0x20;
319 par->CRTC[18] = (var->yres - 1) & 0xFF;
320 par->CRTC[19] = var->xres_virtual >> 4;
321 par->CRTC[20] = 0x00;
322 par->CRTC[21] = (var->yres - 1) & 0xFF;
323 par->CRTC[22] = (vtotal - 1) & 0xFF;
324 par->CRTC[23] = 0xC3;
325 par->CRTC[24] = 0xFF;
326
327 /*
328 * are these unnecessary?
329 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
330 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
331 */
332
333 /*
334 * Graphics Display Controller
335 */
336 par->Graphics[0] = 0x00;
337 par->Graphics[1] = 0x00;
338 par->Graphics[2] = 0x00;
339 par->Graphics[3] = 0x00;
340 par->Graphics[4] = 0x00;
341 par->Graphics[5] = 0x40;
342 par->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
343 par->Graphics[7] = 0x0F;
344 par->Graphics[8] = 0xFF;
345
346
347 par->Attribute[0] = 0x00; /* standard colormap translation */
348 par->Attribute[1] = 0x01;
349 par->Attribute[2] = 0x02;
350 par->Attribute[3] = 0x03;
351 par->Attribute[4] = 0x04;
352 par->Attribute[5] = 0x05;
353 par->Attribute[6] = 0x06;
354 par->Attribute[7] = 0x07;
355 par->Attribute[8] = 0x08;
356 par->Attribute[9] = 0x09;
357 par->Attribute[10] = 0x0A;
358 par->Attribute[11] = 0x0B;
359 par->Attribute[12] = 0x0C;
360 par->Attribute[13] = 0x0D;
361 par->Attribute[14] = 0x0E;
362 par->Attribute[15] = 0x0F;
363 par->Attribute[16] = 0x41;
364 par->Attribute[17] = 0xFF;
365 par->Attribute[18] = 0x0F;
366 par->Attribute[19] = 0x00;
367 par->Attribute[20] = 0x00;
368 return 0;
369 }
370
371 static void vgaHWLock(struct vgastate *state)
372 {
373 /* Protect CRTC[0-7] */
374 vga_wcrt(state->vgabase, 0x11, vga_rcrt(state->vgabase, 0x11) | 0x80);
375 }
376
377 static void vgaHWUnlock(void)
378 {
379 /* Unprotect CRTC[0-7] */
380 vga_wcrt(NULL, 0x11, vga_rcrt(NULL, 0x11) & ~0x80);
381 }
382
383 static void neoLock(struct vgastate *state)
384 {
385 vga_wgfx(state->vgabase, 0x09, 0x00);
386 vgaHWLock(state);
387 }
388
389 static void neoUnlock(void)
390 {
391 vgaHWUnlock();
392 vga_wgfx(NULL, 0x09, 0x26);
393 }
394
395 /*
396 * VGA Palette management
397 */
398 static int paletteEnabled = 0;
399
400 static inline void VGAenablePalette(void)
401 {
402 vga_r(NULL, VGA_IS1_RC);
403 vga_w(NULL, VGA_ATT_W, 0x00);
404 paletteEnabled = 1;
405 }
406
407 static inline void VGAdisablePalette(void)
408 {
409 vga_r(NULL, VGA_IS1_RC);
410 vga_w(NULL, VGA_ATT_W, 0x20);
411 paletteEnabled = 0;
412 }
413
414 static inline void VGAwATTR(u8 index, u8 value)
415 {
416 if (paletteEnabled)
417 index &= ~0x20;
418 else
419 index |= 0x20;
420
421 vga_r(NULL, VGA_IS1_RC);
422 vga_wattr(NULL, index, value);
423 }
424
425 static void vgaHWProtect(int on)
426 {
427 unsigned char tmp;
428
429 if (on) {
430 /*
431 * Turn off screen and disable sequencer.
432 */
433 tmp = vga_rseq(NULL, 0x01);
434 vga_wseq(NULL, 0x00, 0x01); /* Synchronous Reset */
435 vga_wseq(NULL, 0x01, tmp | 0x20); /* disable the display */
436
437 VGAenablePalette();
438 } else {
439 /*
440 * Reenable sequencer, then turn on screen.
441 */
442 tmp = vga_rseq(NULL, 0x01);
443 vga_wseq(NULL, 0x01, tmp & ~0x20); /* reenable display */
444 vga_wseq(NULL, 0x00, 0x03); /* clear synchronousreset */
445
446 VGAdisablePalette();
447 }
448 }
449
450 static void vgaHWRestore(const struct fb_info *info,
451 const struct neofb_par *par)
452 {
453 int i;
454
455 vga_w(NULL, VGA_MIS_W, par->MiscOutReg);
456
457 for (i = 1; i < 5; i++)
458 vga_wseq(NULL, i, par->Sequencer[i]);
459
460 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or CRTC[17] */
461 vga_wcrt(NULL, 17, par->CRTC[17] & ~0x80);
462
463 for (i = 0; i < 25; i++)
464 vga_wcrt(NULL, i, par->CRTC[i]);
465
466 for (i = 0; i < 9; i++)
467 vga_wgfx(NULL, i, par->Graphics[i]);
468
469 VGAenablePalette();
470
471 for (i = 0; i < 21; i++)
472 VGAwATTR(i, par->Attribute[i]);
473
474 VGAdisablePalette();
475 }
476
477
478 /* -------------------- Hardware specific routines ------------------------- */
479
480 /*
481 * Hardware Acceleration for Neo2200+
482 */
483 static inline int neo2200_sync(struct fb_info *info)
484 {
485 struct neofb_par *par = info->par;
486
487 while (readl(&par->neo2200->bltStat) & 1)
488 cpu_relax();
489 return 0;
490 }
491
492 static inline void neo2200_wait_fifo(struct fb_info *info,
493 int requested_fifo_space)
494 {
495 // ndev->neo.waitfifo_calls++;
496 // ndev->neo.waitfifo_sum += requested_fifo_space;
497
498 /* FIXME: does not work
499 if (neo_fifo_space < requested_fifo_space)
500 {
501 neo_fifo_waitcycles++;
502
503 while (1)
504 {
505 neo_fifo_space = (neo2200->bltStat >> 8);
506 if (neo_fifo_space >= requested_fifo_space)
507 break;
508 }
509 }
510 else
511 {
512 neo_fifo_cache_hits++;
513 }
514
515 neo_fifo_space -= requested_fifo_space;
516 */
517
518 neo2200_sync(info);
519 }
520
521 static inline void neo2200_accel_init(struct fb_info *info,
522 struct fb_var_screeninfo *var)
523 {
524 struct neofb_par *par = info->par;
525 Neo2200 __iomem *neo2200 = par->neo2200;
526 u32 bltMod, pitch;
527
528 neo2200_sync(info);
529
530 switch (var->bits_per_pixel) {
531 case 8:
532 bltMod = NEO_MODE1_DEPTH8;
533 pitch = var->xres_virtual;
534 break;
535 case 15:
536 case 16:
537 bltMod = NEO_MODE1_DEPTH16;
538 pitch = var->xres_virtual * 2;
539 break;
540 case 24:
541 bltMod = NEO_MODE1_DEPTH24;
542 pitch = var->xres_virtual * 3;
543 break;
544 default:
545 printk(KERN_ERR
546 "neofb: neo2200_accel_init: unexpected bits per pixel!\n");
547 return;
548 }
549
550 writel(bltMod << 16, &neo2200->bltStat);
551 writel((pitch << 16) | pitch, &neo2200->pitch);
552 }
553
554 /* --------------------------------------------------------------------- */
555
556 static int
557 neofb_open(struct fb_info *info, int user)
558 {
559 struct neofb_par *par = info->par;
560
561 mutex_lock(&par->open_lock);
562 if (!par->ref_count) {
563 memset(&par->state, 0, sizeof(struct vgastate));
564 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
565 save_vga(&par->state);
566 }
567 par->ref_count++;
568 mutex_unlock(&par->open_lock);
569
570 return 0;
571 }
572
573 static int
574 neofb_release(struct fb_info *info, int user)
575 {
576 struct neofb_par *par = info->par;
577
578 mutex_lock(&par->open_lock);
579 if (!par->ref_count) {
580 mutex_unlock(&par->open_lock);
581 return -EINVAL;
582 }
583 if (par->ref_count == 1) {
584 restore_vga(&par->state);
585 }
586 par->ref_count--;
587 mutex_unlock(&par->open_lock);
588
589 return 0;
590 }
591
592 static int
593 neofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
594 {
595 struct neofb_par *par = info->par;
596 int memlen, vramlen;
597 int mode_ok = 0;
598
599 DBG("neofb_check_var");
600
601 if (PICOS2KHZ(var->pixclock) > par->maxClock)
602 return -EINVAL;
603
604 /* Is the mode larger than the LCD panel? */
605 if (par->internal_display &&
606 ((var->xres > par->NeoPanelWidth) ||
607 (var->yres > par->NeoPanelHeight))) {
608 printk(KERN_INFO
609 "Mode (%dx%d) larger than the LCD panel (%dx%d)\n",
610 var->xres, var->yres, par->NeoPanelWidth,
611 par->NeoPanelHeight);
612 return -EINVAL;
613 }
614
615 /* Is the mode one of the acceptable sizes? */
616 if (!par->internal_display)
617 mode_ok = 1;
618 else {
619 switch (var->xres) {
620 case 1280:
621 if (var->yres == 1024)
622 mode_ok = 1;
623 break;
624 case 1024:
625 if (var->yres == 768)
626 mode_ok = 1;
627 break;
628 case 800:
629 if (var->yres == (par->libretto ? 480 : 600))
630 mode_ok = 1;
631 break;
632 case 640:
633 if (var->yres == 480)
634 mode_ok = 1;
635 break;
636 }
637 }
638
639 if (!mode_ok) {
640 printk(KERN_INFO
641 "Mode (%dx%d) won't display properly on LCD\n",
642 var->xres, var->yres);
643 return -EINVAL;
644 }
645
646 var->red.msb_right = 0;
647 var->green.msb_right = 0;
648 var->blue.msb_right = 0;
649 var->transp.msb_right = 0;
650
651 switch (var->bits_per_pixel) {
652 case 8: /* PSEUDOCOLOUR, 256 */
653 var->transp.offset = 0;
654 var->transp.length = 0;
655 var->red.offset = 0;
656 var->red.length = 8;
657 var->green.offset = 0;
658 var->green.length = 8;
659 var->blue.offset = 0;
660 var->blue.length = 8;
661 break;
662
663 case 16: /* DIRECTCOLOUR, 64k */
664 var->transp.offset = 0;
665 var->transp.length = 0;
666 var->red.offset = 11;
667 var->red.length = 5;
668 var->green.offset = 5;
669 var->green.length = 6;
670 var->blue.offset = 0;
671 var->blue.length = 5;
672 break;
673
674 case 24: /* TRUECOLOUR, 16m */
675 var->transp.offset = 0;
676 var->transp.length = 0;
677 var->red.offset = 16;
678 var->red.length = 8;
679 var->green.offset = 8;
680 var->green.length = 8;
681 var->blue.offset = 0;
682 var->blue.length = 8;
683 break;
684
685 #ifdef NO_32BIT_SUPPORT_YET
686 case 32: /* TRUECOLOUR, 16m */
687 var->transp.offset = 24;
688 var->transp.length = 8;
689 var->red.offset = 16;
690 var->red.length = 8;
691 var->green.offset = 8;
692 var->green.length = 8;
693 var->blue.offset = 0;
694 var->blue.length = 8;
695 break;
696 #endif
697 default:
698 printk(KERN_WARNING "neofb: no support for %dbpp\n",
699 var->bits_per_pixel);
700 return -EINVAL;
701 }
702
703 vramlen = info->fix.smem_len;
704 if (vramlen > 4 * 1024 * 1024)
705 vramlen = 4 * 1024 * 1024;
706
707 if (var->yres_virtual < var->yres)
708 var->yres_virtual = var->yres;
709 if (var->xres_virtual < var->xres)
710 var->xres_virtual = var->xres;
711
712 memlen = var->xres_virtual * var->bits_per_pixel * var->yres_virtual >> 3;
713
714 if (memlen > vramlen) {
715 var->yres_virtual = vramlen * 8 / (var->xres_virtual *
716 var->bits_per_pixel);
717 memlen = var->xres_virtual * var->bits_per_pixel *
718 var->yres_virtual / 8;
719 }
720
721 /* we must round yres/xres down, we already rounded y/xres_virtual up
722 if it was possible. We should return -EINVAL, but I disagree */
723 if (var->yres_virtual < var->yres)
724 var->yres = var->yres_virtual;
725 if (var->xres_virtual < var->xres)
726 var->xres = var->xres_virtual;
727 if (var->xoffset + var->xres > var->xres_virtual)
728 var->xoffset = var->xres_virtual - var->xres;
729 if (var->yoffset + var->yres > var->yres_virtual)
730 var->yoffset = var->yres_virtual - var->yres;
731
732 var->nonstd = 0;
733 var->height = -1;
734 var->width = -1;
735
736 if (var->bits_per_pixel >= 24 || !par->neo2200)
737 var->accel_flags &= ~FB_ACCELF_TEXT;
738 return 0;
739 }
740
741 static int neofb_set_par(struct fb_info *info)
742 {
743 struct neofb_par *par = info->par;
744 unsigned char temp;
745 int i, clock_hi = 0;
746 int lcd_stretch;
747 int hoffset, voffset;
748 int vsync_start, vtotal;
749
750 DBG("neofb_set_par");
751
752 neoUnlock();
753
754 vgaHWProtect(1); /* Blank the screen */
755
756 vsync_start = info->var.yres + info->var.lower_margin;
757 vtotal = vsync_start + info->var.vsync_len + info->var.upper_margin;
758
759 /*
760 * This will allocate the datastructure and initialize all of the
761 * generic VGA registers.
762 */
763
764 if (vgaHWInit(&info->var, par))
765 return -EINVAL;
766
767 /*
768 * The default value assigned by vgaHW.c is 0x41, but this does
769 * not work for NeoMagic.
770 */
771 par->Attribute[16] = 0x01;
772
773 switch (info->var.bits_per_pixel) {
774 case 8:
775 par->CRTC[0x13] = info->var.xres_virtual >> 3;
776 par->ExtCRTOffset = info->var.xres_virtual >> 11;
777 par->ExtColorModeSelect = 0x11;
778 break;
779 case 16:
780 par->CRTC[0x13] = info->var.xres_virtual >> 2;
781 par->ExtCRTOffset = info->var.xres_virtual >> 10;
782 par->ExtColorModeSelect = 0x13;
783 break;
784 case 24:
785 par->CRTC[0x13] = (info->var.xres_virtual * 3) >> 3;
786 par->ExtCRTOffset = (info->var.xres_virtual * 3) >> 11;
787 par->ExtColorModeSelect = 0x14;
788 break;
789 #ifdef NO_32BIT_SUPPORT_YET
790 case 32: /* FIXME: guessed values */
791 par->CRTC[0x13] = info->var.xres_virtual >> 1;
792 par->ExtCRTOffset = info->var.xres_virtual >> 9;
793 par->ExtColorModeSelect = 0x15;
794 break;
795 #endif
796 default:
797 break;
798 }
799
800 par->ExtCRTDispAddr = 0x10;
801
802 /* Vertical Extension */
803 par->VerticalExt = (((vtotal - 2) & 0x400) >> 10)
804 | (((info->var.yres - 1) & 0x400) >> 9)
805 | (((vsync_start) & 0x400) >> 8)
806 | (((vsync_start) & 0x400) >> 7);
807
808 /* Fast write bursts on unless disabled. */
809 if (par->pci_burst)
810 par->SysIfaceCntl1 = 0x30;
811 else
812 par->SysIfaceCntl1 = 0x00;
813
814 par->SysIfaceCntl2 = 0xc0; /* VESA Bios sets this to 0x80! */
815
816 /* Initialize: by default, we want display config register to be read */
817 par->PanelDispCntlRegRead = 1;
818
819 /* Enable any user specified display devices. */
820 par->PanelDispCntlReg1 = 0x00;
821 if (par->internal_display)
822 par->PanelDispCntlReg1 |= 0x02;
823 if (par->external_display)
824 par->PanelDispCntlReg1 |= 0x01;
825
826 /* If the user did not specify any display devices, then... */
827 if (par->PanelDispCntlReg1 == 0x00) {
828 /* Default to internal (i.e., LCD) only. */
829 par->PanelDispCntlReg1 = vga_rgfx(NULL, 0x20) & 0x03;
830 }
831
832 /* If we are using a fixed mode, then tell the chip we are. */
833 switch (info->var.xres) {
834 case 1280:
835 par->PanelDispCntlReg1 |= 0x60;
836 break;
837 case 1024:
838 par->PanelDispCntlReg1 |= 0x40;
839 break;
840 case 800:
841 par->PanelDispCntlReg1 |= 0x20;
842 break;
843 case 640:
844 default:
845 break;
846 }
847
848 /* Setup shadow register locking. */
849 switch (par->PanelDispCntlReg1 & 0x03) {
850 case 0x01: /* External CRT only mode: */
851 par->GeneralLockReg = 0x00;
852 /* We need to program the VCLK for external display only mode. */
853 par->ProgramVCLK = 1;
854 break;
855 case 0x02: /* Internal LCD only mode: */
856 case 0x03: /* Simultaneous internal/external (LCD/CRT) mode: */
857 par->GeneralLockReg = 0x01;
858 /* Don't program the VCLK when using the LCD. */
859 par->ProgramVCLK = 0;
860 break;
861 }
862
863 /*
864 * If the screen is to be stretched, turn on stretching for the
865 * various modes.
866 *
867 * OPTION_LCD_STRETCH means stretching should be turned off!
868 */
869 par->PanelDispCntlReg2 = 0x00;
870 par->PanelDispCntlReg3 = 0x00;
871
872 if (par->lcd_stretch && (par->PanelDispCntlReg1 == 0x02) && /* LCD only */
873 (info->var.xres != par->NeoPanelWidth)) {
874 switch (info->var.xres) {
875 case 320: /* Needs testing. KEM -- 24 May 98 */
876 case 400: /* Needs testing. KEM -- 24 May 98 */
877 case 640:
878 case 800:
879 case 1024:
880 lcd_stretch = 1;
881 par->PanelDispCntlReg2 |= 0xC6;
882 break;
883 default:
884 lcd_stretch = 0;
885 /* No stretching in these modes. */
886 }
887 } else
888 lcd_stretch = 0;
889
890 /*
891 * If the screen is to be centerd, turn on the centering for the
892 * various modes.
893 */
894 par->PanelVertCenterReg1 = 0x00;
895 par->PanelVertCenterReg2 = 0x00;
896 par->PanelVertCenterReg3 = 0x00;
897 par->PanelVertCenterReg4 = 0x00;
898 par->PanelVertCenterReg5 = 0x00;
899 par->PanelHorizCenterReg1 = 0x00;
900 par->PanelHorizCenterReg2 = 0x00;
901 par->PanelHorizCenterReg3 = 0x00;
902 par->PanelHorizCenterReg4 = 0x00;
903 par->PanelHorizCenterReg5 = 0x00;
904
905
906 if (par->PanelDispCntlReg1 & 0x02) {
907 if (info->var.xres == par->NeoPanelWidth) {
908 /*
909 * No centering required when the requested display width
910 * equals the panel width.
911 */
912 } else {
913 par->PanelDispCntlReg2 |= 0x01;
914 par->PanelDispCntlReg3 |= 0x10;
915
916 /* Calculate the horizontal and vertical offsets. */
917 if (!lcd_stretch) {
918 hoffset =
919 ((par->NeoPanelWidth -
920 info->var.xres) >> 4) - 1;
921 voffset =
922 ((par->NeoPanelHeight -
923 info->var.yres) >> 1) - 2;
924 } else {
925 /* Stretched modes cannot be centered. */
926 hoffset = 0;
927 voffset = 0;
928 }
929
930 switch (info->var.xres) {
931 case 320: /* Needs testing. KEM -- 24 May 98 */
932 par->PanelHorizCenterReg3 = hoffset;
933 par->PanelVertCenterReg2 = voffset;
934 break;
935 case 400: /* Needs testing. KEM -- 24 May 98 */
936 par->PanelHorizCenterReg4 = hoffset;
937 par->PanelVertCenterReg1 = voffset;
938 break;
939 case 640:
940 par->PanelHorizCenterReg1 = hoffset;
941 par->PanelVertCenterReg3 = voffset;
942 break;
943 case 800:
944 par->PanelHorizCenterReg2 = hoffset;
945 par->PanelVertCenterReg4 = voffset;
946 break;
947 case 1024:
948 par->PanelHorizCenterReg5 = hoffset;
949 par->PanelVertCenterReg5 = voffset;
950 break;
951 case 1280:
952 default:
953 /* No centering in these modes. */
954 break;
955 }
956 }
957 }
958
959 par->biosMode =
960 neoFindMode(info->var.xres, info->var.yres,
961 info->var.bits_per_pixel);
962
963 /*
964 * Calculate the VCLK that most closely matches the requested dot
965 * clock.
966 */
967 neoCalcVCLK(info, par, PICOS2KHZ(info->var.pixclock));
968
969 /* Since we program the clocks ourselves, always use VCLK3. */
970 par->MiscOutReg |= 0x0C;
971
972 /* alread unlocked above */
973 /* BOGUS vga_wgfx(NULL, 0x09, 0x26); */
974
975 /* don't know what this is, but it's 0 from bootup anyway */
976 vga_wgfx(NULL, 0x15, 0x00);
977
978 /* was set to 0x01 by my bios in text and vesa modes */
979 vga_wgfx(NULL, 0x0A, par->GeneralLockReg);
980
981 /*
982 * The color mode needs to be set before calling vgaHWRestore
983 * to ensure the DAC is initialized properly.
984 *
985 * NOTE: Make sure we don't change bits make sure we don't change
986 * any reserved bits.
987 */
988 temp = vga_rgfx(NULL, 0x90);
989 switch (info->fix.accel) {
990 case FB_ACCEL_NEOMAGIC_NM2070:
991 temp &= 0xF0; /* Save bits 7:4 */
992 temp |= (par->ExtColorModeSelect & ~0xF0);
993 break;
994 case FB_ACCEL_NEOMAGIC_NM2090:
995 case FB_ACCEL_NEOMAGIC_NM2093:
996 case FB_ACCEL_NEOMAGIC_NM2097:
997 case FB_ACCEL_NEOMAGIC_NM2160:
998 case FB_ACCEL_NEOMAGIC_NM2200:
999 case FB_ACCEL_NEOMAGIC_NM2230:
1000 case FB_ACCEL_NEOMAGIC_NM2360:
1001 case FB_ACCEL_NEOMAGIC_NM2380:
1002 temp &= 0x70; /* Save bits 6:4 */
1003 temp |= (par->ExtColorModeSelect & ~0x70);
1004 break;
1005 }
1006
1007 vga_wgfx(NULL, 0x90, temp);
1008
1009 /*
1010 * In some rare cases a lockup might occur if we don't delay
1011 * here. (Reported by Miles Lane)
1012 */
1013 //mdelay(200);
1014
1015 /*
1016 * Disable horizontal and vertical graphics and text expansions so
1017 * that vgaHWRestore works properly.
1018 */
1019 temp = vga_rgfx(NULL, 0x25);
1020 temp &= 0x39;
1021 vga_wgfx(NULL, 0x25, temp);
1022
1023 /*
1024 * Sleep for 200ms to make sure that the two operations above have
1025 * had time to take effect.
1026 */
1027 mdelay(200);
1028
1029 /*
1030 * This function handles restoring the generic VGA registers. */
1031 vgaHWRestore(info, par);
1032
1033 /* linear colormap for non palettized modes */
1034 switch (info->var.bits_per_pixel) {
1035 case 8:
1036 /* PseudoColor, 256 */
1037 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1038 break;
1039 case 16:
1040 /* TrueColor, 64k */
1041 info->fix.visual = FB_VISUAL_TRUECOLOR;
1042
1043 for (i = 0; i < 64; i++) {
1044 outb(i, 0x3c8);
1045
1046 outb(i << 1, 0x3c9);
1047 outb(i, 0x3c9);
1048 outb(i << 1, 0x3c9);
1049 }
1050 break;
1051 case 24:
1052 #ifdef NO_32BIT_SUPPORT_YET
1053 case 32:
1054 #endif
1055 /* TrueColor, 16m */
1056 info->fix.visual = FB_VISUAL_TRUECOLOR;
1057
1058 for (i = 0; i < 256; i++) {
1059 outb(i, 0x3c8);
1060
1061 outb(i, 0x3c9);
1062 outb(i, 0x3c9);
1063 outb(i, 0x3c9);
1064 }
1065 break;
1066 }
1067
1068 vga_wgfx(NULL, 0x0E, par->ExtCRTDispAddr);
1069 vga_wgfx(NULL, 0x0F, par->ExtCRTOffset);
1070 temp = vga_rgfx(NULL, 0x10);
1071 temp &= 0x0F; /* Save bits 3:0 */
1072 temp |= (par->SysIfaceCntl1 & ~0x0F); /* VESA Bios sets bit 1! */
1073 vga_wgfx(NULL, 0x10, temp);
1074
1075 vga_wgfx(NULL, 0x11, par->SysIfaceCntl2);
1076 vga_wgfx(NULL, 0x15, 0 /*par->SingleAddrPage */ );
1077 vga_wgfx(NULL, 0x16, 0 /*par->DualAddrPage */ );
1078
1079 temp = vga_rgfx(NULL, 0x20);
1080 switch (info->fix.accel) {
1081 case FB_ACCEL_NEOMAGIC_NM2070:
1082 temp &= 0xFC; /* Save bits 7:2 */
1083 temp |= (par->PanelDispCntlReg1 & ~0xFC);
1084 break;
1085 case FB_ACCEL_NEOMAGIC_NM2090:
1086 case FB_ACCEL_NEOMAGIC_NM2093:
1087 case FB_ACCEL_NEOMAGIC_NM2097:
1088 case FB_ACCEL_NEOMAGIC_NM2160:
1089 temp &= 0xDC; /* Save bits 7:6,4:2 */
1090 temp |= (par->PanelDispCntlReg1 & ~0xDC);
1091 break;
1092 case FB_ACCEL_NEOMAGIC_NM2200:
1093 case FB_ACCEL_NEOMAGIC_NM2230:
1094 case FB_ACCEL_NEOMAGIC_NM2360:
1095 case FB_ACCEL_NEOMAGIC_NM2380:
1096 temp &= 0x98; /* Save bits 7,4:3 */
1097 temp |= (par->PanelDispCntlReg1 & ~0x98);
1098 break;
1099 }
1100 vga_wgfx(NULL, 0x20, temp);
1101
1102 temp = vga_rgfx(NULL, 0x25);
1103 temp &= 0x38; /* Save bits 5:3 */
1104 temp |= (par->PanelDispCntlReg2 & ~0x38);
1105 vga_wgfx(NULL, 0x25, temp);
1106
1107 if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
1108 temp = vga_rgfx(NULL, 0x30);
1109 temp &= 0xEF; /* Save bits 7:5 and bits 3:0 */
1110 temp |= (par->PanelDispCntlReg3 & ~0xEF);
1111 vga_wgfx(NULL, 0x30, temp);
1112 }
1113
1114 vga_wgfx(NULL, 0x28, par->PanelVertCenterReg1);
1115 vga_wgfx(NULL, 0x29, par->PanelVertCenterReg2);
1116 vga_wgfx(NULL, 0x2a, par->PanelVertCenterReg3);
1117
1118 if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
1119 vga_wgfx(NULL, 0x32, par->PanelVertCenterReg4);
1120 vga_wgfx(NULL, 0x33, par->PanelHorizCenterReg1);
1121 vga_wgfx(NULL, 0x34, par->PanelHorizCenterReg2);
1122 vga_wgfx(NULL, 0x35, par->PanelHorizCenterReg3);
1123 }
1124
1125 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2160)
1126 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1127
1128 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
1129 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
1130 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
1131 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
1132 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1133 vga_wgfx(NULL, 0x37, par->PanelVertCenterReg5);
1134 vga_wgfx(NULL, 0x38, par->PanelHorizCenterReg5);
1135
1136 clock_hi = 1;
1137 }
1138
1139 /* Program VCLK3 if needed. */
1140 if (par->ProgramVCLK && ((vga_rgfx(NULL, 0x9B) != par->VCLK3NumeratorLow)
1141 || (vga_rgfx(NULL, 0x9F) != par->VCLK3Denominator)
1142 || (clock_hi && ((vga_rgfx(NULL, 0x8F) & ~0x0f)
1143 != (par->VCLK3NumeratorHigh &
1144 ~0x0F))))) {
1145 vga_wgfx(NULL, 0x9B, par->VCLK3NumeratorLow);
1146 if (clock_hi) {
1147 temp = vga_rgfx(NULL, 0x8F);
1148 temp &= 0x0F; /* Save bits 3:0 */
1149 temp |= (par->VCLK3NumeratorHigh & ~0x0F);
1150 vga_wgfx(NULL, 0x8F, temp);
1151 }
1152 vga_wgfx(NULL, 0x9F, par->VCLK3Denominator);
1153 }
1154
1155 if (par->biosMode)
1156 vga_wcrt(NULL, 0x23, par->biosMode);
1157
1158 vga_wgfx(NULL, 0x93, 0xc0); /* Gives 5x faster framebuffer writes !!! */
1159
1160 /* Program vertical extension register */
1161 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
1162 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
1163 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
1164 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
1165 vga_wcrt(NULL, 0x70, par->VerticalExt);
1166 }
1167
1168 vgaHWProtect(0); /* Turn on screen */
1169
1170 /* Calling this also locks offset registers required in update_start */
1171 neoLock(&par->state);
1172
1173 info->fix.line_length =
1174 info->var.xres_virtual * (info->var.bits_per_pixel >> 3);
1175
1176 switch (info->fix.accel) {
1177 case FB_ACCEL_NEOMAGIC_NM2200:
1178 case FB_ACCEL_NEOMAGIC_NM2230:
1179 case FB_ACCEL_NEOMAGIC_NM2360:
1180 case FB_ACCEL_NEOMAGIC_NM2380:
1181 neo2200_accel_init(info, &info->var);
1182 break;
1183 default:
1184 break;
1185 }
1186 return 0;
1187 }
1188
1189 static void neofb_update_start(struct fb_info *info,
1190 struct fb_var_screeninfo *var)
1191 {
1192 struct neofb_par *par = info->par;
1193 struct vgastate *state = &par->state;
1194 int oldExtCRTDispAddr;
1195 int Base;
1196
1197 DBG("neofb_update_start");
1198
1199 Base = (var->yoffset * var->xres_virtual + var->xoffset) >> 2;
1200 Base *= (var->bits_per_pixel + 7) / 8;
1201
1202 neoUnlock();
1203
1204 /*
1205 * These are the generic starting address registers.
1206 */
1207 vga_wcrt(state->vgabase, 0x0C, (Base & 0x00FF00) >> 8);
1208 vga_wcrt(state->vgabase, 0x0D, (Base & 0x00FF));
1209
1210 /*
1211 * Make sure we don't clobber some other bits that might already
1212 * have been set. NOTE: NM2200 has a writable bit 3, but it shouldn't
1213 * be needed.
1214 */
1215 oldExtCRTDispAddr = vga_rgfx(NULL, 0x0E);
1216 vga_wgfx(state->vgabase, 0x0E, (((Base >> 16) & 0x0f) | (oldExtCRTDispAddr & 0xf0)));
1217
1218 neoLock(state);
1219 }
1220
1221 /*
1222 * Pan or Wrap the Display
1223 */
1224 static int neofb_pan_display(struct fb_var_screeninfo *var,
1225 struct fb_info *info)
1226 {
1227 u_int y_bottom;
1228
1229 y_bottom = var->yoffset;
1230
1231 if (!(var->vmode & FB_VMODE_YWRAP))
1232 y_bottom += var->yres;
1233
1234 if (var->xoffset > (var->xres_virtual - var->xres))
1235 return -EINVAL;
1236 if (y_bottom > info->var.yres_virtual)
1237 return -EINVAL;
1238
1239 neofb_update_start(info, var);
1240
1241 info->var.xoffset = var->xoffset;
1242 info->var.yoffset = var->yoffset;
1243
1244 if (var->vmode & FB_VMODE_YWRAP)
1245 info->var.vmode |= FB_VMODE_YWRAP;
1246 else
1247 info->var.vmode &= ~FB_VMODE_YWRAP;
1248 return 0;
1249 }
1250
1251 static int neofb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1252 u_int transp, struct fb_info *fb)
1253 {
1254 if (regno >= fb->cmap.len || regno > 255)
1255 return -EINVAL;
1256
1257 if (fb->var.bits_per_pixel <= 8) {
1258 outb(regno, 0x3c8);
1259
1260 outb(red >> 10, 0x3c9);
1261 outb(green >> 10, 0x3c9);
1262 outb(blue >> 10, 0x3c9);
1263 } else if (regno < 16) {
1264 switch (fb->var.bits_per_pixel) {
1265 case 16:
1266 ((u32 *) fb->pseudo_palette)[regno] =
1267 ((red & 0xf800)) | ((green & 0xfc00) >> 5) |
1268 ((blue & 0xf800) >> 11);
1269 break;
1270 case 24:
1271 ((u32 *) fb->pseudo_palette)[regno] =
1272 ((red & 0xff00) << 8) | ((green & 0xff00)) |
1273 ((blue & 0xff00) >> 8);
1274 break;
1275 #ifdef NO_32BIT_SUPPORT_YET
1276 case 32:
1277 ((u32 *) fb->pseudo_palette)[regno] =
1278 ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
1279 ((green & 0xff00)) | ((blue & 0xff00) >> 8);
1280 break;
1281 #endif
1282 default:
1283 return 1;
1284 }
1285 }
1286
1287 return 0;
1288 }
1289
1290 /*
1291 * (Un)Blank the display.
1292 */
1293 static int neofb_blank(int blank_mode, struct fb_info *info)
1294 {
1295 /*
1296 * Blank the screen if blank_mode != 0, else unblank.
1297 * Return 0 if blanking succeeded, != 0 if un-/blanking failed due to
1298 * e.g. a video mode which doesn't support it. Implements VESA suspend
1299 * and powerdown modes for monitors, and backlight control on LCDs.
1300 * blank_mode == 0: unblanked (backlight on)
1301 * blank_mode == 1: blank (backlight on)
1302 * blank_mode == 2: suspend vsync (backlight off)
1303 * blank_mode == 3: suspend hsync (backlight off)
1304 * blank_mode == 4: powerdown (backlight off)
1305 *
1306 * wms...Enable VESA DPMS compatible powerdown mode
1307 * run "setterm -powersave powerdown" to take advantage
1308 */
1309 struct neofb_par *par = info->par;
1310 int seqflags, lcdflags, dpmsflags, reg, tmpdisp;
1311
1312 /*
1313 * Read back the register bits related to display configuration. They might
1314 * have been changed underneath the driver via Fn key stroke.
1315 */
1316 neoUnlock();
1317 tmpdisp = vga_rgfx(NULL, 0x20) & 0x03;
1318 neoLock(&par->state);
1319
1320 /* In case we blank the screen, we want to store the possibly new
1321 * configuration in the driver. During un-blank, we re-apply this setting,
1322 * since the LCD bit will be cleared in order to switch off the backlight.
1323 */
1324 if (par->PanelDispCntlRegRead) {
1325 par->PanelDispCntlReg1 = tmpdisp;
1326 }
1327 par->PanelDispCntlRegRead = !blank_mode;
1328
1329 switch (blank_mode) {
1330 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
1331 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1332 lcdflags = 0; /* LCD off */
1333 dpmsflags = NEO_GR01_SUPPRESS_HSYNC |
1334 NEO_GR01_SUPPRESS_VSYNC;
1335 #ifdef CONFIG_TOSHIBA
1336 /* Do we still need this ? */
1337 /* attempt to turn off backlight on toshiba; also turns off external */
1338 {
1339 SMMRegisters regs;
1340
1341 regs.eax = 0xff00; /* HCI_SET */
1342 regs.ebx = 0x0002; /* HCI_BACKLIGHT */
1343 regs.ecx = 0x0000; /* HCI_DISABLE */
1344 tosh_smm(&regs);
1345 }
1346 #endif
1347 break;
1348 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
1349 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1350 lcdflags = 0; /* LCD off */
1351 dpmsflags = NEO_GR01_SUPPRESS_HSYNC;
1352 break;
1353 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
1354 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1355 lcdflags = 0; /* LCD off */
1356 dpmsflags = NEO_GR01_SUPPRESS_VSYNC;
1357 break;
1358 case FB_BLANK_NORMAL: /* just blank screen (backlight stays on) */
1359 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1360 /*
1361 * During a blank operation with the LID shut, we might store "LCD off"
1362 * by mistake. Due to timing issues, the BIOS may switch the lights
1363 * back on, and we turn it back off once we "unblank".
1364 *
1365 * So here is an attempt to implement ">=" - if we are in the process
1366 * of unblanking, and the LCD bit is unset in the driver but set in the
1367 * register, we must keep it.
1368 */
1369 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
1370 dpmsflags = 0x00; /* no hsync/vsync suppression */
1371 break;
1372 case FB_BLANK_UNBLANK: /* unblank */
1373 seqflags = 0; /* Enable sequencer */
1374 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
1375 dpmsflags = 0x00; /* no hsync/vsync suppression */
1376 #ifdef CONFIG_TOSHIBA
1377 /* Do we still need this ? */
1378 /* attempt to re-enable backlight/external on toshiba */
1379 {
1380 SMMRegisters regs;
1381
1382 regs.eax = 0xff00; /* HCI_SET */
1383 regs.ebx = 0x0002; /* HCI_BACKLIGHT */
1384 regs.ecx = 0x0001; /* HCI_ENABLE */
1385 tosh_smm(&regs);
1386 }
1387 #endif
1388 break;
1389 default: /* Anything else we don't understand; return 1 to tell
1390 * fb_blank we didn't aactually do anything */
1391 return 1;
1392 }
1393
1394 neoUnlock();
1395 reg = (vga_rseq(NULL, 0x01) & ~0x20) | seqflags;
1396 vga_wseq(NULL, 0x01, reg);
1397 reg = (vga_rgfx(NULL, 0x20) & ~0x02) | lcdflags;
1398 vga_wgfx(NULL, 0x20, reg);
1399 reg = (vga_rgfx(NULL, 0x01) & ~0xF0) | 0x80 | dpmsflags;
1400 vga_wgfx(NULL, 0x01, reg);
1401 neoLock(&par->state);
1402 return 0;
1403 }
1404
1405 static void
1406 neo2200_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1407 {
1408 struct neofb_par *par = info->par;
1409 u_long dst, rop;
1410
1411 dst = rect->dx + rect->dy * info->var.xres_virtual;
1412 rop = rect->rop ? 0x060000 : 0x0c0000;
1413
1414 neo2200_wait_fifo(info, 4);
1415
1416 /* set blt control */
1417 writel(NEO_BC3_FIFO_EN |
1418 NEO_BC0_SRC_IS_FG | NEO_BC3_SKIP_MAPPING |
1419 // NEO_BC3_DST_XY_ADDR |
1420 // NEO_BC3_SRC_XY_ADDR |
1421 rop, &par->neo2200->bltCntl);
1422
1423 switch (info->var.bits_per_pixel) {
1424 case 8:
1425 writel(rect->color, &par->neo2200->fgColor);
1426 break;
1427 case 16:
1428 case 24:
1429 writel(((u32 *) (info->pseudo_palette))[rect->color],
1430 &par->neo2200->fgColor);
1431 break;
1432 }
1433
1434 writel(dst * ((info->var.bits_per_pixel + 7) >> 3),
1435 &par->neo2200->dstStart);
1436 writel((rect->height << 16) | (rect->width & 0xffff),
1437 &par->neo2200->xyExt);
1438 }
1439
1440 static void
1441 neo2200_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1442 {
1443 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
1444 struct neofb_par *par = info->par;
1445 u_long src, dst, bltCntl;
1446
1447 bltCntl = NEO_BC3_FIFO_EN | NEO_BC3_SKIP_MAPPING | 0x0C0000;
1448
1449 if ((dy > sy) || ((dy == sy) && (dx > sx))) {
1450 /* Start with the lower right corner */
1451 sy += (area->height - 1);
1452 dy += (area->height - 1);
1453 sx += (area->width - 1);
1454 dx += (area->width - 1);
1455
1456 bltCntl |= NEO_BC0_X_DEC | NEO_BC0_DST_Y_DEC | NEO_BC0_SRC_Y_DEC;
1457 }
1458
1459 src = sx * (info->var.bits_per_pixel >> 3) + sy*info->fix.line_length;
1460 dst = dx * (info->var.bits_per_pixel >> 3) + dy*info->fix.line_length;
1461
1462 neo2200_wait_fifo(info, 4);
1463
1464 /* set blt control */
1465 writel(bltCntl, &par->neo2200->bltCntl);
1466
1467 writel(src, &par->neo2200->srcStart);
1468 writel(dst, &par->neo2200->dstStart);
1469 writel((area->height << 16) | (area->width & 0xffff),
1470 &par->neo2200->xyExt);
1471 }
1472
1473 static void
1474 neo2200_imageblit(struct fb_info *info, const struct fb_image *image)
1475 {
1476 struct neofb_par *par = info->par;
1477 int s_pitch = (image->width * image->depth + 7) >> 3;
1478 int scan_align = info->pixmap.scan_align - 1;
1479 int buf_align = info->pixmap.buf_align - 1;
1480 int bltCntl_flags, d_pitch, data_len;
1481
1482 // The data is padded for the hardware
1483 d_pitch = (s_pitch + scan_align) & ~scan_align;
1484 data_len = ((d_pitch * image->height) + buf_align) & ~buf_align;
1485
1486 neo2200_sync(info);
1487
1488 if (image->depth == 1) {
1489 if (info->var.bits_per_pixel == 24 && image->width < 16) {
1490 /* FIXME. There is a bug with accelerated color-expanded
1491 * transfers in 24 bit mode if the image being transferred
1492 * is less than 16 bits wide. This is due to insufficient
1493 * padding when writing the image. We need to adjust
1494 * struct fb_pixmap. Not yet done. */
1495 return cfb_imageblit(info, image);
1496 }
1497 bltCntl_flags = NEO_BC0_SRC_MONO;
1498 } else if (image->depth == info->var.bits_per_pixel) {
1499 bltCntl_flags = 0;
1500 } else {
1501 /* We don't currently support hardware acceleration if image
1502 * depth is different from display */
1503 return cfb_imageblit(info, image);
1504 }
1505
1506 switch (info->var.bits_per_pixel) {
1507 case 8:
1508 writel(image->fg_color, &par->neo2200->fgColor);
1509 writel(image->bg_color, &par->neo2200->bgColor);
1510 break;
1511 case 16:
1512 case 24:
1513 writel(((u32 *) (info->pseudo_palette))[image->fg_color],
1514 &par->neo2200->fgColor);
1515 writel(((u32 *) (info->pseudo_palette))[image->bg_color],
1516 &par->neo2200->bgColor);
1517 break;
1518 }
1519
1520 writel(NEO_BC0_SYS_TO_VID |
1521 NEO_BC3_SKIP_MAPPING | bltCntl_flags |
1522 // NEO_BC3_DST_XY_ADDR |
1523 0x0c0000, &par->neo2200->bltCntl);
1524
1525 writel(0, &par->neo2200->srcStart);
1526 // par->neo2200->dstStart = (image->dy << 16) | (image->dx & 0xffff);
1527 writel(((image->dx & 0xffff) * (info->var.bits_per_pixel >> 3) +
1528 image->dy * info->fix.line_length), &par->neo2200->dstStart);
1529 writel((image->height << 16) | (image->width & 0xffff),
1530 &par->neo2200->xyExt);
1531
1532 memcpy_toio(par->mmio_vbase + 0x100000, image->data, data_len);
1533 }
1534
1535 static void
1536 neofb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1537 {
1538 switch (info->fix.accel) {
1539 case FB_ACCEL_NEOMAGIC_NM2200:
1540 case FB_ACCEL_NEOMAGIC_NM2230:
1541 case FB_ACCEL_NEOMAGIC_NM2360:
1542 case FB_ACCEL_NEOMAGIC_NM2380:
1543 neo2200_fillrect(info, rect);
1544 break;
1545 default:
1546 cfb_fillrect(info, rect);
1547 break;
1548 }
1549 }
1550
1551 static void
1552 neofb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1553 {
1554 switch (info->fix.accel) {
1555 case FB_ACCEL_NEOMAGIC_NM2200:
1556 case FB_ACCEL_NEOMAGIC_NM2230:
1557 case FB_ACCEL_NEOMAGIC_NM2360:
1558 case FB_ACCEL_NEOMAGIC_NM2380:
1559 neo2200_copyarea(info, area);
1560 break;
1561 default:
1562 cfb_copyarea(info, area);
1563 break;
1564 }
1565 }
1566
1567 static void
1568 neofb_imageblit(struct fb_info *info, const struct fb_image *image)
1569 {
1570 switch (info->fix.accel) {
1571 case FB_ACCEL_NEOMAGIC_NM2200:
1572 case FB_ACCEL_NEOMAGIC_NM2230:
1573 case FB_ACCEL_NEOMAGIC_NM2360:
1574 case FB_ACCEL_NEOMAGIC_NM2380:
1575 neo2200_imageblit(info, image);
1576 break;
1577 default:
1578 cfb_imageblit(info, image);
1579 break;
1580 }
1581 }
1582
1583 static int
1584 neofb_sync(struct fb_info *info)
1585 {
1586 switch (info->fix.accel) {
1587 case FB_ACCEL_NEOMAGIC_NM2200:
1588 case FB_ACCEL_NEOMAGIC_NM2230:
1589 case FB_ACCEL_NEOMAGIC_NM2360:
1590 case FB_ACCEL_NEOMAGIC_NM2380:
1591 neo2200_sync(info);
1592 break;
1593 default:
1594 break;
1595 }
1596 return 0;
1597 }
1598
1599 /*
1600 static void
1601 neofb_draw_cursor(struct fb_info *info, u8 *dst, u8 *src, unsigned int width)
1602 {
1603 //memset_io(info->sprite.addr, 0xff, 1);
1604 }
1605
1606 static int
1607 neofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1608 {
1609 struct neofb_par *par = (struct neofb_par *) info->par;
1610
1611 * Disable cursor *
1612 write_le32(NEOREG_CURSCNTL, ~NEO_CURS_ENABLE, par);
1613
1614 if (cursor->set & FB_CUR_SETPOS) {
1615 u32 x = cursor->image.dx;
1616 u32 y = cursor->image.dy;
1617
1618 info->cursor.image.dx = x;
1619 info->cursor.image.dy = y;
1620 write_le32(NEOREG_CURSX, x, par);
1621 write_le32(NEOREG_CURSY, y, par);
1622 }
1623
1624 if (cursor->set & FB_CUR_SETSIZE) {
1625 info->cursor.image.height = cursor->image.height;
1626 info->cursor.image.width = cursor->image.width;
1627 }
1628
1629 if (cursor->set & FB_CUR_SETHOT)
1630 info->cursor.hot = cursor->hot;
1631
1632 if (cursor->set & FB_CUR_SETCMAP) {
1633 if (cursor->image.depth == 1) {
1634 u32 fg = cursor->image.fg_color;
1635 u32 bg = cursor->image.bg_color;
1636
1637 info->cursor.image.fg_color = fg;
1638 info->cursor.image.bg_color = bg;
1639
1640 fg = ((fg & 0xff0000) >> 16) | ((fg & 0xff) << 16) | (fg & 0xff00);
1641 bg = ((bg & 0xff0000) >> 16) | ((bg & 0xff) << 16) | (bg & 0xff00);
1642 write_le32(NEOREG_CURSFGCOLOR, fg, par);
1643 write_le32(NEOREG_CURSBGCOLOR, bg, par);
1644 }
1645 }
1646
1647 if (cursor->set & FB_CUR_SETSHAPE)
1648 fb_load_cursor_image(info);
1649
1650 if (info->cursor.enable)
1651 write_le32(NEOREG_CURSCNTL, NEO_CURS_ENABLE, par);
1652 return 0;
1653 }
1654 */
1655
1656 static struct fb_ops neofb_ops = {
1657 .owner = THIS_MODULE,
1658 .fb_open = neofb_open,
1659 .fb_release = neofb_release,
1660 .fb_check_var = neofb_check_var,
1661 .fb_set_par = neofb_set_par,
1662 .fb_setcolreg = neofb_setcolreg,
1663 .fb_pan_display = neofb_pan_display,
1664 .fb_blank = neofb_blank,
1665 .fb_sync = neofb_sync,
1666 .fb_fillrect = neofb_fillrect,
1667 .fb_copyarea = neofb_copyarea,
1668 .fb_imageblit = neofb_imageblit,
1669 };
1670
1671 /* --------------------------------------------------------------------- */
1672
1673 static struct fb_videomode __devinitdata mode800x480 = {
1674 .xres = 800,
1675 .yres = 480,
1676 .pixclock = 25000,
1677 .left_margin = 88,
1678 .right_margin = 40,
1679 .upper_margin = 23,
1680 .lower_margin = 1,
1681 .hsync_len = 128,
1682 .vsync_len = 4,
1683 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1684 .vmode = FB_VMODE_NONINTERLACED
1685 };
1686
1687 static int __devinit neo_map_mmio(struct fb_info *info,
1688 struct pci_dev *dev)
1689 {
1690 struct neofb_par *par = info->par;
1691
1692 DBG("neo_map_mmio");
1693
1694 switch (info->fix.accel) {
1695 case FB_ACCEL_NEOMAGIC_NM2070:
1696 info->fix.mmio_start = pci_resource_start(dev, 0)+
1697 0x100000;
1698 break;
1699 case FB_ACCEL_NEOMAGIC_NM2090:
1700 case FB_ACCEL_NEOMAGIC_NM2093:
1701 info->fix.mmio_start = pci_resource_start(dev, 0)+
1702 0x200000;
1703 break;
1704 case FB_ACCEL_NEOMAGIC_NM2160:
1705 case FB_ACCEL_NEOMAGIC_NM2097:
1706 case FB_ACCEL_NEOMAGIC_NM2200:
1707 case FB_ACCEL_NEOMAGIC_NM2230:
1708 case FB_ACCEL_NEOMAGIC_NM2360:
1709 case FB_ACCEL_NEOMAGIC_NM2380:
1710 info->fix.mmio_start = pci_resource_start(dev, 1);
1711 break;
1712 default:
1713 info->fix.mmio_start = pci_resource_start(dev, 0);
1714 }
1715 info->fix.mmio_len = MMIO_SIZE;
1716
1717 if (!request_mem_region
1718 (info->fix.mmio_start, MMIO_SIZE, "memory mapped I/O")) {
1719 printk("neofb: memory mapped IO in use\n");
1720 return -EBUSY;
1721 }
1722
1723 par->mmio_vbase = ioremap(info->fix.mmio_start, MMIO_SIZE);
1724 if (!par->mmio_vbase) {
1725 printk("neofb: unable to map memory mapped IO\n");
1726 release_mem_region(info->fix.mmio_start,
1727 info->fix.mmio_len);
1728 return -ENOMEM;
1729 } else
1730 printk(KERN_INFO "neofb: mapped io at %p\n",
1731 par->mmio_vbase);
1732 return 0;
1733 }
1734
1735 static void neo_unmap_mmio(struct fb_info *info)
1736 {
1737 struct neofb_par *par = info->par;
1738
1739 DBG("neo_unmap_mmio");
1740
1741 iounmap(par->mmio_vbase);
1742 par->mmio_vbase = NULL;
1743
1744 release_mem_region(info->fix.mmio_start,
1745 info->fix.mmio_len);
1746 }
1747
1748 static int __devinit neo_map_video(struct fb_info *info,
1749 struct pci_dev *dev, int video_len)
1750 {
1751 //unsigned long addr;
1752
1753 DBG("neo_map_video");
1754
1755 info->fix.smem_start = pci_resource_start(dev, 0);
1756 info->fix.smem_len = video_len;
1757
1758 if (!request_mem_region(info->fix.smem_start, info->fix.smem_len,
1759 "frame buffer")) {
1760 printk("neofb: frame buffer in use\n");
1761 return -EBUSY;
1762 }
1763
1764 info->screen_base =
1765 ioremap(info->fix.smem_start, info->fix.smem_len);
1766 if (!info->screen_base) {
1767 printk("neofb: unable to map screen memory\n");
1768 release_mem_region(info->fix.smem_start,
1769 info->fix.smem_len);
1770 return -ENOMEM;
1771 } else
1772 printk(KERN_INFO "neofb: mapped framebuffer at %p\n",
1773 info->screen_base);
1774
1775 #ifdef CONFIG_MTRR
1776 ((struct neofb_par *)(info->par))->mtrr =
1777 mtrr_add(info->fix.smem_start, pci_resource_len(dev, 0),
1778 MTRR_TYPE_WRCOMB, 1);
1779 #endif
1780
1781 /* Clear framebuffer, it's all white in memory after boot */
1782 memset_io(info->screen_base, 0, info->fix.smem_len);
1783
1784 /* Allocate Cursor drawing pad.
1785 info->fix.smem_len -= PAGE_SIZE;
1786 addr = info->fix.smem_start + info->fix.smem_len;
1787 write_le32(NEOREG_CURSMEMPOS, ((0x000f & (addr >> 10)) << 8) |
1788 ((0x0ff0 & (addr >> 10)) >> 4), par);
1789 addr = (unsigned long) info->screen_base + info->fix.smem_len;
1790 info->sprite.addr = (u8 *) addr; */
1791 return 0;
1792 }
1793
1794 static void neo_unmap_video(struct fb_info *info)
1795 {
1796 DBG("neo_unmap_video");
1797
1798 #ifdef CONFIG_MTRR
1799 {
1800 struct neofb_par *par = info->par;
1801
1802 mtrr_del(par->mtrr, info->fix.smem_start,
1803 info->fix.smem_len);
1804 }
1805 #endif
1806 iounmap(info->screen_base);
1807 info->screen_base = NULL;
1808
1809 release_mem_region(info->fix.smem_start,
1810 info->fix.smem_len);
1811 }
1812
1813 static int __devinit neo_scan_monitor(struct fb_info *info)
1814 {
1815 struct neofb_par *par = info->par;
1816 unsigned char type, display;
1817 int w;
1818
1819 // Eventually we will have i2c support.
1820 info->monspecs.modedb = kmalloc(sizeof(struct fb_videomode), GFP_KERNEL);
1821 if (!info->monspecs.modedb)
1822 return -ENOMEM;
1823 info->monspecs.modedb_len = 1;
1824
1825 /* Determine the panel type */
1826 vga_wgfx(NULL, 0x09, 0x26);
1827 type = vga_rgfx(NULL, 0x21);
1828 display = vga_rgfx(NULL, 0x20);
1829 if (!par->internal_display && !par->external_display) {
1830 par->internal_display = display & 2 || !(display & 3) ? 1 : 0;
1831 par->external_display = display & 1;
1832 printk (KERN_INFO "Autodetected %s display\n",
1833 par->internal_display && par->external_display ? "simultaneous" :
1834 par->internal_display ? "internal" : "external");
1835 }
1836
1837 /* Determine panel width -- used in NeoValidMode. */
1838 w = vga_rgfx(NULL, 0x20);
1839 vga_wgfx(NULL, 0x09, 0x00);
1840 switch ((w & 0x18) >> 3) {
1841 case 0x00:
1842 // 640x480@60
1843 par->NeoPanelWidth = 640;
1844 par->NeoPanelHeight = 480;
1845 memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
1846 break;
1847 case 0x01:
1848 par->NeoPanelWidth = 800;
1849 if (par->libretto) {
1850 par->NeoPanelHeight = 480;
1851 memcpy(info->monspecs.modedb, &mode800x480, sizeof(struct fb_videomode));
1852 } else {
1853 // 800x600@60
1854 par->NeoPanelHeight = 600;
1855 memcpy(info->monspecs.modedb, &vesa_modes[8], sizeof(struct fb_videomode));
1856 }
1857 break;
1858 case 0x02:
1859 // 1024x768@60
1860 par->NeoPanelWidth = 1024;
1861 par->NeoPanelHeight = 768;
1862 memcpy(info->monspecs.modedb, &vesa_modes[13], sizeof(struct fb_videomode));
1863 break;
1864 case 0x03:
1865 /* 1280x1024@60 panel support needs to be added */
1866 #ifdef NOT_DONE
1867 par->NeoPanelWidth = 1280;
1868 par->NeoPanelHeight = 1024;
1869 memcpy(info->monspecs.modedb, &vesa_modes[20], sizeof(struct fb_videomode));
1870 break;
1871 #else
1872 printk(KERN_ERR
1873 "neofb: Only 640x480, 800x600/480 and 1024x768 panels are currently supported\n");
1874 return -1;
1875 #endif
1876 default:
1877 // 640x480@60
1878 par->NeoPanelWidth = 640;
1879 par->NeoPanelHeight = 480;
1880 memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
1881 break;
1882 }
1883
1884 printk(KERN_INFO "Panel is a %dx%d %s %s display\n",
1885 par->NeoPanelWidth,
1886 par->NeoPanelHeight,
1887 (type & 0x02) ? "color" : "monochrome",
1888 (type & 0x10) ? "TFT" : "dual scan");
1889 return 0;
1890 }
1891
1892 static int __devinit neo_init_hw(struct fb_info *info)
1893 {
1894 struct neofb_par *par = info->par;
1895 int videoRam = 896;
1896 int maxClock = 65000;
1897 int CursorMem = 1024;
1898 int CursorOff = 0x100;
1899
1900 DBG("neo_init_hw");
1901
1902 neoUnlock();
1903
1904 #if 0
1905 printk(KERN_DEBUG "--- Neo extended register dump ---\n");
1906 for (int w = 0; w < 0x85; w++)
1907 printk(KERN_DEBUG "CR %p: %p\n", (void *) w,
1908 (void *) vga_rcrt(NULL, w));
1909 for (int w = 0; w < 0xC7; w++)
1910 printk(KERN_DEBUG "GR %p: %p\n", (void *) w,
1911 (void *) vga_rgfx(NULL, w));
1912 #endif
1913 switch (info->fix.accel) {
1914 case FB_ACCEL_NEOMAGIC_NM2070:
1915 videoRam = 896;
1916 maxClock = 65000;
1917 break;
1918 case FB_ACCEL_NEOMAGIC_NM2090:
1919 case FB_ACCEL_NEOMAGIC_NM2093:
1920 case FB_ACCEL_NEOMAGIC_NM2097:
1921 videoRam = 1152;
1922 maxClock = 80000;
1923 break;
1924 case FB_ACCEL_NEOMAGIC_NM2160:
1925 videoRam = 2048;
1926 maxClock = 90000;
1927 break;
1928 case FB_ACCEL_NEOMAGIC_NM2200:
1929 videoRam = 2560;
1930 maxClock = 110000;
1931 break;
1932 case FB_ACCEL_NEOMAGIC_NM2230:
1933 videoRam = 3008;
1934 maxClock = 110000;
1935 break;
1936 case FB_ACCEL_NEOMAGIC_NM2360:
1937 videoRam = 4096;
1938 maxClock = 110000;
1939 break;
1940 case FB_ACCEL_NEOMAGIC_NM2380:
1941 videoRam = 6144;
1942 maxClock = 110000;
1943 break;
1944 }
1945 switch (info->fix.accel) {
1946 case FB_ACCEL_NEOMAGIC_NM2070:
1947 case FB_ACCEL_NEOMAGIC_NM2090:
1948 case FB_ACCEL_NEOMAGIC_NM2093:
1949 CursorMem = 2048;
1950 CursorOff = 0x100;
1951 break;
1952 case FB_ACCEL_NEOMAGIC_NM2097:
1953 case FB_ACCEL_NEOMAGIC_NM2160:
1954 CursorMem = 1024;
1955 CursorOff = 0x100;
1956 break;
1957 case FB_ACCEL_NEOMAGIC_NM2200:
1958 case FB_ACCEL_NEOMAGIC_NM2230:
1959 case FB_ACCEL_NEOMAGIC_NM2360:
1960 case FB_ACCEL_NEOMAGIC_NM2380:
1961 CursorMem = 1024;
1962 CursorOff = 0x1000;
1963
1964 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
1965 break;
1966 }
1967 /*
1968 info->sprite.size = CursorMem;
1969 info->sprite.scan_align = 1;
1970 info->sprite.buf_align = 1;
1971 info->sprite.flags = FB_PIXMAP_IO;
1972 info->sprite.outbuf = neofb_draw_cursor;
1973 */
1974 par->maxClock = maxClock;
1975 par->cursorOff = CursorOff;
1976 return videoRam * 1024;
1977 }
1978
1979
1980 static struct fb_info *__devinit neo_alloc_fb_info(struct pci_dev *dev, const struct
1981 pci_device_id *id)
1982 {
1983 struct fb_info *info;
1984 struct neofb_par *par;
1985
1986 info = framebuffer_alloc(sizeof(struct neofb_par), &dev->dev);
1987
1988 if (!info)
1989 return NULL;
1990
1991 par = info->par;
1992
1993 info->fix.accel = id->driver_data;
1994
1995 mutex_init(&par->open_lock);
1996 par->pci_burst = !nopciburst;
1997 par->lcd_stretch = !nostretch;
1998 par->libretto = libretto;
1999
2000 par->internal_display = internal;
2001 par->external_display = external;
2002 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
2003
2004 switch (info->fix.accel) {
2005 case FB_ACCEL_NEOMAGIC_NM2070:
2006 snprintf(info->fix.id, sizeof(info->fix.id),
2007 "MagicGraph 128");
2008 break;
2009 case FB_ACCEL_NEOMAGIC_NM2090:
2010 snprintf(info->fix.id, sizeof(info->fix.id),
2011 "MagicGraph 128V");
2012 break;
2013 case FB_ACCEL_NEOMAGIC_NM2093:
2014 snprintf(info->fix.id, sizeof(info->fix.id),
2015 "MagicGraph 128ZV");
2016 break;
2017 case FB_ACCEL_NEOMAGIC_NM2097:
2018 snprintf(info->fix.id, sizeof(info->fix.id),
2019 "MagicGraph 128ZV+");
2020 break;
2021 case FB_ACCEL_NEOMAGIC_NM2160:
2022 snprintf(info->fix.id, sizeof(info->fix.id),
2023 "MagicGraph 128XD");
2024 break;
2025 case FB_ACCEL_NEOMAGIC_NM2200:
2026 snprintf(info->fix.id, sizeof(info->fix.id),
2027 "MagicGraph 256AV");
2028 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2029 FBINFO_HWACCEL_COPYAREA |
2030 FBINFO_HWACCEL_FILLRECT;
2031 break;
2032 case FB_ACCEL_NEOMAGIC_NM2230:
2033 snprintf(info->fix.id, sizeof(info->fix.id),
2034 "MagicGraph 256AV+");
2035 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2036 FBINFO_HWACCEL_COPYAREA |
2037 FBINFO_HWACCEL_FILLRECT;
2038 break;
2039 case FB_ACCEL_NEOMAGIC_NM2360:
2040 snprintf(info->fix.id, sizeof(info->fix.id),
2041 "MagicGraph 256ZX");
2042 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2043 FBINFO_HWACCEL_COPYAREA |
2044 FBINFO_HWACCEL_FILLRECT;
2045 break;
2046 case FB_ACCEL_NEOMAGIC_NM2380:
2047 snprintf(info->fix.id, sizeof(info->fix.id),
2048 "MagicGraph 256XL+");
2049 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2050 FBINFO_HWACCEL_COPYAREA |
2051 FBINFO_HWACCEL_FILLRECT;
2052 break;
2053 }
2054
2055 info->fix.type = FB_TYPE_PACKED_PIXELS;
2056 info->fix.type_aux = 0;
2057 info->fix.xpanstep = 0;
2058 info->fix.ypanstep = 4;
2059 info->fix.ywrapstep = 0;
2060 info->fix.accel = id->driver_data;
2061
2062 info->fbops = &neofb_ops;
2063 info->pseudo_palette = par->palette;
2064 return info;
2065 }
2066
2067 static void neo_free_fb_info(struct fb_info *info)
2068 {
2069 if (info) {
2070 /*
2071 * Free the colourmap
2072 */
2073 fb_dealloc_cmap(&info->cmap);
2074 framebuffer_release(info);
2075 }
2076 }
2077
2078 /* --------------------------------------------------------------------- */
2079
2080 static int __devinit neofb_probe(struct pci_dev *dev,
2081 const struct pci_device_id *id)
2082 {
2083 struct fb_info *info;
2084 u_int h_sync, v_sync;
2085 int video_len, err;
2086
2087 DBG("neofb_probe");
2088
2089 err = pci_enable_device(dev);
2090 if (err)
2091 return err;
2092
2093 err = -ENOMEM;
2094 info = neo_alloc_fb_info(dev, id);
2095 if (!info)
2096 return err;
2097
2098 err = neo_map_mmio(info, dev);
2099 if (err)
2100 goto err_map_mmio;
2101
2102 err = neo_scan_monitor(info);
2103 if (err)
2104 goto err_scan_monitor;
2105
2106 video_len = neo_init_hw(info);
2107 if (video_len < 0) {
2108 err = video_len;
2109 goto err_init_hw;
2110 }
2111
2112 err = neo_map_video(info, dev, video_len);
2113 if (err)
2114 goto err_init_hw;
2115
2116 if (!fb_find_mode(&info->var, info, mode_option, NULL, 0,
2117 info->monspecs.modedb, 16)) {
2118 printk(KERN_ERR "neofb: Unable to find usable video mode.\n");
2119 goto err_map_video;
2120 }
2121
2122 /*
2123 * Calculate the hsync and vsync frequencies. Note that
2124 * we split the 1e12 constant up so that we can preserve
2125 * the precision and fit the results into 32-bit registers.
2126 * (1953125000 * 512 = 1e12)
2127 */
2128 h_sync = 1953125000 / info->var.pixclock;
2129 h_sync =
2130 h_sync * 512 / (info->var.xres + info->var.left_margin +
2131 info->var.right_margin + info->var.hsync_len);
2132 v_sync =
2133 h_sync / (info->var.yres + info->var.upper_margin +
2134 info->var.lower_margin + info->var.vsync_len);
2135
2136 printk(KERN_INFO "neofb v" NEOFB_VERSION
2137 ": %dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2138 info->fix.smem_len >> 10, info->var.xres,
2139 info->var.yres, h_sync / 1000, h_sync % 1000, v_sync);
2140
2141 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
2142 goto err_map_video;
2143
2144 err = register_framebuffer(info);
2145 if (err < 0)
2146 goto err_reg_fb;
2147
2148 printk(KERN_INFO "fb%d: %s frame buffer device\n",
2149 info->node, info->fix.id);
2150
2151 /*
2152 * Our driver data
2153 */
2154 pci_set_drvdata(dev, info);
2155 return 0;
2156
2157 err_reg_fb:
2158 fb_dealloc_cmap(&info->cmap);
2159 err_map_video:
2160 neo_unmap_video(info);
2161 err_init_hw:
2162 fb_destroy_modedb(info->monspecs.modedb);
2163 err_scan_monitor:
2164 neo_unmap_mmio(info);
2165 err_map_mmio:
2166 neo_free_fb_info(info);
2167 return err;
2168 }
2169
2170 static void __devexit neofb_remove(struct pci_dev *dev)
2171 {
2172 struct fb_info *info = pci_get_drvdata(dev);
2173
2174 DBG("neofb_remove");
2175
2176 if (info) {
2177 /*
2178 * If unregister_framebuffer fails, then
2179 * we will be leaving hooks that could cause
2180 * oopsen laying around.
2181 */
2182 if (unregister_framebuffer(info))
2183 printk(KERN_WARNING
2184 "neofb: danger danger! Oopsen imminent!\n");
2185
2186 neo_unmap_video(info);
2187 fb_destroy_modedb(info->monspecs.modedb);
2188 neo_unmap_mmio(info);
2189 neo_free_fb_info(info);
2190
2191 /*
2192 * Ensure that the driver data is no longer
2193 * valid.
2194 */
2195 pci_set_drvdata(dev, NULL);
2196 }
2197 }
2198
2199 static struct pci_device_id neofb_devices[] = {
2200 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2070,
2201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2070},
2202
2203 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2090,
2204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2090},
2205
2206 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2093,
2207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2093},
2208
2209 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2097,
2210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2097},
2211
2212 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2160,
2213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2160},
2214
2215 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2200,
2216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2200},
2217
2218 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2230,
2219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2230},
2220
2221 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2360,
2222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2360},
2223
2224 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2380,
2225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2380},
2226
2227 {0, 0, 0, 0, 0, 0, 0}
2228 };
2229
2230 MODULE_DEVICE_TABLE(pci, neofb_devices);
2231
2232 static struct pci_driver neofb_driver = {
2233 .name = "neofb",
2234 .id_table = neofb_devices,
2235 .probe = neofb_probe,
2236 .remove = __devexit_p(neofb_remove)
2237 };
2238
2239 /* ************************* init in-kernel code ************************** */
2240
2241 #ifndef MODULE
2242 static int __init neofb_setup(char *options)
2243 {
2244 char *this_opt;
2245
2246 DBG("neofb_setup");
2247
2248 if (!options || !*options)
2249 return 0;
2250
2251 while ((this_opt = strsep(&options, ",")) != NULL) {
2252 if (!*this_opt)
2253 continue;
2254
2255 if (!strncmp(this_opt, "internal", 8))
2256 internal = 1;
2257 else if (!strncmp(this_opt, "external", 8))
2258 external = 1;
2259 else if (!strncmp(this_opt, "nostretch", 9))
2260 nostretch = 1;
2261 else if (!strncmp(this_opt, "nopciburst", 10))
2262 nopciburst = 1;
2263 else if (!strncmp(this_opt, "libretto", 8))
2264 libretto = 1;
2265 else
2266 mode_option = this_opt;
2267 }
2268 return 0;
2269 }
2270 #endif /* MODULE */
2271
2272 static int __init neofb_init(void)
2273 {
2274 #ifndef MODULE
2275 char *option = NULL;
2276
2277 if (fb_get_options("neofb", &option))
2278 return -ENODEV;
2279 neofb_setup(option);
2280 #endif
2281 return pci_register_driver(&neofb_driver);
2282 }
2283
2284 module_init(neofb_init);
2285
2286 #ifdef MODULE
2287 static void __exit neofb_exit(void)
2288 {
2289 pci_unregister_driver(&neofb_driver);
2290 }
2291
2292 module_exit(neofb_exit);
2293 #endif /* MODULE */
SocketAccessConTroL development