2 * linux/arch/arm/mach-at91/gpio.c
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
21 #include <asm/hardware.h>
22 #include <asm/arch/at91_pio.h>
23 #include <asm/arch/gpio.h>
28 static struct at91_gpio_bank
*gpio
;
29 static int gpio_banks
;
32 static inline void __iomem
*pin_to_controller(unsigned pin
)
34 void __iomem
*sys_base
= (void __iomem
*) AT91_VA_BASE_SYS
;
38 if (likely(pin
< gpio_banks
))
39 return sys_base
+ gpio
[pin
].offset
;
44 static inline unsigned pin_to_mask(unsigned pin
)
47 return 1 << (pin
% 32);
51 /*--------------------------------------------------------------------------*/
53 /* Not all hardware capabilities are exposed through these calls; they
54 * only encapsulate the most common features and modes. (So if you
55 * want to change signals in groups, do it directly.)
57 * Bootloaders will usually handle some of the pin multiplexing setup.
58 * The intent is certainly that by the time Linux is fully booted, all
59 * pins should have been fully initialized. These setup calls should
60 * only be used by board setup routines, or possibly in driver probe().
62 * For bootloaders doing all that setup, these calls could be inlined
63 * as NOPs so Linux won't duplicate any setup code
68 * mux the pin to the "GPIO" peripheral role.
70 int __init_or_module
at91_set_GPIO_periph(unsigned pin
, int use_pullup
)
72 void __iomem
*pio
= pin_to_controller(pin
);
73 unsigned mask
= pin_to_mask(pin
);
77 __raw_writel(mask
, pio
+ PIO_IDR
);
78 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
79 __raw_writel(mask
, pio
+ PIO_PER
);
82 EXPORT_SYMBOL(at91_set_GPIO_periph
);
86 * mux the pin to the "A" internal peripheral role.
88 int __init_or_module
at91_set_A_periph(unsigned pin
, int use_pullup
)
90 void __iomem
*pio
= pin_to_controller(pin
);
91 unsigned mask
= pin_to_mask(pin
);
96 __raw_writel(mask
, pio
+ PIO_IDR
);
97 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
98 __raw_writel(mask
, pio
+ PIO_ASR
);
99 __raw_writel(mask
, pio
+ PIO_PDR
);
102 EXPORT_SYMBOL(at91_set_A_periph
);
106 * mux the pin to the "B" internal peripheral role.
108 int __init_or_module
at91_set_B_periph(unsigned pin
, int use_pullup
)
110 void __iomem
*pio
= pin_to_controller(pin
);
111 unsigned mask
= pin_to_mask(pin
);
116 __raw_writel(mask
, pio
+ PIO_IDR
);
117 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
118 __raw_writel(mask
, pio
+ PIO_BSR
);
119 __raw_writel(mask
, pio
+ PIO_PDR
);
122 EXPORT_SYMBOL(at91_set_B_periph
);
126 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
127 * configure it for an input.
129 int __init_or_module
at91_set_gpio_input(unsigned pin
, int use_pullup
)
131 void __iomem
*pio
= pin_to_controller(pin
);
132 unsigned mask
= pin_to_mask(pin
);
137 __raw_writel(mask
, pio
+ PIO_IDR
);
138 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
139 __raw_writel(mask
, pio
+ PIO_ODR
);
140 __raw_writel(mask
, pio
+ PIO_PER
);
143 EXPORT_SYMBOL(at91_set_gpio_input
);
147 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
148 * and configure it for an output.
150 int __init_or_module
at91_set_gpio_output(unsigned pin
, int value
)
152 void __iomem
*pio
= pin_to_controller(pin
);
153 unsigned mask
= pin_to_mask(pin
);
158 __raw_writel(mask
, pio
+ PIO_IDR
);
159 __raw_writel(mask
, pio
+ PIO_PUDR
);
160 __raw_writel(mask
, pio
+ (value
? PIO_SODR
: PIO_CODR
));
161 __raw_writel(mask
, pio
+ PIO_OER
);
162 __raw_writel(mask
, pio
+ PIO_PER
);
165 EXPORT_SYMBOL(at91_set_gpio_output
);
169 * enable/disable the glitch filter; mostly used with IRQ handling.
171 int __init_or_module
at91_set_deglitch(unsigned pin
, int is_on
)
173 void __iomem
*pio
= pin_to_controller(pin
);
174 unsigned mask
= pin_to_mask(pin
);
178 __raw_writel(mask
, pio
+ (is_on
? PIO_IFER
: PIO_IFDR
));
181 EXPORT_SYMBOL(at91_set_deglitch
);
184 * enable/disable the multi-driver; This is only valid for output and
185 * allows the output pin to run as an open collector output.
187 int __init_or_module
at91_set_multi_drive(unsigned pin
, int is_on
)
189 void __iomem
*pio
= pin_to_controller(pin
);
190 unsigned mask
= pin_to_mask(pin
);
195 __raw_writel(mask
, pio
+ (is_on
? PIO_MDER
: PIO_MDDR
));
198 EXPORT_SYMBOL(at91_set_multi_drive
);
200 /*--------------------------------------------------------------------------*/
202 /* new-style GPIO calls; these expect at91_set_GPIO_periph to have been
203 * called, and maybe at91_set_multi_drive() for putout pins.
206 int gpio_direction_input(unsigned pin
)
208 void __iomem
*pio
= pin_to_controller(pin
);
209 unsigned mask
= pin_to_mask(pin
);
211 if (!pio
|| !(__raw_readl(pio
+ PIO_PSR
) & mask
))
213 __raw_writel(mask
, pio
+ PIO_OER
);
216 EXPORT_SYMBOL(gpio_direction_input
);
218 int gpio_direction_output(unsigned pin
)
220 void __iomem
*pio
= pin_to_controller(pin
);
221 unsigned mask
= pin_to_mask(pin
);
223 if (!pio
|| !(__raw_readl(pio
+ PIO_PSR
) & mask
))
225 __raw_writel(mask
, pio
+ PIO_OER
);
228 EXPORT_SYMBOL(gpio_direction_output
);
230 /*--------------------------------------------------------------------------*/
233 * assuming the pin is muxed as a gpio output, set its value.
235 int at91_set_gpio_value(unsigned pin
, int value
)
237 void __iomem
*pio
= pin_to_controller(pin
);
238 unsigned mask
= pin_to_mask(pin
);
242 __raw_writel(mask
, pio
+ (value
? PIO_SODR
: PIO_CODR
));
245 EXPORT_SYMBOL(at91_set_gpio_value
);
249 * read the pin's value (works even if it's not muxed as a gpio).
251 int at91_get_gpio_value(unsigned pin
)
253 void __iomem
*pio
= pin_to_controller(pin
);
254 unsigned mask
= pin_to_mask(pin
);
259 pdsr
= __raw_readl(pio
+ PIO_PDSR
);
260 return (pdsr
& mask
) != 0;
262 EXPORT_SYMBOL(at91_get_gpio_value
);
264 /*--------------------------------------------------------------------------*/
268 static u32 wakeups
[MAX_GPIO_BANKS
];
269 static u32 backups
[MAX_GPIO_BANKS
];
271 static int gpio_irq_set_wake(unsigned pin
, unsigned state
)
273 unsigned mask
= pin_to_mask(pin
);
274 unsigned bank
= (pin
- PIN_BASE
) / 32;
276 if (unlikely(bank
>= MAX_GPIO_BANKS
))
280 wakeups
[bank
] |= mask
;
282 wakeups
[bank
] &= ~mask
;
284 set_irq_wake(gpio
[bank
].id
, state
);
289 void at91_gpio_suspend(void)
293 for (i
= 0; i
< gpio_banks
; i
++) {
294 u32 pio
= gpio
[i
].offset
;
296 backups
[i
] = at91_sys_read(pio
+ PIO_IMR
);
297 at91_sys_write(pio
+ PIO_IDR
, backups
[i
]);
298 at91_sys_write(pio
+ PIO_IER
, wakeups
[i
]);
301 clk_disable(gpio
[i
].clock
);
303 #ifdef CONFIG_PM_DEBUG
304 printk(KERN_DEBUG
"GPIO-%c may wake for %08x\n", 'A'+i
, wakeups
[i
]);
310 void at91_gpio_resume(void)
314 for (i
= 0; i
< gpio_banks
; i
++) {
315 u32 pio
= gpio
[i
].offset
;
318 clk_enable(gpio
[i
].clock
);
320 at91_sys_write(pio
+ PIO_IDR
, wakeups
[i
]);
321 at91_sys_write(pio
+ PIO_IER
, backups
[i
]);
326 #define gpio_irq_set_wake NULL
330 /* Several AIC controller irqs are dispatched through this GPIO handler.
331 * To use any AT91_PIN_* as an externally triggered IRQ, first call
332 * at91_set_gpio_input() then maybe enable its glitch filter.
333 * Then just request_irq() with the pin ID; it works like any ARM IRQ
334 * handler, though it always triggers on rising and falling edges.
336 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
337 * configuring them with at91_set_a_periph() or at91_set_b_periph().
338 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
341 static void gpio_irq_mask(unsigned pin
)
343 void __iomem
*pio
= pin_to_controller(pin
);
344 unsigned mask
= pin_to_mask(pin
);
347 __raw_writel(mask
, pio
+ PIO_IDR
);
350 static void gpio_irq_unmask(unsigned pin
)
352 void __iomem
*pio
= pin_to_controller(pin
);
353 unsigned mask
= pin_to_mask(pin
);
356 __raw_writel(mask
, pio
+ PIO_IER
);
359 static int gpio_irq_type(unsigned pin
, unsigned type
)
361 return (type
== IRQT_BOTHEDGE
) ? 0 : -EINVAL
;
364 static struct irq_chip gpio_irqchip
= {
366 .mask
= gpio_irq_mask
,
367 .unmask
= gpio_irq_unmask
,
368 .set_type
= gpio_irq_type
,
369 .set_wake
= gpio_irq_set_wake
,
372 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
375 struct irq_desc
*gpio
;
379 pio
= get_irq_chip_data(irq
);
381 /* temporarily mask (level sensitive) parent IRQ */
382 desc
->chip
->ack(irq
);
384 /* reading ISR acks the pending (edge triggered) GPIO interrupt */
385 isr
= __raw_readl(pio
+ PIO_ISR
) & __raw_readl(pio
+ PIO_IMR
);
389 pin
= (unsigned) get_irq_data(irq
);
390 gpio
= &irq_desc
[pin
];
394 if (unlikely(gpio
->depth
)) {
396 * The core ARM interrupt handler lazily disables IRQs so
397 * another IRQ must be generated before it actually gets
398 * here to be disabled on the GPIO controller.
403 desc_handle_irq(pin
, gpio
);
410 desc
->chip
->unmask(irq
);
411 /* now it may re-trigger */
414 /*--------------------------------------------------------------------------*/
417 * Called from the processor-specific init to enable GPIO interrupt support.
419 void __init
at91_gpio_irq_setup(void)
423 for (pioc
= 0, pin
= PIN_BASE
;
426 void __iomem
*controller
;
427 unsigned id
= gpio
[pioc
].id
;
430 clk_enable(gpio
[pioc
].clock
); /* enable PIO controller's clock */
432 controller
= (void __iomem
*) AT91_VA_BASE_SYS
+ gpio
[pioc
].offset
;
433 __raw_writel(~0, controller
+ PIO_IDR
);
435 set_irq_data(id
, (void *) pin
);
436 set_irq_chip_data(id
, controller
);
438 for (i
= 0; i
< 32; i
++, pin
++) {
440 * Can use the "simple" and not "edge" handler since it's
441 * shorter, and the AIC handles interupts sanely.
443 set_irq_chip(pin
, &gpio_irqchip
);
444 set_irq_handler(pin
, handle_simple_irq
);
445 set_irq_flags(pin
, IRQF_VALID
);
448 set_irq_chained_handler(id
, gpio_irq_handler
);
450 pr_info("AT91: %d gpio irqs in %d banks\n", pin
- PIN_BASE
, gpio_banks
);
454 * Called from the processor-specific init to enable GPIO pin support.
456 void __init
at91_gpio_init(struct at91_gpio_bank
*data
, int nr_banks
)
458 BUG_ON(nr_banks
> MAX_GPIO_BANKS
);
461 gpio_banks
= nr_banks
;