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[PATCH] video/matrox/matroxfb_misc.c: remove dead code
[linux-2.6/sactl.git] / drivers / video / matrox / matroxfb_misc.c
blob455a46ce840c3360d93d33ddbc56b16b493b138a
1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
8 *
9 * Version: 1.65 2002/08/14
10 *
11 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
12 *
13 * Contributors: "menion?" <menion@mindless.com>
14 * Betatesting, fixes, ideas
15 *
16 * "Kurt Garloff" <garloff@suse.de>
17 * Betatesting, fixes, ideas, videomodes, videomodes timmings
18 *
19 * "Tom Rini" <trini@kernel.crashing.org>
20 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
21 *
22 * "Bibek Sahu" <scorpio@dodds.net>
23 * Access device through readb|w|l and write b|w|l
24 * Extensive debugging stuff
25 *
26 * "Daniel Haun" <haund@usa.net>
27 * Testing, hardware cursor fixes
28 *
29 * "Scott Wood" <sawst46+@pitt.edu>
30 * Fixes
31 *
32 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
33 * Betatesting
34 *
35 * "Kelly French" <targon@hazmat.com>
36 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
37 * Betatesting, bug reporting
38 *
39 * "Pablo Bianucci" <pbian@pccp.com.ar>
40 * Fixes, ideas, betatesting
41 *
42 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
43 * Fixes, enhandcements, ideas, betatesting
44 *
45 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
46 * PPC betatesting, PPC support, backward compatibility
47 *
48 * "Paul Womar" <Paul@pwomar.demon.co.uk>
49 * "Owen Waller" <O.Waller@ee.qub.ac.uk>
50 * PPC betatesting
51 *
52 * "Thomas Pornin" <pornin@bolet.ens.fr>
53 * Alpha betatesting
54 *
55 * "Pieter van Leuven" <pvl@iae.nl>
56 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
57 * G100 testing
58 *
59 * "H. Peter Arvin" <hpa@transmeta.com>
60 * Ideas
61 *
62 * "Cort Dougan" <cort@cs.nmt.edu>
63 * CHRP fixes and PReP cleanup
64 *
65 * "Mark Vojkovich" <mvojkovi@ucsd.edu>
66 * G400 support
67 *
68 * "David C. Hansen" <haveblue@us.ibm.com>
69 * Fixes
70 *
71 * "Ian Romanick" <idr@us.ibm.com>
72 * Find PInS data in BIOS on PowerPC systems.
73 *
74 * (following author is not in any relation with this code, but his code
75 * is included in this driver)
76 *
77 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
78 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
79 *
80 * (following author is not in any relation with this code, but his ideas
81 * were used when writting this driver)
82 *
83 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
84 *
85 */
86
87 /* make checkconfig does not check includes for this... */
88 #include <linux/config.h>
89
90 #include "matroxfb_misc.h"
91 #include <linux/interrupt.h>
92 #include <linux/matroxfb.h>
93
94 void matroxfb_DAC_out(CPMINFO int reg, int val) {
95 DBG_REG(__FUNCTION__)
96 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
97 mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
98 }
99
100 int matroxfb_DAC_in(CPMINFO int reg) {
101 DBG_REG(__FUNCTION__)
102 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
103 return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
104 }
105
106 void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) {
107 unsigned int pixclock = var->pixclock;
108
109 DBG(__FUNCTION__)
110
111 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
112 mt->pixclock = 1000000000 / pixclock;
113 if (mt->pixclock < 1) mt->pixclock = 1;
114 mt->mnp = -1;
115 mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
116 mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
117 mt->HDisplay = var->xres;
118 mt->HSyncStart = mt->HDisplay + var->right_margin;
119 mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
120 mt->HTotal = mt->HSyncEnd + var->left_margin;
121 mt->VDisplay = var->yres;
122 mt->VSyncStart = mt->VDisplay + var->lower_margin;
123 mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
124 mt->VTotal = mt->VSyncEnd + var->upper_margin;
125 mt->sync = var->sync;
126 }
127
128 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
129 unsigned int* in, unsigned int* feed, unsigned int* post) {
130 unsigned int bestdiff = ~0;
131 unsigned int bestvco = 0;
132 unsigned int fxtal = pll->ref_freq;
133 unsigned int fwant;
134 unsigned int p;
135
136 DBG(__FUNCTION__)
137
138 fwant = freq;
139
140 #ifdef DEBUG
141 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
142 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
143 printk(KERN_ERR "freq: %d\n", freq);
144 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
145 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
146 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
147 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
148 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
149 printk(KERN_ERR "fmax: %d\n", fmax);
150 #endif
151 for (p = 1; p <= pll->post_shift_max; p++) {
152 if (fwant * 2 > fmax)
153 break;
154 fwant *= 2;
155 }
156 if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
157 if (fwant > fmax) fwant = fmax;
158 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
159 unsigned int m;
160
161 if (fwant < pll->vco_freq_min) break;
162 for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
163 unsigned int diff, fvco;
164 unsigned int n;
165
166 n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
167 if (n > pll->feed_div_max)
168 break;
169 if (n < pll->feed_div_min)
170 n = pll->feed_div_min;
171 fvco = (fxtal * (n + 1)) / (m + 1);
172 if (fvco < fwant)
173 diff = fwant - fvco;
174 else
175 diff = fvco - fwant;
176 if (diff < bestdiff) {
177 bestdiff = diff;
178 *post = p;
179 *in = m;
180 *feed = n;
181 bestvco = fvco;
182 }
183 }
184 }
185 dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant);
186 return bestvco;
187 }
188
189 int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
190 unsigned int hd, hs, he, hbe, ht;
191 unsigned int vd, vs, ve, vt, lc;
192 unsigned int wd;
193 unsigned int divider;
194 int i;
195 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
196
197 DBG(__FUNCTION__)
198
199 hw->SEQ[0] = 0x00;
200 hw->SEQ[1] = 0x01; /* or 0x09 */
201 hw->SEQ[2] = 0x0F; /* bitplanes */
202 hw->SEQ[3] = 0x00;
203 hw->SEQ[4] = 0x0E;
204 /* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */
205 if (m->dblscan) {
206 m->VTotal <<= 1;
207 m->VDisplay <<= 1;
208 m->VSyncStart <<= 1;
209 m->VSyncEnd <<= 1;
210 }
211 if (m->interlaced) {
212 m->VTotal >>= 1;
213 m->VDisplay >>= 1;
214 m->VSyncStart >>= 1;
215 m->VSyncEnd >>= 1;
216 }
217
218 /* GCTL is ignored when not using 0xA0000 aperture */
219 hw->GCTL[0] = 0x00;
220 hw->GCTL[1] = 0x00;
221 hw->GCTL[2] = 0x00;
222 hw->GCTL[3] = 0x00;
223 hw->GCTL[4] = 0x00;
224 hw->GCTL[5] = 0x40;
225 hw->GCTL[6] = 0x05;
226 hw->GCTL[7] = 0x0F;
227 hw->GCTL[8] = 0xFF;
228
229 /* Whole ATTR is ignored in PowerGraphics mode */
230 for (i = 0; i < 16; i++)
231 hw->ATTR[i] = i;
232 hw->ATTR[16] = 0x41;
233 hw->ATTR[17] = 0xFF;
234 hw->ATTR[18] = 0x0F;
235 hw->ATTR[19] = 0x00;
236 hw->ATTR[20] = 0x00;
237
238 hd = m->HDisplay >> 3;
239 hs = m->HSyncStart >> 3;
240 he = m->HSyncEnd >> 3;
241 ht = m->HTotal >> 3;
242 /* standard timmings are in 8pixels, but for interleaved we cannot */
243 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
244 /* using 16 or more pixels per unit can save us */
245 divider = ACCESS_FBINFO(curr.final_bppShift);
246 while (divider & 3) {
247 hd >>= 1;
248 hs >>= 1;
249 he >>= 1;
250 ht >>= 1;
251 divider <<= 1;
252 }
253 divider = divider / 4;
254 /* divider can be from 1 to 8 */
255 while (divider > 8) {
256 hd <<= 1;
257 hs <<= 1;
258 he <<= 1;
259 ht <<= 1;
260 divider >>= 1;
261 }
262 hd = hd - 1;
263 hs = hs - 1;
264 he = he - 1;
265 ht = ht - 1;
266 vd = m->VDisplay - 1;
267 vs = m->VSyncStart - 1;
268 ve = m->VSyncEnd - 1;
269 vt = m->VTotal - 2;
270 lc = vd;
271 /* G200 cannot work with (ht & 7) == 6 */
272 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
273 ht++;
274 hbe = ht;
275 wd = ACCESS_FBINFO(fbcon).var.xres_virtual * ACCESS_FBINFO(curr.final_bppShift) / 64;
276
277 hw->CRTCEXT[0] = 0;
278 hw->CRTCEXT[5] = 0;
279 if (m->interlaced) {
280 hw->CRTCEXT[0] = 0x80;
281 hw->CRTCEXT[5] = (hs + he - ht) >> 1;
282 if (!m->dblscan)
283 wd <<= 1;
284 vt &= ~1;
285 }
286 hw->CRTCEXT[0] |= (wd & 0x300) >> 4;
287 hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
288 ((hd & 0x100) >> 7) | /* blanking */
289 ((hs & 0x100) >> 6) | /* sync start */
290 (hbe & 0x040); /* end hor. blanking */
291 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */
292 if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1)
293 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
294 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
295 ((vd & 0x400) >> 8) | /* disp end */
296 ((vd & 0xC00) >> 7) | /* vblanking start */
297 ((vs & 0xC00) >> 5) |
298 ((lc & 0x400) >> 3);
299 hw->CRTCEXT[3] = (divider - 1) | 0x80;
300 hw->CRTCEXT[4] = 0;
301
302 hw->CRTC[0] = ht-4;
303 hw->CRTC[1] = hd;
304 hw->CRTC[2] = hd;
305 hw->CRTC[3] = (hbe & 0x1F) | 0x80;
306 hw->CRTC[4] = hs;
307 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
308 hw->CRTC[6] = vt & 0xFF;
309 hw->CRTC[7] = ((vt & 0x100) >> 8) |
310 ((vd & 0x100) >> 7) |
311 ((vs & 0x100) >> 6) |
312 ((vd & 0x100) >> 5) |
313 ((lc & 0x100) >> 4) |
314 ((vt & 0x200) >> 4) |
315 ((vd & 0x200) >> 3) |
316 ((vs & 0x200) >> 2);
317 hw->CRTC[8] = 0x00;
318 hw->CRTC[9] = ((vd & 0x200) >> 4) |
319 ((lc & 0x200) >> 3);
320 if (m->dblscan && !m->interlaced)
321 hw->CRTC[9] |= 0x80;
322 for (i = 10; i < 16; i++)
323 hw->CRTC[i] = 0x00;
324 hw->CRTC[16] = vs /* & 0xFF */;
325 hw->CRTC[17] = (ve & 0x0F) | 0x20;
326 hw->CRTC[18] = vd /* & 0xFF */;
327 hw->CRTC[19] = wd /* & 0xFF */;
328 hw->CRTC[20] = 0x00;
329 hw->CRTC[21] = vd /* & 0xFF */;
330 hw->CRTC[22] = (vt + 1) /* & 0xFF */;
331 hw->CRTC[23] = 0xC3;
332 hw->CRTC[24] = lc;
333 return 0;
334 };
335
336 void matroxfb_vgaHWrestore(WPMINFO2) {
337 int i;
338 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
339 CRITFLAGS
340
341 DBG(__FUNCTION__)
342
343 dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
344 dprintk(KERN_INFO "SEQ regs: ");
345 for (i = 0; i < 5; i++)
346 dprintk("%02X:", hw->SEQ[i]);
347 dprintk("\n");
348 dprintk(KERN_INFO "GDC regs: ");
349 for (i = 0; i < 9; i++)
350 dprintk("%02X:", hw->GCTL[i]);
351 dprintk("\n");
352 dprintk(KERN_INFO "CRTC regs: ");
353 for (i = 0; i < 25; i++)
354 dprintk("%02X:", hw->CRTC[i]);
355 dprintk("\n");
356 dprintk(KERN_INFO "ATTR regs: ");
357 for (i = 0; i < 21; i++)
358 dprintk("%02X:", hw->ATTR[i]);
359 dprintk("\n");
360
361 CRITBEGIN
362
363 mga_inb(M_ATTR_RESET);
364 mga_outb(M_ATTR_INDEX, 0);
365 mga_outb(M_MISC_REG, hw->MiscOutReg);
366 for (i = 1; i < 5; i++)
367 mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
368 mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
369 for (i = 0; i < 25; i++)
370 mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
371 for (i = 0; i < 9; i++)
372 mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
373 for (i = 0; i < 21; i++) {
374 mga_inb(M_ATTR_RESET);
375 mga_outb(M_ATTR_INDEX, i);
376 mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
377 }
378 mga_outb(M_PALETTE_MASK, 0xFF);
379 mga_outb(M_DAC_REG, 0x00);
380 for (i = 0; i < 768; i++)
381 mga_outb(M_DAC_VAL, hw->DACpal[i]);
382 mga_inb(M_ATTR_RESET);
383 mga_outb(M_ATTR_INDEX, 0x20);
384
385 CRITEND
386 }
387
388 static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) {
389 unsigned int b0 = readb(pins);
390
391 if (b0 == 0x2E && readb(pins+1) == 0x41) {
392 unsigned int pins_len = readb(pins+2);
393 unsigned int i;
394 unsigned char cksum;
395 unsigned char* dst = bd->pins;
396
397 if (pins_len < 3 || pins_len > 128) {
398 return;
399 }
400 *dst++ = 0x2E;
401 *dst++ = 0x41;
402 *dst++ = pins_len;
403 cksum = 0x2E + 0x41 + pins_len;
404 for (i = 3; i < pins_len; i++) {
405 cksum += *dst++ = readb(pins+i);
406 }
407 if (cksum) {
408 return;
409 }
410 bd->pins_len = pins_len;
411 } else if (b0 == 0x40 && readb(pins+1) == 0x00) {
412 unsigned int i;
413 unsigned char* dst = bd->pins;
414
415 *dst++ = 0x40;
416 *dst++ = 0;
417 for (i = 2; i < 0x40; i++) {
418 *dst++ = readb(pins+i);
419 }
420 bd->pins_len = 0x40;
421 }
422 }
423
424 static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) {
425 unsigned int pcir_offset;
426
427 pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8);
428 if (pcir_offset >= 26 && pcir_offset < 0xFFE0 &&
429 readb(vbios + pcir_offset ) == 'P' &&
430 readb(vbios + pcir_offset + 1) == 'C' &&
431 readb(vbios + pcir_offset + 2) == 'I' &&
432 readb(vbios + pcir_offset + 3) == 'R') {
433 unsigned char h;
434
435 h = readb(vbios + pcir_offset + 0x12);
436 bd->version.vMaj = (h >> 4) & 0xF;
437 bd->version.vMin = h & 0xF;
438 bd->version.vRev = readb(vbios + pcir_offset + 0x13);
439 } else {
440 unsigned char h;
441
442 h = readb(vbios + 5);
443 bd->version.vMaj = (h >> 4) & 0xF;
444 bd->version.vMin = h & 0xF;
445 bd->version.vRev = 0;
446 }
447 }
448
449 static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) {
450 unsigned char b;
451
452 b = readb(vbios + 0x7FF1);
453 if (b == 0xFF) {
454 b = 0;
455 }
456 bd->output.state = b;
457 }
458
459 static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) {
460 unsigned int i;
461
462 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
463 bd->output.tvout = 0;
464 if (readb(vbios + 0x1D) != 'I' ||
465 readb(vbios + 0x1E) != 'B' ||
466 readb(vbios + 0x1F) != 'M' ||
467 readb(vbios + 0x20) != ' ') {
468 return;
469 }
470 for (i = 0x2D; i < 0x2D + 128; i++) {
471 unsigned char b = readb(vbios + i);
472
473 if (b == '(' && readb(vbios + i + 1) == 'V') {
474 if (readb(vbios + i + 6) == 'T' &&
475 readb(vbios + i + 7) == 'V' &&
476 readb(vbios + i + 8) == 'O') {
477 bd->output.tvout = 1;
478 }
479 return;
480 }
481 if (b == 0)
482 break;
483 }
484 }
485
486 static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
487 unsigned int pins_offset;
488
489 if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) {
490 return;
491 }
492 bd->bios_valid = 1;
493 get_bios_version(vbios, bd);
494 get_bios_output(vbios, bd);
495 get_bios_tvout(vbios, bd);
496 #if defined(__powerpc__)
497 /* On PowerPC cards, the PInS offset isn't stored at the end of the
498 * BIOS image. Instead, you must search the entire BIOS image for
499 * the magic PInS signature.
500 *
501 * This actually applies to all OpenFirmware base cards. Since these
502 * cards could be put in a MIPS or SPARC system, should the condition
503 * be something different?
504 */
505 for ( pins_offset = 0 ; pins_offset <= 0xFF80 ; pins_offset++ ) {
506 unsigned char header[3];
507
508 header[0] = readb(vbios + pins_offset);
509 header[1] = readb(vbios + pins_offset + 1);
510 header[2] = readb(vbios + pins_offset + 2);
511 if ( (header[0] == 0x2E) && (header[1] == 0x41)
512 && ((header[2] == 0x40) || (header[2] == 0x80)) ) {
513 printk(KERN_INFO "PInS data found at offset %u\n",
514 pins_offset);
515 get_pins(vbios + pins_offset, bd);
516 break;
517 }
518 }
519 #else
520 pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8);
521 if (pins_offset <= 0xFF80) {
522 get_pins(vbios + pins_offset, bd);
523 }
524 #endif
525 }
526
527 #define get_u16(x) (le16_to_cpu(get_unaligned((__u16*)(x))))
528 #define get_u32(x) (le32_to_cpu(get_unaligned((__u32*)(x))))
529 static int parse_pins1(WPMINFO const struct matrox_bios* bd) {
530 unsigned int maxdac;
531
532 switch (bd->pins[22]) {
533 case 0: maxdac = 175000; break;
534 case 1: maxdac = 220000; break;
535 default: maxdac = 240000; break;
536 }
537 if (get_u16(bd->pins + 24)) {
538 maxdac = get_u16(bd->pins + 24) * 10;
539 }
540 MINFO->limits.pixel.vcomax = maxdac;
541 MINFO->values.pll.system = get_u16(bd->pins + 28) ? get_u16(bd->pins + 28) * 10 : 50000;
542 /* ignore 4MB, 8MB, module clocks */
543 MINFO->features.pll.ref_freq = 14318;
544 MINFO->values.reg.mctlwtst = 0x00030101;
545 return 0;
546 }
547
548 static void default_pins1(WPMINFO2) {
549 /* Millennium */
550 MINFO->limits.pixel.vcomax = 220000;
551 MINFO->values.pll.system = 50000;
552 MINFO->features.pll.ref_freq = 14318;
553 MINFO->values.reg.mctlwtst = 0x00030101;
554 }
555
556 static int parse_pins2(WPMINFO const struct matrox_bios* bd) {
557 MINFO->limits.pixel.vcomax =
558 MINFO->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
559 MINFO->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
560 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
561 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
562 ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
563 MINFO->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
564 MINFO->features.pll.ref_freq = 14318;
565 return 0;
566 }
567
568 static void default_pins2(WPMINFO2) {
569 /* Millennium II, Mystique */
570 MINFO->limits.pixel.vcomax =
571 MINFO->limits.system.vcomax = 230000;
572 MINFO->values.reg.mctlwtst = 0x00030101;
573 MINFO->values.pll.system = 50000;
574 MINFO->features.pll.ref_freq = 14318;
575 }
576
577 static int parse_pins3(WPMINFO const struct matrox_bios* bd) {
578 MINFO->limits.pixel.vcomax =
579 MINFO->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
580 MINFO->values.reg.mctlwtst = get_u32(bd->pins + 48) == 0xFFFFFFFF ? 0x01250A21 : get_u32(bd->pins + 48);
581 /* memory config */
582 MINFO->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
583 ((bd->pins[57] << 22) & 0x00C00000) |
584 ((bd->pins[56] << 1) & 0x000001E0) |
585 ( bd->pins[56] & 0x0000000F);
586 MINFO->values.reg.opt = (bd->pins[54] & 7) << 10;
587 MINFO->values.reg.opt2 = bd->pins[58] << 12;
588 MINFO->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
589 return 0;
590 }
591
592 static void default_pins3(WPMINFO2) {
593 /* G100, G200 */
594 MINFO->limits.pixel.vcomax =
595 MINFO->limits.system.vcomax = 230000;
596 MINFO->values.reg.mctlwtst = 0x01250A21;
597 MINFO->values.reg.memrdbk = 0x00000000;
598 MINFO->values.reg.opt = 0x00000C00;
599 MINFO->values.reg.opt2 = 0x00000000;
600 MINFO->features.pll.ref_freq = 27000;
601 }
602
603 static int parse_pins4(WPMINFO const struct matrox_bios* bd) {
604 MINFO->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
605 MINFO->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 38] * 4000;
606 MINFO->values.reg.mctlwtst = get_u32(bd->pins + 71);
607 MINFO->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
608 ((bd->pins[87] << 22) & 0x00C00000) |
609 ((bd->pins[86] << 1) & 0x000001E0) |
610 ( bd->pins[86] & 0x0000000F);
611 MINFO->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
612 ((bd->pins[53] << 22) & 0x10000000) |
613 ((bd->pins[53] << 7) & 0x00001C00);
614 MINFO->values.reg.opt3 = get_u32(bd->pins + 67);
615 MINFO->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
616 MINFO->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
617 return 0;
618 }
619
620 static void default_pins4(WPMINFO2) {
621 /* G400 */
622 MINFO->limits.pixel.vcomax =
623 MINFO->limits.system.vcomax = 252000;
624 MINFO->values.reg.mctlwtst = 0x04A450A1;
625 MINFO->values.reg.memrdbk = 0x000000E7;
626 MINFO->values.reg.opt = 0x10000400;
627 MINFO->values.reg.opt3 = 0x0190A419;
628 MINFO->values.pll.system = 200000;
629 MINFO->features.pll.ref_freq = 27000;
630 }
631
632 static int parse_pins5(WPMINFO const struct matrox_bios* bd) {
633 unsigned int mult;
634
635 mult = bd->pins[4]?8000:6000;
636
637 MINFO->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
638 MINFO->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 36] * mult;
639 MINFO->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? MINFO->limits.system.vcomax : bd->pins[ 37] * mult;
640 MINFO->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
641 MINFO->limits.system.vcomin = (bd->pins[121] == 0xFF) ? MINFO->limits.pixel.vcomin : bd->pins[121] * mult;
642 MINFO->limits.video.vcomin = (bd->pins[122] == 0xFF) ? MINFO->limits.system.vcomin : bd->pins[122] * mult;
643 MINFO->values.pll.system =
644 MINFO->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
645 MINFO->values.reg.opt = get_u32(bd->pins+ 48);
646 MINFO->values.reg.opt2 = get_u32(bd->pins+ 52);
647 MINFO->values.reg.opt3 = get_u32(bd->pins+ 94);
648 MINFO->values.reg.mctlwtst = get_u32(bd->pins+ 98);
649 MINFO->values.reg.memmisc = get_u32(bd->pins+102);
650 MINFO->values.reg.memrdbk = get_u32(bd->pins+106);
651 MINFO->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
652 MINFO->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
653 MINFO->values.memory.dll = (bd->pins[115] & 0x02) != 0;
654 MINFO->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
655 MINFO->values.reg.maccess = MINFO->values.memory.emrswen ? 0x00004000 : 0x00000000;
656 if (bd->pins[115] & 4) {
657 MINFO->values.reg.mctlwtst_core = MINFO->values.reg.mctlwtst;
658 } else {
659 u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 };
660 MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) |
661 wtst_xlat[MINFO->values.reg.mctlwtst & 7];
662 }
663 return 0;
664 }
665
666 static void default_pins5(WPMINFO2) {
667 /* Mine 16MB G450 with SDRAM DDR */
668 MINFO->limits.pixel.vcomax =
669 MINFO->limits.system.vcomax =
670 MINFO->limits.video.vcomax = 600000;
671 MINFO->limits.pixel.vcomin =
672 MINFO->limits.system.vcomin =
673 MINFO->limits.video.vcomin = 256000;
674 MINFO->values.pll.system =
675 MINFO->values.pll.video = 284000;
676 MINFO->values.reg.opt = 0x404A1160;
677 MINFO->values.reg.opt2 = 0x0000AC00;
678 MINFO->values.reg.opt3 = 0x0090A409;
679 MINFO->values.reg.mctlwtst_core =
680 MINFO->values.reg.mctlwtst = 0x0C81462B;
681 MINFO->values.reg.memmisc = 0x80000004;
682 MINFO->values.reg.memrdbk = 0x01001103;
683 MINFO->features.pll.ref_freq = 27000;
684 MINFO->values.memory.ddr = 1;
685 MINFO->values.memory.dll = 1;
686 MINFO->values.memory.emrswen = 1;
687 MINFO->values.reg.maccess = 0x00004000;
688 }
689
690 static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) {
691 unsigned int pins_version;
692 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
693
694 switch (ACCESS_FBINFO(chip)) {
695 case MGA_2064: default_pins1(PMINFO2); break;
696 case MGA_2164:
697 case MGA_1064:
698 case MGA_1164: default_pins2(PMINFO2); break;
699 case MGA_G100:
700 case MGA_G200: default_pins3(PMINFO2); break;
701 case MGA_G400: default_pins4(PMINFO2); break;
702 case MGA_G450:
703 case MGA_G550: default_pins5(PMINFO2); break;
704 }
705 if (!bd->bios_valid) {
706 printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
707 return -1;
708 }
709 if (bd->pins_len < 64) {
710 printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n");
711 return -1;
712 }
713 if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
714 pins_version = bd->pins[5];
715 if (pins_version < 2 || pins_version > 5) {
716 printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version);
717 return -1;
718 }
719 } else {
720 pins_version = 1;
721 }
722 if (bd->pins_len != pinslen[pins_version - 1]) {
723 printk(KERN_INFO "matroxfb: Invalid powerup info\n");
724 return -1;
725 }
726 switch (pins_version) {
727 case 1:
728 return parse_pins1(PMINFO bd);
729 case 2:
730 return parse_pins2(PMINFO bd);
731 case 3:
732 return parse_pins3(PMINFO bd);
733 case 4:
734 return parse_pins4(PMINFO bd);
735 case 5:
736 return parse_pins5(PMINFO bd);
737 default:
738 printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
739 return -1;
740 }
741 }
742
743 void matroxfb_read_pins(WPMINFO2) {
744 u32 opt;
745 u32 biosbase;
746 u32 fbbase;
747 struct pci_dev* pdev = ACCESS_FBINFO(pcidev);
748
749 memset(&ACCESS_FBINFO(bios), 0, sizeof(ACCESS_FBINFO(bios)));
750 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
751 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
752 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
753 pci_read_config_dword(pdev, ACCESS_FBINFO(devflags.fbResource), &fbbase);
754 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
755 parse_bios(vaddr_va(ACCESS_FBINFO(video).vbase), &ACCESS_FBINFO(bios));
756 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
757 pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
758 #ifdef CONFIG_X86
759 if (!ACCESS_FBINFO(bios).bios_valid) {
760 unsigned char __iomem* b;
761
762 b = ioremap(0x000C0000, 65536);
763 if (!b) {
764 printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n");
765 } else {
766 unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8);
767 unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8);
768
769 if (ven != pdev->vendor || dev != pdev->device) {
770 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
771 ven, dev, pdev->vendor, pdev->device);
772 } else {
773 parse_bios(b, &ACCESS_FBINFO(bios));
774 }
775 iounmap(b);
776 }
777 }
778 #endif
779 matroxfb_set_limits(PMINFO &ACCESS_FBINFO(bios));
780 printk(KERN_INFO "PInS memtype = %u\n",
781 (ACCESS_FBINFO(values).reg.opt & 0x1C00) >> 10);
782 }
783
784 EXPORT_SYMBOL(matroxfb_DAC_in);
785 EXPORT_SYMBOL(matroxfb_DAC_out);
786 EXPORT_SYMBOL(matroxfb_var2my);
787 EXPORT_SYMBOL(matroxfb_PLL_calcclock);
788 #ifndef CONFIG_FB_MATROX_MULTIHEAD
789 struct matrox_fb_info matroxfb_global_mxinfo;
790 EXPORT_SYMBOL(matroxfb_global_mxinfo);
791 #endif
792 EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
793 EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
794 EXPORT_SYMBOL(matroxfb_read_pins);
795
796 MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
797 MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards");
798 MODULE_LICENSE("GPL");
SocketAccessConTroL development