drivers/char/tpm/tpm_nsc.c

   1 /*
   2  * Copyright (C) 2004 IBM Corporation
   3  *
   4  * Authors:
   5  * Leendert van Doorn <leendert@watson.ibm.com>
   6  * Dave Safford <safford@watson.ibm.com>
   7  * Reiner Sailer <sailer@watson.ibm.com>
   8  * Kylene Hall <kjhall@us.ibm.com>
   9  *
  10  * Maintained by: <tpmdd_devel@lists.sourceforge.net>
  11  *
  12  * Device driver for TCG/TCPA TPM (trusted platform module).
  13  * Specifications at www.trustedcomputinggroup.org
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation, version 2 of the
  18  * License.
  19  *
  20  */
  21
  22 #include "tpm.h"
  23
  24 /* National definitions */
  25 enum tpm_nsc_addr{
  26         TPM_NSC_IRQ = 0x07,
  27         TPM_NSC_BASE0_HI = 0x60,
  28         TPM_NSC_BASE0_LO = 0x61,
  29         TPM_NSC_BASE1_HI = 0x62,
  30         TPM_NSC_BASE1_LO = 0x63
  31 };
  32
  33 enum tpm_nsc_index {
  34         NSC_LDN_INDEX = 0x07,
  35         NSC_SID_INDEX = 0x20,
  36         NSC_LDC_INDEX = 0x30,
  37         NSC_DIO_INDEX = 0x60,
  38         NSC_CIO_INDEX = 0x62,
  39         NSC_IRQ_INDEX = 0x70,
  40         NSC_ITS_INDEX = 0x71
  41 };
  42
  43 enum tpm_nsc_status_loc {
  44         NSC_STATUS = 0x01,
  45         NSC_COMMAND = 0x01,
  46         NSC_DATA = 0x00
  47 };
  48
  49 /* status bits */
  50 enum tpm_nsc_status {
  51         NSC_STATUS_OBF = 0x01,  /* output buffer full */
  52         NSC_STATUS_IBF = 0x02,  /* input buffer full */
  53         NSC_STATUS_F0 = 0x04,   /* F0 */
  54         NSC_STATUS_A2 = 0x08,   /* A2 */
  55         NSC_STATUS_RDY = 0x10,  /* ready to receive command */
  56         NSC_STATUS_IBR = 0x20   /* ready to receive data */
  57 };
  58
  59 /* command bits */
  60 enum tpm_nsc_cmd_mode {
  61         NSC_COMMAND_NORMAL = 0x01,      /* normal mode */
  62         NSC_COMMAND_EOC = 0x03,
  63         NSC_COMMAND_CANCEL = 0x22
  64 };
  65 /*
  66  * Wait for a certain status to appear
  67  */
  68 static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
  69 {
  70         unsigned long stop;
  71
  72         /* status immediately available check */
  73         *data = inb(chip->vendor->base + NSC_STATUS);
  74         if ((*data & mask) == val)
  75                 return 0;
  76
  77         /* wait for status */
  78         stop = jiffies + 10 * HZ;
  79         do {
  80                 msleep(TPM_TIMEOUT);
  81                 *data = inb(chip->vendor->base + 1);
  82                 if ((*data & mask) == val)
  83                         return 0;
  84         }
  85         while (time_before(jiffies, stop));
  86
  87         return -EBUSY;
  88 }
  89
  90 static int nsc_wait_for_ready(struct tpm_chip *chip)
  91 {
  92         int status;
  93         unsigned long stop;
  94
  95         /* status immediately available check */
  96         status = inb(chip->vendor->base + NSC_STATUS);
  97         if (status & NSC_STATUS_OBF)
  98                 status = inb(chip->vendor->base + NSC_DATA);
  99         if (status & NSC_STATUS_RDY)
 100                 return 0;
 101
 102         /* wait for status */
 103         stop = jiffies + 100;
 104         do {
 105                 msleep(TPM_TIMEOUT);
 106                 status = inb(chip->vendor->base + NSC_STATUS);
 107                 if (status & NSC_STATUS_OBF)
 108                         status = inb(chip->vendor->base + NSC_DATA);
 109                 if (status & NSC_STATUS_RDY)
 110                         return 0;
 111         }
 112         while (time_before(jiffies, stop));
 113
 114         dev_info(&chip->pci_dev->dev, "wait for ready failed\n");
 115         return -EBUSY;
 116 }
 117
 118
 119 static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
 120 {
 121         u8 *buffer = buf;
 122         u8 data, *p;
 123         u32 size;
 124         __be32 *native_size;
 125
 126         if (count < 6)
 127                 return -EIO;
 128
 129         if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
 130                 dev_err(&chip->pci_dev->dev, "F0 timeout\n");
 131                 return -EIO;
 132         }
 133         if ((data =
 134              inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
 135                 dev_err(&chip->pci_dev->dev, "not in normal mode (0x%x)\n",
 136                         data);
 137                 return -EIO;
 138         }
 139
 140         /* read the whole packet */
 141         for (p = buffer; p < &buffer[count]; p++) {
 142                 if (wait_for_stat
 143                     (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
 144                         dev_err(&chip->pci_dev->dev,
 145                                 "OBF timeout (while reading data)\n");
 146                         return -EIO;
 147                 }
 148                 if (data & NSC_STATUS_F0)
 149                         break;
 150                 *p = inb(chip->vendor->base + NSC_DATA);
 151         }
 152
 153         if ((data & NSC_STATUS_F0) == 0 &&
 154         (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
 155                 dev_err(&chip->pci_dev->dev, "F0 not set\n");
 156                 return -EIO;
 157         }
 158         if ((data = inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_EOC) {
 159                 dev_err(&chip->pci_dev->dev,
 160                         "expected end of command(0x%x)\n", data);
 161                 return -EIO;
 162         }
 163
 164         native_size = (__force __be32 *) (buf + 2);
 165         size = be32_to_cpu(*native_size);
 166
 167         if (count < size)
 168                 return -EIO;
 169
 170         return size;
 171 }
 172
 173 static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
 174 {
 175         u8 data;
 176         int i;
 177
 178         /*
 179          * If we hit the chip with back to back commands it locks up
 180          * and never set IBF. Hitting it with this "hammer" seems to
 181          * fix it. Not sure why this is needed, we followed the flow
 182          * chart in the manual to the letter.
 183          */
 184         outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
 185
 186         if (nsc_wait_for_ready(chip) != 0)
 187                 return -EIO;
 188
 189         if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
 190                 dev_err(&chip->pci_dev->dev, "IBF timeout\n");
 191                 return -EIO;
 192         }
 193
 194         outb(NSC_COMMAND_NORMAL, chip->vendor->base + NSC_COMMAND);
 195         if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
 196                 dev_err(&chip->pci_dev->dev, "IBR timeout\n");
 197                 return -EIO;
 198         }
 199
 200         for (i = 0; i < count; i++) {
 201                 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
 202                         dev_err(&chip->pci_dev->dev,
 203                                 "IBF timeout (while writing data)\n");
 204                         return -EIO;
 205                 }
 206                 outb(buf[i], chip->vendor->base + NSC_DATA);
 207         }
 208
 209         if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
 210                 dev_err(&chip->pci_dev->dev, "IBF timeout\n");
 211                 return -EIO;
 212         }
 213         outb(NSC_COMMAND_EOC, chip->vendor->base + NSC_COMMAND);
 214
 215         return count;
 216 }
 217
 218 static void tpm_nsc_cancel(struct tpm_chip *chip)
 219 {
 220         outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
 221 }
 222
 223 static struct file_operations nsc_ops = {
 224         .owner = THIS_MODULE,
 225         .llseek = no_llseek,
 226         .open = tpm_open,
 227         .read = tpm_read,
 228         .write = tpm_write,
 229         .release = tpm_release,
 230 };
 231
 232 static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
 233 static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
 234 static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL);
 235 static DEVICE_ATTR(cancel, S_IWUSR|S_IWGRP, NULL, tpm_store_cancel);
 236
 237 static struct attribute * nsc_attrs[] = {
 238         &dev_attr_pubek.attr,
 239         &dev_attr_pcrs.attr,
 240         &dev_attr_caps.attr,
 241         &dev_attr_cancel.attr,
 242         0,
 243 };
 244
 245 static struct attribute_group nsc_attr_grp = { .attrs = nsc_attrs };
 246
 247 static struct tpm_vendor_specific tpm_nsc = {
 248         .recv = tpm_nsc_recv,
 249         .send = tpm_nsc_send,
 250         .cancel = tpm_nsc_cancel,
 251         .req_complete_mask = NSC_STATUS_OBF,
 252         .req_complete_val = NSC_STATUS_OBF,
 253         .req_canceled = NSC_STATUS_RDY,
 254         .attr_group = &nsc_attr_grp,
 255         .miscdev = { .fops = &nsc_ops, },
 256 };
 257
 258 static int __devinit tpm_nsc_init(struct pci_dev *pci_dev,
 259                                   const struct pci_device_id *pci_id)
 260 {
 261         int rc = 0;
 262         int lo, hi;
 263         int nscAddrBase = TPM_ADDR;
 264
 265
 266         if (pci_enable_device(pci_dev))
 267                 return -EIO;
 268
 269         /* select PM channel 1 */
 270         tpm_write_index(nscAddrBase,NSC_LDN_INDEX, 0x12);
 271
 272         /* verify that it is a National part (SID) */
 273         if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
 274                 nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
 275                         (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
 276                 if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6) {
 277                         rc = -ENODEV;
 278                         goto out_err;
 279                 }
 280         }
 281
 282         hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
 283         lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
 284         tpm_nsc.base = (hi<<8) | lo;
 285
 286         dev_dbg(&pci_dev->dev, "NSC TPM detected\n");
 287         dev_dbg(&pci_dev->dev,
 288                 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
 289                 tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
 290                 tpm_read_index(nscAddrBase,0x27));
 291         dev_dbg(&pci_dev->dev,
 292                 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
 293                 tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
 294                 tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
 295         dev_dbg(&pci_dev->dev, "NSC IO Base0 0x%x\n",
 296                 (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
 297         dev_dbg(&pci_dev->dev, "NSC IO Base1 0x%x\n",
 298                 (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
 299         dev_dbg(&pci_dev->dev, "NSC Interrupt number and wakeup 0x%x\n",
 300                 tpm_read_index(nscAddrBase,0x70));
 301         dev_dbg(&pci_dev->dev, "NSC IRQ type select 0x%x\n",
 302                 tpm_read_index(nscAddrBase,0x71));
 303         dev_dbg(&pci_dev->dev,
 304                 "NSC DMA channel select0 0x%x, select1 0x%x\n",
 305                 tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
 306         dev_dbg(&pci_dev->dev,
 307                 "NSC Config "
 308                 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 309                 tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
 310                 tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
 311                 tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
 312                 tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
 313                 tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
 314
 315         dev_info(&pci_dev->dev,
 316                  "NSC TPM revision %d\n",
 317                  tpm_read_index(nscAddrBase, 0x27) & 0x1F);
 318
 319         /* enable the DPM module */
 320         tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
 321
 322         if ((rc = tpm_register_hardware(pci_dev, &tpm_nsc)) < 0)
 323                 goto out_err;
 324
 325         return 0;
 326
 327 out_err:
 328         pci_disable_device(pci_dev);
 329         return rc;
 330 }
 331
 332 static struct pci_device_id tpm_pci_tbl[] __devinitdata = {
 333         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0)},
 334         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12)},
 335         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)},
 336         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)},
 337         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)},
 338         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0)},
 339         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1)},
 340         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0)},
 341         {PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_LPC)},
 342         {0,}
 343 };
 344
 345 MODULE_DEVICE_TABLE(pci, tpm_pci_tbl);
 346
 347 static struct pci_driver nsc_pci_driver = {
 348         .name = "tpm_nsc",
 349         .id_table = tpm_pci_tbl,
 350         .probe = tpm_nsc_init,
 351         .remove = __devexit_p(tpm_remove),
 352         .suspend = tpm_pm_suspend,
 353         .resume = tpm_pm_resume,
 354 };
 355
 356 static int __init init_nsc(void)
 357 {
 358         return pci_register_driver(&nsc_pci_driver);
 359 }
 360
 361 static void __exit cleanup_nsc(void)
 362 {
 363         pci_unregister_driver(&nsc_pci_driver);
 364 }
 365
 366 module_init(init_nsc);
 367 module_exit(cleanup_nsc);
 368
 369 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
 370 MODULE_DESCRIPTION("TPM Driver");
 371 MODULE_VERSION("2.0");
 372 MODULE_LICENSE("GPL");