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[MIPS] au1xxx: export dbdma functions
[linux-2.6/sactl.git] / arch / mips / au1000 / common / dbdma.c
bloba547e47dd5fd4211c09df5029adde7795be4dafd
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC
9 * dan@embeddededge.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32
33 #include <linux/config.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/module.h>
43 #include <asm/mach-au1x00/au1000.h>
44 #include <asm/mach-au1x00/au1xxx_dbdma.h>
45 #include <asm/system.h>
46
47
48 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
49
50 /*
51 * The Descriptor Based DMA supports up to 16 channels.
52 *
53 * There are 32 devices defined. We keep an internal structure
54 * of devices using these channels, along with additional
55 * information.
56 *
57 * We allocate the descriptors and allow access to them through various
58 * functions. The drivers allocate the data buffers and assign them
59 * to the descriptors.
60 */
61 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
62
63 /* I couldn't find a macro that did this......
64 */
65 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
66
67 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
68 static int dbdma_initialized=0;
69 static void au1xxx_dbdma_init(void);
70
71 static dbdev_tab_t dbdev_tab[] = {
72 #ifdef CONFIG_SOC_AU1550
73 /* UARTS */
74 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
75 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
76 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
77 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
78
79 /* EXT DMA */
80 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
81 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
82 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
83 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
84
85 /* USB DEV */
86 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
87 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
88 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
89 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
90 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
91 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
92
93 /* PSC 0 */
94 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
95 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
96
97 /* PSC 1 */
98 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
99 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
100
101 /* PSC 2 */
102 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
103 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
104
105 /* PSC 3 */
106 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
107 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
108
109 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
110 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
111
112 /* MAC 0 */
113 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
114 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
115
116 /* MAC 1 */
117 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
118 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
119
120 #endif /* CONFIG_SOC_AU1550 */
121
122 #ifdef CONFIG_SOC_AU1200
123 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
124 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
125 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
126 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
127
128 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
129 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
130
131 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
132 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
133 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
134 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
135
136 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
137 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
138 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
139 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
140
141 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
142 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
143
144 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
145 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
146 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
147
148 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
149 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
150 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
151
152 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
153 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
154 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
155 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
156
157 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
158
159 #endif // CONFIG_SOC_AU1200
160
161 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
162 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
163
164 /* Provide 16 user definable device types */
165 { 0, 0, 0, 0, 0, 0, 0 },
166 { 0, 0, 0, 0, 0, 0, 0 },
167 { 0, 0, 0, 0, 0, 0, 0 },
168 { 0, 0, 0, 0, 0, 0, 0 },
169 { 0, 0, 0, 0, 0, 0, 0 },
170 { 0, 0, 0, 0, 0, 0, 0 },
171 { 0, 0, 0, 0, 0, 0, 0 },
172 { 0, 0, 0, 0, 0, 0, 0 },
173 { 0, 0, 0, 0, 0, 0, 0 },
174 { 0, 0, 0, 0, 0, 0, 0 },
175 { 0, 0, 0, 0, 0, 0, 0 },
176 { 0, 0, 0, 0, 0, 0, 0 },
177 { 0, 0, 0, 0, 0, 0, 0 },
178 { 0, 0, 0, 0, 0, 0, 0 },
179 { 0, 0, 0, 0, 0, 0, 0 },
180 { 0, 0, 0, 0, 0, 0, 0 },
181 };
182
183 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
184
185 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
186
187 static dbdev_tab_t *
188 find_dbdev_id (u32 id)
189 {
190 int i;
191 dbdev_tab_t *p;
192 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
193 p = &dbdev_tab[i];
194 if (p->dev_id == id)
195 return p;
196 }
197 return NULL;
198 }
199
200 void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
201 {
202 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
203 }
204 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
205
206 u32
207 au1xxx_ddma_add_device(dbdev_tab_t *dev)
208 {
209 u32 ret = 0;
210 dbdev_tab_t *p=NULL;
211 static u16 new_id=0x1000;
212
213 p = find_dbdev_id(0);
214 if ( NULL != p )
215 {
216 memcpy(p, dev, sizeof(dbdev_tab_t));
217 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
218 ret = p->dev_id;
219 new_id++;
220 #if 0
221 printk("add_device: id:%x flags:%x padd:%x\n",
222 p->dev_id, p->dev_flags, p->dev_physaddr );
223 #endif
224 }
225
226 return ret;
227 }
228 EXPORT_SYMBOL(au1xxx_ddma_add_device);
229
230 /* Allocate a channel and return a non-zero descriptor if successful.
231 */
232 u32
233 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
234 void (*callback)(int, void *, struct pt_regs *), void *callparam)
235 {
236 unsigned long flags;
237 u32 used, chan, rv;
238 u32 dcp;
239 int i;
240 dbdev_tab_t *stp, *dtp;
241 chan_tab_t *ctp;
242 au1x_dma_chan_t *cp;
243
244 /* We do the intialization on the first channel allocation.
245 * We have to wait because of the interrupt handler initialization
246 * which can't be done successfully during board set up.
247 */
248 if (!dbdma_initialized)
249 au1xxx_dbdma_init();
250 dbdma_initialized = 1;
251
252 if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
253 if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
254
255 used = 0;
256 rv = 0;
257
258 /* Check to see if we can get both channels.
259 */
260 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
261 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
262 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
263 /* Got source */
264 stp->dev_flags |= DEV_FLAGS_INUSE;
265 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
266 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
267 /* Got destination */
268 dtp->dev_flags |= DEV_FLAGS_INUSE;
269 }
270 else {
271 /* Can't get dest. Release src.
272 */
273 stp->dev_flags &= ~DEV_FLAGS_INUSE;
274 used++;
275 }
276 }
277 else {
278 used++;
279 }
280 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
281
282 if (!used) {
283 /* Let's see if we can allocate a channel for it.
284 */
285 ctp = NULL;
286 chan = 0;
287 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
288 for (i=0; i<NUM_DBDMA_CHANS; i++) {
289 if (chan_tab_ptr[i] == NULL) {
290 /* If kmalloc fails, it is caught below same
291 * as a channel not available.
292 */
293 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
294 chan_tab_ptr[i] = ctp;
295 break;
296 }
297 }
298 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
299
300 if (ctp != NULL) {
301 memset(ctp, 0, sizeof(chan_tab_t));
302 ctp->chan_index = chan = i;
303 dcp = DDMA_CHANNEL_BASE;
304 dcp += (0x0100 * chan);
305 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
306 cp = (au1x_dma_chan_t *)dcp;
307 ctp->chan_src = stp;
308 ctp->chan_dest = dtp;
309 ctp->chan_callback = callback;
310 ctp->chan_callparam = callparam;
311
312 /* Initialize channel configuration.
313 */
314 i = 0;
315 if (stp->dev_intlevel)
316 i |= DDMA_CFG_SED;
317 if (stp->dev_intpolarity)
318 i |= DDMA_CFG_SP;
319 if (dtp->dev_intlevel)
320 i |= DDMA_CFG_DED;
321 if (dtp->dev_intpolarity)
322 i |= DDMA_CFG_DP;
323 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
324 (dtp->dev_flags & DEV_FLAGS_SYNC))
325 i |= DDMA_CFG_SYNC;
326 cp->ddma_cfg = i;
327 au_sync();
328
329 /* Return a non-zero value that can be used to
330 * find the channel information in subsequent
331 * operations.
332 */
333 rv = (u32)(&chan_tab_ptr[chan]);
334 }
335 else {
336 /* Release devices */
337 stp->dev_flags &= ~DEV_FLAGS_INUSE;
338 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
339 }
340 }
341 return rv;
342 }
343 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
344
345 /* Set the device width if source or destination is a FIFO.
346 * Should be 8, 16, or 32 bits.
347 */
348 u32
349 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
350 {
351 u32 rv;
352 chan_tab_t *ctp;
353 dbdev_tab_t *stp, *dtp;
354
355 ctp = *((chan_tab_t **)chanid);
356 stp = ctp->chan_src;
357 dtp = ctp->chan_dest;
358 rv = 0;
359
360 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
361 rv = stp->dev_devwidth;
362 stp->dev_devwidth = bits;
363 }
364 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
365 rv = dtp->dev_devwidth;
366 dtp->dev_devwidth = bits;
367 }
368
369 return rv;
370 }
371 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
372
373 /* Allocate a descriptor ring, initializing as much as possible.
374 */
375 u32
376 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
377 {
378 int i;
379 u32 desc_base, srcid, destid;
380 u32 cmd0, cmd1, src1, dest1;
381 u32 src0, dest0;
382 chan_tab_t *ctp;
383 dbdev_tab_t *stp, *dtp;
384 au1x_ddma_desc_t *dp;
385
386 /* I guess we could check this to be within the
387 * range of the table......
388 */
389 ctp = *((chan_tab_t **)chanid);
390 stp = ctp->chan_src;
391 dtp = ctp->chan_dest;
392
393 /* The descriptors must be 32-byte aligned. There is a
394 * possibility the allocation will give us such an address,
395 * and if we try that first we are likely to not waste larger
396 * slabs of memory.
397 */
398 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
399 GFP_KERNEL|GFP_DMA);
400 if (desc_base == 0)
401 return 0;
402
403 if (desc_base & 0x1f) {
404 /* Lost....do it again, allocate extra, and round
405 * the address base.
406 */
407 kfree((const void *)desc_base);
408 i = entries * sizeof(au1x_ddma_desc_t);
409 i += (sizeof(au1x_ddma_desc_t) - 1);
410 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
411 return 0;
412
413 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
414 }
415 dp = (au1x_ddma_desc_t *)desc_base;
416
417 /* Keep track of the base descriptor.
418 */
419 ctp->chan_desc_base = dp;
420
421 /* Initialize the rings with as much information as we know.
422 */
423 srcid = stp->dev_id;
424 destid = dtp->dev_id;
425
426 cmd0 = cmd1 = src1 = dest1 = 0;
427 src0 = dest0 = 0;
428
429 cmd0 |= DSCR_CMD0_SID(srcid);
430 cmd0 |= DSCR_CMD0_DID(destid);
431 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
432 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
433
434 /* is it mem to mem transfer? */
435 if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
436 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) {
437 cmd0 |= DSCR_CMD0_MEM;
438 }
439
440 switch (stp->dev_devwidth) {
441 case 8:
442 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
443 break;
444 case 16:
445 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
446 break;
447 case 32:
448 default:
449 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
450 break;
451 }
452
453 switch (dtp->dev_devwidth) {
454 case 8:
455 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
456 break;
457 case 16:
458 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
459 break;
460 case 32:
461 default:
462 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
463 break;
464 }
465
466 /* If the device is marked as an in/out FIFO, ensure it is
467 * set non-coherent.
468 */
469 if (stp->dev_flags & DEV_FLAGS_IN)
470 cmd0 |= DSCR_CMD0_SN; /* Source in fifo */
471 if (dtp->dev_flags & DEV_FLAGS_OUT)
472 cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */
473
474 /* Set up source1. For now, assume no stride and increment.
475 * A channel attribute update can change this later.
476 */
477 switch (stp->dev_tsize) {
478 case 1:
479 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
480 break;
481 case 2:
482 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
483 break;
484 case 4:
485 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
486 break;
487 case 8:
488 default:
489 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
490 break;
491 }
492
493 /* If source input is fifo, set static address.
494 */
495 if (stp->dev_flags & DEV_FLAGS_IN) {
496 if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
497 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
498 else
499 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
500
501 }
502 if (stp->dev_physaddr)
503 src0 = stp->dev_physaddr;
504
505 /* Set up dest1. For now, assume no stride and increment.
506 * A channel attribute update can change this later.
507 */
508 switch (dtp->dev_tsize) {
509 case 1:
510 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
511 break;
512 case 2:
513 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
514 break;
515 case 4:
516 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
517 break;
518 case 8:
519 default:
520 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
521 break;
522 }
523
524 /* If destination output is fifo, set static address.
525 */
526 if (dtp->dev_flags & DEV_FLAGS_OUT) {
527 if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
528 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
529 else
530 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
531 }
532 if (dtp->dev_physaddr)
533 dest0 = dtp->dev_physaddr;
534
535 #if 0
536 printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
537 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
538 #endif
539 for (i=0; i<entries; i++) {
540 dp->dscr_cmd0 = cmd0;
541 dp->dscr_cmd1 = cmd1;
542 dp->dscr_source0 = src0;
543 dp->dscr_source1 = src1;
544 dp->dscr_dest0 = dest0;
545 dp->dscr_dest1 = dest1;
546 dp->dscr_stat = 0;
547 dp->sw_context = 0;
548 dp->sw_status = 0;
549 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
550 dp++;
551 }
552
553 /* Make last descrptor point to the first.
554 */
555 dp--;
556 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
557 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
558
559 return (u32)(ctp->chan_desc_base);
560 }
561 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
562
563 /* Put a source buffer into the DMA ring.
564 * This updates the source pointer and byte count. Normally used
565 * for memory to fifo transfers.
566 */
567 u32
568 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
569 {
570 chan_tab_t *ctp;
571 au1x_ddma_desc_t *dp;
572
573 /* I guess we could check this to be within the
574 * range of the table......
575 */
576 ctp = *((chan_tab_t **)chanid);
577
578 /* We should have multiple callers for a particular channel,
579 * an interrupt doesn't affect this pointer nor the descriptor,
580 * so no locking should be needed.
581 */
582 dp = ctp->put_ptr;
583
584 /* If the descriptor is valid, we are way ahead of the DMA
585 * engine, so just return an error condition.
586 */
587 if (dp->dscr_cmd0 & DSCR_CMD0_V) {
588 return 0;
589 }
590
591 /* Load up buffer address and byte count.
592 */
593 dp->dscr_source0 = virt_to_phys(buf);
594 dp->dscr_cmd1 = nbytes;
595 /* Check flags */
596 if (flags & DDMA_FLAGS_IE)
597 dp->dscr_cmd0 |= DSCR_CMD0_IE;
598 if (flags & DDMA_FLAGS_NOIE)
599 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
600
601 /*
602 * There is an errata on the Au1200/Au1550 parts that could result
603 * in "stale" data being DMA'd. It has to do with the snoop logic on
604 * the dache eviction buffer. NONCOHERENT_IO is on by default for
605 * these parts. If it is fixedin the future, these dma_cache_inv will
606 * just be nothing more than empty macros. See io.h.
607 * */
608 dma_cache_wback_inv((unsigned long)buf, nbytes);
609 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
610 au_sync();
611 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
612 ctp->chan_ptr->ddma_dbell = 0;
613
614 /* Get next descriptor pointer.
615 */
616 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
617
618 /* return something not zero.
619 */
620 return nbytes;
621 }
622 EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
623
624 /* Put a destination buffer into the DMA ring.
625 * This updates the destination pointer and byte count. Normally used
626 * to place an empty buffer into the ring for fifo to memory transfers.
627 */
628 u32
629 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
630 {
631 chan_tab_t *ctp;
632 au1x_ddma_desc_t *dp;
633
634 /* I guess we could check this to be within the
635 * range of the table......
636 */
637 ctp = *((chan_tab_t **)chanid);
638
639 /* We should have multiple callers for a particular channel,
640 * an interrupt doesn't affect this pointer nor the descriptor,
641 * so no locking should be needed.
642 */
643 dp = ctp->put_ptr;
644
645 /* If the descriptor is valid, we are way ahead of the DMA
646 * engine, so just return an error condition.
647 */
648 if (dp->dscr_cmd0 & DSCR_CMD0_V)
649 return 0;
650
651 /* Load up buffer address and byte count */
652
653 /* Check flags */
654 if (flags & DDMA_FLAGS_IE)
655 dp->dscr_cmd0 |= DSCR_CMD0_IE;
656 if (flags & DDMA_FLAGS_NOIE)
657 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
658
659 dp->dscr_dest0 = virt_to_phys(buf);
660 dp->dscr_cmd1 = nbytes;
661 #if 0
662 printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
663 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
664 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
665 #endif
666 /*
667 * There is an errata on the Au1200/Au1550 parts that could result in
668 * "stale" data being DMA'd. It has to do with the snoop logic on the
669 * dache eviction buffer. NONCOHERENT_IO is on by default for these
670 * parts. If it is fixedin the future, these dma_cache_inv will just
671 * be nothing more than empty macros. See io.h.
672 * */
673 dma_cache_inv((unsigned long)buf,nbytes);
674 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
675 au_sync();
676 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
677 ctp->chan_ptr->ddma_dbell = 0;
678
679 /* Get next descriptor pointer.
680 */
681 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
682
683 /* return something not zero.
684 */
685 return nbytes;
686 }
687 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
688
689 /* Get a destination buffer into the DMA ring.
690 * Normally used to get a full buffer from the ring during fifo
691 * to memory transfers. This does not set the valid bit, you will
692 * have to put another destination buffer to keep the DMA going.
693 */
694 u32
695 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
696 {
697 chan_tab_t *ctp;
698 au1x_ddma_desc_t *dp;
699 u32 rv;
700
701 /* I guess we could check this to be within the
702 * range of the table......
703 */
704 ctp = *((chan_tab_t **)chanid);
705
706 /* We should have multiple callers for a particular channel,
707 * an interrupt doesn't affect this pointer nor the descriptor,
708 * so no locking should be needed.
709 */
710 dp = ctp->get_ptr;
711
712 /* If the descriptor is valid, we are way ahead of the DMA
713 * engine, so just return an error condition.
714 */
715 if (dp->dscr_cmd0 & DSCR_CMD0_V)
716 return 0;
717
718 /* Return buffer address and byte count.
719 */
720 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
721 *nbytes = dp->dscr_cmd1;
722 rv = dp->dscr_stat;
723
724 /* Get next descriptor pointer.
725 */
726 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
727
728 /* return something not zero.
729 */
730 return rv;
731 }
732
733 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
734
735 void
736 au1xxx_dbdma_stop(u32 chanid)
737 {
738 chan_tab_t *ctp;
739 au1x_dma_chan_t *cp;
740 int halt_timeout = 0;
741
742 ctp = *((chan_tab_t **)chanid);
743
744 cp = ctp->chan_ptr;
745 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
746 au_sync();
747 while (!(cp->ddma_stat & DDMA_STAT_H)) {
748 udelay(1);
749 halt_timeout++;
750 if (halt_timeout > 100) {
751 printk("warning: DMA channel won't halt\n");
752 break;
753 }
754 }
755 /* clear current desc valid and doorbell */
756 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
757 au_sync();
758 }
759 EXPORT_SYMBOL(au1xxx_dbdma_stop);
760
761 /* Start using the current descriptor pointer. If the dbdma encounters
762 * a not valid descriptor, it will stop. In this case, we can just
763 * continue by adding a buffer to the list and starting again.
764 */
765 void
766 au1xxx_dbdma_start(u32 chanid)
767 {
768 chan_tab_t *ctp;
769 au1x_dma_chan_t *cp;
770
771 ctp = *((chan_tab_t **)chanid);
772 cp = ctp->chan_ptr;
773 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
774 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
775 au_sync();
776 cp->ddma_dbell = 0;
777 au_sync();
778 }
779 EXPORT_SYMBOL(au1xxx_dbdma_start);
780
781 void
782 au1xxx_dbdma_reset(u32 chanid)
783 {
784 chan_tab_t *ctp;
785 au1x_ddma_desc_t *dp;
786
787 au1xxx_dbdma_stop(chanid);
788
789 ctp = *((chan_tab_t **)chanid);
790 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
791
792 /* Run through the descriptors and reset the valid indicator.
793 */
794 dp = ctp->chan_desc_base;
795
796 do {
797 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
798 /* reset our SW status -- this is used to determine
799 * if a descriptor is in use by upper level SW. Since
800 * posting can reset 'V' bit.
801 */
802 dp->sw_status = 0;
803 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
804 } while (dp != ctp->chan_desc_base);
805 }
806 EXPORT_SYMBOL(au1xxx_dbdma_reset);
807
808 u32
809 au1xxx_get_dma_residue(u32 chanid)
810 {
811 chan_tab_t *ctp;
812 au1x_dma_chan_t *cp;
813 u32 rv;
814
815 ctp = *((chan_tab_t **)chanid);
816 cp = ctp->chan_ptr;
817
818 /* This is only valid if the channel is stopped.
819 */
820 rv = cp->ddma_bytecnt;
821 au_sync();
822
823 return rv;
824 }
825
826 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
827
828 void
829 au1xxx_dbdma_chan_free(u32 chanid)
830 {
831 chan_tab_t *ctp;
832 dbdev_tab_t *stp, *dtp;
833
834 ctp = *((chan_tab_t **)chanid);
835 stp = ctp->chan_src;
836 dtp = ctp->chan_dest;
837
838 au1xxx_dbdma_stop(chanid);
839
840 kfree((void *)ctp->chan_desc_base);
841
842 stp->dev_flags &= ~DEV_FLAGS_INUSE;
843 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
844 chan_tab_ptr[ctp->chan_index] = NULL;
845
846 kfree(ctp);
847 }
848 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
849
850 static irqreturn_t
851 dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
852 {
853 u32 intstat;
854 u32 chan_index;
855 chan_tab_t *ctp;
856 au1x_ddma_desc_t *dp;
857 au1x_dma_chan_t *cp;
858
859 intstat = dbdma_gptr->ddma_intstat;
860 au_sync();
861 chan_index = au_ffs(intstat) - 1;
862
863 ctp = chan_tab_ptr[chan_index];
864 cp = ctp->chan_ptr;
865 dp = ctp->cur_ptr;
866
867 /* Reset interrupt.
868 */
869 cp->ddma_irq = 0;
870 au_sync();
871
872 if (ctp->chan_callback)
873 (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
874
875 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
876 return IRQ_RETVAL(1);
877 }
878
879 static void au1xxx_dbdma_init(void)
880 {
881 int irq_nr;
882
883 dbdma_gptr->ddma_config = 0;
884 dbdma_gptr->ddma_throttle = 0;
885 dbdma_gptr->ddma_inten = 0xffff;
886 au_sync();
887
888 #if defined(CONFIG_SOC_AU1550)
889 irq_nr = AU1550_DDMA_INT;
890 #elif defined(CONFIG_SOC_AU1200)
891 irq_nr = AU1200_DDMA_INT;
892 #else
893 #error Unknown Au1x00 SOC
894 #endif
895
896 if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
897 "Au1xxx dbdma", (void *)dbdma_gptr))
898 printk("Can't get 1550 dbdma irq");
899 }
900
901 void
902 au1xxx_dbdma_dump(u32 chanid)
903 {
904 chan_tab_t *ctp;
905 au1x_ddma_desc_t *dp;
906 dbdev_tab_t *stp, *dtp;
907 au1x_dma_chan_t *cp;
908 u32 i = 0;
909
910 ctp = *((chan_tab_t **)chanid);
911 stp = ctp->chan_src;
912 dtp = ctp->chan_dest;
913 cp = ctp->chan_ptr;
914
915 printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
916 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
917 printk("desc base %x, get %x, put %x, cur %x\n",
918 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
919 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
920
921 printk("dbdma chan %x\n", (u32)cp);
922 printk("cfg %08x, desptr %08x, statptr %08x\n",
923 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
924 printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
925 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
926
927
928 /* Run through the descriptors
929 */
930 dp = ctp->chan_desc_base;
931
932 do {
933 printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
934 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
935 printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
936 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
937 printk("stat %08x, nxtptr %08x\n",
938 dp->dscr_stat, dp->dscr_nxtptr);
939 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
940 } while (dp != ctp->chan_desc_base);
941 }
942
943 /* Put a descriptor into the DMA ring.
944 * This updates the source/destination pointers and byte count.
945 */
946 u32
947 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
948 {
949 chan_tab_t *ctp;
950 au1x_ddma_desc_t *dp;
951 u32 nbytes=0;
952
953 /* I guess we could check this to be within the
954 * range of the table......
955 */
956 ctp = *((chan_tab_t **)chanid);
957
958 /* We should have multiple callers for a particular channel,
959 * an interrupt doesn't affect this pointer nor the descriptor,
960 * so no locking should be needed.
961 */
962 dp = ctp->put_ptr;
963
964 /* If the descriptor is valid, we are way ahead of the DMA
965 * engine, so just return an error condition.
966 */
967 if (dp->dscr_cmd0 & DSCR_CMD0_V)
968 return 0;
969
970 /* Load up buffer addresses and byte count.
971 */
972 dp->dscr_dest0 = dscr->dscr_dest0;
973 dp->dscr_source0 = dscr->dscr_source0;
974 dp->dscr_dest1 = dscr->dscr_dest1;
975 dp->dscr_source1 = dscr->dscr_source1;
976 dp->dscr_cmd1 = dscr->dscr_cmd1;
977 nbytes = dscr->dscr_cmd1;
978 /* Allow the caller to specifiy if an interrupt is generated */
979 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
980 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
981 ctp->chan_ptr->ddma_dbell = 0;
982
983 /* Get next descriptor pointer.
984 */
985 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
986
987 /* return something not zero.
988 */
989 return nbytes;
990 }
991
992 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
993
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