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[ARM] fix section mismatch warning in board-sam9260
[linux-2.6/sactl.git] / drivers / net / 8139cp.c
blob12c8453f44bce3e337dc3a3f8d440153ee02061c
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.3"
52 #define DRV_RELDATE "Mar 22, 2004"
53
54
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/compiler.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/delay.h>
65 #include <linux/ethtool.h>
66 #include <linux/mii.h>
67 #include <linux/if_vlan.h>
68 #include <linux/crc32.h>
69 #include <linux/in.h>
70 #include <linux/ip.h>
71 #include <linux/tcp.h>
72 #include <linux/udp.h>
73 #include <linux/cache.h>
74 #include <asm/io.h>
75 #include <asm/irq.h>
76 #include <asm/uaccess.h>
77
78 /* VLAN tagging feature enable/disable */
79 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
80 #define CP_VLAN_TAG_USED 1
81 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
82 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
83 #else
84 #define CP_VLAN_TAG_USED 0
85 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
86 do { (tx_desc)->opts2 = 0; } while (0)
87 #endif
88
89 /* These identify the driver base version and may not be removed. */
90 static char version[] =
91 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
92
93 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
94 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
95 MODULE_VERSION(DRV_VERSION);
96 MODULE_LICENSE("GPL");
97
98 static int debug = -1;
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
101
102 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
103 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
104 static int multicast_filter_limit = 32;
105 module_param(multicast_filter_limit, int, 0);
106 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
107
108 #define PFX DRV_NAME ": "
109
110 #ifndef TRUE
111 #define FALSE 0
112 #define TRUE (!FALSE)
113 #endif
114
115 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
116 NETIF_MSG_PROBE | \
117 NETIF_MSG_LINK)
118 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
119 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
120 #define CP_REGS_SIZE (0xff + 1)
121 #define CP_REGS_VER 1 /* version 1 */
122 #define CP_RX_RING_SIZE 64
123 #define CP_TX_RING_SIZE 64
124 #define CP_RING_BYTES \
125 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
126 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
127 CP_STATS_SIZE)
128 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
129 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
130 #define TX_BUFFS_AVAIL(CP) \
131 (((CP)->tx_tail <= (CP)->tx_head) ? \
132 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
133 (CP)->tx_tail - (CP)->tx_head - 1)
134
135 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
136 #define RX_OFFSET 2
137 #define CP_INTERNAL_PHY 32
138
139 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
140 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
141 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
142 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
143 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
144
145 /* Time in jiffies before concluding the transmitter is hung. */
146 #define TX_TIMEOUT (6*HZ)
147
148 /* hardware minimum and maximum for a single frame's data payload */
149 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
150 #define CP_MAX_MTU 4096
151
152 enum {
153 /* NIC register offsets */
154 MAC0 = 0x00, /* Ethernet hardware address. */
155 MAR0 = 0x08, /* Multicast filter. */
156 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
157 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
158 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
159 Cmd = 0x37, /* Command register */
160 IntrMask = 0x3C, /* Interrupt mask */
161 IntrStatus = 0x3E, /* Interrupt status */
162 TxConfig = 0x40, /* Tx configuration */
163 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
164 RxConfig = 0x44, /* Rx configuration */
165 RxMissed = 0x4C, /* 24 bits valid, write clears */
166 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
167 Config1 = 0x52, /* Config1 */
168 Config3 = 0x59, /* Config3 */
169 Config4 = 0x5A, /* Config4 */
170 MultiIntr = 0x5C, /* Multiple interrupt select */
171 BasicModeCtrl = 0x62, /* MII BMCR */
172 BasicModeStatus = 0x64, /* MII BMSR */
173 NWayAdvert = 0x66, /* MII ADVERTISE */
174 NWayLPAR = 0x68, /* MII LPA */
175 NWayExpansion = 0x6A, /* MII Expansion */
176 Config5 = 0xD8, /* Config5 */
177 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
178 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
179 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
180 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
181 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
182 TxThresh = 0xEC, /* Early Tx threshold */
183 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
184 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
185
186 /* Tx and Rx status descriptors */
187 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
188 RingEnd = (1 << 30), /* End of descriptor ring */
189 FirstFrag = (1 << 29), /* First segment of a packet */
190 LastFrag = (1 << 28), /* Final segment of a packet */
191 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
192 MSSShift = 16, /* MSS value position */
193 MSSMask = 0xfff, /* MSS value: 11 bits */
194 TxError = (1 << 23), /* Tx error summary */
195 RxError = (1 << 20), /* Rx error summary */
196 IPCS = (1 << 18), /* Calculate IP checksum */
197 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
198 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
199 TxVlanTag = (1 << 17), /* Add VLAN tag */
200 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
201 IPFail = (1 << 15), /* IP checksum failed */
202 UDPFail = (1 << 14), /* UDP/IP checksum failed */
203 TCPFail = (1 << 13), /* TCP/IP checksum failed */
204 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
205 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
206 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
207 RxProtoTCP = 1,
208 RxProtoUDP = 2,
209 RxProtoIP = 3,
210 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
211 TxOWC = (1 << 22), /* Tx Out-of-window collision */
212 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
213 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
214 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
215 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
216 RxErrFrame = (1 << 27), /* Rx frame alignment error */
217 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
218 RxErrCRC = (1 << 18), /* Rx CRC error */
219 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
220 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
221 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
222
223 /* StatsAddr register */
224 DumpStats = (1 << 3), /* Begin stats dump */
225
226 /* RxConfig register */
227 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
228 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
229 AcceptErr = 0x20, /* Accept packets with CRC errors */
230 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
231 AcceptBroadcast = 0x08, /* Accept broadcast packets */
232 AcceptMulticast = 0x04, /* Accept multicast packets */
233 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
234 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
235
236 /* IntrMask / IntrStatus registers */
237 PciErr = (1 << 15), /* System error on the PCI bus */
238 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
239 LenChg = (1 << 13), /* Cable length change */
240 SWInt = (1 << 8), /* Software-requested interrupt */
241 TxEmpty = (1 << 7), /* No Tx descriptors available */
242 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
243 LinkChg = (1 << 5), /* Packet underrun, or link change */
244 RxEmpty = (1 << 4), /* No Rx descriptors available */
245 TxErr = (1 << 3), /* Tx error */
246 TxOK = (1 << 2), /* Tx packet sent */
247 RxErr = (1 << 1), /* Rx error */
248 RxOK = (1 << 0), /* Rx packet received */
249 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
250 but hardware likes to raise it */
251
252 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
253 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
254 RxErr | RxOK | IntrResvd,
255
256 /* C mode command register */
257 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
258 RxOn = (1 << 3), /* Rx mode enable */
259 TxOn = (1 << 2), /* Tx mode enable */
260
261 /* C+ mode command register */
262 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
263 RxChkSum = (1 << 5), /* Rx checksum offload enable */
264 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
265 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
266 CpRxOn = (1 << 1), /* Rx mode enable */
267 CpTxOn = (1 << 0), /* Tx mode enable */
268
269 /* Cfg9436 EEPROM control register */
270 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
271 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
272
273 /* TxConfig register */
274 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
275 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
276
277 /* Early Tx Threshold register */
278 TxThreshMask = 0x3f, /* Mask bits 5-0 */
279 TxThreshMax = 2048, /* Max early Tx threshold */
280
281 /* Config1 register */
282 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
283 LWACT = (1 << 4), /* LWAKE active mode */
284 PMEnable = (1 << 0), /* Enable various PM features of chip */
285
286 /* Config3 register */
287 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
288 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
289 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
290
291 /* Config4 register */
292 LWPTN = (1 << 1), /* LWAKE Pattern */
293 LWPME = (1 << 4), /* LANWAKE vs PMEB */
294
295 /* Config5 register */
296 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
297 MWF = (1 << 5), /* Accept Multicast wakeup frame */
298 UWF = (1 << 4), /* Accept Unicast wakeup frame */
299 LANWake = (1 << 1), /* Enable LANWake signal */
300 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
301
302 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
303 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
304 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
305 };
306
307 static const unsigned int cp_rx_config =
308 (RX_FIFO_THRESH << RxCfgFIFOShift) |
309 (RX_DMA_BURST << RxCfgDMAShift);
310
311 struct cp_desc {
312 u32 opts1;
313 u32 opts2;
314 u64 addr;
315 };
316
317 struct cp_dma_stats {
318 u64 tx_ok;
319 u64 rx_ok;
320 u64 tx_err;
321 u32 rx_err;
322 u16 rx_fifo;
323 u16 frame_align;
324 u32 tx_ok_1col;
325 u32 tx_ok_mcol;
326 u64 rx_ok_phys;
327 u64 rx_ok_bcast;
328 u32 rx_ok_mcast;
329 u16 tx_abort;
330 u16 tx_underrun;
331 } __attribute__((packed));
332
333 struct cp_extra_stats {
334 unsigned long rx_frags;
335 };
336
337 struct cp_private {
338 void __iomem *regs;
339 struct net_device *dev;
340 spinlock_t lock;
341 u32 msg_enable;
342
343 struct pci_dev *pdev;
344 u32 rx_config;
345 u16 cpcmd;
346
347 struct net_device_stats net_stats;
348 struct cp_extra_stats cp_stats;
349
350 unsigned rx_head ____cacheline_aligned;
351 unsigned rx_tail;
352 struct cp_desc *rx_ring;
353 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
354
355 unsigned tx_head ____cacheline_aligned;
356 unsigned tx_tail;
357 struct cp_desc *tx_ring;
358 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
359
360 unsigned rx_buf_sz;
361 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
362
363 #if CP_VLAN_TAG_USED
364 struct vlan_group *vlgrp;
365 #endif
366 dma_addr_t ring_dma;
367
368 struct mii_if_info mii_if;
369 };
370
371 #define cpr8(reg) readb(cp->regs + (reg))
372 #define cpr16(reg) readw(cp->regs + (reg))
373 #define cpr32(reg) readl(cp->regs + (reg))
374 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
375 #define cpw16(reg,val) writew((val), cp->regs + (reg))
376 #define cpw32(reg,val) writel((val), cp->regs + (reg))
377 #define cpw8_f(reg,val) do { \
378 writeb((val), cp->regs + (reg)); \
379 readb(cp->regs + (reg)); \
380 } while (0)
381 #define cpw16_f(reg,val) do { \
382 writew((val), cp->regs + (reg)); \
383 readw(cp->regs + (reg)); \
384 } while (0)
385 #define cpw32_f(reg,val) do { \
386 writel((val), cp->regs + (reg)); \
387 readl(cp->regs + (reg)); \
388 } while (0)
389
390
391 static void __cp_set_rx_mode (struct net_device *dev);
392 static void cp_tx (struct cp_private *cp);
393 static void cp_clean_rings (struct cp_private *cp);
394 #ifdef CONFIG_NET_POLL_CONTROLLER
395 static void cp_poll_controller(struct net_device *dev);
396 #endif
397 static int cp_get_eeprom_len(struct net_device *dev);
398 static int cp_get_eeprom(struct net_device *dev,
399 struct ethtool_eeprom *eeprom, u8 *data);
400 static int cp_set_eeprom(struct net_device *dev,
401 struct ethtool_eeprom *eeprom, u8 *data);
402
403 static struct pci_device_id cp_pci_tbl[] = {
404 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
405 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
406 { },
407 };
408 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
409
410 static struct {
411 const char str[ETH_GSTRING_LEN];
412 } ethtool_stats_keys[] = {
413 { "tx_ok" },
414 { "rx_ok" },
415 { "tx_err" },
416 { "rx_err" },
417 { "rx_fifo" },
418 { "frame_align" },
419 { "tx_ok_1col" },
420 { "tx_ok_mcol" },
421 { "rx_ok_phys" },
422 { "rx_ok_bcast" },
423 { "rx_ok_mcast" },
424 { "tx_abort" },
425 { "tx_underrun" },
426 { "rx_frags" },
427 };
428
429
430 #if CP_VLAN_TAG_USED
431 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
432 {
433 struct cp_private *cp = netdev_priv(dev);
434 unsigned long flags;
435
436 spin_lock_irqsave(&cp->lock, flags);
437 cp->vlgrp = grp;
438 cp->cpcmd |= RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
441 }
442
443 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
444 {
445 struct cp_private *cp = netdev_priv(dev);
446 unsigned long flags;
447
448 spin_lock_irqsave(&cp->lock, flags);
449 cp->cpcmd &= ~RxVlanOn;
450 cpw16(CpCmd, cp->cpcmd);
451 vlan_group_set_device(cp->vlgrp, vid, NULL);
452 spin_unlock_irqrestore(&cp->lock, flags);
453 }
454 #endif /* CP_VLAN_TAG_USED */
455
456 static inline void cp_set_rxbufsize (struct cp_private *cp)
457 {
458 unsigned int mtu = cp->dev->mtu;
459
460 if (mtu > ETH_DATA_LEN)
461 /* MTU + ethernet header + FCS + optional VLAN tag */
462 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
463 else
464 cp->rx_buf_sz = PKT_BUF_SZ;
465 }
466
467 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
468 struct cp_desc *desc)
469 {
470 skb->protocol = eth_type_trans (skb, cp->dev);
471
472 cp->net_stats.rx_packets++;
473 cp->net_stats.rx_bytes += skb->len;
474 cp->dev->last_rx = jiffies;
475
476 #if CP_VLAN_TAG_USED
477 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
478 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
479 be16_to_cpu(desc->opts2 & 0xffff));
480 } else
481 #endif
482 netif_receive_skb(skb);
483 }
484
485 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
486 u32 status, u32 len)
487 {
488 if (netif_msg_rx_err (cp))
489 printk (KERN_DEBUG
490 "%s: rx err, slot %d status 0x%x len %d\n",
491 cp->dev->name, rx_tail, status, len);
492 cp->net_stats.rx_errors++;
493 if (status & RxErrFrame)
494 cp->net_stats.rx_frame_errors++;
495 if (status & RxErrCRC)
496 cp->net_stats.rx_crc_errors++;
497 if ((status & RxErrRunt) || (status & RxErrLong))
498 cp->net_stats.rx_length_errors++;
499 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
500 cp->net_stats.rx_length_errors++;
501 if (status & RxErrFIFO)
502 cp->net_stats.rx_fifo_errors++;
503 }
504
505 static inline unsigned int cp_rx_csum_ok (u32 status)
506 {
507 unsigned int protocol = (status >> 16) & 0x3;
508
509 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
510 return 1;
511 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
512 return 1;
513 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
514 return 1;
515 return 0;
516 }
517
518 static int cp_rx_poll (struct net_device *dev, int *budget)
519 {
520 struct cp_private *cp = netdev_priv(dev);
521 unsigned rx_tail = cp->rx_tail;
522 unsigned rx_work = dev->quota;
523 unsigned rx;
524
525 rx_status_loop:
526 rx = 0;
527 cpw16(IntrStatus, cp_rx_intr_mask);
528
529 while (1) {
530 u32 status, len;
531 dma_addr_t mapping;
532 struct sk_buff *skb, *new_skb;
533 struct cp_desc *desc;
534 unsigned buflen;
535
536 skb = cp->rx_skb[rx_tail];
537 BUG_ON(!skb);
538
539 desc = &cp->rx_ring[rx_tail];
540 status = le32_to_cpu(desc->opts1);
541 if (status & DescOwn)
542 break;
543
544 len = (status & 0x1fff) - 4;
545 mapping = le64_to_cpu(desc->addr);
546
547 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
548 /* we don't support incoming fragmented frames.
549 * instead, we attempt to ensure that the
550 * pre-allocated RX skbs are properly sized such
551 * that RX fragments are never encountered
552 */
553 cp_rx_err_acct(cp, rx_tail, status, len);
554 cp->net_stats.rx_dropped++;
555 cp->cp_stats.rx_frags++;
556 goto rx_next;
557 }
558
559 if (status & (RxError | RxErrFIFO)) {
560 cp_rx_err_acct(cp, rx_tail, status, len);
561 goto rx_next;
562 }
563
564 if (netif_msg_rx_status(cp))
565 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
566 dev->name, rx_tail, status, len);
567
568 buflen = cp->rx_buf_sz + RX_OFFSET;
569 new_skb = dev_alloc_skb (buflen);
570 if (!new_skb) {
571 cp->net_stats.rx_dropped++;
572 goto rx_next;
573 }
574
575 skb_reserve(new_skb, RX_OFFSET);
576 new_skb->dev = dev;
577
578 pci_unmap_single(cp->pdev, mapping,
579 buflen, PCI_DMA_FROMDEVICE);
580
581 /* Handle checksum offloading for incoming packets. */
582 if (cp_rx_csum_ok(status))
583 skb->ip_summed = CHECKSUM_UNNECESSARY;
584 else
585 skb->ip_summed = CHECKSUM_NONE;
586
587 skb_put(skb, len);
588
589 mapping = pci_map_single(cp->pdev, new_skb->data, buflen,
590 PCI_DMA_FROMDEVICE);
591 cp->rx_skb[rx_tail] = new_skb;
592
593 cp_rx_skb(cp, skb, desc);
594 rx++;
595
596 rx_next:
597 cp->rx_ring[rx_tail].opts2 = 0;
598 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
599 if (rx_tail == (CP_RX_RING_SIZE - 1))
600 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
601 cp->rx_buf_sz);
602 else
603 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
604 rx_tail = NEXT_RX(rx_tail);
605
606 if (!rx_work--)
607 break;
608 }
609
610 cp->rx_tail = rx_tail;
611
612 dev->quota -= rx;
613 *budget -= rx;
614
615 /* if we did not reach work limit, then we're done with
616 * this round of polling
617 */
618 if (rx_work) {
619 unsigned long flags;
620
621 if (cpr16(IntrStatus) & cp_rx_intr_mask)
622 goto rx_status_loop;
623
624 local_irq_save(flags);
625 cpw16_f(IntrMask, cp_intr_mask);
626 __netif_rx_complete(dev);
627 local_irq_restore(flags);
628
629 return 0; /* done */
630 }
631
632 return 1; /* not done */
633 }
634
635 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
636 {
637 struct net_device *dev = dev_instance;
638 struct cp_private *cp;
639 u16 status;
640
641 if (unlikely(dev == NULL))
642 return IRQ_NONE;
643 cp = netdev_priv(dev);
644
645 status = cpr16(IntrStatus);
646 if (!status || (status == 0xFFFF))
647 return IRQ_NONE;
648
649 if (netif_msg_intr(cp))
650 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
651 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
652
653 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
654
655 spin_lock(&cp->lock);
656
657 /* close possible race's with dev_close */
658 if (unlikely(!netif_running(dev))) {
659 cpw16(IntrMask, 0);
660 spin_unlock(&cp->lock);
661 return IRQ_HANDLED;
662 }
663
664 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
665 if (netif_rx_schedule_prep(dev)) {
666 cpw16_f(IntrMask, cp_norx_intr_mask);
667 __netif_rx_schedule(dev);
668 }
669
670 if (status & (TxOK | TxErr | TxEmpty | SWInt))
671 cp_tx(cp);
672 if (status & LinkChg)
673 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
674
675 spin_unlock(&cp->lock);
676
677 if (status & PciErr) {
678 u16 pci_status;
679
680 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
681 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
682 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
683 dev->name, status, pci_status);
684
685 /* TODO: reset hardware */
686 }
687
688 return IRQ_HANDLED;
689 }
690
691 #ifdef CONFIG_NET_POLL_CONTROLLER
692 /*
693 * Polling receive - used by netconsole and other diagnostic tools
694 * to allow network i/o with interrupts disabled.
695 */
696 static void cp_poll_controller(struct net_device *dev)
697 {
698 disable_irq(dev->irq);
699 cp_interrupt(dev->irq, dev);
700 enable_irq(dev->irq);
701 }
702 #endif
703
704 static void cp_tx (struct cp_private *cp)
705 {
706 unsigned tx_head = cp->tx_head;
707 unsigned tx_tail = cp->tx_tail;
708
709 while (tx_tail != tx_head) {
710 struct cp_desc *txd = cp->tx_ring + tx_tail;
711 struct sk_buff *skb;
712 u32 status;
713
714 rmb();
715 status = le32_to_cpu(txd->opts1);
716 if (status & DescOwn)
717 break;
718
719 skb = cp->tx_skb[tx_tail];
720 BUG_ON(!skb);
721
722 pci_unmap_single(cp->pdev, le64_to_cpu(txd->addr),
723 le32_to_cpu(txd->opts1) & 0xffff,
724 PCI_DMA_TODEVICE);
725
726 if (status & LastFrag) {
727 if (status & (TxError | TxFIFOUnder)) {
728 if (netif_msg_tx_err(cp))
729 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
730 cp->dev->name, status);
731 cp->net_stats.tx_errors++;
732 if (status & TxOWC)
733 cp->net_stats.tx_window_errors++;
734 if (status & TxMaxCol)
735 cp->net_stats.tx_aborted_errors++;
736 if (status & TxLinkFail)
737 cp->net_stats.tx_carrier_errors++;
738 if (status & TxFIFOUnder)
739 cp->net_stats.tx_fifo_errors++;
740 } else {
741 cp->net_stats.collisions +=
742 ((status >> TxColCntShift) & TxColCntMask);
743 cp->net_stats.tx_packets++;
744 cp->net_stats.tx_bytes += skb->len;
745 if (netif_msg_tx_done(cp))
746 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
747 }
748 dev_kfree_skb_irq(skb);
749 }
750
751 cp->tx_skb[tx_tail] = NULL;
752
753 tx_tail = NEXT_TX(tx_tail);
754 }
755
756 cp->tx_tail = tx_tail;
757
758 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
759 netif_wake_queue(cp->dev);
760 }
761
762 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
763 {
764 struct cp_private *cp = netdev_priv(dev);
765 unsigned entry;
766 u32 eor, flags;
767 unsigned long intr_flags;
768 #if CP_VLAN_TAG_USED
769 u32 vlan_tag = 0;
770 #endif
771 int mss = 0;
772
773 spin_lock_irqsave(&cp->lock, intr_flags);
774
775 /* This is a hard error, log it. */
776 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
777 netif_stop_queue(dev);
778 spin_unlock_irqrestore(&cp->lock, intr_flags);
779 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
780 dev->name);
781 return 1;
782 }
783
784 #if CP_VLAN_TAG_USED
785 if (cp->vlgrp && vlan_tx_tag_present(skb))
786 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
787 #endif
788
789 entry = cp->tx_head;
790 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
791 if (dev->features & NETIF_F_TSO)
792 mss = skb_shinfo(skb)->gso_size;
793
794 if (skb_shinfo(skb)->nr_frags == 0) {
795 struct cp_desc *txd = &cp->tx_ring[entry];
796 u32 len;
797 dma_addr_t mapping;
798
799 len = skb->len;
800 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
801 CP_VLAN_TX_TAG(txd, vlan_tag);
802 txd->addr = cpu_to_le64(mapping);
803 wmb();
804
805 flags = eor | len | DescOwn | FirstFrag | LastFrag;
806
807 if (mss)
808 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
809 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
810 const struct iphdr *ip = skb->nh.iph;
811 if (ip->protocol == IPPROTO_TCP)
812 flags |= IPCS | TCPCS;
813 else if (ip->protocol == IPPROTO_UDP)
814 flags |= IPCS | UDPCS;
815 else
816 WARN_ON(1); /* we need a WARN() */
817 }
818
819 txd->opts1 = cpu_to_le32(flags);
820 wmb();
821
822 cp->tx_skb[entry] = skb;
823 entry = NEXT_TX(entry);
824 } else {
825 struct cp_desc *txd;
826 u32 first_len, first_eor;
827 dma_addr_t first_mapping;
828 int frag, first_entry = entry;
829 const struct iphdr *ip = skb->nh.iph;
830
831 /* We must give this initial chunk to the device last.
832 * Otherwise we could race with the device.
833 */
834 first_eor = eor;
835 first_len = skb_headlen(skb);
836 first_mapping = pci_map_single(cp->pdev, skb->data,
837 first_len, PCI_DMA_TODEVICE);
838 cp->tx_skb[entry] = skb;
839 entry = NEXT_TX(entry);
840
841 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
842 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
843 u32 len;
844 u32 ctrl;
845 dma_addr_t mapping;
846
847 len = this_frag->size;
848 mapping = pci_map_single(cp->pdev,
849 ((void *) page_address(this_frag->page) +
850 this_frag->page_offset),
851 len, PCI_DMA_TODEVICE);
852 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
853
854 ctrl = eor | len | DescOwn;
855
856 if (mss)
857 ctrl |= LargeSend |
858 ((mss & MSSMask) << MSSShift);
859 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
860 if (ip->protocol == IPPROTO_TCP)
861 ctrl |= IPCS | TCPCS;
862 else if (ip->protocol == IPPROTO_UDP)
863 ctrl |= IPCS | UDPCS;
864 else
865 BUG();
866 }
867
868 if (frag == skb_shinfo(skb)->nr_frags - 1)
869 ctrl |= LastFrag;
870
871 txd = &cp->tx_ring[entry];
872 CP_VLAN_TX_TAG(txd, vlan_tag);
873 txd->addr = cpu_to_le64(mapping);
874 wmb();
875
876 txd->opts1 = cpu_to_le32(ctrl);
877 wmb();
878
879 cp->tx_skb[entry] = skb;
880 entry = NEXT_TX(entry);
881 }
882
883 txd = &cp->tx_ring[first_entry];
884 CP_VLAN_TX_TAG(txd, vlan_tag);
885 txd->addr = cpu_to_le64(first_mapping);
886 wmb();
887
888 if (skb->ip_summed == CHECKSUM_PARTIAL) {
889 if (ip->protocol == IPPROTO_TCP)
890 txd->opts1 = cpu_to_le32(first_eor | first_len |
891 FirstFrag | DescOwn |
892 IPCS | TCPCS);
893 else if (ip->protocol == IPPROTO_UDP)
894 txd->opts1 = cpu_to_le32(first_eor | first_len |
895 FirstFrag | DescOwn |
896 IPCS | UDPCS);
897 else
898 BUG();
899 } else
900 txd->opts1 = cpu_to_le32(first_eor | first_len |
901 FirstFrag | DescOwn);
902 wmb();
903 }
904 cp->tx_head = entry;
905 if (netif_msg_tx_queued(cp))
906 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
907 dev->name, entry, skb->len);
908 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
909 netif_stop_queue(dev);
910
911 spin_unlock_irqrestore(&cp->lock, intr_flags);
912
913 cpw8(TxPoll, NormalTxPoll);
914 dev->trans_start = jiffies;
915
916 return 0;
917 }
918
919 /* Set or clear the multicast filter for this adaptor.
920 This routine is not state sensitive and need not be SMP locked. */
921
922 static void __cp_set_rx_mode (struct net_device *dev)
923 {
924 struct cp_private *cp = netdev_priv(dev);
925 u32 mc_filter[2]; /* Multicast hash filter */
926 int i, rx_mode;
927 u32 tmp;
928
929 /* Note: do not reorder, GCC is clever about common statements. */
930 if (dev->flags & IFF_PROMISC) {
931 /* Unconditionally log net taps. */
932 rx_mode =
933 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
934 AcceptAllPhys;
935 mc_filter[1] = mc_filter[0] = 0xffffffff;
936 } else if ((dev->mc_count > multicast_filter_limit)
937 || (dev->flags & IFF_ALLMULTI)) {
938 /* Too many to filter perfectly -- accept all multicasts. */
939 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
940 mc_filter[1] = mc_filter[0] = 0xffffffff;
941 } else {
942 struct dev_mc_list *mclist;
943 rx_mode = AcceptBroadcast | AcceptMyPhys;
944 mc_filter[1] = mc_filter[0] = 0;
945 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
946 i++, mclist = mclist->next) {
947 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
948
949 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
950 rx_mode |= AcceptMulticast;
951 }
952 }
953
954 /* We can safely update without stopping the chip. */
955 tmp = cp_rx_config | rx_mode;
956 if (cp->rx_config != tmp) {
957 cpw32_f (RxConfig, tmp);
958 cp->rx_config = tmp;
959 }
960 cpw32_f (MAR0 + 0, mc_filter[0]);
961 cpw32_f (MAR0 + 4, mc_filter[1]);
962 }
963
964 static void cp_set_rx_mode (struct net_device *dev)
965 {
966 unsigned long flags;
967 struct cp_private *cp = netdev_priv(dev);
968
969 spin_lock_irqsave (&cp->lock, flags);
970 __cp_set_rx_mode(dev);
971 spin_unlock_irqrestore (&cp->lock, flags);
972 }
973
974 static void __cp_get_stats(struct cp_private *cp)
975 {
976 /* only lower 24 bits valid; write any value to clear */
977 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
978 cpw32 (RxMissed, 0);
979 }
980
981 static struct net_device_stats *cp_get_stats(struct net_device *dev)
982 {
983 struct cp_private *cp = netdev_priv(dev);
984 unsigned long flags;
985
986 /* The chip only need report frame silently dropped. */
987 spin_lock_irqsave(&cp->lock, flags);
988 if (netif_running(dev) && netif_device_present(dev))
989 __cp_get_stats(cp);
990 spin_unlock_irqrestore(&cp->lock, flags);
991
992 return &cp->net_stats;
993 }
994
995 static void cp_stop_hw (struct cp_private *cp)
996 {
997 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
998 cpw16_f(IntrMask, 0);
999 cpw8(Cmd, 0);
1000 cpw16_f(CpCmd, 0);
1001 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1002
1003 cp->rx_tail = 0;
1004 cp->tx_head = cp->tx_tail = 0;
1005 }
1006
1007 static void cp_reset_hw (struct cp_private *cp)
1008 {
1009 unsigned work = 1000;
1010
1011 cpw8(Cmd, CmdReset);
1012
1013 while (work--) {
1014 if (!(cpr8(Cmd) & CmdReset))
1015 return;
1016
1017 schedule_timeout_uninterruptible(10);
1018 }
1019
1020 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1021 }
1022
1023 static inline void cp_start_hw (struct cp_private *cp)
1024 {
1025 cpw16(CpCmd, cp->cpcmd);
1026 cpw8(Cmd, RxOn | TxOn);
1027 }
1028
1029 static void cp_init_hw (struct cp_private *cp)
1030 {
1031 struct net_device *dev = cp->dev;
1032 dma_addr_t ring_dma;
1033
1034 cp_reset_hw(cp);
1035
1036 cpw8_f (Cfg9346, Cfg9346_Unlock);
1037
1038 /* Restore our idea of the MAC address. */
1039 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1040 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1041
1042 cp_start_hw(cp);
1043 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1044
1045 __cp_set_rx_mode(dev);
1046 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1047
1048 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1049 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1050 cpw8(Config3, PARMEnable);
1051 cp->wol_enabled = 0;
1052
1053 cpw8(Config5, cpr8(Config5) & PMEStatus);
1054
1055 cpw32_f(HiTxRingAddr, 0);
1056 cpw32_f(HiTxRingAddr + 4, 0);
1057
1058 ring_dma = cp->ring_dma;
1059 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1060 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1061
1062 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1063 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1064 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1065
1066 cpw16(MultiIntr, 0);
1067
1068 cpw16_f(IntrMask, cp_intr_mask);
1069
1070 cpw8_f(Cfg9346, Cfg9346_Lock);
1071 }
1072
1073 static int cp_refill_rx (struct cp_private *cp)
1074 {
1075 unsigned i;
1076
1077 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1078 struct sk_buff *skb;
1079 dma_addr_t mapping;
1080
1081 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1082 if (!skb)
1083 goto err_out;
1084
1085 skb->dev = cp->dev;
1086 skb_reserve(skb, RX_OFFSET);
1087
1088 mapping = pci_map_single(cp->pdev, skb->data, cp->rx_buf_sz,
1089 PCI_DMA_FROMDEVICE);
1090 cp->rx_skb[i] = skb;
1091
1092 cp->rx_ring[i].opts2 = 0;
1093 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1094 if (i == (CP_RX_RING_SIZE - 1))
1095 cp->rx_ring[i].opts1 =
1096 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1097 else
1098 cp->rx_ring[i].opts1 =
1099 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1100 }
1101
1102 return 0;
1103
1104 err_out:
1105 cp_clean_rings(cp);
1106 return -ENOMEM;
1107 }
1108
1109 static void cp_init_rings_index (struct cp_private *cp)
1110 {
1111 cp->rx_tail = 0;
1112 cp->tx_head = cp->tx_tail = 0;
1113 }
1114
1115 static int cp_init_rings (struct cp_private *cp)
1116 {
1117 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1118 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1119
1120 cp_init_rings_index(cp);
1121
1122 return cp_refill_rx (cp);
1123 }
1124
1125 static int cp_alloc_rings (struct cp_private *cp)
1126 {
1127 void *mem;
1128
1129 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1130 if (!mem)
1131 return -ENOMEM;
1132
1133 cp->rx_ring = mem;
1134 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1135
1136 return cp_init_rings(cp);
1137 }
1138
1139 static void cp_clean_rings (struct cp_private *cp)
1140 {
1141 struct cp_desc *desc;
1142 unsigned i;
1143
1144 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1145 if (cp->rx_skb[i]) {
1146 desc = cp->rx_ring + i;
1147 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1148 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1149 dev_kfree_skb(cp->rx_skb[i]);
1150 }
1151 }
1152
1153 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1154 if (cp->tx_skb[i]) {
1155 struct sk_buff *skb = cp->tx_skb[i];
1156
1157 desc = cp->tx_ring + i;
1158 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1159 le32_to_cpu(desc->opts1) & 0xffff,
1160 PCI_DMA_TODEVICE);
1161 if (le32_to_cpu(desc->opts1) & LastFrag)
1162 dev_kfree_skb(skb);
1163 cp->net_stats.tx_dropped++;
1164 }
1165 }
1166
1167 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1168 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1169
1170 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1171 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1172 }
1173
1174 static void cp_free_rings (struct cp_private *cp)
1175 {
1176 cp_clean_rings(cp);
1177 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1178 cp->rx_ring = NULL;
1179 cp->tx_ring = NULL;
1180 }
1181
1182 static int cp_open (struct net_device *dev)
1183 {
1184 struct cp_private *cp = netdev_priv(dev);
1185 int rc;
1186
1187 if (netif_msg_ifup(cp))
1188 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1189
1190 rc = cp_alloc_rings(cp);
1191 if (rc)
1192 return rc;
1193
1194 cp_init_hw(cp);
1195
1196 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1197 if (rc)
1198 goto err_out_hw;
1199
1200 netif_carrier_off(dev);
1201 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1202 netif_start_queue(dev);
1203
1204 return 0;
1205
1206 err_out_hw:
1207 cp_stop_hw(cp);
1208 cp_free_rings(cp);
1209 return rc;
1210 }
1211
1212 static int cp_close (struct net_device *dev)
1213 {
1214 struct cp_private *cp = netdev_priv(dev);
1215 unsigned long flags;
1216
1217 if (netif_msg_ifdown(cp))
1218 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1219
1220 spin_lock_irqsave(&cp->lock, flags);
1221
1222 netif_stop_queue(dev);
1223 netif_carrier_off(dev);
1224
1225 cp_stop_hw(cp);
1226
1227 spin_unlock_irqrestore(&cp->lock, flags);
1228
1229 synchronize_irq(dev->irq);
1230 free_irq(dev->irq, dev);
1231
1232 cp_free_rings(cp);
1233 return 0;
1234 }
1235
1236 #ifdef BROKEN
1237 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1238 {
1239 struct cp_private *cp = netdev_priv(dev);
1240 int rc;
1241 unsigned long flags;
1242
1243 /* check for invalid MTU, according to hardware limits */
1244 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1245 return -EINVAL;
1246
1247 /* if network interface not up, no need for complexity */
1248 if (!netif_running(dev)) {
1249 dev->mtu = new_mtu;
1250 cp_set_rxbufsize(cp); /* set new rx buf size */
1251 return 0;
1252 }
1253
1254 spin_lock_irqsave(&cp->lock, flags);
1255
1256 cp_stop_hw(cp); /* stop h/w and free rings */
1257 cp_clean_rings(cp);
1258
1259 dev->mtu = new_mtu;
1260 cp_set_rxbufsize(cp); /* set new rx buf size */
1261
1262 rc = cp_init_rings(cp); /* realloc and restart h/w */
1263 cp_start_hw(cp);
1264
1265 spin_unlock_irqrestore(&cp->lock, flags);
1266
1267 return rc;
1268 }
1269 #endif /* BROKEN */
1270
1271 static const char mii_2_8139_map[8] = {
1272 BasicModeCtrl,
1273 BasicModeStatus,
1274 0,
1275 0,
1276 NWayAdvert,
1277 NWayLPAR,
1278 NWayExpansion,
1279 0
1280 };
1281
1282 static int mdio_read(struct net_device *dev, int phy_id, int location)
1283 {
1284 struct cp_private *cp = netdev_priv(dev);
1285
1286 return location < 8 && mii_2_8139_map[location] ?
1287 readw(cp->regs + mii_2_8139_map[location]) : 0;
1288 }
1289
1290
1291 static void mdio_write(struct net_device *dev, int phy_id, int location,
1292 int value)
1293 {
1294 struct cp_private *cp = netdev_priv(dev);
1295
1296 if (location == 0) {
1297 cpw8(Cfg9346, Cfg9346_Unlock);
1298 cpw16(BasicModeCtrl, value);
1299 cpw8(Cfg9346, Cfg9346_Lock);
1300 } else if (location < 8 && mii_2_8139_map[location])
1301 cpw16(mii_2_8139_map[location], value);
1302 }
1303
1304 /* Set the ethtool Wake-on-LAN settings */
1305 static int netdev_set_wol (struct cp_private *cp,
1306 const struct ethtool_wolinfo *wol)
1307 {
1308 u8 options;
1309
1310 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1311 /* If WOL is being disabled, no need for complexity */
1312 if (wol->wolopts) {
1313 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1314 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1315 }
1316
1317 cpw8 (Cfg9346, Cfg9346_Unlock);
1318 cpw8 (Config3, options);
1319 cpw8 (Cfg9346, Cfg9346_Lock);
1320
1321 options = 0; /* Paranoia setting */
1322 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1323 /* If WOL is being disabled, no need for complexity */
1324 if (wol->wolopts) {
1325 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1326 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1327 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1328 }
1329
1330 cpw8 (Config5, options);
1331
1332 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1333
1334 return 0;
1335 }
1336
1337 /* Get the ethtool Wake-on-LAN settings */
1338 static void netdev_get_wol (struct cp_private *cp,
1339 struct ethtool_wolinfo *wol)
1340 {
1341 u8 options;
1342
1343 wol->wolopts = 0; /* Start from scratch */
1344 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1345 WAKE_MCAST | WAKE_UCAST;
1346 /* We don't need to go on if WOL is disabled */
1347 if (!cp->wol_enabled) return;
1348
1349 options = cpr8 (Config3);
1350 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1351 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1352
1353 options = 0; /* Paranoia setting */
1354 options = cpr8 (Config5);
1355 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1356 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1357 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1358 }
1359
1360 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1361 {
1362 struct cp_private *cp = netdev_priv(dev);
1363
1364 strcpy (info->driver, DRV_NAME);
1365 strcpy (info->version, DRV_VERSION);
1366 strcpy (info->bus_info, pci_name(cp->pdev));
1367 }
1368
1369 static int cp_get_regs_len(struct net_device *dev)
1370 {
1371 return CP_REGS_SIZE;
1372 }
1373
1374 static int cp_get_stats_count (struct net_device *dev)
1375 {
1376 return CP_NUM_STATS;
1377 }
1378
1379 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1380 {
1381 struct cp_private *cp = netdev_priv(dev);
1382 int rc;
1383 unsigned long flags;
1384
1385 spin_lock_irqsave(&cp->lock, flags);
1386 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1387 spin_unlock_irqrestore(&cp->lock, flags);
1388
1389 return rc;
1390 }
1391
1392 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1393 {
1394 struct cp_private *cp = netdev_priv(dev);
1395 int rc;
1396 unsigned long flags;
1397
1398 spin_lock_irqsave(&cp->lock, flags);
1399 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1400 spin_unlock_irqrestore(&cp->lock, flags);
1401
1402 return rc;
1403 }
1404
1405 static int cp_nway_reset(struct net_device *dev)
1406 {
1407 struct cp_private *cp = netdev_priv(dev);
1408 return mii_nway_restart(&cp->mii_if);
1409 }
1410
1411 static u32 cp_get_msglevel(struct net_device *dev)
1412 {
1413 struct cp_private *cp = netdev_priv(dev);
1414 return cp->msg_enable;
1415 }
1416
1417 static void cp_set_msglevel(struct net_device *dev, u32 value)
1418 {
1419 struct cp_private *cp = netdev_priv(dev);
1420 cp->msg_enable = value;
1421 }
1422
1423 static u32 cp_get_rx_csum(struct net_device *dev)
1424 {
1425 struct cp_private *cp = netdev_priv(dev);
1426 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1427 }
1428
1429 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1430 {
1431 struct cp_private *cp = netdev_priv(dev);
1432 u16 cmd = cp->cpcmd, newcmd;
1433
1434 newcmd = cmd;
1435
1436 if (data)
1437 newcmd |= RxChkSum;
1438 else
1439 newcmd &= ~RxChkSum;
1440
1441 if (newcmd != cmd) {
1442 unsigned long flags;
1443
1444 spin_lock_irqsave(&cp->lock, flags);
1445 cp->cpcmd = newcmd;
1446 cpw16_f(CpCmd, newcmd);
1447 spin_unlock_irqrestore(&cp->lock, flags);
1448 }
1449
1450 return 0;
1451 }
1452
1453 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1454 void *p)
1455 {
1456 struct cp_private *cp = netdev_priv(dev);
1457 unsigned long flags;
1458
1459 if (regs->len < CP_REGS_SIZE)
1460 return /* -EINVAL */;
1461
1462 regs->version = CP_REGS_VER;
1463
1464 spin_lock_irqsave(&cp->lock, flags);
1465 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1466 spin_unlock_irqrestore(&cp->lock, flags);
1467 }
1468
1469 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1470 {
1471 struct cp_private *cp = netdev_priv(dev);
1472 unsigned long flags;
1473
1474 spin_lock_irqsave (&cp->lock, flags);
1475 netdev_get_wol (cp, wol);
1476 spin_unlock_irqrestore (&cp->lock, flags);
1477 }
1478
1479 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1480 {
1481 struct cp_private *cp = netdev_priv(dev);
1482 unsigned long flags;
1483 int rc;
1484
1485 spin_lock_irqsave (&cp->lock, flags);
1486 rc = netdev_set_wol (cp, wol);
1487 spin_unlock_irqrestore (&cp->lock, flags);
1488
1489 return rc;
1490 }
1491
1492 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1493 {
1494 switch (stringset) {
1495 case ETH_SS_STATS:
1496 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1497 break;
1498 default:
1499 BUG();
1500 break;
1501 }
1502 }
1503
1504 static void cp_get_ethtool_stats (struct net_device *dev,
1505 struct ethtool_stats *estats, u64 *tmp_stats)
1506 {
1507 struct cp_private *cp = netdev_priv(dev);
1508 struct cp_dma_stats *nic_stats;
1509 dma_addr_t dma;
1510 int i;
1511
1512 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1513 if (!nic_stats)
1514 return;
1515
1516 /* begin NIC statistics dump */
1517 cpw32(StatsAddr + 4, (u64)dma >> 32);
1518 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1519 cpr32(StatsAddr);
1520
1521 for (i = 0; i < 1000; i++) {
1522 if ((cpr32(StatsAddr) & DumpStats) == 0)
1523 break;
1524 udelay(10);
1525 }
1526 cpw32(StatsAddr, 0);
1527 cpw32(StatsAddr + 4, 0);
1528 cpr32(StatsAddr);
1529
1530 i = 0;
1531 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1532 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1533 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1534 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1535 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1536 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1537 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1538 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1539 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1540 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1541 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1542 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1543 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1544 tmp_stats[i++] = cp->cp_stats.rx_frags;
1545 BUG_ON(i != CP_NUM_STATS);
1546
1547 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1548 }
1549
1550 static const struct ethtool_ops cp_ethtool_ops = {
1551 .get_drvinfo = cp_get_drvinfo,
1552 .get_regs_len = cp_get_regs_len,
1553 .get_stats_count = cp_get_stats_count,
1554 .get_settings = cp_get_settings,
1555 .set_settings = cp_set_settings,
1556 .nway_reset = cp_nway_reset,
1557 .get_link = ethtool_op_get_link,
1558 .get_msglevel = cp_get_msglevel,
1559 .set_msglevel = cp_set_msglevel,
1560 .get_rx_csum = cp_get_rx_csum,
1561 .set_rx_csum = cp_set_rx_csum,
1562 .get_tx_csum = ethtool_op_get_tx_csum,
1563 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1564 .get_sg = ethtool_op_get_sg,
1565 .set_sg = ethtool_op_set_sg,
1566 .get_tso = ethtool_op_get_tso,
1567 .set_tso = ethtool_op_set_tso,
1568 .get_regs = cp_get_regs,
1569 .get_wol = cp_get_wol,
1570 .set_wol = cp_set_wol,
1571 .get_strings = cp_get_strings,
1572 .get_ethtool_stats = cp_get_ethtool_stats,
1573 .get_perm_addr = ethtool_op_get_perm_addr,
1574 .get_eeprom_len = cp_get_eeprom_len,
1575 .get_eeprom = cp_get_eeprom,
1576 .set_eeprom = cp_set_eeprom,
1577 };
1578
1579 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1580 {
1581 struct cp_private *cp = netdev_priv(dev);
1582 int rc;
1583 unsigned long flags;
1584
1585 if (!netif_running(dev))
1586 return -EINVAL;
1587
1588 spin_lock_irqsave(&cp->lock, flags);
1589 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1590 spin_unlock_irqrestore(&cp->lock, flags);
1591 return rc;
1592 }
1593
1594 /* Serial EEPROM section. */
1595
1596 /* EEPROM_Ctrl bits. */
1597 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1598 #define EE_CS 0x08 /* EEPROM chip select. */
1599 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1600 #define EE_WRITE_0 0x00
1601 #define EE_WRITE_1 0x02
1602 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1603 #define EE_ENB (0x80 | EE_CS)
1604
1605 /* Delay between EEPROM clock transitions.
1606 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1607 */
1608
1609 #define eeprom_delay() readl(ee_addr)
1610
1611 /* The EEPROM commands include the alway-set leading bit. */
1612 #define EE_EXTEND_CMD (4)
1613 #define EE_WRITE_CMD (5)
1614 #define EE_READ_CMD (6)
1615 #define EE_ERASE_CMD (7)
1616
1617 #define EE_EWDS_ADDR (0)
1618 #define EE_WRAL_ADDR (1)
1619 #define EE_ERAL_ADDR (2)
1620 #define EE_EWEN_ADDR (3)
1621
1622 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1623
1624 static void eeprom_cmd_start(void __iomem *ee_addr)
1625 {
1626 writeb (EE_ENB & ~EE_CS, ee_addr);
1627 writeb (EE_ENB, ee_addr);
1628 eeprom_delay ();
1629 }
1630
1631 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1632 {
1633 int i;
1634
1635 /* Shift the command bits out. */
1636 for (i = cmd_len - 1; i >= 0; i--) {
1637 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1638 writeb (EE_ENB | dataval, ee_addr);
1639 eeprom_delay ();
1640 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1641 eeprom_delay ();
1642 }
1643 writeb (EE_ENB, ee_addr);
1644 eeprom_delay ();
1645 }
1646
1647 static void eeprom_cmd_end(void __iomem *ee_addr)
1648 {
1649 writeb (~EE_CS, ee_addr);
1650 eeprom_delay ();
1651 }
1652
1653 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1654 int addr_len)
1655 {
1656 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1657
1658 eeprom_cmd_start(ee_addr);
1659 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1660 eeprom_cmd_end(ee_addr);
1661 }
1662
1663 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1664 {
1665 int i;
1666 u16 retval = 0;
1667 void __iomem *ee_addr = ioaddr + Cfg9346;
1668 int read_cmd = location | (EE_READ_CMD << addr_len);
1669
1670 eeprom_cmd_start(ee_addr);
1671 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1672
1673 for (i = 16; i > 0; i--) {
1674 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1675 eeprom_delay ();
1676 retval =
1677 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1678 0);
1679 writeb (EE_ENB, ee_addr);
1680 eeprom_delay ();
1681 }
1682
1683 eeprom_cmd_end(ee_addr);
1684
1685 return retval;
1686 }
1687
1688 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1689 int addr_len)
1690 {
1691 int i;
1692 void __iomem *ee_addr = ioaddr + Cfg9346;
1693 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1694
1695 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1696
1697 eeprom_cmd_start(ee_addr);
1698 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1699 eeprom_cmd(ee_addr, val, 16);
1700 eeprom_cmd_end(ee_addr);
1701
1702 eeprom_cmd_start(ee_addr);
1703 for (i = 0; i < 20000; i++)
1704 if (readb(ee_addr) & EE_DATA_READ)
1705 break;
1706 eeprom_cmd_end(ee_addr);
1707
1708 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1709 }
1710
1711 static int cp_get_eeprom_len(struct net_device *dev)
1712 {
1713 struct cp_private *cp = netdev_priv(dev);
1714 int size;
1715
1716 spin_lock_irq(&cp->lock);
1717 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1718 spin_unlock_irq(&cp->lock);
1719
1720 return size;
1721 }
1722
1723 static int cp_get_eeprom(struct net_device *dev,
1724 struct ethtool_eeprom *eeprom, u8 *data)
1725 {
1726 struct cp_private *cp = netdev_priv(dev);
1727 unsigned int addr_len;
1728 u16 val;
1729 u32 offset = eeprom->offset >> 1;
1730 u32 len = eeprom->len;
1731 u32 i = 0;
1732
1733 eeprom->magic = CP_EEPROM_MAGIC;
1734
1735 spin_lock_irq(&cp->lock);
1736
1737 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1738
1739 if (eeprom->offset & 1) {
1740 val = read_eeprom(cp->regs, offset, addr_len);
1741 data[i++] = (u8)(val >> 8);
1742 offset++;
1743 }
1744
1745 while (i < len - 1) {
1746 val = read_eeprom(cp->regs, offset, addr_len);
1747 data[i++] = (u8)val;
1748 data[i++] = (u8)(val >> 8);
1749 offset++;
1750 }
1751
1752 if (i < len) {
1753 val = read_eeprom(cp->regs, offset, addr_len);
1754 data[i] = (u8)val;
1755 }
1756
1757 spin_unlock_irq(&cp->lock);
1758 return 0;
1759 }
1760
1761 static int cp_set_eeprom(struct net_device *dev,
1762 struct ethtool_eeprom *eeprom, u8 *data)
1763 {
1764 struct cp_private *cp = netdev_priv(dev);
1765 unsigned int addr_len;
1766 u16 val;
1767 u32 offset = eeprom->offset >> 1;
1768 u32 len = eeprom->len;
1769 u32 i = 0;
1770
1771 if (eeprom->magic != CP_EEPROM_MAGIC)
1772 return -EINVAL;
1773
1774 spin_lock_irq(&cp->lock);
1775
1776 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1777
1778 if (eeprom->offset & 1) {
1779 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1780 val |= (u16)data[i++] << 8;
1781 write_eeprom(cp->regs, offset, val, addr_len);
1782 offset++;
1783 }
1784
1785 while (i < len - 1) {
1786 val = (u16)data[i++];
1787 val |= (u16)data[i++] << 8;
1788 write_eeprom(cp->regs, offset, val, addr_len);
1789 offset++;
1790 }
1791
1792 if (i < len) {
1793 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1794 val |= (u16)data[i];
1795 write_eeprom(cp->regs, offset, val, addr_len);
1796 }
1797
1798 spin_unlock_irq(&cp->lock);
1799 return 0;
1800 }
1801
1802 /* Put the board into D3cold state and wait for WakeUp signal */
1803 static void cp_set_d3_state (struct cp_private *cp)
1804 {
1805 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1806 pci_set_power_state (cp->pdev, PCI_D3hot);
1807 }
1808
1809 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1810 {
1811 struct net_device *dev;
1812 struct cp_private *cp;
1813 int rc;
1814 void __iomem *regs;
1815 resource_size_t pciaddr;
1816 unsigned int addr_len, i, pci_using_dac;
1817 u8 pci_rev;
1818
1819 #ifndef MODULE
1820 static int version_printed;
1821 if (version_printed++ == 0)
1822 printk("%s", version);
1823 #endif
1824
1825 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1826
1827 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1828 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1829 dev_err(&pdev->dev,
1830 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1831 pdev->vendor, pdev->device, pci_rev);
1832 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1833 return -ENODEV;
1834 }
1835
1836 dev = alloc_etherdev(sizeof(struct cp_private));
1837 if (!dev)
1838 return -ENOMEM;
1839 SET_MODULE_OWNER(dev);
1840 SET_NETDEV_DEV(dev, &pdev->dev);
1841
1842 cp = netdev_priv(dev);
1843 cp->pdev = pdev;
1844 cp->dev = dev;
1845 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1846 spin_lock_init (&cp->lock);
1847 cp->mii_if.dev = dev;
1848 cp->mii_if.mdio_read = mdio_read;
1849 cp->mii_if.mdio_write = mdio_write;
1850 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1851 cp->mii_if.phy_id_mask = 0x1f;
1852 cp->mii_if.reg_num_mask = 0x1f;
1853 cp_set_rxbufsize(cp);
1854
1855 rc = pci_enable_device(pdev);
1856 if (rc)
1857 goto err_out_free;
1858
1859 rc = pci_set_mwi(pdev);
1860 if (rc)
1861 goto err_out_disable;
1862
1863 rc = pci_request_regions(pdev, DRV_NAME);
1864 if (rc)
1865 goto err_out_mwi;
1866
1867 pciaddr = pci_resource_start(pdev, 1);
1868 if (!pciaddr) {
1869 rc = -EIO;
1870 dev_err(&pdev->dev, "no MMIO resource\n");
1871 goto err_out_res;
1872 }
1873 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1874 rc = -EIO;
1875 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1876 (unsigned long long)pci_resource_len(pdev, 1));
1877 goto err_out_res;
1878 }
1879
1880 /* Configure DMA attributes. */
1881 if ((sizeof(dma_addr_t) > 4) &&
1882 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1883 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1884 pci_using_dac = 1;
1885 } else {
1886 pci_using_dac = 0;
1887
1888 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1889 if (rc) {
1890 dev_err(&pdev->dev,
1891 "No usable DMA configuration, aborting.\n");
1892 goto err_out_res;
1893 }
1894 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1895 if (rc) {
1896 dev_err(&pdev->dev,
1897 "No usable consistent DMA configuration, "
1898 "aborting.\n");
1899 goto err_out_res;
1900 }
1901 }
1902
1903 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1904 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1905
1906 regs = ioremap(pciaddr, CP_REGS_SIZE);
1907 if (!regs) {
1908 rc = -EIO;
1909 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1910 (unsigned long long)pci_resource_len(pdev, 1),
1911 (unsigned long long)pciaddr);
1912 goto err_out_res;
1913 }
1914 dev->base_addr = (unsigned long) regs;
1915 cp->regs = regs;
1916
1917 cp_stop_hw(cp);
1918
1919 /* read MAC address from EEPROM */
1920 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1921 for (i = 0; i < 3; i++)
1922 ((u16 *) (dev->dev_addr))[i] =
1923 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1924 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1925
1926 dev->open = cp_open;
1927 dev->stop = cp_close;
1928 dev->set_multicast_list = cp_set_rx_mode;
1929 dev->hard_start_xmit = cp_start_xmit;
1930 dev->get_stats = cp_get_stats;
1931 dev->do_ioctl = cp_ioctl;
1932 dev->poll = cp_rx_poll;
1933 #ifdef CONFIG_NET_POLL_CONTROLLER
1934 dev->poll_controller = cp_poll_controller;
1935 #endif
1936 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1937 #ifdef BROKEN
1938 dev->change_mtu = cp_change_mtu;
1939 #endif
1940 dev->ethtool_ops = &cp_ethtool_ops;
1941 #if 0
1942 dev->tx_timeout = cp_tx_timeout;
1943 dev->watchdog_timeo = TX_TIMEOUT;
1944 #endif
1945
1946 #if CP_VLAN_TAG_USED
1947 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1948 dev->vlan_rx_register = cp_vlan_rx_register;
1949 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1950 #endif
1951
1952 if (pci_using_dac)
1953 dev->features |= NETIF_F_HIGHDMA;
1954
1955 #if 0 /* disabled by default until verified */
1956 dev->features |= NETIF_F_TSO;
1957 #endif
1958
1959 dev->irq = pdev->irq;
1960
1961 rc = register_netdev(dev);
1962 if (rc)
1963 goto err_out_iomap;
1964
1965 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1966 "%02x:%02x:%02x:%02x:%02x:%02x, "
1967 "IRQ %d\n",
1968 dev->name,
1969 dev->base_addr,
1970 dev->dev_addr[0], dev->dev_addr[1],
1971 dev->dev_addr[2], dev->dev_addr[3],
1972 dev->dev_addr[4], dev->dev_addr[5],
1973 dev->irq);
1974
1975 pci_set_drvdata(pdev, dev);
1976
1977 /* enable busmastering and memory-write-invalidate */
1978 pci_set_master(pdev);
1979
1980 if (cp->wol_enabled)
1981 cp_set_d3_state (cp);
1982
1983 return 0;
1984
1985 err_out_iomap:
1986 iounmap(regs);
1987 err_out_res:
1988 pci_release_regions(pdev);
1989 err_out_mwi:
1990 pci_clear_mwi(pdev);
1991 err_out_disable:
1992 pci_disable_device(pdev);
1993 err_out_free:
1994 free_netdev(dev);
1995 return rc;
1996 }
1997
1998 static void cp_remove_one (struct pci_dev *pdev)
1999 {
2000 struct net_device *dev = pci_get_drvdata(pdev);
2001 struct cp_private *cp = netdev_priv(dev);
2002
2003 unregister_netdev(dev);
2004 iounmap(cp->regs);
2005 if (cp->wol_enabled)
2006 pci_set_power_state (pdev, PCI_D0);
2007 pci_release_regions(pdev);
2008 pci_clear_mwi(pdev);
2009 pci_disable_device(pdev);
2010 pci_set_drvdata(pdev, NULL);
2011 free_netdev(dev);
2012 }
2013
2014 #ifdef CONFIG_PM
2015 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2016 {
2017 struct net_device *dev = pci_get_drvdata(pdev);
2018 struct cp_private *cp = netdev_priv(dev);
2019 unsigned long flags;
2020
2021 if (!netif_running(dev))
2022 return 0;
2023
2024 netif_device_detach (dev);
2025 netif_stop_queue (dev);
2026
2027 spin_lock_irqsave (&cp->lock, flags);
2028
2029 /* Disable Rx and Tx */
2030 cpw16 (IntrMask, 0);
2031 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2032
2033 spin_unlock_irqrestore (&cp->lock, flags);
2034
2035 pci_save_state(pdev);
2036 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2037 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2038
2039 return 0;
2040 }
2041
2042 static int cp_resume (struct pci_dev *pdev)
2043 {
2044 struct net_device *dev = pci_get_drvdata (pdev);
2045 struct cp_private *cp = netdev_priv(dev);
2046 unsigned long flags;
2047
2048 if (!netif_running(dev))
2049 return 0;
2050
2051 netif_device_attach (dev);
2052
2053 pci_set_power_state(pdev, PCI_D0);
2054 pci_restore_state(pdev);
2055 pci_enable_wake(pdev, PCI_D0, 0);
2056
2057 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2058 cp_init_rings_index (cp);
2059 cp_init_hw (cp);
2060 netif_start_queue (dev);
2061
2062 spin_lock_irqsave (&cp->lock, flags);
2063
2064 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
2065
2066 spin_unlock_irqrestore (&cp->lock, flags);
2067
2068 return 0;
2069 }
2070 #endif /* CONFIG_PM */
2071
2072 static struct pci_driver cp_driver = {
2073 .name = DRV_NAME,
2074 .id_table = cp_pci_tbl,
2075 .probe = cp_init_one,
2076 .remove = cp_remove_one,
2077 #ifdef CONFIG_PM
2078 .resume = cp_resume,
2079 .suspend = cp_suspend,
2080 #endif
2081 };
2082
2083 static int __init cp_init (void)
2084 {
2085 #ifdef MODULE
2086 printk("%s", version);
2087 #endif
2088 return pci_register_driver(&cp_driver);
2089 }
2090
2091 static void __exit cp_exit (void)
2092 {
2093 pci_unregister_driver (&cp_driver);
2094 }
2095
2096 module_init(cp_init);
2097 module_exit(cp_exit);
SocketAccessConTroL development