drivers/ata/pata_hpt366.c

   1 /*
   2  * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
   3  *
   4  * This driver is heavily based upon:
   5  *
   6  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   7  *
   8  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   9  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  10  * Portions Copyright (C) 2003          Red Hat Inc
  11  *
  12  *
  13  * TODO
  14  *      Maybe PLL mode
  15  *      Look into engine reset on timeout errors. Should not be
  16  *              required.
  17  */
  18
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/init.h>
  24 #include <linux/blkdev.h>
  25 #include <linux/delay.h>
  26 #include <scsi/scsi_host.h>
  27 #include <linux/libata.h>
  28
  29 #define DRV_NAME        "pata_hpt366"
  30 #define DRV_VERSION     "0.6.0"
  31
  32 struct hpt_clock {
  33         u8      xfer_speed;
  34         u32     timing;
  35 };
  36
  37 /* key for bus clock timings
  38  * bit
  39  * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
  40  *        DMA. cycles = value + 1
  41  * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
  42  *        DMA. cycles = value + 1
  43  * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
  44  *        register access.
  45  * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
  46  *        register access.
  47  * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
  48  *        during task file register access.
  49  * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
  50  *        xfer.
  51  * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
  52  *        register access.
  53  * 28     UDMA enable
  54  * 29     DMA enable
  55  * 30     PIO_MST enable. if set, the chip is in bus master mode during
  56  *        PIO.
  57  * 31     FIFO enable.
  58  */
  59
  60 static const struct hpt_clock hpt366_40[] = {
  61         {       XFER_UDMA_4,    0x900fd943      },
  62         {       XFER_UDMA_3,    0x900ad943      },
  63         {       XFER_UDMA_2,    0x900bd943      },
  64         {       XFER_UDMA_1,    0x9008d943      },
  65         {       XFER_UDMA_0,    0x9008d943      },
  66
  67         {       XFER_MW_DMA_2,  0xa008d943      },
  68         {       XFER_MW_DMA_1,  0xa010d955      },
  69         {       XFER_MW_DMA_0,  0xa010d9fc      },
  70
  71         {       XFER_PIO_4,     0xc008d963      },
  72         {       XFER_PIO_3,     0xc010d974      },
  73         {       XFER_PIO_2,     0xc010d997      },
  74         {       XFER_PIO_1,     0xc010d9c7      },
  75         {       XFER_PIO_0,     0xc018d9d9      },
  76         {       0,              0x0120d9d9      }
  77 };
  78
  79 static const struct hpt_clock hpt366_33[] = {
  80         {       XFER_UDMA_4,    0x90c9a731      },
  81         {       XFER_UDMA_3,    0x90cfa731      },
  82         {       XFER_UDMA_2,    0x90caa731      },
  83         {       XFER_UDMA_1,    0x90cba731      },
  84         {       XFER_UDMA_0,    0x90c8a731      },
  85
  86         {       XFER_MW_DMA_2,  0xa0c8a731      },
  87         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
  88         {       XFER_MW_DMA_0,  0xa0c8a797      },
  89
  90         {       XFER_PIO_4,     0xc0c8a731      },
  91         {       XFER_PIO_3,     0xc0c8a742      },
  92         {       XFER_PIO_2,     0xc0d0a753      },
  93         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
  94         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
  95         {       0,              0x0120a7a7      }
  96 };
  97
  98 static const struct hpt_clock hpt366_25[] = {
  99         {       XFER_UDMA_4,    0x90c98521      },
 100         {       XFER_UDMA_3,    0x90cf8521      },
 101         {       XFER_UDMA_2,    0x90cf8521      },
 102         {       XFER_UDMA_1,    0x90cb8521      },
 103         {       XFER_UDMA_0,    0x90cb8521      },
 104
 105         {       XFER_MW_DMA_2,  0xa0ca8521      },
 106         {       XFER_MW_DMA_1,  0xa0ca8532      },
 107         {       XFER_MW_DMA_0,  0xa0ca8575      },
 108
 109         {       XFER_PIO_4,     0xc0ca8521      },
 110         {       XFER_PIO_3,     0xc0ca8532      },
 111         {       XFER_PIO_2,     0xc0ca8542      },
 112         {       XFER_PIO_1,     0xc0d08572      },
 113         {       XFER_PIO_0,     0xc0d08585      },
 114         {       0,              0x01208585      }
 115 };
 116
 117 static const char *bad_ata33[] = {
 118         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 119         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 120         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 121         "Maxtor 90510D4",
 122         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 123         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 124         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 125         NULL
 126 };
 127
 128 static const char *bad_ata66_4[] = {
 129         "IBM-DTLA-307075",
 130         "IBM-DTLA-307060",
 131         "IBM-DTLA-307045",
 132         "IBM-DTLA-307030",
 133         "IBM-DTLA-307020",
 134         "IBM-DTLA-307015",
 135         "IBM-DTLA-305040",
 136         "IBM-DTLA-305030",
 137         "IBM-DTLA-305020",
 138         "IC35L010AVER07-0",
 139         "IC35L020AVER07-0",
 140         "IC35L030AVER07-0",
 141         "IC35L040AVER07-0",
 142         "IC35L060AVER07-0",
 143         "WDC AC310200R",
 144         NULL
 145 };
 146
 147 static const char *bad_ata66_3[] = {
 148         "WDC AC310200R",
 149         NULL
 150 };
 151
 152 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
 153 {
 154         unsigned char model_num[ATA_ID_PROD_LEN + 1];
 155         int i = 0;
 156
 157         ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 158
 159         while (list[i] != NULL) {
 160                 if (!strcmp(list[i], model_num)) {
 161                         printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
 162                                 modestr, list[i]);
 163                         return 1;
 164                 }
 165                 i++;
 166         }
 167         return 0;
 168 }
 169
 170 /**
 171  *      hpt366_filter   -       mode selection filter
 172  *      @ap: ATA interface
 173  *      @adev: ATA device
 174  *
 175  *      Block UDMA on devices that cause trouble with this controller.
 176  */
 177
 178 static unsigned long hpt366_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
 179 {
 180         if (adev->class == ATA_DEV_ATA) {
 181                 if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
 182                         mask &= ~ATA_MASK_UDMA;
 183                 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
 184                         mask &= ~(0x07 << ATA_SHIFT_UDMA);
 185                 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
 186                         mask &= ~(0x0F << ATA_SHIFT_UDMA);
 187         }
 188         return ata_pci_default_filter(ap, adev, mask);
 189 }
 190
 191 /**
 192  *      hpt36x_find_mode        -       reset the hpt36x bus
 193  *      @ap: ATA port
 194  *      @speed: transfer mode
 195  *
 196  *      Return the 32bit register programming information for this channel
 197  *      that matches the speed provided.
 198  */
 199
 200 static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
 201 {
 202         struct hpt_clock *clocks = ap->host->private_data;
 203
 204         while(clocks->xfer_speed) {
 205                 if (clocks->xfer_speed == speed)
 206                         return clocks->timing;
 207                 clocks++;
 208         }
 209         BUG();
 210         return 0xffffffffU;     /* silence compiler warning */
 211 }
 212
 213 static int hpt36x_pre_reset(struct ata_port *ap)
 214 {
 215         static const struct pci_bits hpt36x_enable_bits[] = {
 216                 { 0x50, 1, 0x04, 0x04 },
 217                 { 0x54, 1, 0x04, 0x04 }
 218         };
 219
 220         u8 ata66;
 221         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 222
 223         if (!pci_test_config_bits(pdev, &hpt36x_enable_bits[ap->port_no]))
 224                 return -ENOENT;
 225
 226         pci_read_config_byte(pdev, 0x5A, &ata66);
 227         if (ata66 & (1 << ap->port_no))
 228                 ap->cbl = ATA_CBL_PATA40;
 229         else
 230                 ap->cbl = ATA_CBL_PATA80;
 231         return ata_std_prereset(ap);
 232 }
 233
 234 /**
 235  *      hpt36x_error_handler    -       reset the hpt36x bus
 236  *      @ap: ATA port to reset
 237  *
 238  *      Perform the reset handling for the 366/368
 239  */
 240
 241 static void hpt36x_error_handler(struct ata_port *ap)
 242 {
 243         ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
 244 }
 245
 246 /**
 247  *      hpt366_set_piomode              -       PIO setup
 248  *      @ap: ATA interface
 249  *      @adev: device on the interface
 250  *
 251  *      Perform PIO mode setup.
 252  */
 253
 254 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
 255 {
 256         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 257         u32 addr1, addr2;
 258         u32 reg;
 259         u32 mode;
 260         u8 fast;
 261
 262         addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 263         addr2 = 0x51 + 4 * ap->port_no;
 264
 265         /* Fast interrupt prediction disable, hold off interrupt disable */
 266         pci_read_config_byte(pdev, addr2, &fast);
 267         if (fast & 0x80) {
 268                 fast &= ~0x80;
 269                 pci_write_config_byte(pdev, addr2, fast);
 270         }
 271
 272         pci_read_config_dword(pdev, addr1, &reg);
 273         mode = hpt36x_find_mode(ap, adev->pio_mode);
 274         mode &= ~0x8000000;     /* No FIFO in PIO */
 275         mode &= ~0x30070000;    /* Leave config bits alone */
 276         reg &= 0x30070000;      /* Strip timing bits */
 277         pci_write_config_dword(pdev, addr1, reg | mode);
 278 }
 279
 280 /**
 281  *      hpt366_set_dmamode              -       DMA timing setup
 282  *      @ap: ATA interface
 283  *      @adev: Device being configured
 284  *
 285  *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 286  *      PIO, load the mode number and then set MWDMA or UDMA flag.
 287  */
 288
 289 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 290 {
 291         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 292         u32 addr1, addr2;
 293         u32 reg;
 294         u32 mode;
 295         u8 fast;
 296
 297         addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 298         addr2 = 0x51 + 4 * ap->port_no;
 299
 300         /* Fast interrupt prediction disable, hold off interrupt disable */
 301         pci_read_config_byte(pdev, addr2, &fast);
 302         if (fast & 0x80) {
 303                 fast &= ~0x80;
 304                 pci_write_config_byte(pdev, addr2, fast);
 305         }
 306
 307         pci_read_config_dword(pdev, addr1, &reg);
 308         mode = hpt36x_find_mode(ap, adev->dma_mode);
 309         mode |= 0x8000000;      /* FIFO in MWDMA or UDMA */
 310         mode &= ~0xC0000000;    /* Leave config bits alone */
 311         reg &= 0xC0000000;      /* Strip timing bits */
 312         pci_write_config_dword(pdev, addr1, reg | mode);
 313 }
 314
 315 static struct scsi_host_template hpt36x_sht = {
 316         .module                 = THIS_MODULE,
 317         .name                   = DRV_NAME,
 318         .ioctl                  = ata_scsi_ioctl,
 319         .queuecommand           = ata_scsi_queuecmd,
 320         .can_queue              = ATA_DEF_QUEUE,
 321         .this_id                = ATA_SHT_THIS_ID,
 322         .sg_tablesize           = LIBATA_MAX_PRD,
 323         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 324         .emulated               = ATA_SHT_EMULATED,
 325         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 326         .proc_name              = DRV_NAME,
 327         .dma_boundary           = ATA_DMA_BOUNDARY,
 328         .slave_configure        = ata_scsi_slave_config,
 329         .slave_destroy          = ata_scsi_slave_destroy,
 330         .bios_param             = ata_std_bios_param,
 331 #ifdef CONFIG_PM
 332         .resume                 = ata_scsi_device_resume,
 333         .suspend                = ata_scsi_device_suspend,
 334 #endif
 335 };
 336
 337 /*
 338  *      Configuration for HPT366/68
 339  */
 340
 341 static struct ata_port_operations hpt366_port_ops = {
 342         .port_disable   = ata_port_disable,
 343         .set_piomode    = hpt366_set_piomode,
 344         .set_dmamode    = hpt366_set_dmamode,
 345         .mode_filter    = hpt366_filter,
 346
 347         .tf_load        = ata_tf_load,
 348         .tf_read        = ata_tf_read,
 349         .check_status   = ata_check_status,
 350         .exec_command   = ata_exec_command,
 351         .dev_select     = ata_std_dev_select,
 352
 353         .freeze         = ata_bmdma_freeze,
 354         .thaw           = ata_bmdma_thaw,
 355         .error_handler  = hpt36x_error_handler,
 356         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 357
 358         .bmdma_setup    = ata_bmdma_setup,
 359         .bmdma_start    = ata_bmdma_start,
 360         .bmdma_stop     = ata_bmdma_stop,
 361         .bmdma_status   = ata_bmdma_status,
 362
 363         .qc_prep        = ata_qc_prep,
 364         .qc_issue       = ata_qc_issue_prot,
 365
 366         .data_xfer      = ata_data_xfer,
 367
 368         .irq_handler    = ata_interrupt,
 369         .irq_clear      = ata_bmdma_irq_clear,
 370         .irq_on         = ata_irq_on,
 371         .irq_ack        = ata_irq_ack,
 372
 373         .port_start     = ata_port_start,
 374 };
 375
 376 /**
 377  *      hpt36x_init_chipset     -       common chip setup
 378  *      @dev: PCI device
 379  *
 380  *      Perform the chip setup work that must be done at both init and
 381  *      resume time
 382  */
 383
 384 static void hpt36x_init_chipset(struct pci_dev *dev)
 385 {
 386         u8 drive_fast;
 387         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 388         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 389         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 390         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 391
 392         pci_read_config_byte(dev, 0x51, &drive_fast);
 393         if (drive_fast & 0x80)
 394                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 395 }
 396
 397 /**
 398  *      hpt36x_init_one         -       Initialise an HPT366/368
 399  *      @dev: PCI device
 400  *      @id: Entry in match table
 401  *
 402  *      Initialise an HPT36x device. There are some interesting complications
 403  *      here. Firstly the chip may report 366 and be one of several variants.
 404  *      Secondly all the timings depend on the clock for the chip which we must
 405  *      detect and look up
 406  *
 407  *      This is the known chip mappings. It may be missing a couple of later
 408  *      releases.
 409  *
 410  *      Chip version            PCI             Rev     Notes
 411  *      HPT366                  4 (HPT366)      0       UDMA66
 412  *      HPT366                  4 (HPT366)      1       UDMA66
 413  *      HPT368                  4 (HPT366)      2       UDMA66
 414  *      HPT37x/30x              4 (HPT366)      3+      Other driver
 415  *
 416  */
 417
 418 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 419 {
 420         static struct ata_port_info info_hpt366 = {
 421                 .sht = &hpt36x_sht,
 422                 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
 423                 .pio_mask = 0x1f,
 424                 .mwdma_mask = 0x07,
 425                 .udma_mask = 0x1f,
 426                 .port_ops = &hpt366_port_ops
 427         };
 428         struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366};
 429
 430         u32 class_rev;
 431         u32 reg1;
 432
 433         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 434         class_rev &= 0xFF;
 435
 436         /* May be a later chip in disguise. Check */
 437         /* Newer chips are not in the HPT36x driver. Ignore them */
 438         if (class_rev > 2)
 439                         return -ENODEV;
 440
 441         hpt36x_init_chipset(dev);
 442
 443         pci_read_config_dword(dev, 0x40,  &reg1);
 444
 445         /* PCI clocking determines the ATA timing values to use */
 446         /* info_hpt366 is safe against re-entry so we can scribble on it */
 447         switch((reg1 & 0x700) >> 8) {
 448                 case 5:
 449                         info_hpt366.private_data = &hpt366_40;
 450                         break;
 451                 case 9:
 452                         info_hpt366.private_data = &hpt366_25;
 453                         break;
 454                 default:
 455                         info_hpt366.private_data = &hpt366_33;
 456                         break;
 457         }
 458         /* Now kick off ATA set up */
 459         return ata_pci_init_one(dev, port_info, 2);
 460 }
 461
 462 #ifdef CONFIG_PM
 463 static int hpt36x_reinit_one(struct pci_dev *dev)
 464 {
 465         hpt36x_init_chipset(dev);
 466         return ata_pci_device_resume(dev);
 467 }
 468 #endif
 469
 470 static const struct pci_device_id hpt36x[] = {
 471         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 472         { },
 473 };
 474
 475 static struct pci_driver hpt36x_pci_driver = {
 476         .name           = DRV_NAME,
 477         .id_table       = hpt36x,
 478         .probe          = hpt36x_init_one,
 479         .remove         = ata_pci_remove_one,
 480 #ifdef CONFIG_PM
 481         .suspend        = ata_pci_device_suspend,
 482         .resume         = hpt36x_reinit_one,
 483 #endif
 484 };
 485
 486 static int __init hpt36x_init(void)
 487 {
 488         return pci_register_driver(&hpt36x_pci_driver);
 489 }
 490
 491 static void __exit hpt36x_exit(void)
 492 {
 493         pci_unregister_driver(&hpt36x_pci_driver);
 494 }
 495
 496 MODULE_AUTHOR("Alan Cox");
 497 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
 498 MODULE_LICENSE("GPL");
 499 MODULE_DEVICE_TABLE(pci, hpt36x);
 500 MODULE_VERSION(DRV_VERSION);
 501
 502 module_init(hpt36x_init);
 503 module_exit(hpt36x_exit);