2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/config.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
15 #include <linux/bitops.h>
17 #include <asm/bcache.h>
18 #include <asm/bootinfo.h>
19 #include <asm/cache.h>
20 #include <asm/cacheops.h>
22 #include <asm/cpu-features.h>
25 #include <asm/pgtable.h>
26 #include <asm/r4kcache.h>
27 #include <asm/system.h>
28 #include <asm/mmu_context.h>
30 #include <asm/cacheflush.h> /* for run_uncached() */
35 static unsigned long icache_size __read_mostly
;
36 static unsigned long dcache_size __read_mostly
;
37 static unsigned long scache_size __read_mostly
;
40 * Dummy cache handling routines for machines without boardcaches
42 static void no_sc_noop(void) {}
44 static struct bcache_ops no_sc_ops
= {
45 .bc_enable
= (void *)no_sc_noop
,
46 .bc_disable
= (void *)no_sc_noop
,
47 .bc_wback_inv
= (void *)no_sc_noop
,
48 .bc_inv
= (void *)no_sc_noop
51 struct bcache_ops
*bcops
= &no_sc_ops
;
53 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
54 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
56 #define R4600_HIT_CACHEOP_WAR_IMPL \
58 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
59 *(volatile unsigned long *)CKSEG1; \
60 if (R4600_V1_HIT_CACHEOP_WAR) \
61 __asm__ __volatile__("nop;nop;nop;nop"); \
64 static void (*r4k_blast_dcache_page
)(unsigned long addr
);
66 static inline void r4k_blast_dcache_page_dc32(unsigned long addr
)
68 R4600_HIT_CACHEOP_WAR_IMPL
;
69 blast_dcache32_page(addr
);
72 static inline void r4k_blast_dcache_page_setup(void)
74 unsigned long dc_lsize
= cpu_dcache_line_size();
77 r4k_blast_dcache_page
= blast_dcache16_page
;
78 else if (dc_lsize
== 32)
79 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc32
;
82 static void (* r4k_blast_dcache_page_indexed
)(unsigned long addr
);
84 static inline void r4k_blast_dcache_page_indexed_setup(void)
86 unsigned long dc_lsize
= cpu_dcache_line_size();
89 r4k_blast_dcache_page_indexed
= blast_dcache16_page_indexed
;
90 else if (dc_lsize
== 32)
91 r4k_blast_dcache_page_indexed
= blast_dcache32_page_indexed
;
94 static void (* r4k_blast_dcache
)(void);
96 static inline void r4k_blast_dcache_setup(void)
98 unsigned long dc_lsize
= cpu_dcache_line_size();
101 r4k_blast_dcache
= blast_dcache16
;
102 else if (dc_lsize
== 32)
103 r4k_blast_dcache
= blast_dcache32
;
106 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
107 #define JUMP_TO_ALIGN(order) \
108 __asm__ __volatile__( \
110 ".align\t" #order "\n\t" \
113 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
114 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
116 static inline void blast_r4600_v1_icache32(void)
120 local_irq_save(flags
);
122 local_irq_restore(flags
);
125 static inline void tx49_blast_icache32(void)
127 unsigned long start
= INDEX_BASE
;
128 unsigned long end
= start
+ current_cpu_data
.icache
.waysize
;
129 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
130 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
131 current_cpu_data
.icache
.waybit
;
132 unsigned long ws
, addr
;
134 CACHE32_UNROLL32_ALIGN2
;
135 /* I'm in even chunk. blast odd chunks */
136 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
137 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
138 cache32_unroll32(addr
|ws
,Index_Invalidate_I
);
139 CACHE32_UNROLL32_ALIGN
;
140 /* I'm in odd chunk. blast even chunks */
141 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
142 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
143 cache32_unroll32(addr
|ws
,Index_Invalidate_I
);
146 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page
)
150 local_irq_save(flags
);
151 blast_icache32_page_indexed(page
);
152 local_irq_restore(flags
);
155 static inline void tx49_blast_icache32_page_indexed(unsigned long page
)
157 unsigned long indexmask
= current_cpu_data
.icache
.waysize
- 1;
158 unsigned long start
= INDEX_BASE
+ (page
& indexmask
);
159 unsigned long end
= start
+ PAGE_SIZE
;
160 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
161 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
162 current_cpu_data
.icache
.waybit
;
163 unsigned long ws
, addr
;
165 CACHE32_UNROLL32_ALIGN2
;
166 /* I'm in even chunk. blast odd chunks */
167 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
168 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
169 cache32_unroll32(addr
|ws
,Index_Invalidate_I
);
170 CACHE32_UNROLL32_ALIGN
;
171 /* I'm in odd chunk. blast even chunks */
172 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
173 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
174 cache32_unroll32(addr
|ws
,Index_Invalidate_I
);
177 static void (* r4k_blast_icache_page
)(unsigned long addr
);
179 static inline void r4k_blast_icache_page_setup(void)
181 unsigned long ic_lsize
= cpu_icache_line_size();
184 r4k_blast_icache_page
= blast_icache16_page
;
185 else if (ic_lsize
== 32)
186 r4k_blast_icache_page
= blast_icache32_page
;
187 else if (ic_lsize
== 64)
188 r4k_blast_icache_page
= blast_icache64_page
;
192 static void (* r4k_blast_icache_page_indexed
)(unsigned long addr
);
194 static inline void r4k_blast_icache_page_indexed_setup(void)
196 unsigned long ic_lsize
= cpu_icache_line_size();
199 r4k_blast_icache_page_indexed
= blast_icache16_page_indexed
;
200 else if (ic_lsize
== 32) {
201 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
202 r4k_blast_icache_page_indexed
=
203 blast_icache32_r4600_v1_page_indexed
;
204 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
205 r4k_blast_icache_page_indexed
=
206 tx49_blast_icache32_page_indexed
;
208 r4k_blast_icache_page_indexed
=
209 blast_icache32_page_indexed
;
210 } else if (ic_lsize
== 64)
211 r4k_blast_icache_page_indexed
= blast_icache64_page_indexed
;
214 static void (* r4k_blast_icache
)(void);
216 static inline void r4k_blast_icache_setup(void)
218 unsigned long ic_lsize
= cpu_icache_line_size();
221 r4k_blast_icache
= blast_icache16
;
222 else if (ic_lsize
== 32) {
223 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
224 r4k_blast_icache
= blast_r4600_v1_icache32
;
225 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
226 r4k_blast_icache
= tx49_blast_icache32
;
228 r4k_blast_icache
= blast_icache32
;
229 } else if (ic_lsize
== 64)
230 r4k_blast_icache
= blast_icache64
;
233 static void (* r4k_blast_scache_page
)(unsigned long addr
);
235 static inline void r4k_blast_scache_page_setup(void)
237 unsigned long sc_lsize
= cpu_scache_line_size();
239 if (scache_size
== 0)
240 r4k_blast_scache_page
= (void *)no_sc_noop
;
241 else if (sc_lsize
== 16)
242 r4k_blast_scache_page
= blast_scache16_page
;
243 else if (sc_lsize
== 32)
244 r4k_blast_scache_page
= blast_scache32_page
;
245 else if (sc_lsize
== 64)
246 r4k_blast_scache_page
= blast_scache64_page
;
247 else if (sc_lsize
== 128)
248 r4k_blast_scache_page
= blast_scache128_page
;
251 static void (* r4k_blast_scache_page_indexed
)(unsigned long addr
);
253 static inline void r4k_blast_scache_page_indexed_setup(void)
255 unsigned long sc_lsize
= cpu_scache_line_size();
257 if (scache_size
== 0)
258 r4k_blast_scache_page_indexed
= (void *)no_sc_noop
;
259 else if (sc_lsize
== 16)
260 r4k_blast_scache_page_indexed
= blast_scache16_page_indexed
;
261 else if (sc_lsize
== 32)
262 r4k_blast_scache_page_indexed
= blast_scache32_page_indexed
;
263 else if (sc_lsize
== 64)
264 r4k_blast_scache_page_indexed
= blast_scache64_page_indexed
;
265 else if (sc_lsize
== 128)
266 r4k_blast_scache_page_indexed
= blast_scache128_page_indexed
;
269 static void (* r4k_blast_scache
)(void);
271 static inline void r4k_blast_scache_setup(void)
273 unsigned long sc_lsize
= cpu_scache_line_size();
275 if (scache_size
== 0)
276 r4k_blast_scache
= (void *)no_sc_noop
;
277 else if (sc_lsize
== 16)
278 r4k_blast_scache
= blast_scache16
;
279 else if (sc_lsize
== 32)
280 r4k_blast_scache
= blast_scache32
;
281 else if (sc_lsize
== 64)
282 r4k_blast_scache
= blast_scache64
;
283 else if (sc_lsize
== 128)
284 r4k_blast_scache
= blast_scache128
;
288 * This is former mm's flush_cache_all() which really should be
289 * flush_cache_vunmap these days ...
291 static inline void local_r4k_flush_cache_all(void * args
)
297 static void r4k_flush_cache_all(void)
299 if (!cpu_has_dc_aliases
)
302 on_each_cpu(local_r4k_flush_cache_all
, NULL
, 1, 1);
305 static inline void local_r4k___flush_cache_all(void * args
)
310 switch (current_cpu_data
.cputype
) {
321 static void r4k___flush_cache_all(void)
323 on_each_cpu(local_r4k___flush_cache_all
, NULL
, 1, 1);
326 static inline void local_r4k_flush_cache_range(void * args
)
328 struct vm_area_struct
*vma
= args
;
331 if (!(cpu_context(smp_processor_id(), vma
->vm_mm
)))
334 exec
= vma
->vm_flags
& VM_EXEC
;
335 if (cpu_has_dc_aliases
|| exec
)
341 static void r4k_flush_cache_range(struct vm_area_struct
*vma
,
342 unsigned long start
, unsigned long end
)
344 on_each_cpu(local_r4k_flush_cache_range
, vma
, 1, 1);
347 static inline void local_r4k_flush_cache_mm(void * args
)
349 struct mm_struct
*mm
= args
;
351 if (!cpu_context(smp_processor_id(), mm
))
358 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
359 * only flush the primary caches but R10000 and R12000 behave sane ...
361 if (current_cpu_data
.cputype
== CPU_R4000SC
||
362 current_cpu_data
.cputype
== CPU_R4000MC
||
363 current_cpu_data
.cputype
== CPU_R4400SC
||
364 current_cpu_data
.cputype
== CPU_R4400MC
)
368 static void r4k_flush_cache_mm(struct mm_struct
*mm
)
370 if (!cpu_has_dc_aliases
)
373 on_each_cpu(local_r4k_flush_cache_mm
, mm
, 1, 1);
376 struct flush_cache_page_args
{
377 struct vm_area_struct
*vma
;
382 static inline void local_r4k_flush_cache_page(void *args
)
384 struct flush_cache_page_args
*fcp_args
= args
;
385 struct vm_area_struct
*vma
= fcp_args
->vma
;
386 unsigned long addr
= fcp_args
->addr
;
387 unsigned long paddr
= fcp_args
->pfn
<< PAGE_SHIFT
;
388 int exec
= vma
->vm_flags
& VM_EXEC
;
389 struct mm_struct
*mm
= vma
->vm_mm
;
396 * If ownes no valid ASID yet, cannot possibly have gotten
397 * this page into the cache.
399 if (cpu_context(smp_processor_id(), mm
) == 0)
403 pgdp
= pgd_offset(mm
, addr
);
404 pudp
= pud_offset(pgdp
, addr
);
405 pmdp
= pmd_offset(pudp
, addr
);
406 ptep
= pte_offset(pmdp
, addr
);
409 * If the page isn't marked valid, the page cannot possibly be
412 if (!(pte_val(*ptep
) & _PAGE_PRESENT
))
416 * Doing flushes for another ASID than the current one is
417 * too difficult since stupid R4k caches do a TLB translation
418 * for every cache flush operation. So we do indexed flushes
419 * in that case, which doesn't overly flush the cache too much.
421 if ((mm
== current
->active_mm
) && (pte_val(*ptep
) & _PAGE_VALID
)) {
422 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
)) {
423 r4k_blast_dcache_page(addr
);
424 if (exec
&& !cpu_icache_snoops_remote_store
)
425 r4k_blast_scache_page(addr
);
428 r4k_blast_icache_page(addr
);
434 * Do indexed flush, too much work to get the (possible) TLB refills
437 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
)) {
438 r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache
?
440 if (exec
&& !cpu_icache_snoops_remote_store
) {
441 r4k_blast_scache_page_indexed(paddr
);
445 if (cpu_has_vtag_icache
) {
446 int cpu
= smp_processor_id();
448 if (cpu_context(cpu
, mm
) != 0)
449 drop_mmu_context(mm
, cpu
);
451 r4k_blast_icache_page_indexed(addr
);
455 static void r4k_flush_cache_page(struct vm_area_struct
*vma
,
456 unsigned long addr
, unsigned long pfn
)
458 struct flush_cache_page_args args
;
464 on_each_cpu(local_r4k_flush_cache_page
, &args
, 1, 1);
467 static inline void local_r4k_flush_data_cache_page(void * addr
)
469 r4k_blast_dcache_page((unsigned long) addr
);
472 static void r4k_flush_data_cache_page(unsigned long addr
)
474 on_each_cpu(local_r4k_flush_data_cache_page
, (void *) addr
, 1, 1);
477 struct flush_icache_range_args
{
482 static inline void local_r4k_flush_icache_range(void *args
)
484 struct flush_icache_range_args
*fir_args
= args
;
485 unsigned long start
= fir_args
->start
;
486 unsigned long end
= fir_args
->end
;
488 if (!cpu_has_ic_fills_f_dc
) {
489 if (end
- start
> dcache_size
) {
492 R4600_HIT_CACHEOP_WAR_IMPL
;
493 protected_blast_dcache_range(start
, end
);
496 if (!cpu_icache_snoops_remote_store
&& scache_size
) {
497 if (end
- start
> scache_size
)
500 protected_blast_scache_range(start
, end
);
504 if (end
- start
> icache_size
)
507 protected_blast_icache_range(start
, end
);
510 static void r4k_flush_icache_range(unsigned long start
, unsigned long end
)
512 struct flush_icache_range_args args
;
517 on_each_cpu(local_r4k_flush_icache_range
, &args
, 1, 1);
518 instruction_hazard();
522 * Ok, this seriously sucks. We use them to flush a user page but don't
523 * know the virtual address, so we have to blast away the whole icache
524 * which is significantly more expensive than the real thing. Otoh we at
525 * least know the kernel address of the page so we can flush it
529 struct flush_icache_page_args
{
530 struct vm_area_struct
*vma
;
534 static inline void local_r4k_flush_icache_page(void *args
)
536 struct flush_icache_page_args
*fip_args
= args
;
537 struct vm_area_struct
*vma
= fip_args
->vma
;
538 struct page
*page
= fip_args
->page
;
541 * Tricky ... Because we don't know the virtual address we've got the
542 * choice of either invalidating the entire primary and secondary
543 * caches or invalidating the secondary caches also. With the subset
544 * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
545 * secondary cache will result in any entries in the primary caches
546 * also getting invalidated which hopefully is a bit more economical.
548 if (cpu_has_subset_pcaches
) {
549 unsigned long addr
= (unsigned long) page_address(page
);
551 r4k_blast_scache_page(addr
);
552 ClearPageDcacheDirty(page
);
557 if (!cpu_has_ic_fills_f_dc
) {
558 unsigned long addr
= (unsigned long) page_address(page
);
559 r4k_blast_dcache_page(addr
);
560 if (!cpu_icache_snoops_remote_store
)
561 r4k_blast_scache_page(addr
);
562 ClearPageDcacheDirty(page
);
566 * We're not sure of the virtual address(es) involved here, so
567 * we have to flush the entire I-cache.
569 if (cpu_has_vtag_icache
) {
570 int cpu
= smp_processor_id();
572 if (cpu_context(cpu
, vma
->vm_mm
) != 0)
573 drop_mmu_context(vma
->vm_mm
, cpu
);
578 static void r4k_flush_icache_page(struct vm_area_struct
*vma
,
581 struct flush_icache_page_args args
;
584 * If there's no context yet, or the page isn't executable, no I-cache
587 if (!(vma
->vm_flags
& VM_EXEC
))
593 on_each_cpu(local_r4k_flush_icache_page
, &args
, 1, 1);
597 #ifdef CONFIG_DMA_NONCOHERENT
599 static void r4k_dma_cache_wback_inv(unsigned long addr
, unsigned long size
)
601 /* Catch bad driver code */
604 if (cpu_has_subset_pcaches
) {
605 if (size
>= scache_size
)
608 blast_scache_range(addr
, addr
+ size
);
613 * Either no secondary cache or the available caches don't have the
614 * subset property so we have to flush the primary caches
617 if (size
>= dcache_size
) {
620 R4600_HIT_CACHEOP_WAR_IMPL
;
621 blast_dcache_range(addr
, addr
+ size
);
624 bc_wback_inv(addr
, size
);
627 static void r4k_dma_cache_inv(unsigned long addr
, unsigned long size
)
629 /* Catch bad driver code */
632 if (cpu_has_subset_pcaches
) {
633 if (size
>= scache_size
)
636 blast_scache_range(addr
, addr
+ size
);
640 if (size
>= dcache_size
) {
643 R4600_HIT_CACHEOP_WAR_IMPL
;
644 blast_dcache_range(addr
, addr
+ size
);
649 #endif /* CONFIG_DMA_NONCOHERENT */
652 * While we're protected against bad userland addresses we don't care
653 * very much about what happens in that case. Usually a segmentation
654 * fault will dump the process later on anyway ...
656 static void local_r4k_flush_cache_sigtramp(void * arg
)
658 unsigned long ic_lsize
= cpu_icache_line_size();
659 unsigned long dc_lsize
= cpu_dcache_line_size();
660 unsigned long sc_lsize
= cpu_scache_line_size();
661 unsigned long addr
= (unsigned long) arg
;
663 R4600_HIT_CACHEOP_WAR_IMPL
;
664 protected_writeback_dcache_line(addr
& ~(dc_lsize
- 1));
665 if (!cpu_icache_snoops_remote_store
&& scache_size
)
666 protected_writeback_scache_line(addr
& ~(sc_lsize
- 1));
667 protected_flush_icache_line(addr
& ~(ic_lsize
- 1));
668 if (MIPS4K_ICACHE_REFILL_WAR
) {
669 __asm__
__volatile__ (
684 : "i" (Hit_Invalidate_I
));
686 if (MIPS_CACHE_SYNC_WAR
)
687 __asm__
__volatile__ ("sync");
690 static void r4k_flush_cache_sigtramp(unsigned long addr
)
692 on_each_cpu(local_r4k_flush_cache_sigtramp
, (void *) addr
, 1, 1);
695 static void r4k_flush_icache_all(void)
697 if (cpu_has_vtag_icache
)
701 static inline void rm7k_erratum31(void)
703 const unsigned long ic_lsize
= 32;
706 /* RM7000 erratum #31. The icache is screwed at startup. */
710 for (addr
= INDEX_BASE
; addr
<= INDEX_BASE
+ 4096; addr
+= ic_lsize
) {
711 __asm__
__volatile__ (
715 "cache\t%1, 0(%0)\n\t"
716 "cache\t%1, 0x1000(%0)\n\t"
717 "cache\t%1, 0x2000(%0)\n\t"
718 "cache\t%1, 0x3000(%0)\n\t"
719 "cache\t%2, 0(%0)\n\t"
720 "cache\t%2, 0x1000(%0)\n\t"
721 "cache\t%2, 0x2000(%0)\n\t"
722 "cache\t%2, 0x3000(%0)\n\t"
723 "cache\t%1, 0(%0)\n\t"
724 "cache\t%1, 0x1000(%0)\n\t"
725 "cache\t%1, 0x2000(%0)\n\t"
726 "cache\t%1, 0x3000(%0)\n\t"
729 : "r" (addr
), "i" (Index_Store_Tag_I
), "i" (Fill
));
733 static char *way_string
[] __initdata
= { NULL
, "direct mapped", "2-way",
734 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
737 static void __init
probe_pcache(void)
739 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
740 unsigned int config
= read_c0_config();
741 unsigned int prid
= read_c0_prid();
742 unsigned long config1
;
745 switch (c
->cputype
) {
746 case CPU_R4600
: /* QED style two way caches? */
750 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
751 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
753 c
->icache
.waybit
= __ffs(icache_size
/2);
755 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
756 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
758 c
->dcache
.waybit
= __ffs(dcache_size
/2);
760 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
765 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
766 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
770 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
771 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
773 c
->dcache
.waybit
= 0;
775 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
779 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
780 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
784 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
785 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
787 c
->dcache
.waybit
= 0;
789 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
790 c
->options
|= MIPS_CPU_PREFETCH
;
800 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
801 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
803 c
->icache
.waybit
= 0; /* doesn't matter */
805 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
806 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
808 c
->dcache
.waybit
= 0; /* does not matter */
810 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
815 icache_size
= 1 << (12 + ((config
& R10K_CONF_IC
) >> 29));
816 c
->icache
.linesz
= 64;
818 c
->icache
.waybit
= 0;
820 dcache_size
= 1 << (12 + ((config
& R10K_CONF_DC
) >> 26));
821 c
->dcache
.linesz
= 32;
823 c
->dcache
.waybit
= 0;
825 c
->options
|= MIPS_CPU_PREFETCH
;
829 write_c0_config(config
& ~CONF_EB
);
831 /* Workaround for cache instruction bug of VR4131 */
832 if (c
->processor_id
== 0x0c80U
|| c
->processor_id
== 0x0c81U
||
833 c
->processor_id
== 0x0c82U
) {
834 config
&= ~0x00000030U
;
835 config
|= 0x00410000U
;
836 write_c0_config(config
);
838 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
839 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
841 c
->icache
.waybit
= __ffs(icache_size
/2);
843 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
844 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
846 c
->dcache
.waybit
= __ffs(dcache_size
/2);
848 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
857 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
858 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
860 c
->icache
.waybit
= 0; /* doesn't matter */
862 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
863 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
865 c
->dcache
.waybit
= 0; /* does not matter */
867 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
874 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
875 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
877 c
->icache
.waybit
= __ffs(icache_size
/ c
->icache
.ways
);
879 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
880 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
882 c
->dcache
.waybit
= __ffs(dcache_size
/ c
->dcache
.ways
);
884 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
885 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
887 c
->options
|= MIPS_CPU_PREFETCH
;
891 if (!(config
& MIPS_CONF_M
))
892 panic("Don't know how to probe P-caches on this cpu.");
895 * So we seem to be a MIPS32 or MIPS64 CPU
896 * So let's probe the I-cache ...
898 config1
= read_c0_config1();
900 if ((lsize
= ((config1
>> 19) & 7)))
901 c
->icache
.linesz
= 2 << lsize
;
903 c
->icache
.linesz
= lsize
;
904 c
->icache
.sets
= 64 << ((config1
>> 22) & 7);
905 c
->icache
.ways
= 1 + ((config1
>> 16) & 7);
907 icache_size
= c
->icache
.sets
*
910 c
->icache
.waybit
= __ffs(icache_size
/c
->icache
.ways
);
912 if (config
& 0x8) /* VI bit */
913 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
916 * Now probe the MIPS32 / MIPS64 data cache.
920 if ((lsize
= ((config1
>> 10) & 7)))
921 c
->dcache
.linesz
= 2 << lsize
;
923 c
->dcache
.linesz
= lsize
;
924 c
->dcache
.sets
= 64 << ((config1
>> 13) & 7);
925 c
->dcache
.ways
= 1 + ((config1
>> 7) & 7);
927 dcache_size
= c
->dcache
.sets
*
930 c
->dcache
.waybit
= __ffs(dcache_size
/c
->dcache
.ways
);
932 c
->options
|= MIPS_CPU_PREFETCH
;
937 * Processor configuration sanity check for the R4000SC erratum
938 * #5. With page sizes larger than 32kB there is no possibility
939 * to get a VCE exception anymore so we don't care about this
940 * misconfiguration. The case is rather theoretical anyway;
941 * presumably no vendor is shipping his hardware in the "bad"
944 if ((prid
& 0xff00) == PRID_IMP_R4000
&& (prid
& 0xff) < 0x40 &&
945 !(config
& CONF_SC
) && c
->icache
.linesz
!= 16 &&
947 panic("Improper R4000SC processor configuration detected");
949 /* compute a couple of other cache variables */
950 c
->icache
.waysize
= icache_size
/ c
->icache
.ways
;
951 c
->dcache
.waysize
= dcache_size
/ c
->dcache
.ways
;
953 c
->icache
.sets
= icache_size
/ (c
->icache
.linesz
* c
->icache
.ways
);
954 c
->dcache
.sets
= dcache_size
/ (c
->dcache
.linesz
* c
->dcache
.ways
);
957 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
958 * 2-way virtually indexed so normally would suffer from aliases. So
959 * normally they'd suffer from aliases but magic in the hardware deals
960 * with that for us so we don't need to take care ourselves.
962 switch (c
->cputype
) {
965 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
971 if (!(read_c0_config7() & (1 << 16)))
973 if (c
->dcache
.waysize
> PAGE_SIZE
)
974 c
->dcache
.flags
|= MIPS_CACHE_ALIASES
;
977 switch (c
->cputype
) {
980 * Some older 20Kc chips doesn't have the 'VI' bit in
981 * the config register.
983 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
991 c
->icache
.flags
|= MIPS_CACHE_IC_F_DC
;
995 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
997 cpu_has_vtag_icache
? "virtually tagged" : "physically tagged",
998 way_string
[c
->icache
.ways
], c
->icache
.linesz
);
1000 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
1001 dcache_size
>> 10, way_string
[c
->dcache
.ways
], c
->dcache
.linesz
);
1005 * If you even _breathe_ on this function, look at the gcc output and make sure
1006 * it does not pop things on and off the stack for the cache sizing loop that
1007 * executes in KSEG1 space or else you will crash and burn badly. You have
1010 static int __init
probe_scache(void)
1012 extern unsigned long stext
;
1013 unsigned long flags
, addr
, begin
, end
, pow2
;
1014 unsigned int config
= read_c0_config();
1015 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1018 if (config
& CONF_SC
)
1021 begin
= (unsigned long) &stext
;
1022 begin
&= ~((4 * 1024 * 1024) - 1);
1023 end
= begin
+ (4 * 1024 * 1024);
1026 * This is such a bitch, you'd think they would make it easy to do
1027 * this. Away you daemons of stupidity!
1029 local_irq_save(flags
);
1031 /* Fill each size-multiple cache line with a valid tag. */
1033 for (addr
= begin
; addr
< end
; addr
= (begin
+ pow2
)) {
1034 unsigned long *p
= (unsigned long *) addr
;
1035 __asm__
__volatile__("nop" : : "r" (*p
)); /* whee... */
1039 /* Load first line with zero (therefore invalid) tag. */
1042 __asm__
__volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1043 cache_op(Index_Store_Tag_I
, begin
);
1044 cache_op(Index_Store_Tag_D
, begin
);
1045 cache_op(Index_Store_Tag_SD
, begin
);
1047 /* Now search for the wrap around point. */
1048 pow2
= (128 * 1024);
1050 for (addr
= begin
+ (128 * 1024); addr
< end
; addr
= begin
+ pow2
) {
1051 cache_op(Index_Load_Tag_SD
, addr
);
1052 __asm__
__volatile__("nop; nop; nop; nop;"); /* hazard... */
1053 if (!read_c0_taglo())
1057 local_irq_restore(flags
);
1061 c
->scache
.linesz
= 16 << ((config
& R4K_CONF_SB
) >> 22);
1063 c
->dcache
.waybit
= 0; /* does not matter */
1068 extern int r5k_sc_init(void);
1069 extern int rm7k_sc_init(void);
1071 static void __init
setup_scache(void)
1073 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1074 unsigned int config
= read_c0_config();
1078 * Do the probing thing on R4000SC and R4400SC processors. Other
1079 * processors don't have a S-cache that would be relevant to the
1080 * Linux memory managment.
1082 switch (c
->cputype
) {
1087 sc_present
= run_uncached(probe_scache
);
1089 c
->options
|= MIPS_CPU_CACHE_CDEX_S
;
1094 scache_size
= 0x80000 << ((config
& R10K_CONF_SS
) >> 16);
1095 c
->scache
.linesz
= 64 << ((config
>> 13) & 1);
1097 c
->scache
.waybit
= 0;
1103 #ifdef CONFIG_R5000_CPU_SCACHE
1110 #ifdef CONFIG_RM7000_CPU_SCACHE
1122 if ((c
->isa_level
== MIPS_CPU_ISA_M32R1
||
1123 c
->isa_level
== MIPS_CPU_ISA_M64R1
) &&
1124 !(c
->scache
.flags
& MIPS_CACHE_NOT_PRESENT
))
1125 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1127 /* compute a couple of other cache variables */
1128 c
->scache
.waysize
= scache_size
/ c
->scache
.ways
;
1130 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1132 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1133 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1135 c
->options
|= MIPS_CPU_SUBSET_CACHES
;
1138 static inline void coherency_setup(void)
1140 change_c0_config(CONF_CM_CMASK
, CONF_CM_DEFAULT
);
1143 * c0_status.cu=0 specifies that updates by the sc instruction use
1144 * the coherency mode specified by the TLB; 1 means cachable
1145 * coherent update on write will be used. Not all processors have
1146 * this bit and; some wire it to zero, others like Toshiba had the
1147 * silly idea of putting something else there ...
1149 switch (current_cpu_data
.cputype
) {
1156 clear_c0_config(CONF_CU
);
1161 void __init
r4k_cache_init(void)
1163 extern void build_clear_page(void);
1164 extern void build_copy_page(void);
1165 extern char except_vec2_generic
;
1166 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1168 /* Default cache error handler for R4000 and R5000 family */
1169 set_uncached_handler (0x100, &except_vec2_generic
, 0x80);
1174 r4k_blast_dcache_page_setup();
1175 r4k_blast_dcache_page_indexed_setup();
1176 r4k_blast_dcache_setup();
1177 r4k_blast_icache_page_setup();
1178 r4k_blast_icache_page_indexed_setup();
1179 r4k_blast_icache_setup();
1180 r4k_blast_scache_page_setup();
1181 r4k_blast_scache_page_indexed_setup();
1182 r4k_blast_scache_setup();
1185 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1186 * This code supports virtually indexed processors and will be
1187 * unnecessarily inefficient on physically indexed processors.
1189 shm_align_mask
= max_t( unsigned long,
1190 c
->dcache
.sets
* c
->dcache
.linesz
- 1,
1193 flush_cache_all
= r4k_flush_cache_all
;
1194 __flush_cache_all
= r4k___flush_cache_all
;
1195 flush_cache_mm
= r4k_flush_cache_mm
;
1196 flush_cache_page
= r4k_flush_cache_page
;
1197 flush_icache_page
= r4k_flush_icache_page
;
1198 flush_cache_range
= r4k_flush_cache_range
;
1200 flush_cache_sigtramp
= r4k_flush_cache_sigtramp
;
1201 flush_icache_all
= r4k_flush_icache_all
;
1202 local_flush_data_cache_page
= local_r4k_flush_data_cache_page
;
1203 flush_data_cache_page
= r4k_flush_data_cache_page
;
1204 flush_icache_range
= r4k_flush_icache_range
;
1206 #ifdef CONFIG_DMA_NONCOHERENT
1207 _dma_cache_wback_inv
= r4k_dma_cache_wback_inv
;
1208 _dma_cache_wback
= r4k_dma_cache_wback_inv
;
1209 _dma_cache_inv
= r4k_dma_cache_inv
;
1214 local_r4k___flush_cache_all(NULL
);