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[PATCH] sata_sis: Fix typo in sata port2 initialisation
[linux-2.6/sactl.git] / drivers / scsi / sata_sis.c
blob237c1986f0128628743ea5c731256319b81002a1
1 /*
2 * sata_sis.c - Silicon Integrated Systems SATA
3 *
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 Uwe Koziolek
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/config.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include "scsi.h"
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
44
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "0.5"
47
48 enum {
49 sis_180 = 0,
50 SIS_SCR_PCI_BAR = 5,
51
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
58 SIS_PMR_COMBINED = 0x30,
59
60 /* random bits */
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
62
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
64 };
65
66 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
67 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
68 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
69
70 static struct pci_device_id sis_pci_tbl[] = {
71 { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
72 { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
73 { PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
74 { } /* terminate list */
75 };
76
77
78 static struct pci_driver sis_pci_driver = {
79 .name = DRV_NAME,
80 .id_table = sis_pci_tbl,
81 .probe = sis_init_one,
82 .remove = ata_pci_remove_one,
83 };
84
85 static Scsi_Host_Template sis_sht = {
86 .module = THIS_MODULE,
87 .name = DRV_NAME,
88 .ioctl = ata_scsi_ioctl,
89 .queuecommand = ata_scsi_queuecmd,
90 .eh_strategy_handler = ata_scsi_error,
91 .can_queue = ATA_DEF_QUEUE,
92 .this_id = ATA_SHT_THIS_ID,
93 .sg_tablesize = ATA_MAX_PRD,
94 .max_sectors = ATA_MAX_SECTORS,
95 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
96 .emulated = ATA_SHT_EMULATED,
97 .use_clustering = ATA_SHT_USE_CLUSTERING,
98 .proc_name = DRV_NAME,
99 .dma_boundary = ATA_DMA_BOUNDARY,
100 .slave_configure = ata_scsi_slave_config,
101 .bios_param = ata_std_bios_param,
102 .ordered_flush = 1,
103 };
104
105 static struct ata_port_operations sis_ops = {
106 .port_disable = ata_port_disable,
107 .tf_load = ata_tf_load,
108 .tf_read = ata_tf_read,
109 .check_status = ata_check_status,
110 .exec_command = ata_exec_command,
111 .dev_select = ata_std_dev_select,
112 .phy_reset = sata_phy_reset,
113 .bmdma_setup = ata_bmdma_setup,
114 .bmdma_start = ata_bmdma_start,
115 .bmdma_stop = ata_bmdma_stop,
116 .bmdma_status = ata_bmdma_status,
117 .qc_prep = ata_qc_prep,
118 .qc_issue = ata_qc_issue_prot,
119 .eng_timeout = ata_eng_timeout,
120 .irq_handler = ata_interrupt,
121 .irq_clear = ata_bmdma_irq_clear,
122 .scr_read = sis_scr_read,
123 .scr_write = sis_scr_write,
124 .port_start = ata_port_start,
125 .port_stop = ata_port_stop,
126 .host_stop = ata_host_stop,
127 };
128
129 static struct ata_port_info sis_port_info = {
130 .sht = &sis_sht,
131 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
132 ATA_FLAG_NO_LEGACY,
133 .pio_mask = 0x1f,
134 .mwdma_mask = 0x7,
135 .udma_mask = 0x7f,
136 .port_ops = &sis_ops,
137 };
138
139
140 MODULE_AUTHOR("Uwe Koziolek");
141 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
142 MODULE_LICENSE("GPL");
143 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
144 MODULE_VERSION(DRV_VERSION);
145
146 static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
147 {
148 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
149
150 if (port_no) {
151 if (device == 0x182)
152 addr += SIS182_SATA1_OFS;
153 else
154 addr += SIS180_SATA1_OFS;
155 }
156
157 return addr;
158 }
159
160 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
161 {
162 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
163 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
164 u32 val, val2;
165 u8 pmr;
166
167 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
168 return 0xffffffff;
169
170 pci_read_config_byte(pdev, SIS_PMR, &pmr);
171
172 pci_read_config_dword(pdev, cfg_addr, &val);
173
174 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
175 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
176
177 return val|val2;
178 }
179
180 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
181 {
182 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
183 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
184 u8 pmr;
185
186 if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
187 return;
188
189 pci_read_config_byte(pdev, SIS_PMR, &pmr);
190
191 pci_write_config_dword(pdev, cfg_addr, val);
192
193 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
194 pci_write_config_dword(pdev, cfg_addr+0x10, val);
195 }
196
197 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
198 {
199 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
200 u32 val, val2 = 0;
201 u8 pmr;
202
203 if (sc_reg > SCR_CONTROL)
204 return 0xffffffffU;
205
206 if (ap->flags & SIS_FLAG_CFGSCR)
207 return sis_scr_cfg_read(ap, sc_reg);
208
209 pci_read_config_byte(pdev, SIS_PMR, &pmr);
210
211 val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
212
213 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
214 val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
215
216 return val | val2;
217 }
218
219 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
220 {
221 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
222 u8 pmr;
223
224 if (sc_reg > SCR_CONTROL)
225 return;
226
227 pci_read_config_byte(pdev, SIS_PMR, &pmr);
228
229 if (ap->flags & SIS_FLAG_CFGSCR)
230 sis_scr_cfg_write(ap, sc_reg, val);
231 else {
232 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
233 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
234 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
235 }
236 }
237
238 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
239 {
240 struct ata_probe_ent *probe_ent = NULL;
241 int rc;
242 u32 genctl;
243 struct ata_port_info *ppi;
244 int pci_dev_busy = 0;
245 u8 pmr;
246 u8 port2_start;
247
248 rc = pci_enable_device(pdev);
249 if (rc)
250 return rc;
251
252 rc = pci_request_regions(pdev, DRV_NAME);
253 if (rc) {
254 pci_dev_busy = 1;
255 goto err_out;
256 }
257
258 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
259 if (rc)
260 goto err_out_regions;
261 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
262 if (rc)
263 goto err_out_regions;
264
265 ppi = &sis_port_info;
266 probe_ent = ata_pci_init_native_mode(pdev, &ppi);
267 if (!probe_ent) {
268 rc = -ENOMEM;
269 goto err_out_regions;
270 }
271
272 /* check and see if the SCRs are in IO space or PCI cfg space */
273 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
274 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
275 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
276
277 /* if hardware thinks SCRs are in IO space, but there are
278 * no IO resources assigned, change to PCI cfg space.
279 */
280 if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
281 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
282 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
283 genctl &= ~GENCTL_IOMAPPED_SCR;
284 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
285 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
286 }
287
288 pci_read_config_byte(pdev, SIS_PMR, &pmr);
289 if (ent->device != 0x182) {
290 if ((pmr & SIS_PMR_COMBINED) == 0) {
291 printk(KERN_INFO "sata_sis: Detected SiS 180/181 chipset in SATA mode\n");
292 port2_start = 64;
293 }
294 else {
295 printk(KERN_INFO "sata_sis: Detected SiS 180/181 chipset in combined mode\n");
296 port2_start=0;
297 }
298 }
299 else {
300 printk(KERN_INFO "sata_sis: Detected SiS 182 chipset\n");
301 port2_start = 0x20;
302 }
303
304 if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
305 probe_ent->port[0].scr_addr =
306 pci_resource_start(pdev, SIS_SCR_PCI_BAR);
307 probe_ent->port[1].scr_addr =
308 pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
309 }
310
311 pci_set_master(pdev);
312 pci_intx(pdev, 1);
313
314 /* FIXME: check ata_device_add return value */
315 ata_device_add(probe_ent);
316 kfree(probe_ent);
317
318 return 0;
319
320 err_out_regions:
321 pci_release_regions(pdev);
322
323 err_out:
324 if (!pci_dev_busy)
325 pci_disable_device(pdev);
326 return rc;
327
328 }
329
330 static int __init sis_init(void)
331 {
332 return pci_module_init(&sis_pci_driver);
333 }
334
335 static void __exit sis_exit(void)
336 {
337 pci_unregister_driver(&sis_pci_driver);
338 }
339
340 module_init(sis_init);
341 module_exit(sis_exit);
342
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