2 * include/asm-x86_64/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_X86_64_PROCESSOR_H
8 #define __ASM_X86_64_PROCESSOR_H
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
15 #include <linux/config.h>
16 #include <linux/threads.h>
18 #include <asm/current.h>
19 #include <asm/system.h>
20 #include <asm/mmsegment.h>
21 #include <asm/percpu.h>
22 #include <linux/personality.h>
24 #define TF_MASK 0x00000100
25 #define IF_MASK 0x00000200
26 #define IOPL_MASK 0x00003000
27 #define NT_MASK 0x00004000
28 #define VM_MASK 0x00020000
29 #define AC_MASK 0x00040000
30 #define VIF_MASK 0x00080000 /* virtual interrupt flag */
31 #define VIP_MASK 0x00100000 /* virtual interrupt pending */
32 #define ID_MASK 0x00200000
34 #define desc_empty(desc) \
35 (!((desc)->a + (desc)->b))
37 #define desc_equal(desc1, desc2) \
38 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
41 * Default implementation of macro that returns current
42 * instruction pointer ("program counter").
44 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
47 * CPU type and hardware bug flags. Kept separately for each CPU.
51 __u8 x86
; /* CPU family */
52 __u8 x86_vendor
; /* CPU vendor */
55 int cpuid_level
; /* Maximum supported CPUID level, -1=no CPUID */
56 __u32 x86_capability
[NCAPINTS
];
57 char x86_vendor_id
[16];
58 char x86_model_id
[64];
59 int x86_cache_size
; /* in KB */
61 int x86_cache_alignment
;
62 int x86_tlbsize
; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
63 __u8 x86_virt_bits
, x86_phys_bits
;
66 __u32 extended_cpuid_level
; /* Max extended CPUID function supported */
67 unsigned long loops_per_jiffy
;
68 } ____cacheline_aligned
;
70 #define X86_VENDOR_INTEL 0
71 #define X86_VENDOR_CYRIX 1
72 #define X86_VENDOR_AMD 2
73 #define X86_VENDOR_UMC 3
74 #define X86_VENDOR_NEXGEN 4
75 #define X86_VENDOR_CENTAUR 5
76 #define X86_VENDOR_RISE 6
77 #define X86_VENDOR_TRANSMETA 7
78 #define X86_VENDOR_NUM 8
79 #define X86_VENDOR_UNKNOWN 0xff
82 extern struct cpuinfo_x86 cpu_data
[];
83 #define current_cpu_data cpu_data[smp_processor_id()]
85 #define cpu_data (&boot_cpu_data)
86 #define current_cpu_data boot_cpu_data
89 extern char ignore_irq13
;
91 extern void identify_cpu(struct cpuinfo_x86
*);
92 extern void print_cpu_info(struct cpuinfo_x86
*);
93 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
98 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
99 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
100 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
101 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
102 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
103 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
104 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
105 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
106 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
107 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
108 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
109 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
110 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
111 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
112 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
113 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
114 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
117 * Intel CPU features in CR4
119 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
120 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
121 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
122 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
123 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
124 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
125 #define X86_CR4_MCE 0x0040 /* Machine check enable */
126 #define X86_CR4_PGE 0x0080 /* enable global pages */
127 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
128 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
129 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
132 * Save the cr4 feature set we're using (ie
133 * Pentium 4MB enable and PPro Global page
134 * enable), so that any CPU's that boot up
135 * after us can get the correct flags.
137 extern unsigned long mmu_cr4_features
;
139 static inline void set_in_cr4 (unsigned long mask
)
141 mmu_cr4_features
|= mask
;
142 __asm__("movq %%cr4,%%rax\n\t"
149 static inline void clear_in_cr4 (unsigned long mask
)
151 mmu_cr4_features
&= ~mask
;
152 __asm__("movq %%cr4,%%rax\n\t"
161 * User space process size. 47bits minus one guard page.
163 #define TASK_SIZE64 (0x800000000000UL - 4096)
165 /* This decides where the kernel will search for a free chunk of vm
166 * space during mmap's.
168 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
170 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
171 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
173 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
178 #define IO_BITMAP_BITS 65536
179 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
180 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
181 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
182 #define INVALID_IO_BITMAP_OFFSET 0x8000
184 struct i387_fxsave_struct
{
193 u32 st_space
[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
194 u32 xmm_space
[64]; /* 16*16 bytes for each XMM-reg = 128 bytes */
196 } __attribute__ ((aligned (16)));
199 struct i387_fxsave_struct fxsave
;
214 * The extra 1 is there because the CPU will access an
215 * additional byte beyond the end of the IO permission
216 * bitmap. The extra byte must be all 1 bits, and must
217 * be within the limit. Thus we have:
219 * 128 bytes, the bitmap itself, for ports 0..0x3ff
220 * 8 bytes, for an extra "long" of ~0UL
222 unsigned long io_bitmap
[IO_BITMAP_LONGS
+ 1];
223 } __attribute__((packed
)) ____cacheline_aligned
;
225 extern struct cpuinfo_x86 boot_cpu_data
;
226 DECLARE_PER_CPU(struct tss_struct
,init_tss
);
228 #define ARCH_MIN_TASKALIGN 16
230 struct thread_struct
{
233 unsigned long userrsp
; /* Copy from PDA */
236 unsigned short es
, ds
, fsindex
, gsindex
;
237 /* Hardware debugging registers */
238 unsigned long debugreg0
;
239 unsigned long debugreg1
;
240 unsigned long debugreg2
;
241 unsigned long debugreg3
;
242 unsigned long debugreg6
;
243 unsigned long debugreg7
;
245 unsigned long cr2
, trap_no
, error_code
;
246 /* floating point info */
247 union i387_union i387
__attribute__((aligned(16)));
248 /* IO permissions. the bitmap could be moved into the GDT, that would make
249 switch faster for a limited number of ioperm using tasks. -AK */
251 unsigned long *io_bitmap_ptr
;
252 unsigned io_bitmap_max
;
253 /* cached TLS descriptors. */
254 u64 tls_array
[GDT_ENTRY_TLS_ENTRIES
];
255 } __attribute__((aligned(16)));
257 #define INIT_THREAD {}
260 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
262 #define STACKFAULT_STACK 1
263 #define DOUBLEFAULT_STACK 2
265 #define DEBUG_STACK 4
267 #define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
268 #define EXCEPTION_STKSZ (PAGE_SIZE << EXCEPTION_STACK_ORDER)
269 #define EXCEPTION_STACK_ORDER 0
271 #define start_thread(regs,new_rip,new_rsp) do { \
272 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
274 (regs)->rip = (new_rip); \
275 (regs)->rsp = (new_rsp); \
276 write_pda(oldrsp, (new_rsp)); \
277 (regs)->cs = __USER_CS; \
278 (regs)->ss = __USER_DS; \
279 (regs)->eflags = 0x200; \
283 #define get_debugreg(var, register) \
284 __asm__("movq %%db" #register ", %0" \
286 #define set_debugreg(value, register) \
287 __asm__("movq %0,%%db" #register \
294 /* Free all resources held by a thread. */
295 extern void release_thread(struct task_struct
*);
297 /* Prepare to copy thread state - unlazy all lazy status */
298 extern void prepare_to_copy(struct task_struct
*tsk
);
301 * create a kernel thread without removing it from tasklists
303 extern long kernel_thread(int (*fn
)(void *), void * arg
, unsigned long flags
);
306 * Return saved PC of a blocked thread.
307 * What is this good for? it will be always the scheduler or ret_from_fork.
309 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.rsp - 8))
311 extern unsigned long get_wchan(struct task_struct
*p
);
312 #define KSTK_EIP(tsk) \
313 (((struct pt_regs *)(tsk->thread.rsp0 - sizeof(struct pt_regs)))->rip)
314 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
317 struct microcode_header
{
325 unsigned int datasize
;
326 unsigned int totalsize
;
327 unsigned int reserved
[3];
331 struct microcode_header hdr
;
332 unsigned int bits
[0];
335 typedef struct microcode microcode_t
;
336 typedef struct microcode_header microcode_header_t
;
338 /* microcode format is extended from prescott processors */
339 struct extended_signature
{
345 struct extended_sigtable
{
348 unsigned int reserved
[3];
349 struct extended_signature sigs
[0];
352 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
353 #define MICROCODE_IOCFREE _IO('6',0)
356 #define ASM_NOP1 K8_NOP1
357 #define ASM_NOP2 K8_NOP2
358 #define ASM_NOP3 K8_NOP3
359 #define ASM_NOP4 K8_NOP4
360 #define ASM_NOP5 K8_NOP5
361 #define ASM_NOP6 K8_NOP6
362 #define ASM_NOP7 K8_NOP7
363 #define ASM_NOP8 K8_NOP8
366 #define K8_NOP1 ".byte 0x90\n"
367 #define K8_NOP2 ".byte 0x66,0x90\n"
368 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
369 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
370 #define K8_NOP5 K8_NOP3 K8_NOP2
371 #define K8_NOP6 K8_NOP3 K8_NOP3
372 #define K8_NOP7 K8_NOP4 K8_NOP3
373 #define K8_NOP8 K8_NOP4 K8_NOP4
375 #define ASM_NOP_MAX 8
377 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
378 extern inline void rep_nop(void)
380 __asm__
__volatile__("rep;nop": : :"memory");
383 /* Stop speculative execution */
384 extern inline void sync_core(void)
387 asm volatile("cpuid" : "=a" (tmp
) : "0" (1) : "ebx","ecx","edx","memory");
390 #define cpu_has_fpu 1
392 #define ARCH_HAS_PREFETCH
393 static inline void prefetch(void *x
)
395 asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x
));
398 #define ARCH_HAS_PREFETCHW 1
399 static inline void prefetchw(void *x
)
401 alternative_input(ASM_NOP5
,
407 #define ARCH_HAS_SPINLOCK_PREFETCH 1
409 #define spin_lock_prefetch(x) prefetchw(x)
411 #define cpu_relax() rep_nop()
414 * NSC/Cyrix CPU configuration register indexes
416 #define CX86_CCR0 0xc0
417 #define CX86_CCR1 0xc1
418 #define CX86_CCR2 0xc2
419 #define CX86_CCR3 0xc3
420 #define CX86_CCR4 0xe8
421 #define CX86_CCR5 0xe9
422 #define CX86_CCR6 0xea
423 #define CX86_CCR7 0xeb
424 #define CX86_DIR0 0xfe
425 #define CX86_DIR1 0xff
426 #define CX86_ARR_BASE 0xc4
427 #define CX86_RCR_BASE 0xdc
430 * NSC/Cyrix CPU indexed register access macros
433 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
435 #define setCx86(reg, data) do { \
437 outb((data), 0x23); \
440 static inline void __monitor(const void *eax
, unsigned long ecx
,
443 /* "monitor %eax,%ecx,%edx;" */
445 ".byte 0x0f,0x01,0xc8;"
446 : :"a" (eax
), "c" (ecx
), "d"(edx
));
449 static inline void __mwait(unsigned long eax
, unsigned long ecx
)
451 /* "mwait %eax,%ecx;" */
453 ".byte 0x0f,0x01,0xc9;"
454 : :"a" (eax
), "c" (ecx
));
457 #define stack_current() \
459 struct thread_info *ti; \
460 asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
464 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
466 extern unsigned long boot_option_idle_override
;
467 /* Boot loader type from the setup header */
468 extern int bootloader_type
;
470 #endif /* __ASM_X86_64_PROCESSOR_H */