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[MIPS] IP27: Move definition of nic_t to its sole user.
[linux-2.6/sactl.git] / drivers / ata / sata_promise.c
blobf055874a6ec5d303a11960fe88605c8975e7923c
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.05"
50
51
52 enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_FLASH_CTL = 0x44, /* Flash control register */
56 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
57 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
58 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
59 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
60 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
61 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
62
63 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
65
66 board_2037x = 0, /* FastTrak S150 TX2plus */
67 board_20319 = 1, /* FastTrak S150 TX4 */
68 board_20619 = 2, /* FastTrak TX4000 */
69 board_2057x = 3, /* SATAII150 Tx2plus */
70 board_40518 = 4, /* SATAII150 Tx4 */
71
72 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
73
74 /* PDC_CTLSTAT bit definitions */
75 PDC_DMA_ENABLE = (1 << 7),
76 PDC_IRQ_DISABLE = (1 << 10),
77 PDC_RESET = (1 << 11), /* HDMA reset */
78
79 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
80 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
81 ATA_FLAG_PIO_POLLING,
82
83 /* hp->flags bits */
84 PDC_FLAG_GEN_II = (1 << 0),
85 };
86
87
88 struct pdc_port_priv {
89 u8 *pkt;
90 dma_addr_t pkt_dma;
91 };
92
93 struct pdc_host_priv {
94 unsigned long flags;
95 };
96
97 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
98 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
99 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
100 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
101 static void pdc_eng_timeout(struct ata_port *ap);
102 static int pdc_port_start(struct ata_port *ap);
103 static void pdc_port_stop(struct ata_port *ap);
104 static void pdc_pata_phy_reset(struct ata_port *ap);
105 static void pdc_qc_prep(struct ata_queued_cmd *qc);
106 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
107 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
108 static void pdc_irq_clear(struct ata_port *ap);
109 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
110 static void pdc_host_stop(struct ata_host *host);
111 static void pdc_freeze(struct ata_port *ap);
112 static void pdc_thaw(struct ata_port *ap);
113 static void pdc_error_handler(struct ata_port *ap);
114 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
115
116
117 static struct scsi_host_template pdc_ata_sht = {
118 .module = THIS_MODULE,
119 .name = DRV_NAME,
120 .ioctl = ata_scsi_ioctl,
121 .queuecommand = ata_scsi_queuecmd,
122 .can_queue = ATA_DEF_QUEUE,
123 .this_id = ATA_SHT_THIS_ID,
124 .sg_tablesize = LIBATA_MAX_PRD,
125 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
126 .emulated = ATA_SHT_EMULATED,
127 .use_clustering = ATA_SHT_USE_CLUSTERING,
128 .proc_name = DRV_NAME,
129 .dma_boundary = ATA_DMA_BOUNDARY,
130 .slave_configure = ata_scsi_slave_config,
131 .slave_destroy = ata_scsi_slave_destroy,
132 .bios_param = ata_std_bios_param,
133 };
134
135 static const struct ata_port_operations pdc_sata_ops = {
136 .port_disable = ata_port_disable,
137 .tf_load = pdc_tf_load_mmio,
138 .tf_read = ata_tf_read,
139 .check_status = ata_check_status,
140 .exec_command = pdc_exec_command_mmio,
141 .dev_select = ata_std_dev_select,
142
143 .qc_prep = pdc_qc_prep,
144 .qc_issue = pdc_qc_issue_prot,
145 .freeze = pdc_freeze,
146 .thaw = pdc_thaw,
147 .error_handler = pdc_error_handler,
148 .post_internal_cmd = pdc_post_internal_cmd,
149 .data_xfer = ata_mmio_data_xfer,
150 .irq_handler = pdc_interrupt,
151 .irq_clear = pdc_irq_clear,
152
153 .scr_read = pdc_sata_scr_read,
154 .scr_write = pdc_sata_scr_write,
155 .port_start = pdc_port_start,
156 .port_stop = pdc_port_stop,
157 .host_stop = pdc_host_stop,
158 };
159
160 static const struct ata_port_operations pdc_pata_ops = {
161 .port_disable = ata_port_disable,
162 .tf_load = pdc_tf_load_mmio,
163 .tf_read = ata_tf_read,
164 .check_status = ata_check_status,
165 .exec_command = pdc_exec_command_mmio,
166 .dev_select = ata_std_dev_select,
167
168 .phy_reset = pdc_pata_phy_reset,
169
170 .qc_prep = pdc_qc_prep,
171 .qc_issue = pdc_qc_issue_prot,
172 .data_xfer = ata_mmio_data_xfer,
173 .eng_timeout = pdc_eng_timeout,
174 .irq_handler = pdc_interrupt,
175 .irq_clear = pdc_irq_clear,
176
177 .port_start = pdc_port_start,
178 .port_stop = pdc_port_stop,
179 .host_stop = pdc_host_stop,
180 };
181
182 static const struct ata_port_info pdc_port_info[] = {
183 /* board_2037x */
184 {
185 .sht = &pdc_ata_sht,
186 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
187 .pio_mask = 0x1f, /* pio0-4 */
188 .mwdma_mask = 0x07, /* mwdma0-2 */
189 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
190 .port_ops = &pdc_sata_ops,
191 },
192
193 /* board_20319 */
194 {
195 .sht = &pdc_ata_sht,
196 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
197 .pio_mask = 0x1f, /* pio0-4 */
198 .mwdma_mask = 0x07, /* mwdma0-2 */
199 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
200 .port_ops = &pdc_sata_ops,
201 },
202
203 /* board_20619 */
204 {
205 .sht = &pdc_ata_sht,
206 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
207 .pio_mask = 0x1f, /* pio0-4 */
208 .mwdma_mask = 0x07, /* mwdma0-2 */
209 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
210 .port_ops = &pdc_pata_ops,
211 },
212
213 /* board_2057x */
214 {
215 .sht = &pdc_ata_sht,
216 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
217 .pio_mask = 0x1f, /* pio0-4 */
218 .mwdma_mask = 0x07, /* mwdma0-2 */
219 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
220 .port_ops = &pdc_sata_ops,
221 },
222
223 /* board_40518 */
224 {
225 .sht = &pdc_ata_sht,
226 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
227 .pio_mask = 0x1f, /* pio0-4 */
228 .mwdma_mask = 0x07, /* mwdma0-2 */
229 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
230 .port_ops = &pdc_sata_ops,
231 },
232 };
233
234 static const struct pci_device_id pdc_ata_pci_tbl[] = {
235 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
236 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
237 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
238 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
239 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
240 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
241 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
242 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
243 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
244 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
245
246 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
247 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
248 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
249 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
250 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
251 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
252
253 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
254
255 { } /* terminate list */
256 };
257
258
259 static struct pci_driver pdc_ata_pci_driver = {
260 .name = DRV_NAME,
261 .id_table = pdc_ata_pci_tbl,
262 .probe = pdc_ata_init_one,
263 .remove = ata_pci_remove_one,
264 };
265
266
267 static int pdc_port_start(struct ata_port *ap)
268 {
269 struct device *dev = ap->host->dev;
270 struct pdc_host_priv *hp = ap->host->private_data;
271 struct pdc_port_priv *pp;
272 int rc;
273
274 rc = ata_port_start(ap);
275 if (rc)
276 return rc;
277
278 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
279 if (!pp) {
280 rc = -ENOMEM;
281 goto err_out;
282 }
283
284 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
285 if (!pp->pkt) {
286 rc = -ENOMEM;
287 goto err_out_kfree;
288 }
289
290 ap->private_data = pp;
291
292 /* fix up PHYMODE4 align timing */
293 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
294 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
295 unsigned int tmp;
296
297 tmp = readl(mmio + 0x014);
298 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
299 writel(tmp, mmio + 0x014);
300 }
301
302 return 0;
303
304 err_out_kfree:
305 kfree(pp);
306 err_out:
307 ata_port_stop(ap);
308 return rc;
309 }
310
311
312 static void pdc_port_stop(struct ata_port *ap)
313 {
314 struct device *dev = ap->host->dev;
315 struct pdc_port_priv *pp = ap->private_data;
316
317 ap->private_data = NULL;
318 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
319 kfree(pp);
320 ata_port_stop(ap);
321 }
322
323
324 static void pdc_host_stop(struct ata_host *host)
325 {
326 struct pdc_host_priv *hp = host->private_data;
327
328 ata_pci_host_stop(host);
329
330 kfree(hp);
331 }
332
333
334 static void pdc_reset_port(struct ata_port *ap)
335 {
336 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
337 unsigned int i;
338 u32 tmp;
339
340 for (i = 11; i > 0; i--) {
341 tmp = readl(mmio);
342 if (tmp & PDC_RESET)
343 break;
344
345 udelay(100);
346
347 tmp |= PDC_RESET;
348 writel(tmp, mmio);
349 }
350
351 tmp &= ~PDC_RESET;
352 writel(tmp, mmio);
353 readl(mmio); /* flush */
354 }
355
356 static void pdc_pata_cbl_detect(struct ata_port *ap)
357 {
358 u8 tmp;
359 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
360
361 tmp = readb(mmio);
362
363 if (tmp & 0x01) {
364 ap->cbl = ATA_CBL_PATA40;
365 ap->udma_mask &= ATA_UDMA_MASK_40C;
366 } else
367 ap->cbl = ATA_CBL_PATA80;
368 }
369
370 static void pdc_pata_phy_reset(struct ata_port *ap)
371 {
372 pdc_pata_cbl_detect(ap);
373 pdc_reset_port(ap);
374 ata_port_probe(ap);
375 ata_bus_reset(ap);
376 }
377
378 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
379 {
380 if (sc_reg > SCR_CONTROL)
381 return 0xffffffffU;
382 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
383 }
384
385
386 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
387 u32 val)
388 {
389 if (sc_reg > SCR_CONTROL)
390 return;
391 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
392 }
393
394 static void pdc_qc_prep(struct ata_queued_cmd *qc)
395 {
396 struct pdc_port_priv *pp = qc->ap->private_data;
397 unsigned int i;
398
399 VPRINTK("ENTER\n");
400
401 switch (qc->tf.protocol) {
402 case ATA_PROT_DMA:
403 ata_qc_prep(qc);
404 /* fall through */
405
406 case ATA_PROT_NODATA:
407 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
408 qc->dev->devno, pp->pkt);
409
410 if (qc->tf.flags & ATA_TFLAG_LBA48)
411 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
412 else
413 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
414
415 pdc_pkt_footer(&qc->tf, pp->pkt, i);
416 break;
417
418 default:
419 break;
420 }
421 }
422
423 static void pdc_freeze(struct ata_port *ap)
424 {
425 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
426 u32 tmp;
427
428 tmp = readl(mmio + PDC_CTLSTAT);
429 tmp |= PDC_IRQ_DISABLE;
430 tmp &= ~PDC_DMA_ENABLE;
431 writel(tmp, mmio + PDC_CTLSTAT);
432 readl(mmio + PDC_CTLSTAT); /* flush */
433 }
434
435 static void pdc_thaw(struct ata_port *ap)
436 {
437 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
438 u32 tmp;
439
440 /* clear IRQ */
441 readl(mmio + PDC_INT_SEQMASK);
442
443 /* turn IRQ back on */
444 tmp = readl(mmio + PDC_CTLSTAT);
445 tmp &= ~PDC_IRQ_DISABLE;
446 writel(tmp, mmio + PDC_CTLSTAT);
447 readl(mmio + PDC_CTLSTAT); /* flush */
448 }
449
450 static void pdc_error_handler(struct ata_port *ap)
451 {
452 ata_reset_fn_t hardreset;
453
454 if (!(ap->pflags & ATA_PFLAG_FROZEN))
455 pdc_reset_port(ap);
456
457 hardreset = NULL;
458 if (sata_scr_valid(ap))
459 hardreset = sata_std_hardreset;
460
461 /* perform recovery */
462 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
463 ata_std_postreset);
464 }
465
466 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
467 {
468 struct ata_port *ap = qc->ap;
469
470 if (qc->flags & ATA_QCFLAG_FAILED)
471 qc->err_mask |= AC_ERR_OTHER;
472
473 /* make DMA engine forget about the failed command */
474 if (qc->err_mask)
475 pdc_reset_port(ap);
476 }
477
478 static void pdc_eng_timeout(struct ata_port *ap)
479 {
480 struct ata_host *host = ap->host;
481 u8 drv_stat;
482 struct ata_queued_cmd *qc;
483 unsigned long flags;
484
485 DPRINTK("ENTER\n");
486
487 spin_lock_irqsave(&host->lock, flags);
488
489 qc = ata_qc_from_tag(ap, ap->active_tag);
490
491 switch (qc->tf.protocol) {
492 case ATA_PROT_DMA:
493 case ATA_PROT_NODATA:
494 ata_port_printk(ap, KERN_ERR, "command timeout\n");
495 drv_stat = ata_wait_idle(ap);
496 qc->err_mask |= __ac_err_mask(drv_stat);
497 break;
498
499 default:
500 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
501
502 ata_port_printk(ap, KERN_ERR,
503 "unknown timeout, cmd 0x%x stat 0x%x\n",
504 qc->tf.command, drv_stat);
505
506 qc->err_mask |= ac_err_mask(drv_stat);
507 break;
508 }
509
510 spin_unlock_irqrestore(&host->lock, flags);
511 ata_eh_qc_complete(qc);
512 DPRINTK("EXIT\n");
513 }
514
515 static inline unsigned int pdc_host_intr( struct ata_port *ap,
516 struct ata_queued_cmd *qc)
517 {
518 unsigned int handled = 0;
519 u32 tmp;
520 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
521
522 tmp = readl(mmio);
523 if (tmp & PDC_ERR_MASK) {
524 qc->err_mask |= AC_ERR_DEV;
525 pdc_reset_port(ap);
526 }
527
528 switch (qc->tf.protocol) {
529 case ATA_PROT_DMA:
530 case ATA_PROT_NODATA:
531 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
532 ata_qc_complete(qc);
533 handled = 1;
534 break;
535
536 default:
537 ap->stats.idle_irq++;
538 break;
539 }
540
541 return handled;
542 }
543
544 static void pdc_irq_clear(struct ata_port *ap)
545 {
546 struct ata_host *host = ap->host;
547 void __iomem *mmio = host->mmio_base;
548
549 readl(mmio + PDC_INT_SEQMASK);
550 }
551
552 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
553 {
554 struct ata_host *host = dev_instance;
555 struct ata_port *ap;
556 u32 mask = 0;
557 unsigned int i, tmp;
558 unsigned int handled = 0;
559 void __iomem *mmio_base;
560
561 VPRINTK("ENTER\n");
562
563 if (!host || !host->mmio_base) {
564 VPRINTK("QUICK EXIT\n");
565 return IRQ_NONE;
566 }
567
568 mmio_base = host->mmio_base;
569
570 /* reading should also clear interrupts */
571 mask = readl(mmio_base + PDC_INT_SEQMASK);
572
573 if (mask == 0xffffffff) {
574 VPRINTK("QUICK EXIT 2\n");
575 return IRQ_NONE;
576 }
577
578 spin_lock(&host->lock);
579
580 mask &= 0xffff; /* only 16 tags possible */
581 if (!mask) {
582 VPRINTK("QUICK EXIT 3\n");
583 goto done_irq;
584 }
585
586 writel(mask, mmio_base + PDC_INT_SEQMASK);
587
588 for (i = 0; i < host->n_ports; i++) {
589 VPRINTK("port %u\n", i);
590 ap = host->ports[i];
591 tmp = mask & (1 << (i + 1));
592 if (tmp && ap &&
593 !(ap->flags & ATA_FLAG_DISABLED)) {
594 struct ata_queued_cmd *qc;
595
596 qc = ata_qc_from_tag(ap, ap->active_tag);
597 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
598 handled += pdc_host_intr(ap, qc);
599 }
600 }
601
602 VPRINTK("EXIT\n");
603
604 done_irq:
605 spin_unlock(&host->lock);
606 return IRQ_RETVAL(handled);
607 }
608
609 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
610 {
611 struct ata_port *ap = qc->ap;
612 struct pdc_port_priv *pp = ap->private_data;
613 unsigned int port_no = ap->port_no;
614 u8 seq = (u8) (port_no + 1);
615
616 VPRINTK("ENTER, ap %p\n", ap);
617
618 writel(0x00000001, ap->host->mmio_base + (seq * 4));
619 readl(ap->host->mmio_base + (seq * 4)); /* flush */
620
621 pp->pkt[2] = seq;
622 wmb(); /* flush PRD, pkt writes */
623 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
624 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
625 }
626
627 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
628 {
629 switch (qc->tf.protocol) {
630 case ATA_PROT_DMA:
631 case ATA_PROT_NODATA:
632 pdc_packet_start(qc);
633 return 0;
634
635 case ATA_PROT_ATAPI_DMA:
636 BUG();
637 break;
638
639 default:
640 break;
641 }
642
643 return ata_qc_issue_prot(qc);
644 }
645
646 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
647 {
648 WARN_ON (tf->protocol == ATA_PROT_DMA ||
649 tf->protocol == ATA_PROT_NODATA);
650 ata_tf_load(ap, tf);
651 }
652
653
654 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
655 {
656 WARN_ON (tf->protocol == ATA_PROT_DMA ||
657 tf->protocol == ATA_PROT_NODATA);
658 ata_exec_command(ap, tf);
659 }
660
661
662 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
663 {
664 port->cmd_addr = base;
665 port->data_addr = base;
666 port->feature_addr =
667 port->error_addr = base + 0x4;
668 port->nsect_addr = base + 0x8;
669 port->lbal_addr = base + 0xc;
670 port->lbam_addr = base + 0x10;
671 port->lbah_addr = base + 0x14;
672 port->device_addr = base + 0x18;
673 port->command_addr =
674 port->status_addr = base + 0x1c;
675 port->altstatus_addr =
676 port->ctl_addr = base + 0x38;
677 }
678
679
680 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
681 {
682 void __iomem *mmio = pe->mmio_base;
683 struct pdc_host_priv *hp = pe->private_data;
684 int hotplug_offset;
685 u32 tmp;
686
687 if (hp->flags & PDC_FLAG_GEN_II)
688 hotplug_offset = PDC2_SATA_PLUG_CSR;
689 else
690 hotplug_offset = PDC_SATA_PLUG_CSR;
691
692 /*
693 * Except for the hotplug stuff, this is voodoo from the
694 * Promise driver. Label this entire section
695 * "TODO: figure out why we do this"
696 */
697
698 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
699 tmp = readl(mmio + PDC_FLASH_CTL);
700 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
701 if (!(hp->flags & PDC_FLAG_GEN_II))
702 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
703 writel(tmp, mmio + PDC_FLASH_CTL);
704
705 /* clear plug/unplug flags for all ports */
706 tmp = readl(mmio + hotplug_offset);
707 writel(tmp | 0xff, mmio + hotplug_offset);
708
709 /* mask plug/unplug ints */
710 tmp = readl(mmio + hotplug_offset);
711 writel(tmp | 0xff0000, mmio + hotplug_offset);
712
713 /* don't initialise TBG or SLEW on 2nd generation chips */
714 if (hp->flags & PDC_FLAG_GEN_II)
715 return;
716
717 /* reduce TBG clock to 133 Mhz. */
718 tmp = readl(mmio + PDC_TBG_MODE);
719 tmp &= ~0x30000; /* clear bit 17, 16*/
720 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
721 writel(tmp, mmio + PDC_TBG_MODE);
722
723 readl(mmio + PDC_TBG_MODE); /* flush */
724 msleep(10);
725
726 /* adjust slew rate control register. */
727 tmp = readl(mmio + PDC_SLEW_CTL);
728 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
729 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
730 writel(tmp, mmio + PDC_SLEW_CTL);
731 }
732
733 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
734 {
735 static int printed_version;
736 struct ata_probe_ent *probe_ent = NULL;
737 struct pdc_host_priv *hp;
738 unsigned long base;
739 void __iomem *mmio_base;
740 unsigned int board_idx = (unsigned int) ent->driver_data;
741 int pci_dev_busy = 0;
742 int rc;
743
744 if (!printed_version++)
745 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
746
747 rc = pci_enable_device(pdev);
748 if (rc)
749 return rc;
750
751 rc = pci_request_regions(pdev, DRV_NAME);
752 if (rc) {
753 pci_dev_busy = 1;
754 goto err_out;
755 }
756
757 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
758 if (rc)
759 goto err_out_regions;
760 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
761 if (rc)
762 goto err_out_regions;
763
764 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
765 if (probe_ent == NULL) {
766 rc = -ENOMEM;
767 goto err_out_regions;
768 }
769
770 probe_ent->dev = pci_dev_to_dev(pdev);
771 INIT_LIST_HEAD(&probe_ent->node);
772
773 mmio_base = pci_iomap(pdev, 3, 0);
774 if (mmio_base == NULL) {
775 rc = -ENOMEM;
776 goto err_out_free_ent;
777 }
778 base = (unsigned long) mmio_base;
779
780 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
781 if (hp == NULL) {
782 rc = -ENOMEM;
783 goto err_out_free_ent;
784 }
785
786 probe_ent->private_data = hp;
787
788 probe_ent->sht = pdc_port_info[board_idx].sht;
789 probe_ent->port_flags = pdc_port_info[board_idx].flags;
790 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
791 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
792 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
793 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
794
795 probe_ent->irq = pdev->irq;
796 probe_ent->irq_flags = IRQF_SHARED;
797 probe_ent->mmio_base = mmio_base;
798
799 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
800 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
801
802 probe_ent->port[0].scr_addr = base + 0x400;
803 probe_ent->port[1].scr_addr = base + 0x500;
804
805 /* notice 4-port boards */
806 switch (board_idx) {
807 case board_40518:
808 hp->flags |= PDC_FLAG_GEN_II;
809 /* Fall through */
810 case board_20319:
811 probe_ent->n_ports = 4;
812
813 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
814 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
815
816 probe_ent->port[2].scr_addr = base + 0x600;
817 probe_ent->port[3].scr_addr = base + 0x700;
818 break;
819 case board_2057x:
820 hp->flags |= PDC_FLAG_GEN_II;
821 /* Fall through */
822 case board_2037x:
823 probe_ent->n_ports = 2;
824 break;
825 case board_20619:
826 probe_ent->n_ports = 4;
827
828 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
829 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
830
831 probe_ent->port[2].scr_addr = base + 0x600;
832 probe_ent->port[3].scr_addr = base + 0x700;
833 break;
834 default:
835 BUG();
836 break;
837 }
838
839 pci_set_master(pdev);
840
841 /* initialize adapter */
842 pdc_host_init(board_idx, probe_ent);
843
844 /* FIXME: Need any other frees than hp? */
845 if (!ata_device_add(probe_ent))
846 kfree(hp);
847
848 kfree(probe_ent);
849
850 return 0;
851
852 err_out_free_ent:
853 kfree(probe_ent);
854 err_out_regions:
855 pci_release_regions(pdev);
856 err_out:
857 if (!pci_dev_busy)
858 pci_disable_device(pdev);
859 return rc;
860 }
861
862
863 static int __init pdc_ata_init(void)
864 {
865 return pci_register_driver(&pdc_ata_pci_driver);
866 }
867
868
869 static void __exit pdc_ata_exit(void)
870 {
871 pci_unregister_driver(&pdc_ata_pci_driver);
872 }
873
874
875 MODULE_AUTHOR("Jeff Garzik");
876 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
877 MODULE_LICENSE("GPL");
878 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
879 MODULE_VERSION(DRV_VERSION);
880
881 module_init(pdc_ata_init);
882 module_exit(pdc_ata_exit);
SocketAccessConTroL development