2 * linux/arch/alpha/kernel/pci_iommu.c
5 #include <linux/kernel.h>
8 #include <linux/slab.h>
9 #include <linux/bootmem.h>
10 #include <linux/scatterlist.h>
11 #include <linux/log2.h>
12 #include <linux/dma-mapping.h>
15 #include <asm/hwrpb.h>
23 # define DBGA(args...) printk(KERN_DEBUG args)
25 # define DBGA(args...)
28 # define DBGA2(args...) printk(KERN_DEBUG args)
30 # define DBGA2(args...)
33 #define DEBUG_NODIRECT 0
34 #define DEBUG_FORCEDAC 0
36 #define ISA_DMA_MASK 0x00ffffff
38 static inline unsigned long
39 mk_iommu_pte(unsigned long paddr
)
41 return (paddr
>> (PAGE_SHIFT
-1)) | 1;
45 calc_npages(long bytes
)
47 return (bytes
+ PAGE_SIZE
- 1) >> PAGE_SHIFT
;
51 /* Return the minimum of MAX or the first power of two larger
55 size_for_memory(unsigned long max
)
57 unsigned long mem
= max_low_pfn
<< PAGE_SHIFT
;
59 max
= roundup_pow_of_two(mem
);
63 struct pci_iommu_arena
* __init
64 iommu_arena_new_node(int nid
, struct pci_controller
*hose
, dma_addr_t base
,
65 unsigned long window_size
, unsigned long align
)
67 unsigned long mem_size
;
68 struct pci_iommu_arena
*arena
;
70 mem_size
= window_size
/ (PAGE_SIZE
/ sizeof(unsigned long));
72 /* Note that the TLB lookup logic uses bitwise concatenation,
73 not addition, so the required arena alignment is based on
74 the size of the window. Retain the align parameter so that
75 particular systems can over-align the arena. */
80 #ifdef CONFIG_DISCONTIGMEM
82 if (!NODE_DATA(nid
) ||
83 (NULL
== (arena
= alloc_bootmem_node(NODE_DATA(nid
),
85 printk("%s: couldn't allocate arena from node %d\n"
86 " falling back to system-wide allocation\n",
88 arena
= alloc_bootmem(sizeof(*arena
));
91 if (!NODE_DATA(nid
) ||
92 (NULL
== (arena
->ptes
= __alloc_bootmem_node(NODE_DATA(nid
),
96 printk("%s: couldn't allocate arena ptes from node %d\n"
97 " falling back to system-wide allocation\n",
99 arena
->ptes
= __alloc_bootmem(mem_size
, align
, 0);
102 #else /* CONFIG_DISCONTIGMEM */
104 arena
= alloc_bootmem(sizeof(*arena
));
105 arena
->ptes
= __alloc_bootmem(mem_size
, align
, 0);
107 #endif /* CONFIG_DISCONTIGMEM */
109 spin_lock_init(&arena
->lock
);
111 arena
->dma_base
= base
;
112 arena
->size
= window_size
;
113 arena
->next_entry
= 0;
115 /* Align allocations to a multiple of a page size. Not needed
116 unless there are chip bugs. */
117 arena
->align_entry
= 1;
122 struct pci_iommu_arena
* __init
123 iommu_arena_new(struct pci_controller
*hose
, dma_addr_t base
,
124 unsigned long window_size
, unsigned long align
)
126 return iommu_arena_new_node(0, hose
, base
, window_size
, align
);
129 /* Must be called with the arena lock held */
131 iommu_arena_find_pages(struct pci_iommu_arena
*arena
, long n
, long mask
)
137 /* Search forward for the first mask-aligned sequence of N free ptes */
139 nent
= arena
->size
>> PAGE_SHIFT
;
140 p
= ALIGN(arena
->next_entry
, mask
+ 1);
144 while (i
< n
&& p
+i
< nent
) {
146 p
= ALIGN(p
+ i
+ 1, mask
+ 1), i
= 0;
154 * Reached the end. Flush the TLB and restart
155 * the search from the beginning.
157 alpha_mv
.mv_pci_tbi(arena
->hose
, 0, -1);
167 /* Success. It's the responsibility of the caller to mark them
168 in use before releasing the lock */
173 iommu_arena_alloc(struct pci_iommu_arena
*arena
, long n
, unsigned int align
)
179 spin_lock_irqsave(&arena
->lock
, flags
);
181 /* Search for N empty ptes */
183 mask
= max(align
, arena
->align_entry
) - 1;
184 p
= iommu_arena_find_pages(arena
, n
, mask
);
186 spin_unlock_irqrestore(&arena
->lock
, flags
);
190 /* Success. Mark them all in use, ie not zero and invalid
191 for the iommu tlb that could load them from under us.
192 The chip specific bits will fill this in with something
193 kosher when we return. */
194 for (i
= 0; i
< n
; ++i
)
195 ptes
[p
+i
] = IOMMU_INVALID_PTE
;
197 arena
->next_entry
= p
+ n
;
198 spin_unlock_irqrestore(&arena
->lock
, flags
);
204 iommu_arena_free(struct pci_iommu_arena
*arena
, long ofs
, long n
)
209 p
= arena
->ptes
+ ofs
;
210 for (i
= 0; i
< n
; ++i
)
214 /* True if the machine supports DAC addressing, and DEV can
215 make use of it given MASK. */
216 static int pci_dac_dma_supported(struct pci_dev
*hwdev
, u64 mask
);
218 /* Map a single buffer of the indicated size for PCI DMA in streaming
219 mode. The 32-bit PCI bus mastering address to use is returned.
220 Once the device is given the dma address, the device owns this memory
221 until either pci_unmap_single or pci_dma_sync_single is performed. */
224 pci_map_single_1(struct pci_dev
*pdev
, void *cpu_addr
, size_t size
,
227 struct pci_controller
*hose
= pdev
? pdev
->sysdata
: pci_isa_hose
;
228 dma_addr_t max_dma
= pdev
? pdev
->dma_mask
: ISA_DMA_MASK
;
229 struct pci_iommu_arena
*arena
;
230 long npages
, dma_ofs
, i
;
233 unsigned int align
= 0;
235 paddr
= __pa(cpu_addr
);
238 /* First check to see if we can use the direct map window. */
239 if (paddr
+ size
+ __direct_map_base
- 1 <= max_dma
240 && paddr
+ size
<= __direct_map_size
) {
241 ret
= paddr
+ __direct_map_base
;
243 DBGA2("pci_map_single: [%p,%lx] -> direct %lx from %p\n",
244 cpu_addr
, size
, ret
, __builtin_return_address(0));
250 /* Next, use DAC if selected earlier. */
252 ret
= paddr
+ alpha_mv
.pci_dac_offset
;
254 DBGA2("pci_map_single: [%p,%lx] -> DAC %lx from %p\n",
255 cpu_addr
, size
, ret
, __builtin_return_address(0));
260 /* If the machine doesn't define a pci_tbi routine, we have to
261 assume it doesn't support sg mapping, and, since we tried to
262 use direct_map above, it now must be considered an error. */
263 if (! alpha_mv
.mv_pci_tbi
) {
264 static int been_here
= 0; /* Only print the message once. */
266 printk(KERN_WARNING
"pci_map_single: no HW sg\n");
272 arena
= hose
->sg_pci
;
273 if (!arena
|| arena
->dma_base
+ arena
->size
- 1 > max_dma
)
274 arena
= hose
->sg_isa
;
276 npages
= calc_npages((paddr
& ~PAGE_MASK
) + size
);
278 /* Force allocation to 64KB boundary for ISA bridges. */
279 if (pdev
&& pdev
== isa_bridge
)
281 dma_ofs
= iommu_arena_alloc(arena
, npages
, align
);
283 printk(KERN_WARNING
"pci_map_single failed: "
284 "could not allocate dma page tables\n");
289 for (i
= 0; i
< npages
; ++i
, paddr
+= PAGE_SIZE
)
290 arena
->ptes
[i
+ dma_ofs
] = mk_iommu_pte(paddr
);
292 ret
= arena
->dma_base
+ dma_ofs
* PAGE_SIZE
;
293 ret
+= (unsigned long)cpu_addr
& ~PAGE_MASK
;
295 DBGA2("pci_map_single: [%p,%lx] np %ld -> sg %lx from %p\n",
296 cpu_addr
, size
, npages
, ret
, __builtin_return_address(0));
302 pci_map_single(struct pci_dev
*pdev
, void *cpu_addr
, size_t size
, int dir
)
306 if (dir
== PCI_DMA_NONE
)
309 dac_allowed
= pdev
? pci_dac_dma_supported(pdev
, pdev
->dma_mask
) : 0;
310 return pci_map_single_1(pdev
, cpu_addr
, size
, dac_allowed
);
312 EXPORT_SYMBOL(pci_map_single
);
315 pci_map_page(struct pci_dev
*pdev
, struct page
*page
, unsigned long offset
,
316 size_t size
, int dir
)
320 if (dir
== PCI_DMA_NONE
)
323 dac_allowed
= pdev
? pci_dac_dma_supported(pdev
, pdev
->dma_mask
) : 0;
324 return pci_map_single_1(pdev
, (char *)page_address(page
) + offset
,
327 EXPORT_SYMBOL(pci_map_page
);
329 /* Unmap a single streaming mode DMA translation. The DMA_ADDR and
330 SIZE must match what was provided for in a previous pci_map_single
331 call. All other usages are undefined. After this call, reads by
332 the cpu to the buffer are guaranteed to see whatever the device
336 pci_unmap_single(struct pci_dev
*pdev
, dma_addr_t dma_addr
, size_t size
,
340 struct pci_controller
*hose
= pdev
? pdev
->sysdata
: pci_isa_hose
;
341 struct pci_iommu_arena
*arena
;
342 long dma_ofs
, npages
;
344 if (direction
== PCI_DMA_NONE
)
347 if (dma_addr
>= __direct_map_base
348 && dma_addr
< __direct_map_base
+ __direct_map_size
) {
351 DBGA2("pci_unmap_single: direct [%lx,%lx] from %p\n",
352 dma_addr
, size
, __builtin_return_address(0));
357 if (dma_addr
> 0xffffffff) {
358 DBGA2("pci64_unmap_single: DAC [%lx,%lx] from %p\n",
359 dma_addr
, size
, __builtin_return_address(0));
363 arena
= hose
->sg_pci
;
364 if (!arena
|| dma_addr
< arena
->dma_base
)
365 arena
= hose
->sg_isa
;
367 dma_ofs
= (dma_addr
- arena
->dma_base
) >> PAGE_SHIFT
;
368 if (dma_ofs
* PAGE_SIZE
>= arena
->size
) {
369 printk(KERN_ERR
"Bogus pci_unmap_single: dma_addr %lx "
370 " base %lx size %x\n", dma_addr
, arena
->dma_base
,
376 npages
= calc_npages((dma_addr
& ~PAGE_MASK
) + size
);
378 spin_lock_irqsave(&arena
->lock
, flags
);
380 iommu_arena_free(arena
, dma_ofs
, npages
);
382 /* If we're freeing ptes above the `next_entry' pointer (they
383 may have snuck back into the TLB since the last wrap flush),
384 we need to flush the TLB before reallocating the latter. */
385 if (dma_ofs
>= arena
->next_entry
)
386 alpha_mv
.mv_pci_tbi(hose
, dma_addr
, dma_addr
+ size
- 1);
388 spin_unlock_irqrestore(&arena
->lock
, flags
);
390 DBGA2("pci_unmap_single: sg [%lx,%lx] np %ld from %p\n",
391 dma_addr
, size
, npages
, __builtin_return_address(0));
393 EXPORT_SYMBOL(pci_unmap_single
);
396 pci_unmap_page(struct pci_dev
*pdev
, dma_addr_t dma_addr
,
397 size_t size
, int direction
)
399 pci_unmap_single(pdev
, dma_addr
, size
, direction
);
401 EXPORT_SYMBOL(pci_unmap_page
);
403 /* Allocate and map kernel buffer using consistent mode DMA for PCI
404 device. Returns non-NULL cpu-view pointer to the buffer if
405 successful and sets *DMA_ADDRP to the pci side dma address as well,
406 else DMA_ADDRP is undefined. */
409 pci_alloc_consistent(struct pci_dev
*pdev
, size_t size
, dma_addr_t
*dma_addrp
)
412 long order
= get_order(size
);
413 gfp_t gfp
= GFP_ATOMIC
;
416 cpu_addr
= (void *)__get_free_pages(gfp
, order
);
418 printk(KERN_INFO
"pci_alloc_consistent: "
419 "get_free_pages failed from %p\n",
420 __builtin_return_address(0));
421 /* ??? Really atomic allocation? Otherwise we could play
422 with vmalloc and sg if we can't find contiguous memory. */
425 memset(cpu_addr
, 0, size
);
427 *dma_addrp
= pci_map_single_1(pdev
, cpu_addr
, size
, 0);
428 if (*dma_addrp
== 0) {
429 free_pages((unsigned long)cpu_addr
, order
);
430 if (alpha_mv
.mv_pci_tbi
|| (gfp
& GFP_DMA
))
432 /* The address doesn't fit required mask and we
433 do not have iommu. Try again with GFP_DMA. */
438 DBGA2("pci_alloc_consistent: %lx -> [%p,%x] from %p\n",
439 size
, cpu_addr
, *dma_addrp
, __builtin_return_address(0));
443 EXPORT_SYMBOL(pci_alloc_consistent
);
445 /* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
446 be values that were returned from pci_alloc_consistent. SIZE must
447 be the same as what as passed into pci_alloc_consistent.
448 References to the memory and mappings associated with CPU_ADDR or
449 DMA_ADDR past this call are illegal. */
452 pci_free_consistent(struct pci_dev
*pdev
, size_t size
, void *cpu_addr
,
455 pci_unmap_single(pdev
, dma_addr
, size
, PCI_DMA_BIDIRECTIONAL
);
456 free_pages((unsigned long)cpu_addr
, get_order(size
));
458 DBGA2("pci_free_consistent: [%x,%lx] from %p\n",
459 dma_addr
, size
, __builtin_return_address(0));
461 EXPORT_SYMBOL(pci_free_consistent
);
463 /* Classify the elements of the scatterlist. Write dma_address
464 of each element with:
465 0 : Followers all physically adjacent.
466 1 : Followers all virtually adjacent.
467 -1 : Not leader, physically adjacent to previous.
468 -2 : Not leader, virtually adjacent to previous.
469 Write dma_length of each leader with the combined lengths of
470 the mergable followers. */
472 #define SG_ENT_VIRT_ADDRESS(SG) (sg_virt((SG)))
473 #define SG_ENT_PHYS_ADDRESS(SG) __pa(SG_ENT_VIRT_ADDRESS(SG))
476 sg_classify(struct device
*dev
, struct scatterlist
*sg
, struct scatterlist
*end
,
479 unsigned long next_paddr
;
480 struct scatterlist
*leader
;
481 long leader_flag
, leader_length
;
482 unsigned int max_seg_size
;
486 leader_length
= leader
->length
;
487 next_paddr
= SG_ENT_PHYS_ADDRESS(leader
) + leader_length
;
489 /* we will not marge sg without device. */
490 max_seg_size
= dev
? dma_get_max_seg_size(dev
) : 0;
491 for (++sg
; sg
< end
; ++sg
) {
492 unsigned long addr
, len
;
493 addr
= SG_ENT_PHYS_ADDRESS(sg
);
496 if (leader_length
+ len
> max_seg_size
)
499 if (next_paddr
== addr
) {
500 sg
->dma_address
= -1;
501 leader_length
+= len
;
502 } else if (((next_paddr
| addr
) & ~PAGE_MASK
) == 0 && virt_ok
) {
503 sg
->dma_address
= -2;
505 leader_length
+= len
;
508 leader
->dma_address
= leader_flag
;
509 leader
->dma_length
= leader_length
;
515 next_paddr
= addr
+ len
;
518 leader
->dma_address
= leader_flag
;
519 leader
->dma_length
= leader_length
;
522 /* Given a scatterlist leader, choose an allocation method and fill
526 sg_fill(struct device
*dev
, struct scatterlist
*leader
, struct scatterlist
*end
,
527 struct scatterlist
*out
, struct pci_iommu_arena
*arena
,
528 dma_addr_t max_dma
, int dac_allowed
)
530 unsigned long paddr
= SG_ENT_PHYS_ADDRESS(leader
);
531 long size
= leader
->dma_length
;
532 struct scatterlist
*sg
;
534 long npages
, dma_ofs
, i
;
537 /* If everything is physically contiguous, and the addresses
538 fall into the direct-map window, use it. */
539 if (leader
->dma_address
== 0
540 && paddr
+ size
+ __direct_map_base
- 1 <= max_dma
541 && paddr
+ size
<= __direct_map_size
) {
542 out
->dma_address
= paddr
+ __direct_map_base
;
543 out
->dma_length
= size
;
545 DBGA(" sg_fill: [%p,%lx] -> direct %lx\n",
546 __va(paddr
), size
, out
->dma_address
);
552 /* If physically contiguous and DAC is available, use it. */
553 if (leader
->dma_address
== 0 && dac_allowed
) {
554 out
->dma_address
= paddr
+ alpha_mv
.pci_dac_offset
;
555 out
->dma_length
= size
;
557 DBGA(" sg_fill: [%p,%lx] -> DAC %lx\n",
558 __va(paddr
), size
, out
->dma_address
);
563 /* Otherwise, we'll use the iommu to make the pages virtually
567 npages
= calc_npages(paddr
+ size
);
568 dma_ofs
= iommu_arena_alloc(arena
, npages
, 0);
570 /* If we attempted a direct map above but failed, die. */
571 if (leader
->dma_address
== 0)
574 /* Otherwise, break up the remaining virtually contiguous
575 hunks into individual direct maps and retry. */
576 sg_classify(dev
, leader
, end
, 0);
577 return sg_fill(dev
, leader
, end
, out
, arena
, max_dma
, dac_allowed
);
580 out
->dma_address
= arena
->dma_base
+ dma_ofs
*PAGE_SIZE
+ paddr
;
581 out
->dma_length
= size
;
583 DBGA(" sg_fill: [%p,%lx] -> sg %lx np %ld\n",
584 __va(paddr
), size
, out
->dma_address
, npages
);
586 /* All virtually contiguous. We need to find the length of each
587 physically contiguous subsegment to fill in the ptes. */
588 ptes
= &arena
->ptes
[dma_ofs
];
592 struct scatterlist
*last_sg
= sg
;
596 paddr
= SG_ENT_PHYS_ADDRESS(sg
);
598 while (sg
+1 < end
&& (int) sg
[1].dma_address
== -1) {
599 size
+= sg
[1].length
;
603 npages
= calc_npages((paddr
& ~PAGE_MASK
) + size
);
606 for (i
= 0; i
< npages
; ++i
, paddr
+= PAGE_SIZE
)
607 *ptes
++ = mk_iommu_pte(paddr
);
610 DBGA(" (%ld) [%p,%x] np %ld\n",
611 last_sg
- leader
, SG_ENT_VIRT_ADDRESS(last_sg
),
612 last_sg
->length
, npages
);
613 while (++last_sg
<= sg
) {
614 DBGA(" (%ld) [%p,%x] cont\n",
615 last_sg
- leader
, SG_ENT_VIRT_ADDRESS(last_sg
),
619 } while (++sg
< end
&& (int) sg
->dma_address
< 0);
625 pci_map_sg(struct pci_dev
*pdev
, struct scatterlist
*sg
, int nents
,
628 struct scatterlist
*start
, *end
, *out
;
629 struct pci_controller
*hose
;
630 struct pci_iommu_arena
*arena
;
635 if (direction
== PCI_DMA_NONE
)
638 dac_allowed
= pdev
? pci_dac_dma_supported(pdev
, pdev
->dma_mask
) : 0;
640 dev
= pdev
? &pdev
->dev
: NULL
;
642 /* Fast path single entry scatterlists. */
644 sg
->dma_length
= sg
->length
;
646 = pci_map_single_1(pdev
, SG_ENT_VIRT_ADDRESS(sg
),
647 sg
->length
, dac_allowed
);
648 return sg
->dma_address
!= 0;
654 /* First, prepare information about the entries. */
655 sg_classify(dev
, sg
, end
, alpha_mv
.mv_pci_tbi
!= 0);
657 /* Second, figure out where we're going to map things. */
658 if (alpha_mv
.mv_pci_tbi
) {
659 hose
= pdev
? pdev
->sysdata
: pci_isa_hose
;
660 max_dma
= pdev
? pdev
->dma_mask
: ISA_DMA_MASK
;
661 arena
= hose
->sg_pci
;
662 if (!arena
|| arena
->dma_base
+ arena
->size
- 1 > max_dma
)
663 arena
= hose
->sg_isa
;
670 /* Third, iterate over the scatterlist leaders and allocate
671 dma space as needed. */
672 for (out
= sg
; sg
< end
; ++sg
) {
673 if ((int) sg
->dma_address
< 0)
675 if (sg_fill(dev
, sg
, end
, out
, arena
, max_dma
, dac_allowed
) < 0)
680 /* Mark the end of the list for pci_unmap_sg. */
684 if (out
- start
== 0)
685 printk(KERN_WARNING
"pci_map_sg failed: no entries?\n");
686 DBGA("pci_map_sg: %ld entries\n", out
- start
);
691 printk(KERN_WARNING
"pci_map_sg failed: "
692 "could not allocate dma page tables\n");
694 /* Some allocation failed while mapping the scatterlist
695 entries. Unmap them now. */
697 pci_unmap_sg(pdev
, start
, out
- start
, direction
);
700 EXPORT_SYMBOL(pci_map_sg
);
702 /* Unmap a set of streaming mode DMA translations. Again, cpu read
703 rules concerning calls here are the same as for pci_unmap_single()
707 pci_unmap_sg(struct pci_dev
*pdev
, struct scatterlist
*sg
, int nents
,
711 struct pci_controller
*hose
;
712 struct pci_iommu_arena
*arena
;
713 struct scatterlist
*end
;
715 dma_addr_t fbeg
, fend
;
717 if (direction
== PCI_DMA_NONE
)
720 if (! alpha_mv
.mv_pci_tbi
)
723 hose
= pdev
? pdev
->sysdata
: pci_isa_hose
;
724 max_dma
= pdev
? pdev
->dma_mask
: ISA_DMA_MASK
;
725 arena
= hose
->sg_pci
;
726 if (!arena
|| arena
->dma_base
+ arena
->size
- 1 > max_dma
)
727 arena
= hose
->sg_isa
;
731 spin_lock_irqsave(&arena
->lock
, flags
);
733 for (end
= sg
+ nents
; sg
< end
; ++sg
) {
739 addr
= sg
->dma_address
;
740 size
= sg
->dma_length
;
744 if (addr
> 0xffffffff) {
745 /* It's a DAC address -- nothing to do. */
746 DBGA(" (%ld) DAC [%lx,%lx]\n",
747 sg
- end
+ nents
, addr
, size
);
751 if (addr
>= __direct_map_base
752 && addr
< __direct_map_base
+ __direct_map_size
) {
754 DBGA(" (%ld) direct [%lx,%lx]\n",
755 sg
- end
+ nents
, addr
, size
);
759 DBGA(" (%ld) sg [%lx,%lx]\n",
760 sg
- end
+ nents
, addr
, size
);
762 npages
= calc_npages((addr
& ~PAGE_MASK
) + size
);
763 ofs
= (addr
- arena
->dma_base
) >> PAGE_SHIFT
;
764 iommu_arena_free(arena
, ofs
, npages
);
766 tend
= addr
+ size
- 1;
767 if (fbeg
> addr
) fbeg
= addr
;
768 if (fend
< tend
) fend
= tend
;
771 /* If we're freeing ptes above the `next_entry' pointer (they
772 may have snuck back into the TLB since the last wrap flush),
773 we need to flush the TLB before reallocating the latter. */
774 if ((fend
- arena
->dma_base
) >> PAGE_SHIFT
>= arena
->next_entry
)
775 alpha_mv
.mv_pci_tbi(hose
, fbeg
, fend
);
777 spin_unlock_irqrestore(&arena
->lock
, flags
);
779 DBGA("pci_unmap_sg: %ld entries\n", nents
- (end
- sg
));
781 EXPORT_SYMBOL(pci_unmap_sg
);
784 /* Return whether the given PCI device DMA address mask can be
785 supported properly. */
788 pci_dma_supported(struct pci_dev
*pdev
, u64 mask
)
790 struct pci_controller
*hose
;
791 struct pci_iommu_arena
*arena
;
793 /* If there exists a direct map, and the mask fits either
794 the entire direct mapped space or the total system memory as
795 shifted by the map base */
796 if (__direct_map_size
!= 0
797 && (__direct_map_base
+ __direct_map_size
- 1 <= mask
||
798 __direct_map_base
+ (max_low_pfn
<< PAGE_SHIFT
) - 1 <= mask
))
801 /* Check that we have a scatter-gather arena that fits. */
802 hose
= pdev
? pdev
->sysdata
: pci_isa_hose
;
803 arena
= hose
->sg_isa
;
804 if (arena
&& arena
->dma_base
+ arena
->size
- 1 <= mask
)
806 arena
= hose
->sg_pci
;
807 if (arena
&& arena
->dma_base
+ arena
->size
- 1 <= mask
)
810 /* As last resort try ZONE_DMA. */
811 if (!__direct_map_base
&& MAX_DMA_ADDRESS
- IDENT_ADDR
- 1 <= mask
)
816 EXPORT_SYMBOL(pci_dma_supported
);
820 * AGP GART extensions to the IOMMU
823 iommu_reserve(struct pci_iommu_arena
*arena
, long pg_count
, long align_mask
)
829 if (!arena
) return -EINVAL
;
831 spin_lock_irqsave(&arena
->lock
, flags
);
833 /* Search for N empty ptes. */
835 p
= iommu_arena_find_pages(arena
, pg_count
, align_mask
);
837 spin_unlock_irqrestore(&arena
->lock
, flags
);
841 /* Success. Mark them all reserved (ie not zero and invalid)
842 for the iommu tlb that could load them from under us.
843 They will be filled in with valid bits by _bind() */
844 for (i
= 0; i
< pg_count
; ++i
)
845 ptes
[p
+i
] = IOMMU_RESERVED_PTE
;
847 arena
->next_entry
= p
+ pg_count
;
848 spin_unlock_irqrestore(&arena
->lock
, flags
);
854 iommu_release(struct pci_iommu_arena
*arena
, long pg_start
, long pg_count
)
859 if (!arena
) return -EINVAL
;
863 /* Make sure they're all reserved first... */
864 for(i
= pg_start
; i
< pg_start
+ pg_count
; i
++)
865 if (ptes
[i
] != IOMMU_RESERVED_PTE
)
868 iommu_arena_free(arena
, pg_start
, pg_count
);
873 iommu_bind(struct pci_iommu_arena
*arena
, long pg_start
, long pg_count
,
874 unsigned long *physaddrs
)
880 if (!arena
) return -EINVAL
;
882 spin_lock_irqsave(&arena
->lock
, flags
);
886 for(j
= pg_start
; j
< pg_start
+ pg_count
; j
++) {
887 if (ptes
[j
] != IOMMU_RESERVED_PTE
) {
888 spin_unlock_irqrestore(&arena
->lock
, flags
);
893 for(i
= 0, j
= pg_start
; i
< pg_count
; i
++, j
++)
894 ptes
[j
] = mk_iommu_pte(physaddrs
[i
]);
896 spin_unlock_irqrestore(&arena
->lock
, flags
);
902 iommu_unbind(struct pci_iommu_arena
*arena
, long pg_start
, long pg_count
)
907 if (!arena
) return -EINVAL
;
909 p
= arena
->ptes
+ pg_start
;
910 for(i
= 0; i
< pg_count
; i
++)
911 p
[i
] = IOMMU_RESERVED_PTE
;
916 /* True if the machine supports DAC addressing, and DEV can
917 make use of it given MASK. */
920 pci_dac_dma_supported(struct pci_dev
*dev
, u64 mask
)
922 dma64_addr_t dac_offset
= alpha_mv
.pci_dac_offset
;
925 /* If this is not set, the machine doesn't support DAC at all. */
929 /* The device has to be able to address our DAC bit. */
930 if ((dac_offset
& dev
->dma_mask
) != dac_offset
)
933 /* If both conditions above are met, we are fine. */
934 DBGA("pci_dac_dma_supported %s from %p\n",
935 ok
? "yes" : "no", __builtin_return_address(0));
940 /* Helper for generic DMA-mapping functions. */
943 alpha_gendev_to_pci(struct device
*dev
)
945 if (dev
&& dev
->bus
== &pci_bus_type
)
946 return to_pci_dev(dev
);
948 /* Assume that non-PCI devices asking for DMA are either ISA or EISA,
952 /* Assume non-busmaster ISA DMA when dma_mask is not set (the ISA
953 bridge is bus master then). */
954 if (!dev
|| !dev
->dma_mask
|| !*dev
->dma_mask
)
957 /* For EISA bus masters, return isa_bridge (it might have smaller
958 dma_mask due to wiring limitations). */
959 if (*dev
->dma_mask
>= isa_bridge
->dma_mask
)
962 /* This assumes ISA bus master with dma_mask 0xffffff. */
965 EXPORT_SYMBOL(alpha_gendev_to_pci
);
968 dma_set_mask(struct device
*dev
, u64 mask
)
970 if (!dev
->dma_mask
||
971 !pci_dma_supported(alpha_gendev_to_pci(dev
), mask
))
974 *dev
->dma_mask
= mask
;
978 EXPORT_SYMBOL(dma_set_mask
);