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[POWERPC] Fake NUMA emulation for PowerPC
[linux-2.6/sactl.git] / drivers / net / smc91x.h
blob271c28dc9baae1057681ce326ea4bc81e50e8756
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57 #define SMC_IRQ_FLAGS (-1) /* from resource */
58
59 #elif defined(CONFIG_BLACKFIN)
60
61 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
62 #define RPC_LSA_DEFAULT RPC_LED_100_10
63 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
64
65 # if defined (CONFIG_BFIN561_EZKIT)
66 #define SMC_CAN_USE_8BIT 0
67 #define SMC_CAN_USE_16BIT 1
68 #define SMC_CAN_USE_32BIT 1
69 #define SMC_IO_SHIFT 0
70 #define SMC_NOWAIT 1
71 #define SMC_USE_BFIN_DMA 0
72
73
74 #define SMC_inw(a, r) readw((a) + (r))
75 #define SMC_outw(v, a, r) writew(v, (a) + (r))
76 #define SMC_inl(a, r) readl((a) + (r))
77 #define SMC_outl(v, a, r) writel(v, (a) + (r))
78 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
79 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
80 # else
81 #define SMC_CAN_USE_8BIT 0
82 #define SMC_CAN_USE_16BIT 1
83 #define SMC_CAN_USE_32BIT 0
84 #define SMC_IO_SHIFT 0
85 #define SMC_NOWAIT 1
86 #define SMC_USE_BFIN_DMA 0
87
88
89 #define SMC_inw(a, r) readw((a) + (r))
90 #define SMC_outw(v, a, r) writew(v, (a) + (r))
91 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
92 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
93 # endif
94 /* check if the mac in reg is valid */
95 #define SMC_GET_MAC_ADDR(addr) \
96 do { \
97 unsigned int __v; \
98 __v = SMC_inw(ioaddr, ADDR0_REG); \
99 addr[0] = __v; addr[1] = __v >> 8; \
100 __v = SMC_inw(ioaddr, ADDR1_REG); \
101 addr[2] = __v; addr[3] = __v >> 8; \
102 __v = SMC_inw(ioaddr, ADDR2_REG); \
103 addr[4] = __v; addr[5] = __v >> 8; \
104 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
105 random_ether_addr(addr); \
106 } \
107 } while (0)
108 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
109
110 /* We can only do 16-bit reads and writes in the static memory space. */
111 #define SMC_CAN_USE_8BIT 0
112 #define SMC_CAN_USE_16BIT 1
113 #define SMC_CAN_USE_32BIT 0
114 #define SMC_NOWAIT 1
115
116 #define SMC_IO_SHIFT 0
117
118 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
119 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
120 #define SMC_insw(a, r, p, l) \
121 do { \
122 unsigned long __port = (a) + (r); \
123 u16 *__p = (u16 *)(p); \
124 int __l = (l); \
125 insw(__port, __p, __l); \
126 while (__l > 0) { \
127 *__p = swab16(*__p); \
128 __p++; \
129 __l--; \
130 } \
131 } while (0)
132 #define SMC_outsw(a, r, p, l) \
133 do { \
134 unsigned long __port = (a) + (r); \
135 u16 *__p = (u16 *)(p); \
136 int __l = (l); \
137 while (__l > 0) { \
138 /* Believe it or not, the swab isn't needed. */ \
139 outw( /* swab16 */ (*__p++), __port); \
140 __l--; \
141 } \
142 } while (0)
143 #define SMC_IRQ_FLAGS (0)
144
145 #elif defined(CONFIG_SA1100_PLEB)
146 /* We can only do 16-bit reads and writes in the static memory space. */
147 #define SMC_CAN_USE_8BIT 1
148 #define SMC_CAN_USE_16BIT 1
149 #define SMC_CAN_USE_32BIT 0
150 #define SMC_IO_SHIFT 0
151 #define SMC_NOWAIT 1
152
153 #define SMC_inb(a, r) readb((a) + (r))
154 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
155 #define SMC_inw(a, r) readw((a) + (r))
156 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
157 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
158 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
159 #define SMC_outw(v, a, r) writew(v, (a) + (r))
160 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
161
162 #define SMC_IRQ_FLAGS (-1)
163
164 #elif defined(CONFIG_SA1100_ASSABET)
165
166 #include <asm/arch/neponset.h>
167
168 /* We can only do 8-bit reads and writes in the static memory space. */
169 #define SMC_CAN_USE_8BIT 1
170 #define SMC_CAN_USE_16BIT 0
171 #define SMC_CAN_USE_32BIT 0
172 #define SMC_NOWAIT 1
173
174 /* The first two address lines aren't connected... */
175 #define SMC_IO_SHIFT 2
176
177 #define SMC_inb(a, r) readb((a) + (r))
178 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
179 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
180 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
181 #define SMC_IRQ_FLAGS (-1) /* from resource */
182
183 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
184
185 #define SMC_CAN_USE_8BIT 0
186 #define SMC_CAN_USE_16BIT 1
187 #define SMC_CAN_USE_32BIT 0
188 #define SMC_IO_SHIFT 0
189 #define SMC_NOWAIT 1
190
191 #define SMC_inw(a, r) readw((a) + (r))
192 #define SMC_outw(v, a, r) writew(v, (a) + (r))
193 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
194 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
195
196 #elif defined(CONFIG_ARCH_INNOKOM) || \
197 defined(CONFIG_MACH_MAINSTONE) || \
198 defined(CONFIG_ARCH_PXA_IDP) || \
199 defined(CONFIG_ARCH_RAMSES) || \
200 defined(CONFIG_ARCH_PCM027)
201
202 #define SMC_CAN_USE_8BIT 1
203 #define SMC_CAN_USE_16BIT 1
204 #define SMC_CAN_USE_32BIT 1
205 #define SMC_IO_SHIFT 0
206 #define SMC_NOWAIT 1
207 #define SMC_USE_PXA_DMA 1
208
209 #define SMC_inb(a, r) readb((a) + (r))
210 #define SMC_inw(a, r) readw((a) + (r))
211 #define SMC_inl(a, r) readl((a) + (r))
212 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
213 #define SMC_outl(v, a, r) writel(v, (a) + (r))
214 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
215 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
216 #define SMC_IRQ_FLAGS (-1) /* from resource */
217
218 /* We actually can't write halfwords properly if not word aligned */
219 static inline void
220 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
221 {
222 if (reg & 2) {
223 unsigned int v = val << 16;
224 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
225 writel(v, ioaddr + (reg & ~2));
226 } else {
227 writew(val, ioaddr + reg);
228 }
229 }
230
231 #elif defined(CONFIG_MACH_ZYLONITE)
232
233 #define SMC_CAN_USE_8BIT 1
234 #define SMC_CAN_USE_16BIT 1
235 #define SMC_CAN_USE_32BIT 0
236 #define SMC_IO_SHIFT 0
237 #define SMC_NOWAIT 1
238 #define SMC_USE_PXA_DMA 1
239 #define SMC_inb(a, r) readb((a) + (r))
240 #define SMC_inw(a, r) readw((a) + (r))
241 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
242 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
243 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
244 #define SMC_outw(v, a, r) writew(v, (a) + (r))
245 #define SMC_IRQ_FLAGS (-1) /* from resource */
246
247 #elif defined(CONFIG_ARCH_OMAP)
248
249 /* We can only do 16-bit reads and writes in the static memory space. */
250 #define SMC_CAN_USE_8BIT 0
251 #define SMC_CAN_USE_16BIT 1
252 #define SMC_CAN_USE_32BIT 0
253 #define SMC_IO_SHIFT 0
254 #define SMC_NOWAIT 1
255
256 #define SMC_inw(a, r) readw((a) + (r))
257 #define SMC_outw(v, a, r) writew(v, (a) + (r))
258 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
259 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
260 #define SMC_IRQ_FLAGS (-1) /* from resource */
261
262 #elif defined(CONFIG_SH_SH4202_MICRODEV)
263
264 #define SMC_CAN_USE_8BIT 0
265 #define SMC_CAN_USE_16BIT 1
266 #define SMC_CAN_USE_32BIT 0
267
268 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
269 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
270 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
271 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
272 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
273 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
274 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
275 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
276 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
277 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
278
279 #define SMC_IRQ_FLAGS (0)
280
281 #elif defined(CONFIG_ISA)
282
283 #define SMC_CAN_USE_8BIT 1
284 #define SMC_CAN_USE_16BIT 1
285 #define SMC_CAN_USE_32BIT 0
286
287 #define SMC_inb(a, r) inb((a) + (r))
288 #define SMC_inw(a, r) inw((a) + (r))
289 #define SMC_outb(v, a, r) outb(v, (a) + (r))
290 #define SMC_outw(v, a, r) outw(v, (a) + (r))
291 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
292 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
293
294 #elif defined(CONFIG_SUPERH)
295
296 #ifdef CONFIG_SOLUTION_ENGINE
297 #define SMC_IRQ_FLAGS (0)
298 #define SMC_CAN_USE_8BIT 0
299 #define SMC_CAN_USE_16BIT 1
300 #define SMC_CAN_USE_32BIT 0
301 #define SMC_IO_SHIFT 0
302 #define SMC_NOWAIT 1
303
304 #define SMC_inw(a, r) inw((a) + (r))
305 #define SMC_outw(v, a, r) outw(v, (a) + (r))
306 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
307 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
308
309 #else /* BOARDS */
310
311 #define SMC_CAN_USE_8BIT 1
312 #define SMC_CAN_USE_16BIT 1
313 #define SMC_CAN_USE_32BIT 0
314
315 #define SMC_inb(a, r) inb((a) + (r))
316 #define SMC_inw(a, r) inw((a) + (r))
317 #define SMC_outb(v, a, r) outb(v, (a) + (r))
318 #define SMC_outw(v, a, r) outw(v, (a) + (r))
319 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
320 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
321
322 #endif /* BOARDS */
323
324 #elif defined(CONFIG_M32R)
325
326 #define SMC_CAN_USE_8BIT 0
327 #define SMC_CAN_USE_16BIT 1
328 #define SMC_CAN_USE_32BIT 0
329
330 #define SMC_inb(a, r) inb(((u32)a) + (r))
331 #define SMC_inw(a, r) inw(((u32)a) + (r))
332 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
333 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
334 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
335 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
336
337 #define SMC_IRQ_FLAGS (0)
338
339 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
340 #define RPC_LSB_DEFAULT RPC_LED_100_10
341
342 #elif defined(CONFIG_MACH_LPD79520) \
343 || defined(CONFIG_MACH_LPD7A400) \
344 || defined(CONFIG_MACH_LPD7A404)
345
346 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
347 * way that the CPU handles chip selects and the way that the SMC chip
348 * expects the chip select to operate. Refer to
349 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
350 * IOBARRIER is a byte, in order that we read the least-common
351 * denominator. It would be wasteful to read 32 bits from an 8-bit
352 * accessible region.
353 *
354 * There is no explicit protection against interrupts intervening
355 * between the writew and the IOBARRIER. In SMC ISR there is a
356 * preamble that performs an IOBARRIER in the extremely unlikely event
357 * that the driver interrupts itself between a writew to the chip an
358 * the IOBARRIER that follows *and* the cache is large enough that the
359 * first off-chip access while handing the interrupt is to the SMC
360 * chip. Other devices in the same address space as the SMC chip must
361 * be aware of the potential for trouble and perform a similar
362 * IOBARRIER on entry to their ISR.
363 */
364
365 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
366
367 #define SMC_CAN_USE_8BIT 0
368 #define SMC_CAN_USE_16BIT 1
369 #define SMC_CAN_USE_32BIT 0
370 #define SMC_NOWAIT 0
371 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
372
373 #define SMC_inw(a,r)\
374 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
375 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
376
377 #define SMC_insw LPD7_SMC_insw
378 static inline void LPD7_SMC_insw (unsigned char* a, int r,
379 unsigned char* p, int l)
380 {
381 unsigned short* ps = (unsigned short*) p;
382 while (l-- > 0) {
383 *ps++ = readw (a + r);
384 LPD7X_IOBARRIER;
385 }
386 }
387
388 #define SMC_outsw LPD7_SMC_outsw
389 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
390 unsigned char* p, int l)
391 {
392 unsigned short* ps = (unsigned short*) p;
393 while (l-- > 0) {
394 writew (*ps++, a + r);
395 LPD7X_IOBARRIER;
396 }
397 }
398
399 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
400
401 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
402 #define RPC_LSB_DEFAULT RPC_LED_100_10
403
404 #elif defined(CONFIG_SOC_AU1X00)
405
406 #include <au1xxx.h>
407
408 /* We can only do 16-bit reads and writes in the static memory space. */
409 #define SMC_CAN_USE_8BIT 0
410 #define SMC_CAN_USE_16BIT 1
411 #define SMC_CAN_USE_32BIT 0
412 #define SMC_IO_SHIFT 0
413 #define SMC_NOWAIT 1
414
415 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
416 #define SMC_insw(a, r, p, l) \
417 do { \
418 unsigned long _a = (unsigned long)((a) + (r)); \
419 int _l = (l); \
420 u16 *_p = (u16 *)(p); \
421 while (_l-- > 0) \
422 *_p++ = au_readw(_a); \
423 } while(0)
424 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
425 #define SMC_outsw(a, r, p, l) \
426 do { \
427 unsigned long _a = (unsigned long)((a) + (r)); \
428 int _l = (l); \
429 const u16 *_p = (const u16 *)(p); \
430 while (_l-- > 0) \
431 au_writew(*_p++ , _a); \
432 } while(0)
433
434 #define SMC_IRQ_FLAGS (0)
435
436 #elif defined(CONFIG_ARCH_VERSATILE)
437
438 #define SMC_CAN_USE_8BIT 1
439 #define SMC_CAN_USE_16BIT 1
440 #define SMC_CAN_USE_32BIT 1
441 #define SMC_NOWAIT 1
442
443 #define SMC_inb(a, r) readb((a) + (r))
444 #define SMC_inw(a, r) readw((a) + (r))
445 #define SMC_inl(a, r) readl((a) + (r))
446 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
447 #define SMC_outw(v, a, r) writew(v, (a) + (r))
448 #define SMC_outl(v, a, r) writel(v, (a) + (r))
449 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
450 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
451 #define SMC_IRQ_FLAGS (-1) /* from resource */
452
453 #else
454
455 #define SMC_CAN_USE_8BIT 1
456 #define SMC_CAN_USE_16BIT 1
457 #define SMC_CAN_USE_32BIT 1
458 #define SMC_NOWAIT 1
459
460 #define SMC_inb(a, r) readb((a) + (r))
461 #define SMC_inw(a, r) readw((a) + (r))
462 #define SMC_inl(a, r) readl((a) + (r))
463 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
464 #define SMC_outw(v, a, r) writew(v, (a) + (r))
465 #define SMC_outl(v, a, r) writel(v, (a) + (r))
466 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
467 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
468
469 #define RPC_LSA_DEFAULT RPC_LED_100_10
470 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
471
472 #endif
473
474
475 /* store this information for the driver.. */
476 struct smc_local {
477 /*
478 * If I have to wait until memory is available to send a
479 * packet, I will store the skbuff here, until I get the
480 * desired memory. Then, I'll send it out and free it.
481 */
482 struct sk_buff *pending_tx_skb;
483 struct tasklet_struct tx_task;
484
485 /* version/revision of the SMC91x chip */
486 int version;
487
488 /* Contains the current active transmission mode */
489 int tcr_cur_mode;
490
491 /* Contains the current active receive mode */
492 int rcr_cur_mode;
493
494 /* Contains the current active receive/phy mode */
495 int rpc_cur_mode;
496 int ctl_rfduplx;
497 int ctl_rspeed;
498
499 u32 msg_enable;
500 u32 phy_type;
501 struct mii_if_info mii;
502
503 /* work queue */
504 struct work_struct phy_configure;
505 struct net_device *dev;
506 int work_pending;
507
508 spinlock_t lock;
509
510 #ifdef SMC_USE_PXA_DMA
511 /* DMA needs the physical address of the chip */
512 u_long physaddr;
513 struct device *device;
514 #endif
515 void __iomem *base;
516 void __iomem *datacs;
517 };
518
519
520 #ifdef SMC_USE_PXA_DMA
521 /*
522 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
523 * always happening in irq context so no need to worry about races. TX is
524 * different and probably not worth it for that reason, and not as critical
525 * as RX which can overrun memory and lose packets.
526 */
527 #include <linux/dma-mapping.h>
528 #include <asm/dma.h>
529 #include <asm/arch/pxa-regs.h>
530
531 #ifdef SMC_insl
532 #undef SMC_insl
533 #define SMC_insl(a, r, p, l) \
534 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
535 static inline void
536 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
537 u_char *buf, int len)
538 {
539 u_long physaddr = lp->physaddr;
540 dma_addr_t dmabuf;
541
542 /* fallback if no DMA available */
543 if (dma == (unsigned char)-1) {
544 readsl(ioaddr + reg, buf, len);
545 return;
546 }
547
548 /* 64 bit alignment is required for memory to memory DMA */
549 if ((long)buf & 4) {
550 *((u32 *)buf) = SMC_inl(ioaddr, reg);
551 buf += 4;
552 len--;
553 }
554
555 len *= 4;
556 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
557 DCSR(dma) = DCSR_NODESC;
558 DTADR(dma) = dmabuf;
559 DSADR(dma) = physaddr + reg;
560 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
561 DCMD_WIDTH4 | (DCMD_LENGTH & len));
562 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
563 while (!(DCSR(dma) & DCSR_STOPSTATE))
564 cpu_relax();
565 DCSR(dma) = 0;
566 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
567 }
568 #endif
569
570 #ifdef SMC_insw
571 #undef SMC_insw
572 #define SMC_insw(a, r, p, l) \
573 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
574 static inline void
575 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
576 u_char *buf, int len)
577 {
578 u_long physaddr = lp->physaddr;
579 dma_addr_t dmabuf;
580
581 /* fallback if no DMA available */
582 if (dma == (unsigned char)-1) {
583 readsw(ioaddr + reg, buf, len);
584 return;
585 }
586
587 /* 64 bit alignment is required for memory to memory DMA */
588 while ((long)buf & 6) {
589 *((u16 *)buf) = SMC_inw(ioaddr, reg);
590 buf += 2;
591 len--;
592 }
593
594 len *= 2;
595 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
596 DCSR(dma) = DCSR_NODESC;
597 DTADR(dma) = dmabuf;
598 DSADR(dma) = physaddr + reg;
599 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
600 DCMD_WIDTH2 | (DCMD_LENGTH & len));
601 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
602 while (!(DCSR(dma) & DCSR_STOPSTATE))
603 cpu_relax();
604 DCSR(dma) = 0;
605 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
606 }
607 #endif
608
609 static void
610 smc_pxa_dma_irq(int dma, void *dummy)
611 {
612 DCSR(dma) = 0;
613 }
614 #endif /* SMC_USE_PXA_DMA */
615
616
617 /*
618 * Everything a particular hardware setup needs should have been defined
619 * at this point. Add stubs for the undefined cases, mainly to avoid
620 * compilation warnings since they'll be optimized away, or to prevent buggy
621 * use of them.
622 */
623
624 #if ! SMC_CAN_USE_32BIT
625 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
626 #define SMC_outl(x, ioaddr, reg) BUG()
627 #define SMC_insl(a, r, p, l) BUG()
628 #define SMC_outsl(a, r, p, l) BUG()
629 #endif
630
631 #if !defined(SMC_insl) || !defined(SMC_outsl)
632 #define SMC_insl(a, r, p, l) BUG()
633 #define SMC_outsl(a, r, p, l) BUG()
634 #endif
635
636 #if ! SMC_CAN_USE_16BIT
637
638 /*
639 * Any 16-bit access is performed with two 8-bit accesses if the hardware
640 * can't do it directly. Most registers are 16-bit so those are mandatory.
641 */
642 #define SMC_outw(x, ioaddr, reg) \
643 do { \
644 unsigned int __val16 = (x); \
645 SMC_outb( __val16, ioaddr, reg ); \
646 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
647 } while (0)
648 #define SMC_inw(ioaddr, reg) \
649 ({ \
650 unsigned int __val16; \
651 __val16 = SMC_inb( ioaddr, reg ); \
652 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
653 __val16; \
654 })
655
656 #define SMC_insw(a, r, p, l) BUG()
657 #define SMC_outsw(a, r, p, l) BUG()
658
659 #endif
660
661 #if !defined(SMC_insw) || !defined(SMC_outsw)
662 #define SMC_insw(a, r, p, l) BUG()
663 #define SMC_outsw(a, r, p, l) BUG()
664 #endif
665
666 #if ! SMC_CAN_USE_8BIT
667 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
668 #define SMC_outb(x, ioaddr, reg) BUG()
669 #define SMC_insb(a, r, p, l) BUG()
670 #define SMC_outsb(a, r, p, l) BUG()
671 #endif
672
673 #if !defined(SMC_insb) || !defined(SMC_outsb)
674 #define SMC_insb(a, r, p, l) BUG()
675 #define SMC_outsb(a, r, p, l) BUG()
676 #endif
677
678 #ifndef SMC_CAN_USE_DATACS
679 #define SMC_CAN_USE_DATACS 0
680 #endif
681
682 #ifndef SMC_IO_SHIFT
683 #define SMC_IO_SHIFT 0
684 #endif
685
686 #ifndef SMC_IRQ_FLAGS
687 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
688 #endif
689
690 #ifndef SMC_INTERRUPT_PREAMBLE
691 #define SMC_INTERRUPT_PREAMBLE
692 #endif
693
694
695 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
696 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
697 #define SMC_DATA_EXTENT (4)
698
699 /*
700 . Bank Select Register:
701 .
702 . yyyy yyyy 0000 00xx
703 . xx = bank number
704 . yyyy yyyy = 0x33, for identification purposes.
705 */
706 #define BANK_SELECT (14 << SMC_IO_SHIFT)
707
708
709 // Transmit Control Register
710 /* BANK 0 */
711 #define TCR_REG SMC_REG(0x0000, 0)
712 #define TCR_ENABLE 0x0001 // When 1 we can transmit
713 #define TCR_LOOP 0x0002 // Controls output pin LBK
714 #define TCR_FORCOL 0x0004 // When 1 will force a collision
715 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
716 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
717 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
718 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
719 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
720 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
721 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
722
723 #define TCR_CLEAR 0 /* do NOTHING */
724 /* the default settings for the TCR register : */
725 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
726
727
728 // EPH Status Register
729 /* BANK 0 */
730 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
731 #define ES_TX_SUC 0x0001 // Last TX was successful
732 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
733 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
734 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
735 #define ES_16COL 0x0010 // 16 Collisions Reached
736 #define ES_SQET 0x0020 // Signal Quality Error Test
737 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
738 #define ES_TXDEFR 0x0080 // Transmit Deferred
739 #define ES_LATCOL 0x0200 // Late collision detected on last tx
740 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
741 #define ES_EXC_DEF 0x0800 // Excessive Deferral
742 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
743 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
744 #define ES_TXUNRN 0x8000 // Tx Underrun
745
746
747 // Receive Control Register
748 /* BANK 0 */
749 #define RCR_REG SMC_REG(0x0004, 0)
750 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
751 #define RCR_PRMS 0x0002 // Enable promiscuous mode
752 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
753 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
754 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
755 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
756 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
757 #define RCR_SOFTRST 0x8000 // resets the chip
758
759 /* the normal settings for the RCR register : */
760 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
761 #define RCR_CLEAR 0x0 // set it to a base state
762
763
764 // Counter Register
765 /* BANK 0 */
766 #define COUNTER_REG SMC_REG(0x0006, 0)
767
768
769 // Memory Information Register
770 /* BANK 0 */
771 #define MIR_REG SMC_REG(0x0008, 0)
772
773
774 // Receive/Phy Control Register
775 /* BANK 0 */
776 #define RPC_REG SMC_REG(0x000A, 0)
777 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
778 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
779 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
780 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
781 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
782 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
783 #define RPC_LED_RES (0x01) // LED = Reserved
784 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
785 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
786 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
787 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
788 #define RPC_LED_TX (0x06) // LED = TX packet occurred
789 #define RPC_LED_RX (0x07) // LED = RX packet occurred
790
791 #ifndef RPC_LSA_DEFAULT
792 #define RPC_LSA_DEFAULT RPC_LED_100
793 #endif
794 #ifndef RPC_LSB_DEFAULT
795 #define RPC_LSB_DEFAULT RPC_LED_FD
796 #endif
797
798 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
799
800
801 /* Bank 0 0x0C is reserved */
802
803 // Bank Select Register
804 /* All Banks */
805 #define BSR_REG 0x000E
806
807
808 // Configuration Reg
809 /* BANK 1 */
810 #define CONFIG_REG SMC_REG(0x0000, 1)
811 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
812 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
813 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
814 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
815
816 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
817 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
818
819
820 // Base Address Register
821 /* BANK 1 */
822 #define BASE_REG SMC_REG(0x0002, 1)
823
824
825 // Individual Address Registers
826 /* BANK 1 */
827 #define ADDR0_REG SMC_REG(0x0004, 1)
828 #define ADDR1_REG SMC_REG(0x0006, 1)
829 #define ADDR2_REG SMC_REG(0x0008, 1)
830
831
832 // General Purpose Register
833 /* BANK 1 */
834 #define GP_REG SMC_REG(0x000A, 1)
835
836
837 // Control Register
838 /* BANK 1 */
839 #define CTL_REG SMC_REG(0x000C, 1)
840 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
841 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
842 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
843 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
844 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
845 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
846 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
847 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
848
849
850 // MMU Command Register
851 /* BANK 2 */
852 #define MMU_CMD_REG SMC_REG(0x0000, 2)
853 #define MC_BUSY 1 // When 1 the last release has not completed
854 #define MC_NOP (0<<5) // No Op
855 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
856 #define MC_RESET (2<<5) // Reset MMU to initial state
857 #define MC_REMOVE (3<<5) // Remove the current rx packet
858 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
859 #define MC_FREEPKT (5<<5) // Release packet in PNR register
860 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
861 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
862
863
864 // Packet Number Register
865 /* BANK 2 */
866 #define PN_REG SMC_REG(0x0002, 2)
867
868
869 // Allocation Result Register
870 /* BANK 2 */
871 #define AR_REG SMC_REG(0x0003, 2)
872 #define AR_FAILED 0x80 // Alocation Failed
873
874
875 // TX FIFO Ports Register
876 /* BANK 2 */
877 #define TXFIFO_REG SMC_REG(0x0004, 2)
878 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
879
880 // RX FIFO Ports Register
881 /* BANK 2 */
882 #define RXFIFO_REG SMC_REG(0x0005, 2)
883 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
884
885 #define FIFO_REG SMC_REG(0x0004, 2)
886
887 // Pointer Register
888 /* BANK 2 */
889 #define PTR_REG SMC_REG(0x0006, 2)
890 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
891 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
892 #define PTR_READ 0x2000 // When 1 the operation is a read
893
894
895 // Data Register
896 /* BANK 2 */
897 #define DATA_REG SMC_REG(0x0008, 2)
898
899
900 // Interrupt Status/Acknowledge Register
901 /* BANK 2 */
902 #define INT_REG SMC_REG(0x000C, 2)
903
904
905 // Interrupt Mask Register
906 /* BANK 2 */
907 #define IM_REG SMC_REG(0x000D, 2)
908 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
909 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
910 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
911 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
912 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
913 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
914 #define IM_TX_INT 0x02 // Transmit Interrupt
915 #define IM_RCV_INT 0x01 // Receive Interrupt
916
917
918 // Multicast Table Registers
919 /* BANK 3 */
920 #define MCAST_REG1 SMC_REG(0x0000, 3)
921 #define MCAST_REG2 SMC_REG(0x0002, 3)
922 #define MCAST_REG3 SMC_REG(0x0004, 3)
923 #define MCAST_REG4 SMC_REG(0x0006, 3)
924
925
926 // Management Interface Register (MII)
927 /* BANK 3 */
928 #define MII_REG SMC_REG(0x0008, 3)
929 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
930 #define MII_MDOE 0x0008 // MII Output Enable
931 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
932 #define MII_MDI 0x0002 // MII Input, pin MDI
933 #define MII_MDO 0x0001 // MII Output, pin MDO
934
935
936 // Revision Register
937 /* BANK 3 */
938 /* ( hi: chip id low: rev # ) */
939 #define REV_REG SMC_REG(0x000A, 3)
940
941
942 // Early RCV Register
943 /* BANK 3 */
944 /* this is NOT on SMC9192 */
945 #define ERCV_REG SMC_REG(0x000C, 3)
946 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
947 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
948
949
950 // External Register
951 /* BANK 7 */
952 #define EXT_REG SMC_REG(0x0000, 7)
953
954
955 #define CHIP_9192 3
956 #define CHIP_9194 4
957 #define CHIP_9195 5
958 #define CHIP_9196 6
959 #define CHIP_91100 7
960 #define CHIP_91100FD 8
961 #define CHIP_91111FD 9
962
963 static const char * chip_ids[ 16 ] = {
964 NULL, NULL, NULL,
965 /* 3 */ "SMC91C90/91C92",
966 /* 4 */ "SMC91C94",
967 /* 5 */ "SMC91C95",
968 /* 6 */ "SMC91C96",
969 /* 7 */ "SMC91C100",
970 /* 8 */ "SMC91C100FD",
971 /* 9 */ "SMC91C11xFD",
972 NULL, NULL, NULL,
973 NULL, NULL, NULL};
974
975
976 /*
977 . Receive status bits
978 */
979 #define RS_ALGNERR 0x8000
980 #define RS_BRODCAST 0x4000
981 #define RS_BADCRC 0x2000
982 #define RS_ODDFRAME 0x1000
983 #define RS_TOOLONG 0x0800
984 #define RS_TOOSHORT 0x0400
985 #define RS_MULTICAST 0x0001
986 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
987
988
989 /*
990 * PHY IDs
991 * LAN83C183 == LAN91C111 Internal PHY
992 */
993 #define PHY_LAN83C183 0x0016f840
994 #define PHY_LAN83C180 0x02821c50
995
996 /*
997 * PHY Register Addresses (LAN91C111 Internal PHY)
998 *
999 * Generic PHY registers can be found in <linux/mii.h>
1000 *
1001 * These phy registers are specific to our on-board phy.
1002 */
1003
1004 // PHY Configuration Register 1
1005 #define PHY_CFG1_REG 0x10
1006 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
1007 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
1008 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1009 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1010 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1011 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1012 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1013 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1014 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1015 #define PHY_CFG1_TLVL_MASK 0x003C
1016 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1017
1018
1019 // PHY Configuration Register 2
1020 #define PHY_CFG2_REG 0x11
1021 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1022 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1023 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1024 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1025
1026 // PHY Status Output (and Interrupt status) Register
1027 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1028 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1029 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1030 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1031 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1032 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1033 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1034 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1035 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1036 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1037 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1038
1039 // PHY Interrupt/Status Mask Register
1040 #define PHY_MASK_REG 0x13 // Interrupt Mask
1041 // Uses the same bit definitions as PHY_INT_REG
1042
1043
1044 /*
1045 * SMC91C96 ethernet config and status registers.
1046 * These are in the "attribute" space.
1047 */
1048 #define ECOR 0x8000
1049 #define ECOR_RESET 0x80
1050 #define ECOR_LEVEL_IRQ 0x40
1051 #define ECOR_WR_ATTRIB 0x04
1052 #define ECOR_ENABLE 0x01
1053
1054 #define ECSR 0x8002
1055 #define ECSR_IOIS8 0x20
1056 #define ECSR_PWRDWN 0x04
1057 #define ECSR_INT 0x02
1058
1059 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1060
1061
1062 /*
1063 * Macros to abstract register access according to the data bus
1064 * capabilities. Please use those and not the in/out primitives.
1065 * Note: the following macros do *not* select the bank -- this must
1066 * be done separately as needed in the main code. The SMC_REG() macro
1067 * only uses the bank argument for debugging purposes (when enabled).
1068 *
1069 * Note: despite inline functions being safer, everything leading to this
1070 * should preferably be macros to let BUG() display the line number in
1071 * the core source code since we're interested in the top call site
1072 * not in any inline function location.
1073 */
1074
1075 #if SMC_DEBUG > 0
1076 #define SMC_REG(reg, bank) \
1077 ({ \
1078 int __b = SMC_CURRENT_BANK(); \
1079 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1080 printk( "%s: bank reg screwed (0x%04x)\n", \
1081 CARDNAME, __b ); \
1082 BUG(); \
1083 } \
1084 reg<<SMC_IO_SHIFT; \
1085 })
1086 #else
1087 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1088 #endif
1089
1090 /*
1091 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1092 * aligned to a 32 bit boundary. I tell you that does exist!
1093 * Fortunately the affected register accesses can be easily worked around
1094 * since we can write zeroes to the preceeding 16 bits without adverse
1095 * effects and use a 32-bit access.
1096 *
1097 * Enforce it on any 32-bit capable setup for now.
1098 */
1099 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1100
1101 #define SMC_GET_PN() \
1102 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1103 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1104
1105 #define SMC_SET_PN(x) \
1106 do { \
1107 if (SMC_MUST_ALIGN_WRITE) \
1108 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1109 else if (SMC_CAN_USE_8BIT) \
1110 SMC_outb(x, ioaddr, PN_REG); \
1111 else \
1112 SMC_outw(x, ioaddr, PN_REG); \
1113 } while (0)
1114
1115 #define SMC_GET_AR() \
1116 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1117 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1118
1119 #define SMC_GET_TXFIFO() \
1120 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1121 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1122
1123 #define SMC_GET_RXFIFO() \
1124 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1125 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1126
1127 #define SMC_GET_INT() \
1128 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1129 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1130
1131 #define SMC_ACK_INT(x) \
1132 do { \
1133 if (SMC_CAN_USE_8BIT) \
1134 SMC_outb(x, ioaddr, INT_REG); \
1135 else { \
1136 unsigned long __flags; \
1137 int __mask; \
1138 local_irq_save(__flags); \
1139 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1140 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1141 local_irq_restore(__flags); \
1142 } \
1143 } while (0)
1144
1145 #define SMC_GET_INT_MASK() \
1146 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1147 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1148
1149 #define SMC_SET_INT_MASK(x) \
1150 do { \
1151 if (SMC_CAN_USE_8BIT) \
1152 SMC_outb(x, ioaddr, IM_REG); \
1153 else \
1154 SMC_outw((x) << 8, ioaddr, INT_REG); \
1155 } while (0)
1156
1157 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1158
1159 #define SMC_SELECT_BANK(x) \
1160 do { \
1161 if (SMC_MUST_ALIGN_WRITE) \
1162 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1163 else \
1164 SMC_outw(x, ioaddr, BANK_SELECT); \
1165 } while (0)
1166
1167 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1168
1169 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1170
1171 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1172
1173 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1174
1175 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1176
1177 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1178
1179 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1180
1181 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1182
1183 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1184
1185 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1186
1187 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1188
1189 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1190
1191 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1192
1193 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1194
1195 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1196
1197 #define SMC_SET_PTR(x) \
1198 do { \
1199 if (SMC_MUST_ALIGN_WRITE) \
1200 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1201 else \
1202 SMC_outw(x, ioaddr, PTR_REG); \
1203 } while (0)
1204
1205 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1206
1207 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1208
1209 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1210
1211 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1212
1213 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1214
1215 #define SMC_SET_RPC(x) \
1216 do { \
1217 if (SMC_MUST_ALIGN_WRITE) \
1218 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1219 else \
1220 SMC_outw(x, ioaddr, RPC_REG); \
1221 } while (0)
1222
1223 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1224
1225 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1226
1227 #ifndef SMC_GET_MAC_ADDR
1228 #define SMC_GET_MAC_ADDR(addr) \
1229 do { \
1230 unsigned int __v; \
1231 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1232 addr[0] = __v; addr[1] = __v >> 8; \
1233 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1234 addr[2] = __v; addr[3] = __v >> 8; \
1235 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1236 addr[4] = __v; addr[5] = __v >> 8; \
1237 } while (0)
1238 #endif
1239
1240 #define SMC_SET_MAC_ADDR(addr) \
1241 do { \
1242 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1243 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1244 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1245 } while (0)
1246
1247 #define SMC_SET_MCAST(x) \
1248 do { \
1249 const unsigned char *mt = (x); \
1250 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1251 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1252 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1253 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1254 } while (0)
1255
1256 #define SMC_PUT_PKT_HDR(status, length) \
1257 do { \
1258 if (SMC_CAN_USE_32BIT) \
1259 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1260 else { \
1261 SMC_outw(status, ioaddr, DATA_REG); \
1262 SMC_outw(length, ioaddr, DATA_REG); \
1263 } \
1264 } while (0)
1265
1266 #define SMC_GET_PKT_HDR(status, length) \
1267 do { \
1268 if (SMC_CAN_USE_32BIT) { \
1269 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1270 (status) = __val & 0xffff; \
1271 (length) = __val >> 16; \
1272 } else { \
1273 (status) = SMC_inw(ioaddr, DATA_REG); \
1274 (length) = SMC_inw(ioaddr, DATA_REG); \
1275 } \
1276 } while (0)
1277
1278 #define SMC_PUSH_DATA(p, l) \
1279 do { \
1280 if (SMC_CAN_USE_32BIT) { \
1281 void *__ptr = (p); \
1282 int __len = (l); \
1283 void __iomem *__ioaddr = ioaddr; \
1284 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1285 __len -= 2; \
1286 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1287 __ptr += 2; \
1288 } \
1289 if (SMC_CAN_USE_DATACS && lp->datacs) \
1290 __ioaddr = lp->datacs; \
1291 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1292 if (__len & 2) { \
1293 __ptr += (__len & ~3); \
1294 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1295 } \
1296 } else if (SMC_CAN_USE_16BIT) \
1297 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1298 else if (SMC_CAN_USE_8BIT) \
1299 SMC_outsb(ioaddr, DATA_REG, p, l); \
1300 } while (0)
1301
1302 #define SMC_PULL_DATA(p, l) \
1303 do { \
1304 if (SMC_CAN_USE_32BIT) { \
1305 void *__ptr = (p); \
1306 int __len = (l); \
1307 void __iomem *__ioaddr = ioaddr; \
1308 if ((unsigned long)__ptr & 2) { \
1309 /* \
1310 * We want 32bit alignment here. \
1311 * Since some buses perform a full \
1312 * 32bit fetch even for 16bit data \
1313 * we can't use SMC_inw() here. \
1314 * Back both source (on-chip) and \
1315 * destination pointers of 2 bytes. \
1316 * This is possible since the call to \
1317 * SMC_GET_PKT_HDR() already advanced \
1318 * the source pointer of 4 bytes, and \
1319 * the skb_reserve(skb, 2) advanced \
1320 * the destination pointer of 2 bytes. \
1321 */ \
1322 __ptr -= 2; \
1323 __len += 2; \
1324 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1325 } \
1326 if (SMC_CAN_USE_DATACS && lp->datacs) \
1327 __ioaddr = lp->datacs; \
1328 __len += 2; \
1329 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1330 } else if (SMC_CAN_USE_16BIT) \
1331 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1332 else if (SMC_CAN_USE_8BIT) \
1333 SMC_insb(ioaddr, DATA_REG, p, l); \
1334 } while (0)
1335
1336 #endif /* _SMC91X_H_ */
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