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[ARM] 4982/1: [AT91] Drop old-style UART initialization (Part 1)
[linux-2.6/sactl.git] / arch / arm / mach-at91 / at91sam9263_devices.c
blobb6454c52596227a640c77b15ec3699d05fcd1b3e
1 /*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18
19 #include <linux/fb.h>
20 #include <video/atmel_lcdc.h>
21
22 #include <asm/arch/board.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/at91sam9263.h>
25 #include <asm/arch/at91sam9263_matrix.h>
26 #include <asm/arch/at91sam9_smc.h>
27
28 #include "generic.h"
29
30
31 /* --------------------------------------------------------------------
32 * USB Host
33 * -------------------------------------------------------------------- */
34
35 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
36 static u64 ohci_dmamask = DMA_BIT_MASK(32);
37 static struct at91_usbh_data usbh_data;
38
39 static struct resource usbh_resources[] = {
40 [0] = {
41 .start = AT91SAM9263_UHP_BASE,
42 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = AT91SAM9263_ID_UHP,
47 .end = AT91SAM9263_ID_UHP,
48 .flags = IORESOURCE_IRQ,
49 },
50 };
51
52 static struct platform_device at91_usbh_device = {
53 .name = "at91_ohci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &ohci_dmamask,
57 .coherent_dma_mask = DMA_BIT_MASK(32),
58 .platform_data = &usbh_data,
59 },
60 .resource = usbh_resources,
61 .num_resources = ARRAY_SIZE(usbh_resources),
62 };
63
64 void __init at91_add_device_usbh(struct at91_usbh_data *data)
65 {
66 int i;
67
68 if (!data)
69 return;
70
71 /* Enable VBus control for UHP ports */
72 for (i = 0; i < data->ports; i++) {
73 if (data->vbus_pin[i])
74 at91_set_gpio_output(data->vbus_pin[i], 0);
75 }
76
77 usbh_data = *data;
78 platform_device_register(&at91_usbh_device);
79 }
80 #else
81 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
82 #endif
83
84
85 /* --------------------------------------------------------------------
86 * USB Device (Gadget)
87 * -------------------------------------------------------------------- */
88
89 #ifdef CONFIG_USB_GADGET_AT91
90 static struct at91_udc_data udc_data;
91
92 static struct resource udc_resources[] = {
93 [0] = {
94 .start = AT91SAM9263_BASE_UDP,
95 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = AT91SAM9263_ID_UDP,
100 .end = AT91SAM9263_ID_UDP,
101 .flags = IORESOURCE_IRQ,
102 },
103 };
104
105 static struct platform_device at91_udc_device = {
106 .name = "at91_udc",
107 .id = -1,
108 .dev = {
109 .platform_data = &udc_data,
110 },
111 .resource = udc_resources,
112 .num_resources = ARRAY_SIZE(udc_resources),
113 };
114
115 void __init at91_add_device_udc(struct at91_udc_data *data)
116 {
117 if (!data)
118 return;
119
120 if (data->vbus_pin) {
121 at91_set_gpio_input(data->vbus_pin, 0);
122 at91_set_deglitch(data->vbus_pin, 1);
123 }
124
125 /* Pullup pin is handled internally by USB device peripheral */
126
127 udc_data = *data;
128 platform_device_register(&at91_udc_device);
129 }
130 #else
131 void __init at91_add_device_udc(struct at91_udc_data *data) {}
132 #endif
133
134
135 /* --------------------------------------------------------------------
136 * Ethernet
137 * -------------------------------------------------------------------- */
138
139 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
140 static u64 eth_dmamask = DMA_BIT_MASK(32);
141 static struct at91_eth_data eth_data;
142
143 static struct resource eth_resources[] = {
144 [0] = {
145 .start = AT91SAM9263_BASE_EMAC,
146 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 [1] = {
150 .start = AT91SAM9263_ID_EMAC,
151 .end = AT91SAM9263_ID_EMAC,
152 .flags = IORESOURCE_IRQ,
153 },
154 };
155
156 static struct platform_device at91sam9263_eth_device = {
157 .name = "macb",
158 .id = -1,
159 .dev = {
160 .dma_mask = &eth_dmamask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 .platform_data = &eth_data,
163 },
164 .resource = eth_resources,
165 .num_resources = ARRAY_SIZE(eth_resources),
166 };
167
168 void __init at91_add_device_eth(struct at91_eth_data *data)
169 {
170 if (!data)
171 return;
172
173 if (data->phy_irq_pin) {
174 at91_set_gpio_input(data->phy_irq_pin, 0);
175 at91_set_deglitch(data->phy_irq_pin, 1);
176 }
177
178 /* Pins used for MII and RMII */
179 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
180 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
181 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
182 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
183 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
184 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
185 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
186 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
187 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
188 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
189
190 if (!data->is_rmii) {
191 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
192 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
193 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
194 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
195 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
196 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
197 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
198 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
199 }
200
201 eth_data = *data;
202 platform_device_register(&at91sam9263_eth_device);
203 }
204 #else
205 void __init at91_add_device_eth(struct at91_eth_data *data) {}
206 #endif
207
208
209 /* --------------------------------------------------------------------
210 * MMC / SD
211 * -------------------------------------------------------------------- */
212
213 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
214 static u64 mmc_dmamask = DMA_BIT_MASK(32);
215 static struct at91_mmc_data mmc0_data, mmc1_data;
216
217 static struct resource mmc0_resources[] = {
218 [0] = {
219 .start = AT91SAM9263_BASE_MCI0,
220 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = AT91SAM9263_ID_MCI0,
225 .end = AT91SAM9263_ID_MCI0,
226 .flags = IORESOURCE_IRQ,
227 },
228 };
229
230 static struct platform_device at91sam9263_mmc0_device = {
231 .name = "at91_mci",
232 .id = 0,
233 .dev = {
234 .dma_mask = &mmc_dmamask,
235 .coherent_dma_mask = DMA_BIT_MASK(32),
236 .platform_data = &mmc0_data,
237 },
238 .resource = mmc0_resources,
239 .num_resources = ARRAY_SIZE(mmc0_resources),
240 };
241
242 static struct resource mmc1_resources[] = {
243 [0] = {
244 .start = AT91SAM9263_BASE_MCI1,
245 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = AT91SAM9263_ID_MCI1,
250 .end = AT91SAM9263_ID_MCI1,
251 .flags = IORESOURCE_IRQ,
252 },
253 };
254
255 static struct platform_device at91sam9263_mmc1_device = {
256 .name = "at91_mci",
257 .id = 1,
258 .dev = {
259 .dma_mask = &mmc_dmamask,
260 .coherent_dma_mask = DMA_BIT_MASK(32),
261 .platform_data = &mmc1_data,
262 },
263 .resource = mmc1_resources,
264 .num_resources = ARRAY_SIZE(mmc1_resources),
265 };
266
267 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
268 {
269 if (!data)
270 return;
271
272 /* input/irq */
273 if (data->det_pin) {
274 at91_set_gpio_input(data->det_pin, 1);
275 at91_set_deglitch(data->det_pin, 1);
276 }
277 if (data->wp_pin)
278 at91_set_gpio_input(data->wp_pin, 1);
279 if (data->vcc_pin)
280 at91_set_gpio_output(data->vcc_pin, 0);
281
282 if (mmc_id == 0) { /* MCI0 */
283 /* CLK */
284 at91_set_A_periph(AT91_PIN_PA12, 0);
285
286 if (data->slot_b) {
287 /* CMD */
288 at91_set_A_periph(AT91_PIN_PA16, 1);
289
290 /* DAT0, maybe DAT1..DAT3 */
291 at91_set_A_periph(AT91_PIN_PA17, 1);
292 if (data->wire4) {
293 at91_set_A_periph(AT91_PIN_PA18, 1);
294 at91_set_A_periph(AT91_PIN_PA19, 1);
295 at91_set_A_periph(AT91_PIN_PA20, 1);
296 }
297 } else {
298 /* CMD */
299 at91_set_A_periph(AT91_PIN_PA1, 1);
300
301 /* DAT0, maybe DAT1..DAT3 */
302 at91_set_A_periph(AT91_PIN_PA0, 1);
303 if (data->wire4) {
304 at91_set_A_periph(AT91_PIN_PA3, 1);
305 at91_set_A_periph(AT91_PIN_PA4, 1);
306 at91_set_A_periph(AT91_PIN_PA5, 1);
307 }
308 }
309
310 mmc0_data = *data;
311 at91_clock_associate("mci0_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
312 platform_device_register(&at91sam9263_mmc0_device);
313 } else { /* MCI1 */
314 /* CLK */
315 at91_set_A_periph(AT91_PIN_PA6, 0);
316
317 if (data->slot_b) {
318 /* CMD */
319 at91_set_A_periph(AT91_PIN_PA21, 1);
320
321 /* DAT0, maybe DAT1..DAT3 */
322 at91_set_A_periph(AT91_PIN_PA22, 1);
323 if (data->wire4) {
324 at91_set_A_periph(AT91_PIN_PA23, 1);
325 at91_set_A_periph(AT91_PIN_PA24, 1);
326 at91_set_A_periph(AT91_PIN_PA25, 1);
327 }
328 } else {
329 /* CMD */
330 at91_set_A_periph(AT91_PIN_PA7, 1);
331
332 /* DAT0, maybe DAT1..DAT3 */
333 at91_set_A_periph(AT91_PIN_PA8, 1);
334 if (data->wire4) {
335 at91_set_A_periph(AT91_PIN_PA9, 1);
336 at91_set_A_periph(AT91_PIN_PA10, 1);
337 at91_set_A_periph(AT91_PIN_PA11, 1);
338 }
339 }
340
341 mmc1_data = *data;
342 at91_clock_associate("mci1_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
343 platform_device_register(&at91sam9263_mmc1_device);
344 }
345 }
346 #else
347 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
348 #endif
349
350
351 /* --------------------------------------------------------------------
352 * NAND / SmartMedia
353 * -------------------------------------------------------------------- */
354
355 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
356 static struct at91_nand_data nand_data;
357
358 #define NAND_BASE AT91_CHIPSELECT_3
359
360 static struct resource nand_resources[] = {
361 [0] = {
362 .start = NAND_BASE,
363 .end = NAND_BASE + SZ_256M - 1,
364 .flags = IORESOURCE_MEM,
365 },
366 [1] = {
367 .start = AT91_BASE_SYS + AT91_ECC0,
368 .end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
369 .flags = IORESOURCE_MEM,
370 }
371 };
372
373 static struct platform_device at91sam9263_nand_device = {
374 .name = "at91_nand",
375 .id = -1,
376 .dev = {
377 .platform_data = &nand_data,
378 },
379 .resource = nand_resources,
380 .num_resources = ARRAY_SIZE(nand_resources),
381 };
382
383 void __init at91_add_device_nand(struct at91_nand_data *data)
384 {
385 unsigned long csa, mode;
386
387 if (!data)
388 return;
389
390 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
391 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
392
393 /* set the bus interface characteristics */
394 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
395 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
396
397 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
398 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
399
400 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
401
402 if (data->bus_width_16)
403 mode = AT91_SMC_DBW_16;
404 else
405 mode = AT91_SMC_DBW_8;
406 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
407
408 /* enable pin */
409 if (data->enable_pin)
410 at91_set_gpio_output(data->enable_pin, 1);
411
412 /* ready/busy pin */
413 if (data->rdy_pin)
414 at91_set_gpio_input(data->rdy_pin, 1);
415
416 /* card detect pin */
417 if (data->det_pin)
418 at91_set_gpio_input(data->det_pin, 1);
419
420 nand_data = *data;
421 platform_device_register(&at91sam9263_nand_device);
422 }
423 #else
424 void __init at91_add_device_nand(struct at91_nand_data *data) {}
425 #endif
426
427
428 /* --------------------------------------------------------------------
429 * TWI (i2c)
430 * -------------------------------------------------------------------- */
431
432 /*
433 * Prefer the GPIO code since the TWI controller isn't robust
434 * (gets overruns and underruns under load) and can only issue
435 * repeated STARTs in one scenario (the driver doesn't yet handle them).
436 */
437 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
438
439 static struct i2c_gpio_platform_data pdata = {
440 .sda_pin = AT91_PIN_PB4,
441 .sda_is_open_drain = 1,
442 .scl_pin = AT91_PIN_PB5,
443 .scl_is_open_drain = 1,
444 .udelay = 2, /* ~100 kHz */
445 };
446
447 static struct platform_device at91sam9263_twi_device = {
448 .name = "i2c-gpio",
449 .id = -1,
450 .dev.platform_data = &pdata,
451 };
452
453 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
454 {
455 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
456 at91_set_multi_drive(AT91_PIN_PB4, 1);
457
458 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
459 at91_set_multi_drive(AT91_PIN_PB5, 1);
460
461 i2c_register_board_info(0, devices, nr_devices);
462 platform_device_register(&at91sam9263_twi_device);
463 }
464
465 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
466
467 static struct resource twi_resources[] = {
468 [0] = {
469 .start = AT91SAM9263_BASE_TWI,
470 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
471 .flags = IORESOURCE_MEM,
472 },
473 [1] = {
474 .start = AT91SAM9263_ID_TWI,
475 .end = AT91SAM9263_ID_TWI,
476 .flags = IORESOURCE_IRQ,
477 },
478 };
479
480 static struct platform_device at91sam9263_twi_device = {
481 .name = "at91_i2c",
482 .id = -1,
483 .resource = twi_resources,
484 .num_resources = ARRAY_SIZE(twi_resources),
485 };
486
487 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
488 {
489 /* pins used for TWI interface */
490 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
491 at91_set_multi_drive(AT91_PIN_PB4, 1);
492
493 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
494 at91_set_multi_drive(AT91_PIN_PB5, 1);
495
496 i2c_register_board_info(0, devices, nr_devices);
497 platform_device_register(&at91sam9263_twi_device);
498 }
499 #else
500 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
501 #endif
502
503
504 /* --------------------------------------------------------------------
505 * SPI
506 * -------------------------------------------------------------------- */
507
508 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
509 static u64 spi_dmamask = DMA_BIT_MASK(32);
510
511 static struct resource spi0_resources[] = {
512 [0] = {
513 .start = AT91SAM9263_BASE_SPI0,
514 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
515 .flags = IORESOURCE_MEM,
516 },
517 [1] = {
518 .start = AT91SAM9263_ID_SPI0,
519 .end = AT91SAM9263_ID_SPI0,
520 .flags = IORESOURCE_IRQ,
521 },
522 };
523
524 static struct platform_device at91sam9263_spi0_device = {
525 .name = "atmel_spi",
526 .id = 0,
527 .dev = {
528 .dma_mask = &spi_dmamask,
529 .coherent_dma_mask = DMA_BIT_MASK(32),
530 },
531 .resource = spi0_resources,
532 .num_resources = ARRAY_SIZE(spi0_resources),
533 };
534
535 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
536
537 static struct resource spi1_resources[] = {
538 [0] = {
539 .start = AT91SAM9263_BASE_SPI1,
540 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
541 .flags = IORESOURCE_MEM,
542 },
543 [1] = {
544 .start = AT91SAM9263_ID_SPI1,
545 .end = AT91SAM9263_ID_SPI1,
546 .flags = IORESOURCE_IRQ,
547 },
548 };
549
550 static struct platform_device at91sam9263_spi1_device = {
551 .name = "atmel_spi",
552 .id = 1,
553 .dev = {
554 .dma_mask = &spi_dmamask,
555 .coherent_dma_mask = DMA_BIT_MASK(32),
556 },
557 .resource = spi1_resources,
558 .num_resources = ARRAY_SIZE(spi1_resources),
559 };
560
561 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
562
563 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
564 {
565 int i;
566 unsigned long cs_pin;
567 short enable_spi0 = 0;
568 short enable_spi1 = 0;
569
570 /* Choose SPI chip-selects */
571 for (i = 0; i < nr_devices; i++) {
572 if (devices[i].controller_data)
573 cs_pin = (unsigned long) devices[i].controller_data;
574 else if (devices[i].bus_num == 0)
575 cs_pin = spi0_standard_cs[devices[i].chip_select];
576 else
577 cs_pin = spi1_standard_cs[devices[i].chip_select];
578
579 if (devices[i].bus_num == 0)
580 enable_spi0 = 1;
581 else
582 enable_spi1 = 1;
583
584 /* enable chip-select pin */
585 at91_set_gpio_output(cs_pin, 1);
586
587 /* pass chip-select pin to driver */
588 devices[i].controller_data = (void *) cs_pin;
589 }
590
591 spi_register_board_info(devices, nr_devices);
592
593 /* Configure SPI bus(es) */
594 if (enable_spi0) {
595 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
596 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
597 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
598
599 at91_clock_associate("spi0_clk", &at91sam9263_spi0_device.dev, "spi_clk");
600 platform_device_register(&at91sam9263_spi0_device);
601 }
602 if (enable_spi1) {
603 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
604 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
605 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
606
607 at91_clock_associate("spi1_clk", &at91sam9263_spi1_device.dev, "spi_clk");
608 platform_device_register(&at91sam9263_spi1_device);
609 }
610 }
611 #else
612 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
613 #endif
614
615
616 /* --------------------------------------------------------------------
617 * AC97
618 * -------------------------------------------------------------------- */
619
620 #if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
621 static u64 ac97_dmamask = DMA_BIT_MASK(32);
622 static struct atmel_ac97_data ac97_data;
623
624 static struct resource ac97_resources[] = {
625 [0] = {
626 .start = AT91SAM9263_BASE_AC97C,
627 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
628 .flags = IORESOURCE_MEM,
629 },
630 [1] = {
631 .start = AT91SAM9263_ID_AC97C,
632 .end = AT91SAM9263_ID_AC97C,
633 .flags = IORESOURCE_IRQ,
634 },
635 };
636
637 static struct platform_device at91sam9263_ac97_device = {
638 .name = "ac97c",
639 .id = 1,
640 .dev = {
641 .dma_mask = &ac97_dmamask,
642 .coherent_dma_mask = DMA_BIT_MASK(32),
643 .platform_data = &ac97_data,
644 },
645 .resource = ac97_resources,
646 .num_resources = ARRAY_SIZE(ac97_resources),
647 };
648
649 void __init at91_add_device_ac97(struct atmel_ac97_data *data)
650 {
651 if (!data)
652 return;
653
654 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
655 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
656 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
657 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
658
659 /* reset */
660 if (data->reset_pin)
661 at91_set_gpio_output(data->reset_pin, 0);
662
663 ac97_data = *ek_data;
664 platform_device_register(&at91sam9263_ac97_device);
665 }
666 #else
667 void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
668 #endif
669
670
671 /* --------------------------------------------------------------------
672 * LCD Controller
673 * -------------------------------------------------------------------- */
674
675 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
676 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
677 static struct atmel_lcdfb_info lcdc_data;
678
679 static struct resource lcdc_resources[] = {
680 [0] = {
681 .start = AT91SAM9263_LCDC_BASE,
682 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
683 .flags = IORESOURCE_MEM,
684 },
685 [1] = {
686 .start = AT91SAM9263_ID_LCDC,
687 .end = AT91SAM9263_ID_LCDC,
688 .flags = IORESOURCE_IRQ,
689 },
690 };
691
692 static struct platform_device at91_lcdc_device = {
693 .name = "atmel_lcdfb",
694 .id = 0,
695 .dev = {
696 .dma_mask = &lcdc_dmamask,
697 .coherent_dma_mask = DMA_BIT_MASK(32),
698 .platform_data = &lcdc_data,
699 },
700 .resource = lcdc_resources,
701 .num_resources = ARRAY_SIZE(lcdc_resources),
702 };
703
704 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
705 {
706 if (!data)
707 return;
708
709 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
710 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
711 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
712 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
713 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
714 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
715 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
716 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
717 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
718 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
719 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
720 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
721 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
722 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
723 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
724 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
725 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
726 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
727 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
728 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
729 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
730 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
731
732 lcdc_data = *data;
733 platform_device_register(&at91_lcdc_device);
734 }
735 #else
736 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
737 #endif
738
739
740 /* --------------------------------------------------------------------
741 * Image Sensor Interface
742 * -------------------------------------------------------------------- */
743
744 #if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
745
746 struct resource isi_resources[] = {
747 [0] = {
748 .start = AT91SAM9263_BASE_ISI,
749 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
750 .flags = IORESOURCE_MEM,
751 },
752 [1] = {
753 .start = AT91SAM9263_ID_ISI,
754 .end = AT91SAM9263_ID_ISI,
755 .flags = IORESOURCE_IRQ,
756 },
757 };
758
759 static struct platform_device at91sam9263_isi_device = {
760 .name = "at91_isi",
761 .id = -1,
762 .resource = isi_resources,
763 .num_resources = ARRAY_SIZE(isi_resources),
764 };
765
766 void __init at91_add_device_isi(void)
767 {
768 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
769 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
770 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
771 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
772 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
773 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
774 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
775 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
776 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
777 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
778 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
779 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
780 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
781 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
782 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
783 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
784 }
785 #else
786 void __init at91_add_device_isi(void) {}
787 #endif
788
789
790 /* --------------------------------------------------------------------
791 * Timer/Counter block
792 * -------------------------------------------------------------------- */
793
794 #ifdef CONFIG_ATMEL_TCLIB
795
796 static struct resource tcb_resources[] = {
797 [0] = {
798 .start = AT91SAM9263_BASE_TCB0,
799 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
800 .flags = IORESOURCE_MEM,
801 },
802 [1] = {
803 .start = AT91SAM9263_ID_TCB,
804 .end = AT91SAM9263_ID_TCB,
805 .flags = IORESOURCE_IRQ,
806 },
807 };
808
809 static struct platform_device at91sam9263_tcb_device = {
810 .name = "atmel_tcb",
811 .id = 0,
812 .resource = tcb_resources,
813 .num_resources = ARRAY_SIZE(tcb_resources),
814 };
815
816 static void __init at91_add_device_tc(void)
817 {
818 /* this chip has one clock and irq for all three TC channels */
819 at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
820 platform_device_register(&at91sam9263_tcb_device);
821 }
822 #else
823 static void __init at91_add_device_tc(void) { }
824 #endif
825
826
827 /* --------------------------------------------------------------------
828 * RTT
829 * -------------------------------------------------------------------- */
830
831 static struct resource rtt0_resources[] = {
832 {
833 .start = AT91_BASE_SYS + AT91_RTT0,
834 .end = AT91_BASE_SYS + AT91_RTT0 + SZ_16 - 1,
835 .flags = IORESOURCE_MEM,
836 }
837 };
838
839 static struct platform_device at91sam9263_rtt0_device = {
840 .name = "at91_rtt",
841 .id = 0,
842 .resource = rtt0_resources,
843 .num_resources = ARRAY_SIZE(rtt0_resources),
844 };
845
846 static struct resource rtt1_resources[] = {
847 {
848 .start = AT91_BASE_SYS + AT91_RTT1,
849 .end = AT91_BASE_SYS + AT91_RTT1 + SZ_16 - 1,
850 .flags = IORESOURCE_MEM,
851 }
852 };
853
854 static struct platform_device at91sam9263_rtt1_device = {
855 .name = "at91_rtt",
856 .id = 1,
857 .resource = rtt1_resources,
858 .num_resources = ARRAY_SIZE(rtt1_resources),
859 };
860
861 static void __init at91_add_device_rtt(void)
862 {
863 platform_device_register(&at91sam9263_rtt0_device);
864 platform_device_register(&at91sam9263_rtt1_device);
865 }
866
867
868 /* --------------------------------------------------------------------
869 * Watchdog
870 * -------------------------------------------------------------------- */
871
872 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
873 static struct platform_device at91sam9263_wdt_device = {
874 .name = "at91_wdt",
875 .id = -1,
876 .num_resources = 0,
877 };
878
879 static void __init at91_add_device_watchdog(void)
880 {
881 platform_device_register(&at91sam9263_wdt_device);
882 }
883 #else
884 static void __init at91_add_device_watchdog(void) {}
885 #endif
886
887
888 /* --------------------------------------------------------------------
889 * SSC -- Synchronous Serial Controller
890 * -------------------------------------------------------------------- */
891
892 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
893 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
894
895 static struct resource ssc0_resources[] = {
896 [0] = {
897 .start = AT91SAM9263_BASE_SSC0,
898 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
899 .flags = IORESOURCE_MEM,
900 },
901 [1] = {
902 .start = AT91SAM9263_ID_SSC0,
903 .end = AT91SAM9263_ID_SSC0,
904 .flags = IORESOURCE_IRQ,
905 },
906 };
907
908 static struct platform_device at91sam9263_ssc0_device = {
909 .name = "ssc",
910 .id = 0,
911 .dev = {
912 .dma_mask = &ssc0_dmamask,
913 .coherent_dma_mask = DMA_BIT_MASK(32),
914 },
915 .resource = ssc0_resources,
916 .num_resources = ARRAY_SIZE(ssc0_resources),
917 };
918
919 static inline void configure_ssc0_pins(unsigned pins)
920 {
921 if (pins & ATMEL_SSC_TF)
922 at91_set_B_periph(AT91_PIN_PB0, 1);
923 if (pins & ATMEL_SSC_TK)
924 at91_set_B_periph(AT91_PIN_PB1, 1);
925 if (pins & ATMEL_SSC_TD)
926 at91_set_B_periph(AT91_PIN_PB2, 1);
927 if (pins & ATMEL_SSC_RD)
928 at91_set_B_periph(AT91_PIN_PB3, 1);
929 if (pins & ATMEL_SSC_RK)
930 at91_set_B_periph(AT91_PIN_PB4, 1);
931 if (pins & ATMEL_SSC_RF)
932 at91_set_B_periph(AT91_PIN_PB5, 1);
933 }
934
935 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
936
937 static struct resource ssc1_resources[] = {
938 [0] = {
939 .start = AT91SAM9263_BASE_SSC1,
940 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
941 .flags = IORESOURCE_MEM,
942 },
943 [1] = {
944 .start = AT91SAM9263_ID_SSC1,
945 .end = AT91SAM9263_ID_SSC1,
946 .flags = IORESOURCE_IRQ,
947 },
948 };
949
950 static struct platform_device at91sam9263_ssc1_device = {
951 .name = "ssc",
952 .id = 1,
953 .dev = {
954 .dma_mask = &ssc1_dmamask,
955 .coherent_dma_mask = DMA_BIT_MASK(32),
956 },
957 .resource = ssc1_resources,
958 .num_resources = ARRAY_SIZE(ssc1_resources),
959 };
960
961 static inline void configure_ssc1_pins(unsigned pins)
962 {
963 if (pins & ATMEL_SSC_TF)
964 at91_set_A_periph(AT91_PIN_PB6, 1);
965 if (pins & ATMEL_SSC_TK)
966 at91_set_A_periph(AT91_PIN_PB7, 1);
967 if (pins & ATMEL_SSC_TD)
968 at91_set_A_periph(AT91_PIN_PB8, 1);
969 if (pins & ATMEL_SSC_RD)
970 at91_set_A_periph(AT91_PIN_PB9, 1);
971 if (pins & ATMEL_SSC_RK)
972 at91_set_A_periph(AT91_PIN_PB10, 1);
973 if (pins & ATMEL_SSC_RF)
974 at91_set_A_periph(AT91_PIN_PB11, 1);
975 }
976
977 /*
978 * SSC controllers are accessed through library code, instead of any
979 * kind of all-singing/all-dancing driver. For example one could be
980 * used by a particular I2S audio codec's driver, while another one
981 * on the same system might be used by a custom data capture driver.
982 */
983 void __init at91_add_device_ssc(unsigned id, unsigned pins)
984 {
985 struct platform_device *pdev;
986
987 /*
988 * NOTE: caller is responsible for passing information matching
989 * "pins" to whatever will be using each particular controller.
990 */
991 switch (id) {
992 case AT91SAM9263_ID_SSC0:
993 pdev = &at91sam9263_ssc0_device;
994 configure_ssc0_pins(pins);
995 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
996 break;
997 case AT91SAM9263_ID_SSC1:
998 pdev = &at91sam9263_ssc1_device;
999 configure_ssc1_pins(pins);
1000 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
1001 break;
1002 default:
1003 return;
1004 }
1005
1006 platform_device_register(pdev);
1007 }
1008
1009 #else
1010 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1011 #endif
1012
1013
1014 /* --------------------------------------------------------------------
1015 * UART
1016 * -------------------------------------------------------------------- */
1017
1018 #if defined(CONFIG_SERIAL_ATMEL)
1019
1020 static struct resource dbgu_resources[] = {
1021 [0] = {
1022 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1023 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1024 .flags = IORESOURCE_MEM,
1025 },
1026 [1] = {
1027 .start = AT91_ID_SYS,
1028 .end = AT91_ID_SYS,
1029 .flags = IORESOURCE_IRQ,
1030 },
1031 };
1032
1033 static struct atmel_uart_data dbgu_data = {
1034 .use_dma_tx = 0,
1035 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1036 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1037 };
1038
1039 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1040
1041 static struct platform_device at91sam9263_dbgu_device = {
1042 .name = "atmel_usart",
1043 .id = 0,
1044 .dev = {
1045 .dma_mask = &dbgu_dmamask,
1046 .coherent_dma_mask = DMA_BIT_MASK(32),
1047 .platform_data = &dbgu_data,
1048 },
1049 .resource = dbgu_resources,
1050 .num_resources = ARRAY_SIZE(dbgu_resources),
1051 };
1052
1053 static inline void configure_dbgu_pins(void)
1054 {
1055 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1056 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1057 }
1058
1059 static struct resource uart0_resources[] = {
1060 [0] = {
1061 .start = AT91SAM9263_BASE_US0,
1062 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1063 .flags = IORESOURCE_MEM,
1064 },
1065 [1] = {
1066 .start = AT91SAM9263_ID_US0,
1067 .end = AT91SAM9263_ID_US0,
1068 .flags = IORESOURCE_IRQ,
1069 },
1070 };
1071
1072 static struct atmel_uart_data uart0_data = {
1073 .use_dma_tx = 1,
1074 .use_dma_rx = 1,
1075 };
1076
1077 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1078
1079 static struct platform_device at91sam9263_uart0_device = {
1080 .name = "atmel_usart",
1081 .id = 1,
1082 .dev = {
1083 .dma_mask = &uart0_dmamask,
1084 .coherent_dma_mask = DMA_BIT_MASK(32),
1085 .platform_data = &uart0_data,
1086 },
1087 .resource = uart0_resources,
1088 .num_resources = ARRAY_SIZE(uart0_resources),
1089 };
1090
1091 static inline void configure_usart0_pins(unsigned pins)
1092 {
1093 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1094 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
1095
1096 if (pins & ATMEL_UART_RTS)
1097 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1098 if (pins & ATMEL_UART_CTS)
1099 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
1100 }
1101
1102 static struct resource uart1_resources[] = {
1103 [0] = {
1104 .start = AT91SAM9263_BASE_US1,
1105 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1106 .flags = IORESOURCE_MEM,
1107 },
1108 [1] = {
1109 .start = AT91SAM9263_ID_US1,
1110 .end = AT91SAM9263_ID_US1,
1111 .flags = IORESOURCE_IRQ,
1112 },
1113 };
1114
1115 static struct atmel_uart_data uart1_data = {
1116 .use_dma_tx = 1,
1117 .use_dma_rx = 1,
1118 };
1119
1120 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1121
1122 static struct platform_device at91sam9263_uart1_device = {
1123 .name = "atmel_usart",
1124 .id = 2,
1125 .dev = {
1126 .dma_mask = &uart1_dmamask,
1127 .coherent_dma_mask = DMA_BIT_MASK(32),
1128 .platform_data = &uart1_data,
1129 },
1130 .resource = uart1_resources,
1131 .num_resources = ARRAY_SIZE(uart1_resources),
1132 };
1133
1134 static inline void configure_usart1_pins(unsigned pins)
1135 {
1136 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1137 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1138
1139 if (pins & ATMEL_UART_RTS)
1140 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1141 if (pins & ATMEL_UART_CTS)
1142 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1143 }
1144
1145 static struct resource uart2_resources[] = {
1146 [0] = {
1147 .start = AT91SAM9263_BASE_US2,
1148 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1149 .flags = IORESOURCE_MEM,
1150 },
1151 [1] = {
1152 .start = AT91SAM9263_ID_US2,
1153 .end = AT91SAM9263_ID_US2,
1154 .flags = IORESOURCE_IRQ,
1155 },
1156 };
1157
1158 static struct atmel_uart_data uart2_data = {
1159 .use_dma_tx = 1,
1160 .use_dma_rx = 1,
1161 };
1162
1163 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1164
1165 static struct platform_device at91sam9263_uart2_device = {
1166 .name = "atmel_usart",
1167 .id = 3,
1168 .dev = {
1169 .dma_mask = &uart2_dmamask,
1170 .coherent_dma_mask = DMA_BIT_MASK(32),
1171 .platform_data = &uart2_data,
1172 },
1173 .resource = uart2_resources,
1174 .num_resources = ARRAY_SIZE(uart2_resources),
1175 };
1176
1177 static inline void configure_usart2_pins(unsigned pins)
1178 {
1179 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1180 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1181
1182 if (pins & ATMEL_UART_RTS)
1183 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1184 if (pins & ATMEL_UART_CTS)
1185 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1186 }
1187
1188 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1189 struct platform_device *atmel_default_console_device; /* the serial console device */
1190
1191 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1192 {
1193 struct platform_device *pdev;
1194
1195 switch (id) {
1196 case 0: /* DBGU */
1197 pdev = &at91sam9263_dbgu_device;
1198 configure_dbgu_pins();
1199 at91_clock_associate("mck", &pdev->dev, "usart");
1200 break;
1201 case AT91SAM9263_ID_US0:
1202 pdev = &at91sam9263_uart0_device;
1203 configure_usart0_pins(pins);
1204 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1205 break;
1206 case AT91SAM9263_ID_US1:
1207 pdev = &at91sam9263_uart1_device;
1208 configure_usart1_pins(pins);
1209 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1210 break;
1211 case AT91SAM9263_ID_US2:
1212 pdev = &at91sam9263_uart2_device;
1213 configure_usart2_pins(pins);
1214 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1215 break;
1216 default:
1217 return;
1218 }
1219 pdev->id = portnr; /* update to mapped ID */
1220
1221 if (portnr < ATMEL_MAX_UART)
1222 at91_uarts[portnr] = pdev;
1223 }
1224
1225 void __init at91_set_serial_console(unsigned portnr)
1226 {
1227 if (portnr < ATMEL_MAX_UART)
1228 atmel_default_console_device = at91_uarts[portnr];
1229 }
1230
1231 void __init at91_add_device_serial(void)
1232 {
1233 int i;
1234
1235 for (i = 0; i < ATMEL_MAX_UART; i++) {
1236 if (at91_uarts[i])
1237 platform_device_register(at91_uarts[i]);
1238 }
1239
1240 if (!atmel_default_console_device)
1241 printk(KERN_INFO "AT91: No default serial console defined.\n");
1242 }
1243 #else
1244 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1245 void __init at91_set_serial_console(unsigned portnr) {}
1246 void __init at91_add_device_serial(void) {}
1247 #endif
1248
1249
1250 /* -------------------------------------------------------------------- */
1251 /*
1252 * These devices are always present and don't need any board-specific
1253 * setup.
1254 */
1255 static int __init at91_add_standard_devices(void)
1256 {
1257 at91_add_device_rtt();
1258 at91_add_device_watchdog();
1259 at91_add_device_tc();
1260 return 0;
1261 }
1262
1263 arch_initcall(at91_add_standard_devices);
SocketAccessConTroL development