arch/ppc/kernel/pci.c

   1 /*
   2  * Common prep/chrp pci routines. -- Cort
   3  */
   4
   5 #include <linux/config.h>
   6 #include <linux/kernel.h>
   7 #include <linux/pci.h>
   8 #include <linux/delay.h>
   9 #include <linux/string.h>
  10 #include <linux/init.h>
  11 #include <linux/capability.h>
  12 #include <linux/sched.h>
  13 #include <linux/errno.h>
  14 #include <linux/bootmem.h>
  15
  16 #include <asm/processor.h>
  17 #include <asm/io.h>
  18 #include <asm/prom.h>
  19 #include <asm/sections.h>
  20 #include <asm/pci-bridge.h>
  21 #include <asm/byteorder.h>
  22 #include <asm/irq.h>
  23 #include <asm/uaccess.h>
  24 #include <asm/machdep.h>
  25
  26 #undef DEBUG
  27
  28 #ifdef DEBUG
  29 #define DBG(x...) printk(x)
  30 #else
  31 #define DBG(x...)
  32 #endif
  33
  34 unsigned long isa_io_base     = 0;
  35 unsigned long isa_mem_base    = 0;
  36 unsigned long pci_dram_offset = 0;
  37 int pcibios_assign_bus_offset = 1;
  38
  39 void pcibios_make_OF_bus_map(void);
  40
  41 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
  42 static int probe_resource(struct pci_bus *parent, struct resource *pr,
  43                           struct resource *res, struct resource **conflict);
  44 static void update_bridge_base(struct pci_bus *bus, int i);
  45 static void pcibios_fixup_resources(struct pci_dev* dev);
  46 static void fixup_broken_pcnet32(struct pci_dev* dev);
  47 static int reparent_resources(struct resource *parent, struct resource *res);
  48 static void fixup_cpc710_pci64(struct pci_dev* dev);
  49
  50 /* By default, we don't re-assign bus numbers.
  51  */
  52 int pci_assign_all_buses;
  53
  54 struct pci_controller* hose_head;
  55 struct pci_controller** hose_tail = &hose_head;
  56
  57 static int pci_bus_count;
  58
  59 static void
  60 fixup_broken_pcnet32(struct pci_dev* dev)
  61 {
  62         if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
  63                 dev->vendor = PCI_VENDOR_ID_AMD;
  64                 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
  65         }
  66 }
  67 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID,                     fixup_broken_pcnet32);
  68
  69 static void
  70 fixup_cpc710_pci64(struct pci_dev* dev)
  71 {
  72         /* Hide the PCI64 BARs from the kernel as their content doesn't
  73          * fit well in the resource management
  74          */
  75         dev->resource[0].start = dev->resource[0].end = 0;
  76         dev->resource[0].flags = 0;
  77         dev->resource[1].start = dev->resource[1].end = 0;
  78         dev->resource[1].flags = 0;
  79 }
  80 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,     PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
  81
  82 static void
  83 pcibios_fixup_resources(struct pci_dev *dev)
  84 {
  85         struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
  86         int i;
  87         unsigned long offset;
  88
  89         if (!hose) {
  90                 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
  91                 return;
  92         }
  93         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  94                 struct resource *res = dev->resource + i;
  95                 if (!res->flags)
  96                         continue;
  97                 if (res->end == 0xffffffff) {
  98                         DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n",
  99                             pci_name(dev), i, res->start, res->end);
 100                         res->end -= res->start;
 101                         res->start = 0;
 102                         res->flags |= IORESOURCE_UNSET;
 103                         continue;
 104                 }
 105                 offset = 0;
 106                 if (res->flags & IORESOURCE_MEM) {
 107                         offset = hose->pci_mem_offset;
 108                 } else if (res->flags & IORESOURCE_IO) {
 109                         offset = (unsigned long) hose->io_base_virt
 110                                 - isa_io_base;
 111                 }
 112                 if (offset != 0) {
 113                         res->start += offset;
 114                         res->end += offset;
 115 #ifdef DEBUG
 116                         printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
 117                                i, res->flags, pci_name(dev),
 118                                res->start - offset, res->start);
 119 #endif
 120                 }
 121         }
 122
 123         /* Call machine specific resource fixup */
 124         if (ppc_md.pcibios_fixup_resources)
 125                 ppc_md.pcibios_fixup_resources(dev);
 126 }
 127 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID,            PCI_ANY_ID,                     pcibios_fixup_resources);
 128
 129 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 130                         struct resource *res)
 131 {
 132         unsigned long offset = 0;
 133         struct pci_controller *hose = dev->sysdata;
 134
 135         if (hose && res->flags & IORESOURCE_IO)
 136                 offset = (unsigned long)hose->io_base_virt - isa_io_base;
 137         else if (hose && res->flags & IORESOURCE_MEM)
 138                 offset = hose->pci_mem_offset;
 139         region->start = res->start - offset;
 140         region->end = res->end - offset;
 141 }
 142 EXPORT_SYMBOL(pcibios_resource_to_bus);
 143
 144 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 145                              struct pci_bus_region *region)
 146 {
 147         unsigned long offset = 0;
 148         struct pci_controller *hose = dev->sysdata;
 149
 150         if (hose && res->flags & IORESOURCE_IO)
 151                 offset = (unsigned long)hose->io_base_virt - isa_io_base;
 152         else if (hose && res->flags & IORESOURCE_MEM)
 153                 offset = hose->pci_mem_offset;
 154         res->start = region->start + offset;
 155         res->end = region->end + offset;
 156 }
 157 EXPORT_SYMBOL(pcibios_bus_to_resource);
 158
 159 /*
 160  * We need to avoid collisions with `mirrored' VGA ports
 161  * and other strange ISA hardware, so we always want the
 162  * addresses to be allocated in the 0x000-0x0ff region
 163  * modulo 0x400.
 164  *
 165  * Why? Because some silly external IO cards only decode
 166  * the low 10 bits of the IO address. The 0x00-0xff region
 167  * is reserved for motherboard devices that decode all 16
 168  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 169  * but we want to try to avoid allocating at 0x2900-0x2bff
 170  * which might have be mirrored at 0x0100-0x03ff..
 171  */
 172 void pcibios_align_resource(void *data, struct resource *res, unsigned long size,
 173                        unsigned long align)
 174 {
 175         struct pci_dev *dev = data;
 176
 177         if (res->flags & IORESOURCE_IO) {
 178                 unsigned long start = res->start;
 179
 180                 if (size > 0x100) {
 181                         printk(KERN_ERR "PCI: I/O Region %s/%d too large"
 182                                " (%ld bytes)\n", pci_name(dev),
 183                                dev->resource - res, size);
 184                 }
 185
 186                 if (start & 0x300) {
 187                         start = (start + 0x3ff) & ~0x3ff;
 188                         res->start = start;
 189                 }
 190         }
 191 }
 192 EXPORT_SYMBOL(pcibios_align_resource);
 193
 194 /*
 195  *  Handle resources of PCI devices.  If the world were perfect, we could
 196  *  just allocate all the resource regions and do nothing more.  It isn't.
 197  *  On the other hand, we cannot just re-allocate all devices, as it would
 198  *  require us to know lots of host bridge internals.  So we attempt to
 199  *  keep as much of the original configuration as possible, but tweak it
 200  *  when it's found to be wrong.
 201  *
 202  *  Known BIOS problems we have to work around:
 203  *      - I/O or memory regions not configured
 204  *      - regions configured, but not enabled in the command register
 205  *      - bogus I/O addresses above 64K used
 206  *      - expansion ROMs left enabled (this may sound harmless, but given
 207  *        the fact the PCI specs explicitly allow address decoders to be
 208  *        shared between expansion ROMs and other resource regions, it's
 209  *        at least dangerous)
 210  *
 211  *  Our solution:
 212  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
 213  *          This gives us fixed barriers on where we can allocate.
 214  *      (2) Allocate resources for all enabled devices.  If there is
 215  *          a collision, just mark the resource as unallocated. Also
 216  *          disable expansion ROMs during this step.
 217  *      (3) Try to allocate resources for disabled devices.  If the
 218  *          resources were assigned correctly, everything goes well,
 219  *          if they weren't, they won't disturb allocation of other
 220  *          resources.
 221  *      (4) Assign new addresses to resources which were either
 222  *          not configured at all or misconfigured.  If explicitly
 223  *          requested by the user, configure expansion ROM address
 224  *          as well.
 225  */
 226
 227 static void __init
 228 pcibios_allocate_bus_resources(struct list_head *bus_list)
 229 {
 230         struct pci_bus *bus;
 231         int i;
 232         struct resource *res, *pr;
 233
 234         /* Depth-First Search on bus tree */
 235         list_for_each_entry(bus, bus_list, node) {
 236                 for (i = 0; i < 4; ++i) {
 237                         if ((res = bus->resource[i]) == NULL || !res->flags
 238                             || res->start > res->end)
 239                                 continue;
 240                         if (bus->parent == NULL)
 241                                 pr = (res->flags & IORESOURCE_IO)?
 242                                         &ioport_resource: &iomem_resource;
 243                         else {
 244                                 pr = pci_find_parent_resource(bus->self, res);
 245                                 if (pr == res) {
 246                                         /* this happens when the generic PCI
 247                                          * code (wrongly) decides that this
 248                                          * bridge is transparent  -- paulus
 249                                          */
 250                                         continue;
 251                                 }
 252                         }
 253
 254                         DBG("PCI: bridge rsrc %lx..%lx (%lx), parent %p\n",
 255                             res->start, res->end, res->flags, pr);
 256                         if (pr) {
 257                                 if (request_resource(pr, res) == 0)
 258                                         continue;
 259                                 /*
 260                                  * Must be a conflict with an existing entry.
 261                                  * Move that entry (or entries) under the
 262                                  * bridge resource and try again.
 263                                  */
 264                                 if (reparent_resources(pr, res) == 0)
 265                                         continue;
 266                         }
 267                         printk(KERN_ERR "PCI: Cannot allocate resource region "
 268                                "%d of PCI bridge %d\n", i, bus->number);
 269                         if (pci_relocate_bridge_resource(bus, i))
 270                                 bus->resource[i] = NULL;
 271                 }
 272                 pcibios_allocate_bus_resources(&bus->children);
 273         }
 274 }
 275
 276 /*
 277  * Reparent resource children of pr that conflict with res
 278  * under res, and make res replace those children.
 279  */
 280 static int __init
 281 reparent_resources(struct resource *parent, struct resource *res)
 282 {
 283         struct resource *p, **pp;
 284         struct resource **firstpp = NULL;
 285
 286         for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
 287                 if (p->end < res->start)
 288                         continue;
 289                 if (res->end < p->start)
 290                         break;
 291                 if (p->start < res->start || p->end > res->end)
 292                         return -1;      /* not completely contained */
 293                 if (firstpp == NULL)
 294                         firstpp = pp;
 295         }
 296         if (firstpp == NULL)
 297                 return -1;      /* didn't find any conflicting entries? */
 298         res->parent = parent;
 299         res->child = *firstpp;
 300         res->sibling = *pp;
 301         *firstpp = res;
 302         *pp = NULL;
 303         for (p = res->child; p != NULL; p = p->sibling) {
 304                 p->parent = res;
 305                 DBG(KERN_INFO "PCI: reparented %s [%lx..%lx] under %s\n",
 306                     p->name, p->start, p->end, res->name);
 307         }
 308         return 0;
 309 }
 310
 311 /*
 312  * A bridge has been allocated a range which is outside the range
 313  * of its parent bridge, so it needs to be moved.
 314  */
 315 static int __init
 316 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
 317 {
 318         struct resource *res, *pr, *conflict;
 319         unsigned long try, size;
 320         int j;
 321         struct pci_bus *parent = bus->parent;
 322
 323         if (parent == NULL) {
 324                 /* shouldn't ever happen */
 325                 printk(KERN_ERR "PCI: can't move host bridge resource\n");
 326                 return -1;
 327         }
 328         res = bus->resource[i];
 329         if (res == NULL)
 330                 return -1;
 331         pr = NULL;
 332         for (j = 0; j < 4; j++) {
 333                 struct resource *r = parent->resource[j];
 334                 if (!r)
 335                         continue;
 336                 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
 337                         continue;
 338                 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
 339                         pr = r;
 340                         break;
 341                 }
 342                 if (res->flags & IORESOURCE_PREFETCH)
 343                         pr = r;
 344         }
 345         if (pr == NULL)
 346                 return -1;
 347         size = res->end - res->start;
 348         if (pr->start > pr->end || size > pr->end - pr->start)
 349                 return -1;
 350         try = pr->end;
 351         for (;;) {
 352                 res->start = try - size;
 353                 res->end = try;
 354                 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
 355                         break;
 356                 if (conflict->start <= pr->start + size)
 357                         return -1;
 358                 try = conflict->start - 1;
 359         }
 360         if (request_resource(pr, res)) {
 361                 DBG(KERN_ERR "PCI: huh? couldn't move to %lx..%lx\n",
 362                     res->start, res->end);
 363                 return -1;              /* "can't happen" */
 364         }
 365         update_bridge_base(bus, i);
 366         printk(KERN_INFO "PCI: bridge %d resource %d moved to %lx..%lx\n",
 367                bus->number, i, res->start, res->end);
 368         return 0;
 369 }
 370
 371 static int __init
 372 probe_resource(struct pci_bus *parent, struct resource *pr,
 373                struct resource *res, struct resource **conflict)
 374 {
 375         struct pci_bus *bus;
 376         struct pci_dev *dev;
 377         struct resource *r;
 378         int i;
 379
 380         for (r = pr->child; r != NULL; r = r->sibling) {
 381                 if (r->end >= res->start && res->end >= r->start) {
 382                         *conflict = r;
 383                         return 1;
 384                 }
 385         }
 386         list_for_each_entry(bus, &parent->children, node) {
 387                 for (i = 0; i < 4; ++i) {
 388                         if ((r = bus->resource[i]) == NULL)
 389                                 continue;
 390                         if (!r->flags || r->start > r->end || r == res)
 391                                 continue;
 392                         if (pci_find_parent_resource(bus->self, r) != pr)
 393                                 continue;
 394                         if (r->end >= res->start && res->end >= r->start) {
 395                                 *conflict = r;
 396                                 return 1;
 397                         }
 398                 }
 399         }
 400         list_for_each_entry(dev, &parent->devices, bus_list) {
 401                 for (i = 0; i < 6; ++i) {
 402                         r = &dev->resource[i];
 403                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
 404                                 continue;
 405                         if (pci_find_parent_resource(dev, r) != pr)
 406                                 continue;
 407                         if (r->end >= res->start && res->end >= r->start) {
 408                                 *conflict = r;
 409                                 return 1;
 410                         }
 411                 }
 412         }
 413         return 0;
 414 }
 415
 416 static void __init
 417 update_bridge_base(struct pci_bus *bus, int i)
 418 {
 419         struct resource *res = bus->resource[i];
 420         u8 io_base_lo, io_limit_lo;
 421         u16 mem_base, mem_limit;
 422         u16 cmd;
 423         unsigned long start, end, off;
 424         struct pci_dev *dev = bus->self;
 425         struct pci_controller *hose = dev->sysdata;
 426
 427         if (!hose) {
 428                 printk("update_bridge_base: no hose?\n");
 429                 return;
 430         }
 431         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 432         pci_write_config_word(dev, PCI_COMMAND,
 433                               cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
 434         if (res->flags & IORESOURCE_IO) {
 435                 off = (unsigned long) hose->io_base_virt - isa_io_base;
 436                 start = res->start - off;
 437                 end = res->end - off;
 438                 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
 439                 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
 440                 if (end > 0xffff) {
 441                         pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
 442                                               start >> 16);
 443                         pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
 444                                               end >> 16);
 445                         io_base_lo |= PCI_IO_RANGE_TYPE_32;
 446                 } else
 447                         io_base_lo |= PCI_IO_RANGE_TYPE_16;
 448                 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
 449                 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
 450
 451         } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
 452                    == IORESOURCE_MEM) {
 453                 off = hose->pci_mem_offset;
 454                 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
 455                 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
 456                 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
 457                 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
 458
 459         } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
 460                    == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
 461                 off = hose->pci_mem_offset;
 462                 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
 463                 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
 464                 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
 465                 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
 466
 467         } else {
 468                 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
 469                     pci_name(dev), i, res->flags);
 470         }
 471         pci_write_config_word(dev, PCI_COMMAND, cmd);
 472 }
 473
 474 static inline void alloc_resource(struct pci_dev *dev, int idx)
 475 {
 476         struct resource *pr, *r = &dev->resource[idx];
 477
 478         DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",
 479             pci_name(dev), idx, r->start, r->end, r->flags);
 480         pr = pci_find_parent_resource(dev, r);
 481         if (!pr || request_resource(pr, r) < 0) {
 482                 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
 483                        " of device %s\n", idx, pci_name(dev));
 484                 if (pr)
 485                         DBG("PCI:  parent is %p: %08lx-%08lx (f=%lx)\n",
 486                             pr, pr->start, pr->end, pr->flags);
 487                 /* We'll assign a new address later */
 488                 r->flags |= IORESOURCE_UNSET;
 489                 r->end -= r->start;
 490                 r->start = 0;
 491         }
 492 }
 493
 494 static void __init
 495 pcibios_allocate_resources(int pass)
 496 {
 497         struct pci_dev *dev = NULL;
 498         int idx, disabled;
 499         u16 command;
 500         struct resource *r;
 501
 502         for_each_pci_dev(dev) {
 503                 pci_read_config_word(dev, PCI_COMMAND, &command);
 504                 for (idx = 0; idx < 6; idx++) {
 505                         r = &dev->resource[idx];
 506                         if (r->parent)          /* Already allocated */
 507                                 continue;
 508                         if (!r->flags || (r->flags & IORESOURCE_UNSET))
 509                                 continue;       /* Not assigned at all */
 510                         if (r->flags & IORESOURCE_IO)
 511                                 disabled = !(command & PCI_COMMAND_IO);
 512                         else
 513                                 disabled = !(command & PCI_COMMAND_MEMORY);
 514                         if (pass == disabled)
 515                                 alloc_resource(dev, idx);
 516                 }
 517                 if (pass)
 518                         continue;
 519                 r = &dev->resource[PCI_ROM_RESOURCE];
 520                 if (r->flags & IORESOURCE_ROM_ENABLE) {
 521                         /* Turn the ROM off, leave the resource region, but keep it unregistered. */
 522                         u32 reg;
 523                         DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
 524                         r->flags &= ~IORESOURCE_ROM_ENABLE;
 525                         pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 526                         pci_write_config_dword(dev, dev->rom_base_reg,
 527                                                reg & ~PCI_ROM_ADDRESS_ENABLE);
 528                 }
 529         }
 530 }
 531
 532 static void __init
 533 pcibios_assign_resources(void)
 534 {
 535         struct pci_dev *dev = NULL;
 536         int idx;
 537         struct resource *r;
 538
 539         for_each_pci_dev(dev) {
 540                 int class = dev->class >> 8;
 541
 542                 /* Don't touch classless devices and host bridges */
 543                 if (!class || class == PCI_CLASS_BRIDGE_HOST)
 544                         continue;
 545
 546                 for (idx = 0; idx < 6; idx++) {
 547                         r = &dev->resource[idx];
 548
 549                         /*
 550                          * We shall assign a new address to this resource,
 551                          * either because the BIOS (sic) forgot to do so
 552                          * or because we have decided the old address was
 553                          * unusable for some reason.
 554                          */
 555                         if ((r->flags & IORESOURCE_UNSET) && r->end &&
 556                             (!ppc_md.pcibios_enable_device_hook ||
 557                              !ppc_md.pcibios_enable_device_hook(dev, 1))) {
 558                                 r->flags &= ~IORESOURCE_UNSET;
 559                                 pci_assign_resource(dev, idx);
 560                         }
 561                 }
 562
 563 #if 0 /* don't assign ROMs */
 564                 r = &dev->resource[PCI_ROM_RESOURCE];
 565                 r->end -= r->start;
 566                 r->start = 0;
 567                 if (r->end)
 568                         pci_assign_resource(dev, PCI_ROM_RESOURCE);
 569 #endif
 570         }
 571 }
 572
 573
 574 int
 575 pcibios_enable_resources(struct pci_dev *dev, int mask)
 576 {
 577         u16 cmd, old_cmd;
 578         int idx;
 579         struct resource *r;
 580
 581         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 582         old_cmd = cmd;
 583         for (idx=0; idx<6; idx++) {
 584                 /* Only set up the requested stuff */
 585                 if (!(mask & (1<<idx)))
 586                         continue;
 587
 588                 r = &dev->resource[idx];
 589                 if (r->flags & IORESOURCE_UNSET) {
 590                         printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
 591                         return -EINVAL;
 592                 }
 593                 if (r->flags & IORESOURCE_IO)
 594                         cmd |= PCI_COMMAND_IO;
 595                 if (r->flags & IORESOURCE_MEM)
 596                         cmd |= PCI_COMMAND_MEMORY;
 597         }
 598         if (dev->resource[PCI_ROM_RESOURCE].start)
 599                 cmd |= PCI_COMMAND_MEMORY;
 600         if (cmd != old_cmd) {
 601                 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
 602                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 603         }
 604         return 0;
 605 }
 606
 607 static int next_controller_index;
 608
 609 struct pci_controller * __init
 610 pcibios_alloc_controller(void)
 611 {
 612         struct pci_controller *hose;
 613
 614         hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
 615         memset(hose, 0, sizeof(struct pci_controller));
 616
 617         *hose_tail = hose;
 618         hose_tail = &hose->next;
 619
 620         hose->index = next_controller_index++;
 621
 622         return hose;
 623 }
 624
 625 void pcibios_make_OF_bus_map(void)
 626 {
 627 }
 628
 629 /* Add sysfs properties */
 630 void pcibios_add_platform_entries(struct pci_dev *pdev)
 631 {
 632 }
 633
 634
 635 static int __init
 636 pcibios_init(void)
 637 {
 638         struct pci_controller *hose;
 639         struct pci_bus *bus;
 640         int next_busno;
 641
 642         printk(KERN_INFO "PCI: Probing PCI hardware\n");
 643
 644         /* Scan all of the recorded PCI controllers.  */
 645         for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
 646                 if (pci_assign_all_buses)
 647                         hose->first_busno = next_busno;
 648                 hose->last_busno = 0xff;
 649                 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
 650                 hose->last_busno = bus->subordinate;
 651                 if (pci_assign_all_buses || next_busno <= hose->last_busno)
 652                         next_busno = hose->last_busno + pcibios_assign_bus_offset;
 653         }
 654         pci_bus_count = next_busno;
 655
 656         /* OpenFirmware based machines need a map of OF bus
 657          * numbers vs. kernel bus numbers since we may have to
 658          * remap them.
 659          */
 660         if (pci_assign_all_buses && have_of)
 661                 pcibios_make_OF_bus_map();
 662
 663         /* Do machine dependent PCI interrupt routing */
 664         if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
 665                 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
 666
 667         /* Call machine dependent fixup */
 668         if (ppc_md.pcibios_fixup)
 669                 ppc_md.pcibios_fixup();
 670
 671         /* Allocate and assign resources */
 672         pcibios_allocate_bus_resources(&pci_root_buses);
 673         pcibios_allocate_resources(0);
 674         pcibios_allocate_resources(1);
 675         pcibios_assign_resources();
 676
 677         /* Call machine dependent post-init code */
 678         if (ppc_md.pcibios_after_init)
 679                 ppc_md.pcibios_after_init();
 680
 681         return 0;
 682 }
 683
 684 subsys_initcall(pcibios_init);
 685
 686 unsigned char __init
 687 common_swizzle(struct pci_dev *dev, unsigned char *pinp)
 688 {
 689         struct pci_controller *hose = dev->sysdata;
 690
 691         if (dev->bus->number != hose->first_busno) {
 692                 u8 pin = *pinp;
 693                 do {
 694                         pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
 695                         /* Move up the chain of bridges. */
 696                         dev = dev->bus->self;
 697                 } while (dev->bus->self);
 698                 *pinp = pin;
 699
 700                 /* The slot is the idsel of the last bridge. */
 701         }
 702         return PCI_SLOT(dev->devfn);
 703 }
 704
 705 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
 706                              unsigned long start, unsigned long size)
 707 {
 708         return start;
 709 }
 710
 711 void __init pcibios_fixup_bus(struct pci_bus *bus)
 712 {
 713         struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
 714         unsigned long io_offset;
 715         struct resource *res;
 716         int i;
 717
 718         io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
 719         if (bus->parent == NULL) {
 720                 /* This is a host bridge - fill in its resources */
 721                 hose->bus = bus;
 722
 723                 bus->resource[0] = res = &hose->io_resource;
 724                 if (!res->flags) {
 725                         if (io_offset)
 726                                 printk(KERN_ERR "I/O resource not set for host"
 727                                        " bridge %d\n", hose->index);
 728                         res->start = 0;
 729                         res->end = IO_SPACE_LIMIT;
 730                         res->flags = IORESOURCE_IO;
 731                 }
 732                 res->start += io_offset;
 733                 res->end += io_offset;
 734
 735                 for (i = 0; i < 3; ++i) {
 736                         res = &hose->mem_resources[i];
 737                         if (!res->flags) {
 738                                 if (i > 0)
 739                                         continue;
 740                                 printk(KERN_ERR "Memory resource not set for "
 741                                        "host bridge %d\n", hose->index);
 742                                 res->start = hose->pci_mem_offset;
 743                                 res->end = ~0U;
 744                                 res->flags = IORESOURCE_MEM;
 745                         }
 746                         bus->resource[i+1] = res;
 747                 }
 748         } else {
 749                 /* This is a subordinate bridge */
 750                 pci_read_bridge_bases(bus);
 751
 752                 for (i = 0; i < 4; ++i) {
 753                         if ((res = bus->resource[i]) == NULL)
 754                                 continue;
 755                         if (!res->flags)
 756                                 continue;
 757                         if (io_offset && (res->flags & IORESOURCE_IO)) {
 758                                 res->start += io_offset;
 759                                 res->end += io_offset;
 760                         } else if (hose->pci_mem_offset
 761                                    && (res->flags & IORESOURCE_MEM)) {
 762                                 res->start += hose->pci_mem_offset;
 763                                 res->end += hose->pci_mem_offset;
 764                         }
 765                 }
 766         }
 767
 768         if (ppc_md.pcibios_fixup_bus)
 769                 ppc_md.pcibios_fixup_bus(bus);
 770 }
 771
 772 char __init *pcibios_setup(char *str)
 773 {
 774         return str;
 775 }
 776
 777 /* the next one is stolen from the alpha port... */
 778 void __init
 779 pcibios_update_irq(struct pci_dev *dev, int irq)
 780 {
 781         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 782         /* XXX FIXME - update OF device tree node interrupt property */
 783 }
 784
 785 int pcibios_enable_device(struct pci_dev *dev, int mask)
 786 {
 787         u16 cmd, old_cmd;
 788         int idx;
 789         struct resource *r;
 790
 791         if (ppc_md.pcibios_enable_device_hook)
 792                 if (ppc_md.pcibios_enable_device_hook(dev, 0))
 793                         return -EINVAL;
 794
 795         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 796         old_cmd = cmd;
 797         for (idx=0; idx<6; idx++) {
 798                 r = &dev->resource[idx];
 799                 if (r->flags & IORESOURCE_UNSET) {
 800                         printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
 801                         return -EINVAL;
 802                 }
 803                 if (r->flags & IORESOURCE_IO)
 804                         cmd |= PCI_COMMAND_IO;
 805                 if (r->flags & IORESOURCE_MEM)
 806                         cmd |= PCI_COMMAND_MEMORY;
 807         }
 808         if (cmd != old_cmd) {
 809                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
 810                        pci_name(dev), old_cmd, cmd);
 811                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 812         }
 813         return 0;
 814 }
 815
 816 struct pci_controller*
 817 pci_bus_to_hose(int bus)
 818 {
 819         struct pci_controller* hose = hose_head;
 820
 821         for (; hose; hose = hose->next)
 822                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 823                         return hose;
 824         return NULL;
 825 }
 826
 827 void __iomem *
 828 pci_bus_io_base(unsigned int bus)
 829 {
 830         struct pci_controller *hose;
 831
 832         hose = pci_bus_to_hose(bus);
 833         if (!hose)
 834                 return NULL;
 835         return hose->io_base_virt;
 836 }
 837
 838 unsigned long
 839 pci_bus_io_base_phys(unsigned int bus)
 840 {
 841         struct pci_controller *hose;
 842
 843         hose = pci_bus_to_hose(bus);
 844         if (!hose)
 845                 return 0;
 846         return hose->io_base_phys;
 847 }
 848
 849 unsigned long
 850 pci_bus_mem_base_phys(unsigned int bus)
 851 {
 852         struct pci_controller *hose;
 853
 854         hose = pci_bus_to_hose(bus);
 855         if (!hose)
 856                 return 0;
 857         return hose->pci_mem_offset;
 858 }
 859
 860 unsigned long
 861 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
 862 {
 863         /* Hack alert again ! See comments in chrp_pci.c
 864          */
 865         struct pci_controller* hose =
 866                 (struct pci_controller *)pdev->sysdata;
 867         if (hose && res->flags & IORESOURCE_MEM)
 868                 return res->start - hose->pci_mem_offset;
 869         /* We may want to do something with IOs here... */
 870         return res->start;
 871 }
 872
 873
 874 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
 875                                                unsigned long *offset,
 876                                                enum pci_mmap_state mmap_state)
 877 {
 878         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
 879         unsigned long io_offset = 0;
 880         int i, res_bit;
 881
 882         if (hose == 0)
 883                 return NULL;            /* should never happen */
 884
 885         /* If memory, add on the PCI bridge address offset */
 886         if (mmap_state == pci_mmap_mem) {
 887                 *offset += hose->pci_mem_offset;
 888                 res_bit = IORESOURCE_MEM;
 889         } else {
 890                 io_offset = hose->io_base_virt - ___IO_BASE;
 891                 *offset += io_offset;
 892                 res_bit = IORESOURCE_IO;
 893         }
 894
 895         /*
 896          * Check that the offset requested corresponds to one of the
 897          * resources of the device.
 898          */
 899         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 900                 struct resource *rp = &dev->resource[i];
 901                 int flags = rp->flags;
 902
 903                 /* treat ROM as memory (should be already) */
 904                 if (i == PCI_ROM_RESOURCE)
 905                         flags |= IORESOURCE_MEM;
 906
 907                 /* Active and same type? */
 908                 if ((flags & res_bit) == 0)
 909                         continue;
 910
 911                 /* In the range of this resource? */
 912                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
 913                         continue;
 914
 915                 /* found it! construct the final physical address */
 916                 if (mmap_state == pci_mmap_io)
 917                         *offset += hose->io_base_phys - io_offset;
 918                 return rp;
 919         }
 920
 921         return NULL;
 922 }
 923
 924 /*
 925  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 926  * device mapping.
 927  */
 928 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
 929                                       pgprot_t protection,
 930                                       enum pci_mmap_state mmap_state,
 931                                       int write_combine)
 932 {
 933         unsigned long prot = pgprot_val(protection);
 934
 935         /* Write combine is always 0 on non-memory space mappings. On
 936          * memory space, if the user didn't pass 1, we check for a
 937          * "prefetchable" resource. This is a bit hackish, but we use
 938          * this to workaround the inability of /sysfs to provide a write
 939          * combine bit
 940          */
 941         if (mmap_state != pci_mmap_mem)
 942                 write_combine = 0;
 943         else if (write_combine == 0) {
 944                 if (rp->flags & IORESOURCE_PREFETCH)
 945                         write_combine = 1;
 946         }
 947
 948         /* XXX would be nice to have a way to ask for write-through */
 949         prot |= _PAGE_NO_CACHE;
 950         if (write_combine)
 951                 prot &= ~_PAGE_GUARDED;
 952         else
 953                 prot |= _PAGE_GUARDED;
 954
 955         printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
 956                prot);
 957
 958         return __pgprot(prot);
 959 }
 960
 961 /*
 962  * This one is used by /dev/mem and fbdev who have no clue about the
 963  * PCI device, it tries to find the PCI device first and calls the
 964  * above routine
 965  */
 966 pgprot_t pci_phys_mem_access_prot(struct file *file,
 967                                   unsigned long pfn,
 968                                   unsigned long size,
 969                                   pgprot_t protection)
 970 {
 971         struct pci_dev *pdev = NULL;
 972         struct resource *found = NULL;
 973         unsigned long prot = pgprot_val(protection);
 974         unsigned long offset = pfn << PAGE_SHIFT;
 975         int i;
 976
 977         if (page_is_ram(pfn))
 978                 return prot;
 979
 980         prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
 981
 982         for_each_pci_dev(pdev) {
 983                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 984                         struct resource *rp = &pdev->resource[i];
 985                         int flags = rp->flags;
 986
 987                         /* Active and same type? */
 988                         if ((flags & IORESOURCE_MEM) == 0)
 989                                 continue;
 990                         /* In the range of this resource? */
 991                         if (offset < (rp->start & PAGE_MASK) ||
 992                             offset > rp->end)
 993                                 continue;
 994                         found = rp;
 995                         break;
 996                 }
 997                 if (found)
 998                         break;
 999         }
1000         if (found) {
1001                 if (found->flags & IORESOURCE_PREFETCH)
1002                         prot &= ~_PAGE_GUARDED;
1003                 pci_dev_put(pdev);
1004         }
1005
1006         DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
1007
1008         return __pgprot(prot);
1009 }
1010
1011
1012 /*
1013  * Perform the actual remap of the pages for a PCI device mapping, as
1014  * appropriate for this architecture.  The region in the process to map
1015  * is described by vm_start and vm_end members of VMA, the base physical
1016  * address is found in vm_pgoff.
1017  * The pci device structure is provided so that architectures may make mapping
1018  * decisions on a per-device or per-bus basis.
1019  *
1020  * Returns a negative error code on failure, zero on success.
1021  */
1022 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1023                         enum pci_mmap_state mmap_state,
1024                         int write_combine)
1025 {
1026         unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1027         struct resource *rp;
1028         int ret;
1029
1030         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
1031         if (rp == NULL)
1032                 return -EINVAL;
1033
1034         vma->vm_pgoff = offset >> PAGE_SHIFT;
1035         vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
1036         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
1037                                                   vma->vm_page_prot,
1038                                                   mmap_state, write_combine);
1039
1040         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1041                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
1042
1043         return ret;
1044 }
1045
1046 /* Obsolete functions. Should be removed once the symbios driver
1047  * is fixed
1048  */
1049 unsigned long
1050 phys_to_bus(unsigned long pa)
1051 {
1052         struct pci_controller *hose;
1053         int i;
1054
1055         for (hose = hose_head; hose; hose = hose->next) {
1056                 for (i = 0; i < 3; ++i) {
1057                         if (pa >= hose->mem_resources[i].start
1058                             && pa <= hose->mem_resources[i].end) {
1059                                 /*
1060                                  * XXX the hose->pci_mem_offset really
1061                                  * only applies to mem_resources[0].
1062                                  * We need a way to store an offset for
1063                                  * the others.  -- paulus
1064                                  */
1065                                 if (i == 0)
1066                                         pa -= hose->pci_mem_offset;
1067                                 return pa;
1068                         }
1069                 }
1070         }
1071         /* hmmm, didn't find it */
1072         return 0;
1073 }
1074
1075 unsigned long
1076 pci_phys_to_bus(unsigned long pa, int busnr)
1077 {
1078         struct pci_controller* hose = pci_bus_to_hose(busnr);
1079         if (!hose)
1080                 return pa;
1081         return pa - hose->pci_mem_offset;
1082 }
1083
1084 unsigned long
1085 pci_bus_to_phys(unsigned int ba, int busnr)
1086 {
1087         struct pci_controller* hose = pci_bus_to_hose(busnr);
1088         if (!hose)
1089                 return ba;
1090         return ba + hose->pci_mem_offset;
1091 }
1092
1093 /* Provide information on locations of various I/O regions in physical
1094  * memory.  Do this on a per-card basis so that we choose the right
1095  * root bridge.
1096  * Note that the returned IO or memory base is a physical address
1097  */
1098
1099 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1100 {
1101         struct pci_controller* hose;
1102         long result = -EOPNOTSUPP;
1103
1104         hose = pci_bus_to_hose(bus);
1105         if (!hose)
1106                 return -ENODEV;
1107
1108         switch (which) {
1109         case IOBASE_BRIDGE_NUMBER:
1110                 return (long)hose->first_busno;
1111         case IOBASE_MEMORY:
1112                 return (long)hose->pci_mem_offset;
1113         case IOBASE_IO:
1114                 return (long)hose->io_base_phys;
1115         case IOBASE_ISA_IO:
1116                 return (long)isa_io_base;
1117         case IOBASE_ISA_MEM:
1118                 return (long)isa_mem_base;
1119         }
1120
1121         return result;
1122 }
1123
1124 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1125                           const struct resource *rsrc,
1126                           u64 *start, u64 *end)
1127 {
1128         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1129         unsigned long offset = 0;
1130
1131         if (hose == NULL)
1132                 return;
1133
1134         if (rsrc->flags & IORESOURCE_IO)
1135                 offset = ___IO_BASE - hose->io_base_virt + hose->io_base_phys;
1136
1137         *start = rsrc->start + offset;
1138         *end = rsrc->end + offset;
1139 }
1140
1141 void __init
1142 pci_init_resource(struct resource *res, unsigned long start, unsigned long end,
1143                   int flags, char *name)
1144 {
1145         res->start = start;
1146         res->end = end;
1147         res->flags = flags;
1148         res->name = name;
1149         res->parent = NULL;
1150         res->sibling = NULL;
1151         res->child = NULL;
1152 }
1153
1154 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
1155 {
1156         unsigned long start = pci_resource_start(dev, bar);
1157         unsigned long len = pci_resource_len(dev, bar);
1158         unsigned long flags = pci_resource_flags(dev, bar);
1159
1160         if (!len)
1161                 return NULL;
1162         if (max && len > max)
1163                 len = max;
1164         if (flags & IORESOURCE_IO)
1165                 return ioport_map(start, len);
1166         if (flags & IORESOURCE_MEM)
1167                 /* Not checking IORESOURCE_CACHEABLE because PPC does
1168                  * not currently distinguish between ioremap and
1169                  * ioremap_nocache.
1170                  */
1171                 return ioremap(start, len);
1172         /* What? */
1173         return NULL;
1174 }
1175
1176 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1177 {
1178         /* Nothing to do */
1179 }
1180 EXPORT_SYMBOL(pci_iomap);
1181 EXPORT_SYMBOL(pci_iounmap);
1182
1183 unsigned long pci_address_to_pio(phys_addr_t address)
1184 {
1185         struct pci_controller* hose = hose_head;
1186
1187         for (; hose; hose = hose->next) {
1188                 unsigned int size = hose->io_resource.end -
1189                         hose->io_resource.start + 1;
1190                 if (address >= hose->io_base_phys &&
1191                     address < (hose->io_base_phys + size)) {
1192                         unsigned long base =
1193                                 (unsigned long)hose->io_base_virt - _IO_BASE;
1194                         return base + (address - hose->io_base_phys);
1195                 }
1196         }
1197         return (unsigned int)-1;
1198 }
1199 EXPORT_SYMBOL(pci_address_to_pio);
1200
1201 /*
1202  * Null PCI config access functions, for the case when we can't
1203  * find a hose.
1204  */
1205 #define NULL_PCI_OP(rw, size, type)                                     \
1206 static int                                                              \
1207 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1208 {                                                                       \
1209         return PCIBIOS_DEVICE_NOT_FOUND;                                \
1210 }
1211
1212 static int
1213 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1214                  int len, u32 *val)
1215 {
1216         return PCIBIOS_DEVICE_NOT_FOUND;
1217 }
1218
1219 static int
1220 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1221                   int len, u32 val)
1222 {
1223         return PCIBIOS_DEVICE_NOT_FOUND;
1224 }
1225
1226 static struct pci_ops null_pci_ops =
1227 {
1228         null_read_config,
1229         null_write_config
1230 };
1231
1232 /*
1233  * These functions are used early on before PCI scanning is done
1234  * and all of the pci_dev and pci_bus structures have been created.
1235  */
1236 static struct pci_bus *
1237 fake_pci_bus(struct pci_controller *hose, int busnr)
1238 {
1239         static struct pci_bus bus;
1240
1241         if (hose == 0) {
1242                 hose = pci_bus_to_hose(busnr);
1243                 if (hose == 0)
1244                         printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1245         }
1246         bus.number = busnr;
1247         bus.sysdata = hose;
1248         bus.ops = hose? hose->ops: &null_pci_ops;
1249         return &bus;
1250 }
1251
1252 #define EARLY_PCI_OP(rw, size, type)                                    \
1253 int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1254                                int devfn, int offset, type value)       \
1255 {                                                                       \
1256         return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1257                                             devfn, offset, value);      \
1258 }
1259
1260 EARLY_PCI_OP(read, byte, u8 *)
1261 EARLY_PCI_OP(read, word, u16 *)
1262 EARLY_PCI_OP(read, dword, u32 *)
1263 EARLY_PCI_OP(write, byte, u8)
1264 EARLY_PCI_OP(write, word, u16)
1265 EARLY_PCI_OP(write, dword, u32)