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libata: PIIX3 support
[linux-2.6/s3c2410-cpufreq.git] / drivers / ata / ata_piix.c
blob33bbeac785cc339e0e3beadd0ed27df2d7e41726
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00ac7"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
107
108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
110
111 /* combined mode. if set, PATA is channel 0.
112 * if clear, PATA is channel 1.
113 */
114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
116
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119
120 /* controller IDs */
121 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
123 ich_pata_66 = 2, /* ICH up to 66 Mhz */
124 ich_pata_100 = 3, /* ICH up to UDMA 100 */
125 ich_pata_133 = 4, /* ICH up to UDMA 133 */
126 ich5_sata = 5,
127 ich6_sata = 6,
128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9,
131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
132
133 /* constants for mapping table */
134 P0 = 0, /* port 0 */
135 P1 = 1, /* port 1 */
136 P2 = 2, /* port 2 */
137 P3 = 3, /* port 3 */
138 IDE = -1, /* IDE */
139 NA = -2, /* not avaliable */
140 RV = -3, /* reserved */
141
142 PIIX_AHCI_DEVICE = 6,
143 };
144
145 struct piix_map_db {
146 const u32 mask;
147 const u16 port_enable;
148 const int map[][4];
149 };
150
151 struct piix_host_priv {
152 const int *map;
153 };
154
155 static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
157 static void piix_host_stop(struct ata_host *host);
158 static void piix_pata_error_handler(struct ata_port *ap);
159 static void ich_pata_error_handler(struct ata_port *ap);
160 static void piix_sata_error_handler(struct ata_port *ap);
161 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
162 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
163 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
164
165 static unsigned int in_module_init = 1;
166
167 static const struct pci_device_id piix_pci_tbl[] = {
168 #ifdef ATA_ENABLE_PATA
169 /* Intel PIIX3 for the 430HX etc */
170 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
171 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
172 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
173 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
174 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
175 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
176 /* Intel PIIX4 */
177 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178 /* Intel PIIX4 */
179 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 /* Intel PIIX */
181 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel ICH (i810, i815, i840) UDMA 66*/
183 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
184 /* Intel ICH0 : UDMA 33*/
185 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
186 /* Intel ICH2M */
187 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
189 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190 /* Intel ICH3M */
191 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH3 (E7500/1) UDMA 100 */
193 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
195 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH5 */
198 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
199 /* C-ICH (i810E2) */
200 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
202 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* ICH6 (and 6) (i915) UDMA 100 */
204 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* ICH7/7-R (i945, i975) UDMA 100*/
206 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
207 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 #endif
209
210 /* NOTE: The following PCI ids must be kept in sync with the
211 * list in drivers/pci/quirks.c.
212 */
213
214 /* 82801EB (ICH5) */
215 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
216 /* 82801EB (ICH5) */
217 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
218 /* 6300ESB (ICH5 variant with broken PCS present bits) */
219 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
220 /* 6300ESB pretending RAID */
221 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
222 /* 82801FB/FW (ICH6/ICH6W) */
223 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
224 /* 82801FR/FRW (ICH6R/ICH6RW) */
225 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
226 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
227 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
228 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
229 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
230 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
231 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
232 /* Enterprise Southbridge 2 (631xESB/632xESB) */
233 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
234 /* SATA Controller 1 IDE (ICH8) */
235 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
236 /* SATA Controller 2 IDE (ICH8) */
237 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
238 /* Mobile SATA Controller IDE (ICH8M) */
239 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
240 /* SATA Controller IDE (ICH9) */
241 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
242 /* SATA Controller IDE (ICH9) */
243 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
244 /* SATA Controller IDE (ICH9) */
245 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
246 /* SATA Controller IDE (ICH9M) */
247 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
248 /* SATA Controller IDE (ICH9M) */
249 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
250 /* SATA Controller IDE (ICH9M) */
251 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
252
253 { } /* terminate list */
254 };
255
256 static struct pci_driver piix_pci_driver = {
257 .name = DRV_NAME,
258 .id_table = piix_pci_tbl,
259 .probe = piix_init_one,
260 .remove = ata_pci_remove_one,
261 .suspend = ata_pci_device_suspend,
262 .resume = ata_pci_device_resume,
263 };
264
265 static struct scsi_host_template piix_sht = {
266 .module = THIS_MODULE,
267 .name = DRV_NAME,
268 .ioctl = ata_scsi_ioctl,
269 .queuecommand = ata_scsi_queuecmd,
270 .can_queue = ATA_DEF_QUEUE,
271 .this_id = ATA_SHT_THIS_ID,
272 .sg_tablesize = LIBATA_MAX_PRD,
273 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
274 .emulated = ATA_SHT_EMULATED,
275 .use_clustering = ATA_SHT_USE_CLUSTERING,
276 .proc_name = DRV_NAME,
277 .dma_boundary = ATA_DMA_BOUNDARY,
278 .slave_configure = ata_scsi_slave_config,
279 .slave_destroy = ata_scsi_slave_destroy,
280 .bios_param = ata_std_bios_param,
281 .resume = ata_scsi_device_resume,
282 .suspend = ata_scsi_device_suspend,
283 };
284
285 static const struct ata_port_operations piix_pata_ops = {
286 .port_disable = ata_port_disable,
287 .set_piomode = piix_set_piomode,
288 .set_dmamode = piix_set_dmamode,
289 .mode_filter = ata_pci_default_filter,
290
291 .tf_load = ata_tf_load,
292 .tf_read = ata_tf_read,
293 .check_status = ata_check_status,
294 .exec_command = ata_exec_command,
295 .dev_select = ata_std_dev_select,
296
297 .bmdma_setup = ata_bmdma_setup,
298 .bmdma_start = ata_bmdma_start,
299 .bmdma_stop = ata_bmdma_stop,
300 .bmdma_status = ata_bmdma_status,
301 .qc_prep = ata_qc_prep,
302 .qc_issue = ata_qc_issue_prot,
303 .data_xfer = ata_pio_data_xfer,
304
305 .freeze = ata_bmdma_freeze,
306 .thaw = ata_bmdma_thaw,
307 .error_handler = piix_pata_error_handler,
308 .post_internal_cmd = ata_bmdma_post_internal_cmd,
309
310 .irq_handler = ata_interrupt,
311 .irq_clear = ata_bmdma_irq_clear,
312
313 .port_start = ata_port_start,
314 .port_stop = ata_port_stop,
315 .host_stop = piix_host_stop,
316 };
317
318 static const struct ata_port_operations ich_pata_ops = {
319 .port_disable = ata_port_disable,
320 .set_piomode = piix_set_piomode,
321 .set_dmamode = ich_set_dmamode,
322 .mode_filter = ata_pci_default_filter,
323
324 .tf_load = ata_tf_load,
325 .tf_read = ata_tf_read,
326 .check_status = ata_check_status,
327 .exec_command = ata_exec_command,
328 .dev_select = ata_std_dev_select,
329
330 .bmdma_setup = ata_bmdma_setup,
331 .bmdma_start = ata_bmdma_start,
332 .bmdma_stop = ata_bmdma_stop,
333 .bmdma_status = ata_bmdma_status,
334 .qc_prep = ata_qc_prep,
335 .qc_issue = ata_qc_issue_prot,
336 .data_xfer = ata_pio_data_xfer,
337
338 .freeze = ata_bmdma_freeze,
339 .thaw = ata_bmdma_thaw,
340 .error_handler = ich_pata_error_handler,
341 .post_internal_cmd = ata_bmdma_post_internal_cmd,
342
343 .irq_handler = ata_interrupt,
344 .irq_clear = ata_bmdma_irq_clear,
345
346 .port_start = ata_port_start,
347 .port_stop = ata_port_stop,
348 .host_stop = piix_host_stop,
349 };
350
351 static const struct ata_port_operations piix_sata_ops = {
352 .port_disable = ata_port_disable,
353
354 .tf_load = ata_tf_load,
355 .tf_read = ata_tf_read,
356 .check_status = ata_check_status,
357 .exec_command = ata_exec_command,
358 .dev_select = ata_std_dev_select,
359
360 .bmdma_setup = ata_bmdma_setup,
361 .bmdma_start = ata_bmdma_start,
362 .bmdma_stop = ata_bmdma_stop,
363 .bmdma_status = ata_bmdma_status,
364 .qc_prep = ata_qc_prep,
365 .qc_issue = ata_qc_issue_prot,
366 .data_xfer = ata_pio_data_xfer,
367
368 .freeze = ata_bmdma_freeze,
369 .thaw = ata_bmdma_thaw,
370 .error_handler = piix_sata_error_handler,
371 .post_internal_cmd = ata_bmdma_post_internal_cmd,
372
373 .irq_handler = ata_interrupt,
374 .irq_clear = ata_bmdma_irq_clear,
375
376 .port_start = ata_port_start,
377 .port_stop = ata_port_stop,
378 .host_stop = piix_host_stop,
379 };
380
381 static const struct piix_map_db ich5_map_db = {
382 .mask = 0x7,
383 .port_enable = 0x3,
384 .map = {
385 /* PM PS SM SS MAP */
386 { P0, NA, P1, NA }, /* 000b */
387 { P1, NA, P0, NA }, /* 001b */
388 { RV, RV, RV, RV },
389 { RV, RV, RV, RV },
390 { P0, P1, IDE, IDE }, /* 100b */
391 { P1, P0, IDE, IDE }, /* 101b */
392 { IDE, IDE, P0, P1 }, /* 110b */
393 { IDE, IDE, P1, P0 }, /* 111b */
394 },
395 };
396
397 static const struct piix_map_db ich6_map_db = {
398 .mask = 0x3,
399 .port_enable = 0xf,
400 .map = {
401 /* PM PS SM SS MAP */
402 { P0, P2, P1, P3 }, /* 00b */
403 { IDE, IDE, P1, P3 }, /* 01b */
404 { P0, P2, IDE, IDE }, /* 10b */
405 { RV, RV, RV, RV },
406 },
407 };
408
409 static const struct piix_map_db ich6m_map_db = {
410 .mask = 0x3,
411 .port_enable = 0x5,
412
413 /* Map 01b isn't specified in the doc but some notebooks use
414 * it anyway. MAP 01b have been spotted on both ICH6M and
415 * ICH7M.
416 */
417 .map = {
418 /* PM PS SM SS MAP */
419 { P0, P2, RV, RV }, /* 00b */
420 { IDE, IDE, P1, P3 }, /* 01b */
421 { P0, P2, IDE, IDE }, /* 10b */
422 { RV, RV, RV, RV },
423 },
424 };
425
426 static const struct piix_map_db ich8_map_db = {
427 .mask = 0x3,
428 .port_enable = 0x3,
429 .map = {
430 /* PM PS SM SS MAP */
431 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
432 { RV, RV, RV, RV },
433 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
434 { RV, RV, RV, RV },
435 },
436 };
437
438 static const struct piix_map_db *piix_map_db_table[] = {
439 [ich5_sata] = &ich5_map_db,
440 [ich6_sata] = &ich6_map_db,
441 [ich6_sata_ahci] = &ich6_map_db,
442 [ich6m_sata_ahci] = &ich6m_map_db,
443 [ich8_sata_ahci] = &ich8_map_db,
444 };
445
446 static struct ata_port_info piix_port_info[] = {
447 /* piix_pata_33: 0: PIIX4 at 33MHz */
448 {
449 .sht = &piix_sht,
450 .flags = PIIX_PATA_FLAGS,
451 .pio_mask = 0x1f, /* pio0-4 */
452 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
453 .udma_mask = ATA_UDMA_MASK_40C,
454 .port_ops = &piix_pata_ops,
455 },
456
457 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
458 {
459 .sht = &piix_sht,
460 .flags = PIIX_PATA_FLAGS,
461 .pio_mask = 0x1f, /* pio 0-4 */
462 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
463 .udma_mask = ATA_UDMA2, /* UDMA33 */
464 .port_ops = &ich_pata_ops,
465 },
466 /* ich_pata_66: 2 ICH controllers up to 66MHz */
467 {
468 .sht = &piix_sht,
469 .flags = PIIX_PATA_FLAGS,
470 .pio_mask = 0x1f, /* pio 0-4 */
471 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
472 .udma_mask = ATA_UDMA4,
473 .port_ops = &ich_pata_ops,
474 },
475
476 /* ich_pata_100: 3 */
477 {
478 .sht = &piix_sht,
479 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
480 .pio_mask = 0x1f, /* pio0-4 */
481 .mwdma_mask = 0x06, /* mwdma1-2 */
482 .udma_mask = ATA_UDMA5, /* udma0-5 */
483 .port_ops = &ich_pata_ops,
484 },
485
486 /* ich_pata_133: 4 ICH with full UDMA6 */
487 {
488 .sht = &piix_sht,
489 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
490 .pio_mask = 0x1f, /* pio 0-4 */
491 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
492 .udma_mask = ATA_UDMA6, /* UDMA133 */
493 .port_ops = &ich_pata_ops,
494 },
495
496 /* ich5_sata: 5 */
497 {
498 .sht = &piix_sht,
499 .flags = PIIX_SATA_FLAGS,
500 .pio_mask = 0x1f, /* pio0-4 */
501 .mwdma_mask = 0x07, /* mwdma0-2 */
502 .udma_mask = 0x7f, /* udma0-6 */
503 .port_ops = &piix_sata_ops,
504 },
505
506 /* ich6_sata: 6 */
507 {
508 .sht = &piix_sht,
509 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
510 .pio_mask = 0x1f, /* pio0-4 */
511 .mwdma_mask = 0x07, /* mwdma0-2 */
512 .udma_mask = 0x7f, /* udma0-6 */
513 .port_ops = &piix_sata_ops,
514 },
515
516 /* ich6_sata_ahci: 7 */
517 {
518 .sht = &piix_sht,
519 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
520 PIIX_FLAG_AHCI,
521 .pio_mask = 0x1f, /* pio0-4 */
522 .mwdma_mask = 0x07, /* mwdma0-2 */
523 .udma_mask = 0x7f, /* udma0-6 */
524 .port_ops = &piix_sata_ops,
525 },
526
527 /* ich6m_sata_ahci: 8 */
528 {
529 .sht = &piix_sht,
530 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
531 PIIX_FLAG_AHCI,
532 .pio_mask = 0x1f, /* pio0-4 */
533 .mwdma_mask = 0x07, /* mwdma0-2 */
534 .udma_mask = 0x7f, /* udma0-6 */
535 .port_ops = &piix_sata_ops,
536 },
537
538 /* ich8_sata_ahci: 9 */
539 {
540 .sht = &piix_sht,
541 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
542 PIIX_FLAG_AHCI,
543 .pio_mask = 0x1f, /* pio0-4 */
544 .mwdma_mask = 0x07, /* mwdma0-2 */
545 .udma_mask = 0x7f, /* udma0-6 */
546 .port_ops = &piix_sata_ops,
547 },
548
549 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
550 {
551 .sht = &piix_sht,
552 .flags = PIIX_PATA_FLAGS,
553 .pio_mask = 0x1f, /* pio0-4 */
554 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
555 .port_ops = &piix_pata_ops,
556 },
557 };
558
559 static struct pci_bits piix_enable_bits[] = {
560 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
561 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
562 };
563
564 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
565 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
566 MODULE_LICENSE("GPL");
567 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
568 MODULE_VERSION(DRV_VERSION);
569
570 struct ich_laptop {
571 u16 device;
572 u16 subvendor;
573 u16 subdevice;
574 };
575
576 /*
577 * List of laptops that use short cables rather than 80 wire
578 */
579
580 static const struct ich_laptop ich_laptop[] = {
581 /* devid, subvendor, subdev */
582 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
583 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
584 /* end marker */
585 { 0, }
586 };
587
588 /**
589 * piix_pata_cbl_detect - Probe host controller cable detect info
590 * @ap: Port for which cable detect info is desired
591 *
592 * Read 80c cable indicator from ATA PCI device's PCI config
593 * register. This register is normally set by firmware (BIOS).
594 *
595 * LOCKING:
596 * None (inherited from caller).
597 */
598
599 static void ich_pata_cbl_detect(struct ata_port *ap)
600 {
601 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
602 const struct ich_laptop *lap = &ich_laptop[0];
603 u8 tmp, mask;
604
605 /* no 80c support in host controller? */
606 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
607 goto cbl40;
608
609 /* Check for specials - Acer Aspire 5602WLMi */
610 while (lap->device) {
611 if (lap->device == pdev->device &&
612 lap->subvendor == pdev->subsystem_vendor &&
613 lap->subdevice == pdev->subsystem_device) {
614 ap->cbl = ATA_CBL_PATA40_SHORT;
615 return;
616 }
617 lap++;
618 }
619
620 /* check BIOS cable detect results */
621 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
622 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
623 if ((tmp & mask) == 0)
624 goto cbl40;
625
626 ap->cbl = ATA_CBL_PATA80;
627 return;
628
629 cbl40:
630 ap->cbl = ATA_CBL_PATA40;
631 }
632
633 /**
634 * piix_pata_prereset - prereset for PATA host controller
635 * @ap: Target port
636 *
637 *
638 * LOCKING:
639 * None (inherited from caller).
640 */
641 static int piix_pata_prereset(struct ata_port *ap)
642 {
643 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
644
645 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
646 return -ENOENT;
647
648 ap->cbl = ATA_CBL_PATA40;
649 return ata_std_prereset(ap);
650 }
651
652 static void piix_pata_error_handler(struct ata_port *ap)
653 {
654 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
655 ata_std_postreset);
656 }
657
658
659 /**
660 * ich_pata_prereset - prereset for PATA host controller
661 * @ap: Target port
662 *
663 *
664 * LOCKING:
665 * None (inherited from caller).
666 */
667 static int ich_pata_prereset(struct ata_port *ap)
668 {
669 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
670
671 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
672 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
673 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
674 return 0;
675 }
676
677 ich_pata_cbl_detect(ap);
678
679 return ata_std_prereset(ap);
680 }
681
682 static void ich_pata_error_handler(struct ata_port *ap)
683 {
684 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
685 ata_std_postreset);
686 }
687
688 static void piix_sata_error_handler(struct ata_port *ap)
689 {
690 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
691 ata_std_postreset);
692 }
693
694 /**
695 * piix_set_piomode - Initialize host controller PATA PIO timings
696 * @ap: Port whose timings we are configuring
697 * @adev: um
698 *
699 * Set PIO mode for device, in host controller PCI config space.
700 *
701 * LOCKING:
702 * None (inherited from caller).
703 */
704
705 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
706 {
707 unsigned int pio = adev->pio_mode - XFER_PIO_0;
708 struct pci_dev *dev = to_pci_dev(ap->host->dev);
709 unsigned int is_slave = (adev->devno != 0);
710 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
711 unsigned int slave_port = 0x44;
712 u16 master_data;
713 u8 slave_data;
714 u8 udma_enable;
715 int control = 0;
716
717 /*
718 * See Intel Document 298600-004 for the timing programing rules
719 * for ICH controllers.
720 */
721
722 static const /* ISP RTC */
723 u8 timings[][2] = { { 0, 0 },
724 { 0, 0 },
725 { 1, 0 },
726 { 2, 1 },
727 { 2, 3 }, };
728
729 if (pio >= 2)
730 control |= 1; /* TIME1 enable */
731 if (ata_pio_need_iordy(adev))
732 control |= 2; /* IE enable */
733
734 /* Intel specifies that the PPE functionality is for disk only */
735 if (adev->class == ATA_DEV_ATA)
736 control |= 4; /* PPE enable */
737
738 pci_read_config_word(dev, master_port, &master_data);
739 if (is_slave) {
740 /* Enable SITRE (seperate slave timing register) */
741 master_data |= 0x4000;
742 /* enable PPE1, IE1 and TIME1 as needed */
743 master_data |= (control << 4);
744 pci_read_config_byte(dev, slave_port, &slave_data);
745 slave_data &= (ap->port_no ? 0x0f : 0xf0);
746 /* Load the timing nibble for this slave */
747 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
748 } else {
749 /* Master keeps the bits in a different format */
750 master_data &= 0xccf8;
751 /* Enable PPE, IE and TIME as appropriate */
752 master_data |= control;
753 master_data |=
754 (timings[pio][0] << 12) |
755 (timings[pio][1] << 8);
756 }
757 pci_write_config_word(dev, master_port, master_data);
758 if (is_slave)
759 pci_write_config_byte(dev, slave_port, slave_data);
760
761 /* Ensure the UDMA bit is off - it will be turned back on if
762 UDMA is selected */
763
764 if (ap->udma_mask) {
765 pci_read_config_byte(dev, 0x48, &udma_enable);
766 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
767 pci_write_config_byte(dev, 0x48, udma_enable);
768 }
769 }
770
771 /**
772 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
773 * @ap: Port whose timings we are configuring
774 * @adev: Drive in question
775 * @udma: udma mode, 0 - 6
776 * @isich: set if the chip is an ICH device
777 *
778 * Set UDMA mode for device, in host controller PCI config space.
779 *
780 * LOCKING:
781 * None (inherited from caller).
782 */
783
784 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
785 {
786 struct pci_dev *dev = to_pci_dev(ap->host->dev);
787 u8 master_port = ap->port_no ? 0x42 : 0x40;
788 u16 master_data;
789 u8 speed = adev->dma_mode;
790 int devid = adev->devno + 2 * ap->port_no;
791 u8 udma_enable;
792
793 static const /* ISP RTC */
794 u8 timings[][2] = { { 0, 0 },
795 { 0, 0 },
796 { 1, 0 },
797 { 2, 1 },
798 { 2, 3 }, };
799
800 pci_read_config_word(dev, master_port, &master_data);
801 if (ap->udma_mask)
802 pci_read_config_byte(dev, 0x48, &udma_enable);
803
804 if (speed >= XFER_UDMA_0) {
805 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
806 u16 udma_timing;
807 u16 ideconf;
808 int u_clock, u_speed;
809
810 /*
811 * UDMA is handled by a combination of clock switching and
812 * selection of dividers
813 *
814 * Handy rule: Odd modes are UDMATIMx 01, even are 02
815 * except UDMA0 which is 00
816 */
817 u_speed = min(2 - (udma & 1), udma);
818 if (udma == 5)
819 u_clock = 0x1000; /* 100Mhz */
820 else if (udma > 2)
821 u_clock = 1; /* 66Mhz */
822 else
823 u_clock = 0; /* 33Mhz */
824
825 udma_enable |= (1 << devid);
826
827 /* Load the CT/RP selection */
828 pci_read_config_word(dev, 0x4A, &udma_timing);
829 udma_timing &= ~(3 << (4 * devid));
830 udma_timing |= u_speed << (4 * devid);
831 pci_write_config_word(dev, 0x4A, udma_timing);
832
833 if (isich) {
834 /* Select a 33/66/100Mhz clock */
835 pci_read_config_word(dev, 0x54, &ideconf);
836 ideconf &= ~(0x1001 << devid);
837 ideconf |= u_clock << devid;
838 /* For ICH or later we should set bit 10 for better
839 performance (WR_PingPong_En) */
840 pci_write_config_word(dev, 0x54, ideconf);
841 }
842 } else {
843 /*
844 * MWDMA is driven by the PIO timings. We must also enable
845 * IORDY unconditionally along with TIME1. PPE has already
846 * been set when the PIO timing was set.
847 */
848 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
849 unsigned int control;
850 u8 slave_data;
851 const unsigned int needed_pio[3] = {
852 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
853 };
854 int pio = needed_pio[mwdma] - XFER_PIO_0;
855
856 control = 3; /* IORDY|TIME1 */
857
858 /* If the drive MWDMA is faster than it can do PIO then
859 we must force PIO into PIO0 */
860
861 if (adev->pio_mode < needed_pio[mwdma])
862 /* Enable DMA timing only */
863 control |= 8; /* PIO cycles in PIO0 */
864
865 if (adev->devno) { /* Slave */
866 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
867 master_data |= control << 4;
868 pci_read_config_byte(dev, 0x44, &slave_data);
869 slave_data &= (0x0F + 0xE1 * ap->port_no);
870 /* Load the matching timing */
871 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
872 pci_write_config_byte(dev, 0x44, slave_data);
873 } else { /* Master */
874 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
875 and master timing bits */
876 master_data |= control;
877 master_data |=
878 (timings[pio][0] << 12) |
879 (timings[pio][1] << 8);
880 }
881 udma_enable &= ~(1 << devid);
882 pci_write_config_word(dev, master_port, master_data);
883 }
884 /* Don't scribble on 0x48 if the controller does not support UDMA */
885 if (ap->udma_mask)
886 pci_write_config_byte(dev, 0x48, udma_enable);
887 }
888
889 /**
890 * piix_set_dmamode - Initialize host controller PATA DMA timings
891 * @ap: Port whose timings we are configuring
892 * @adev: um
893 *
894 * Set MW/UDMA mode for device, in host controller PCI config space.
895 *
896 * LOCKING:
897 * None (inherited from caller).
898 */
899
900 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
901 {
902 do_pata_set_dmamode(ap, adev, 0);
903 }
904
905 /**
906 * ich_set_dmamode - Initialize host controller PATA DMA timings
907 * @ap: Port whose timings we are configuring
908 * @adev: um
909 *
910 * Set MW/UDMA mode for device, in host controller PCI config space.
911 *
912 * LOCKING:
913 * None (inherited from caller).
914 */
915
916 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
917 {
918 do_pata_set_dmamode(ap, adev, 1);
919 }
920
921 #define AHCI_PCI_BAR 5
922 #define AHCI_GLOBAL_CTL 0x04
923 #define AHCI_ENABLE (1 << 31)
924 static int piix_disable_ahci(struct pci_dev *pdev)
925 {
926 void __iomem *mmio;
927 u32 tmp;
928 int rc = 0;
929
930 /* BUG: pci_enable_device has not yet been called. This
931 * works because this device is usually set up by BIOS.
932 */
933
934 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
935 !pci_resource_len(pdev, AHCI_PCI_BAR))
936 return 0;
937
938 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
939 if (!mmio)
940 return -ENOMEM;
941
942 tmp = readl(mmio + AHCI_GLOBAL_CTL);
943 if (tmp & AHCI_ENABLE) {
944 tmp &= ~AHCI_ENABLE;
945 writel(tmp, mmio + AHCI_GLOBAL_CTL);
946
947 tmp = readl(mmio + AHCI_GLOBAL_CTL);
948 if (tmp & AHCI_ENABLE)
949 rc = -EIO;
950 }
951
952 pci_iounmap(pdev, mmio);
953 return rc;
954 }
955
956 /**
957 * piix_check_450nx_errata - Check for problem 450NX setup
958 * @ata_dev: the PCI device to check
959 *
960 * Check for the present of 450NX errata #19 and errata #25. If
961 * they are found return an error code so we can turn off DMA
962 */
963
964 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
965 {
966 struct pci_dev *pdev = NULL;
967 u16 cfg;
968 u8 rev;
969 int no_piix_dma = 0;
970
971 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
972 {
973 /* Look for 450NX PXB. Check for problem configurations
974 A PCI quirk checks bit 6 already */
975 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
976 pci_read_config_word(pdev, 0x41, &cfg);
977 /* Only on the original revision: IDE DMA can hang */
978 if (rev == 0x00)
979 no_piix_dma = 1;
980 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
981 else if (cfg & (1<<14) && rev < 5)
982 no_piix_dma = 2;
983 }
984 if (no_piix_dma)
985 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
986 if (no_piix_dma == 2)
987 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
988 return no_piix_dma;
989 }
990
991 static void __devinit piix_init_pcs(struct pci_dev *pdev,
992 struct ata_port_info *pinfo,
993 const struct piix_map_db *map_db)
994 {
995 u16 pcs, new_pcs;
996
997 pci_read_config_word(pdev, ICH5_PCS, &pcs);
998
999 new_pcs = pcs | map_db->port_enable;
1000
1001 if (new_pcs != pcs) {
1002 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1003 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1004 msleep(150);
1005 }
1006 }
1007
1008 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1009 struct ata_port_info *pinfo,
1010 const struct piix_map_db *map_db)
1011 {
1012 struct piix_host_priv *hpriv = pinfo[0].private_data;
1013 const unsigned int *map;
1014 int i, invalid_map = 0;
1015 u8 map_value;
1016
1017 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1018
1019 map = map_db->map[map_value & map_db->mask];
1020
1021 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1022 for (i = 0; i < 4; i++) {
1023 switch (map[i]) {
1024 case RV:
1025 invalid_map = 1;
1026 printk(" XX");
1027 break;
1028
1029 case NA:
1030 printk(" --");
1031 break;
1032
1033 case IDE:
1034 WARN_ON((i & 1) || map[i + 1] != IDE);
1035 pinfo[i / 2] = piix_port_info[ich_pata_100];
1036 pinfo[i / 2].private_data = hpriv;
1037 i++;
1038 printk(" IDE IDE");
1039 break;
1040
1041 default:
1042 printk(" P%d", map[i]);
1043 if (i & 1)
1044 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1045 break;
1046 }
1047 }
1048 printk(" ]\n");
1049
1050 if (invalid_map)
1051 dev_printk(KERN_ERR, &pdev->dev,
1052 "invalid MAP value %u\n", map_value);
1053
1054 hpriv->map = map;
1055 }
1056
1057 /**
1058 * piix_init_one - Register PIIX ATA PCI device with kernel services
1059 * @pdev: PCI device to register
1060 * @ent: Entry in piix_pci_tbl matching with @pdev
1061 *
1062 * Called from kernel PCI layer. We probe for combined mode (sigh),
1063 * and then hand over control to libata, for it to do the rest.
1064 *
1065 * LOCKING:
1066 * Inherited from PCI layer (may sleep).
1067 *
1068 * RETURNS:
1069 * Zero on success, or -ERRNO value.
1070 */
1071
1072 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1073 {
1074 static int printed_version;
1075 struct ata_port_info port_info[2];
1076 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
1077 struct piix_host_priv *hpriv;
1078 unsigned long port_flags;
1079
1080 if (!printed_version++)
1081 dev_printk(KERN_DEBUG, &pdev->dev,
1082 "version " DRV_VERSION "\n");
1083
1084 /* no hotplugging support (FIXME) */
1085 if (!in_module_init)
1086 return -ENODEV;
1087
1088 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1089 if (!hpriv)
1090 return -ENOMEM;
1091
1092 port_info[0] = piix_port_info[ent->driver_data];
1093 port_info[1] = piix_port_info[ent->driver_data];
1094 port_info[0].private_data = hpriv;
1095 port_info[1].private_data = hpriv;
1096
1097 port_flags = port_info[0].flags;
1098
1099 if (port_flags & PIIX_FLAG_AHCI) {
1100 u8 tmp;
1101 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1102 if (tmp == PIIX_AHCI_DEVICE) {
1103 int rc = piix_disable_ahci(pdev);
1104 if (rc)
1105 return rc;
1106 }
1107 }
1108
1109 /* Initialize SATA map */
1110 if (port_flags & ATA_FLAG_SATA) {
1111 piix_init_sata_map(pdev, port_info,
1112 piix_map_db_table[ent->driver_data]);
1113 piix_init_pcs(pdev, port_info,
1114 piix_map_db_table[ent->driver_data]);
1115 }
1116
1117 /* On ICH5, some BIOSen disable the interrupt using the
1118 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1119 * On ICH6, this bit has the same effect, but only when
1120 * MSI is disabled (and it is disabled, as we don't use
1121 * message-signalled interrupts currently).
1122 */
1123 if (port_flags & PIIX_FLAG_CHECKINTR)
1124 pci_intx(pdev, 1);
1125
1126 if (piix_check_450nx_errata(pdev)) {
1127 /* This writes into the master table but it does not
1128 really matter for this errata as we will apply it to
1129 all the PIIX devices on the board */
1130 port_info[0].mwdma_mask = 0;
1131 port_info[0].udma_mask = 0;
1132 port_info[1].mwdma_mask = 0;
1133 port_info[1].udma_mask = 0;
1134 }
1135 return ata_pci_init_one(pdev, ppinfo, 2);
1136 }
1137
1138 static void piix_host_stop(struct ata_host *host)
1139 {
1140 struct piix_host_priv *hpriv = host->private_data;
1141
1142 ata_host_stop(host);
1143
1144 kfree(hpriv);
1145 }
1146
1147 static int __init piix_init(void)
1148 {
1149 int rc;
1150
1151 DPRINTK("pci_register_driver\n");
1152 rc = pci_register_driver(&piix_pci_driver);
1153 if (rc)
1154 return rc;
1155
1156 in_module_init = 0;
1157
1158 DPRINTK("done\n");
1159 return 0;
1160 }
1161
1162 static void __exit piix_exit(void)
1163 {
1164 pci_unregister_driver(&piix_pci_driver);
1165 }
1166
1167 module_init(piix_init);
1168 module_exit(piix_exit);
cpufreq for S3C2410