Linux 2.6.25
[linux-2.6/s3c2410-cpufreq.git] / drivers / acpi / processor_idle.c
blob788da9781f80ffb5311b396cd3557b0786376dcd
1 /*
2 * processor_idle - idle state submodule to the ACPI processor driver
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
8 * - Added processor hotplug support
9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
10 * - Added support for C3 on SMP
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/cpufreq.h>
35 #include <linux/proc_fs.h>
36 #include <linux/seq_file.h>
37 #include <linux/acpi.h>
38 #include <linux/dmi.h>
39 #include <linux/moduleparam.h>
40 #include <linux/sched.h> /* need_resched() */
41 #include <linux/pm_qos_params.h>
42 #include <linux/clockchips.h>
43 #include <linux/cpuidle.h>
46 * Include the apic definitions for x86 to have the APIC timer related defines
47 * available also for UP (on SMP it gets magically included via linux/smp.h).
48 * asm/acpi.h is not an option, as it would require more include magic. Also
49 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
51 #ifdef CONFIG_X86
52 #include <asm/apic.h>
53 #endif
55 #include <asm/io.h>
56 #include <asm/uaccess.h>
58 #include <acpi/acpi_bus.h>
59 #include <acpi/processor.h>
61 #define ACPI_PROCESSOR_COMPONENT 0x01000000
62 #define ACPI_PROCESSOR_CLASS "processor"
63 #define _COMPONENT ACPI_PROCESSOR_COMPONENT
64 ACPI_MODULE_NAME("processor_idle");
65 #define ACPI_PROCESSOR_FILE_POWER "power"
66 #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000)
67 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
68 #ifndef CONFIG_CPU_IDLE
69 #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */
70 #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */
71 static void (*pm_idle_save) (void) __read_mostly;
72 #else
73 #define C2_OVERHEAD 1 /* 1us */
74 #define C3_OVERHEAD 1 /* 1us */
75 #endif
76 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
78 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
79 #ifdef CONFIG_CPU_IDLE
80 module_param(max_cstate, uint, 0000);
81 #else
82 module_param(max_cstate, uint, 0644);
83 #endif
84 static unsigned int nocst __read_mostly;
85 module_param(nocst, uint, 0000);
87 #ifndef CONFIG_CPU_IDLE
89 * bm_history -- bit-mask with a bit per jiffy of bus-master activity
90 * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms
91 * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms
92 * 100 HZ: 0x0000000F: 4 jiffies = 40ms
93 * reduce history for more aggressive entry into C3
95 static unsigned int bm_history __read_mostly =
96 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1));
97 module_param(bm_history, uint, 0644);
99 static int acpi_processor_set_power_policy(struct acpi_processor *pr);
101 #else /* CONFIG_CPU_IDLE */
102 static unsigned int latency_factor __read_mostly = 2;
103 module_param(latency_factor, uint, 0644);
104 #endif
107 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
108 * For now disable this. Probably a bug somewhere else.
110 * To skip this limit, boot/load with a large max_cstate limit.
112 static int set_max_cstate(const struct dmi_system_id *id)
114 if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
115 return 0;
117 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
118 " Override with \"processor.max_cstate=%d\"\n", id->ident,
119 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
121 max_cstate = (long)id->driver_data;
123 return 0;
126 /* Actually this shouldn't be __cpuinitdata, would be better to fix the
127 callers to only run once -AK */
128 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
129 { set_max_cstate, "IBM ThinkPad R40e", {
130 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
131 DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1},
132 { set_max_cstate, "IBM ThinkPad R40e", {
133 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
134 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1},
135 { set_max_cstate, "IBM ThinkPad R40e", {
136 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
137 DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1},
138 { set_max_cstate, "IBM ThinkPad R40e", {
139 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
140 DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1},
141 { set_max_cstate, "IBM ThinkPad R40e", {
142 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
143 DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1},
144 { set_max_cstate, "IBM ThinkPad R40e", {
145 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
146 DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1},
147 { set_max_cstate, "IBM ThinkPad R40e", {
148 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
149 DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1},
150 { set_max_cstate, "IBM ThinkPad R40e", {
151 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
152 DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1},
153 { set_max_cstate, "IBM ThinkPad R40e", {
154 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
155 DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1},
156 { set_max_cstate, "IBM ThinkPad R40e", {
157 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
158 DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1},
159 { set_max_cstate, "IBM ThinkPad R40e", {
160 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
161 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1},
162 { set_max_cstate, "IBM ThinkPad R40e", {
163 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
164 DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1},
165 { set_max_cstate, "IBM ThinkPad R40e", {
166 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
167 DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1},
168 { set_max_cstate, "IBM ThinkPad R40e", {
169 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
170 DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1},
171 { set_max_cstate, "IBM ThinkPad R40e", {
172 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
173 DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1},
174 { set_max_cstate, "IBM ThinkPad R40e", {
175 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
176 DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1},
177 { set_max_cstate, "Medion 41700", {
178 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
179 DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1},
180 { set_max_cstate, "Clevo 5600D", {
181 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
182 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
183 (void *)2},
187 static inline u32 ticks_elapsed(u32 t1, u32 t2)
189 if (t2 >= t1)
190 return (t2 - t1);
191 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
192 return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
193 else
194 return ((0xFFFFFFFF - t1) + t2);
197 static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2)
199 if (t2 >= t1)
200 return PM_TIMER_TICKS_TO_US(t2 - t1);
201 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
202 return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
203 else
204 return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2);
208 * Callers should disable interrupts before the call and enable
209 * interrupts after return.
211 static void acpi_safe_halt(void)
213 current_thread_info()->status &= ~TS_POLLING;
215 * TS_POLLING-cleared state must be visible before we
216 * test NEED_RESCHED:
218 smp_mb();
219 if (!need_resched()) {
220 safe_halt();
221 local_irq_disable();
223 current_thread_info()->status |= TS_POLLING;
226 #ifndef CONFIG_CPU_IDLE
228 static void
229 acpi_processor_power_activate(struct acpi_processor *pr,
230 struct acpi_processor_cx *new)
232 struct acpi_processor_cx *old;
234 if (!pr || !new)
235 return;
237 old = pr->power.state;
239 if (old)
240 old->promotion.count = 0;
241 new->demotion.count = 0;
243 /* Cleanup from old state. */
244 if (old) {
245 switch (old->type) {
246 case ACPI_STATE_C3:
247 /* Disable bus master reload */
248 if (new->type != ACPI_STATE_C3 && pr->flags.bm_check)
249 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
250 break;
254 /* Prepare to use new state. */
255 switch (new->type) {
256 case ACPI_STATE_C3:
257 /* Enable bus master reload */
258 if (old->type != ACPI_STATE_C3 && pr->flags.bm_check)
259 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
260 break;
263 pr->power.state = new;
265 return;
268 static atomic_t c3_cpu_count;
270 /* Common C-state entry for C2, C3, .. */
271 static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
273 if (cstate->entry_method == ACPI_CSTATE_FFH) {
274 /* Call into architectural FFH based C-state */
275 acpi_processor_ffh_cstate_enter(cstate);
276 } else {
277 int unused;
278 /* IO port based C-state */
279 inb(cstate->address);
280 /* Dummy wait op - must do something useless after P_LVL2 read
281 because chipsets cannot guarantee that STPCLK# signal
282 gets asserted in time to freeze execution properly. */
283 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
286 #endif /* !CONFIG_CPU_IDLE */
288 #ifdef ARCH_APICTIMER_STOPS_ON_C3
291 * Some BIOS implementations switch to C3 in the published C2 state.
292 * This seems to be a common problem on AMD boxen, but other vendors
293 * are affected too. We pick the most conservative approach: we assume
294 * that the local APIC stops in both C2 and C3.
296 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
297 struct acpi_processor_cx *cx)
299 struct acpi_processor_power *pwr = &pr->power;
300 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
303 * Check, if one of the previous states already marked the lapic
304 * unstable
306 if (pwr->timer_broadcast_on_state < state)
307 return;
309 if (cx->type >= type)
310 pr->power.timer_broadcast_on_state = state;
313 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr)
315 unsigned long reason;
317 reason = pr->power.timer_broadcast_on_state < INT_MAX ?
318 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
320 clockevents_notify(reason, &pr->id);
323 /* Power(C) State timer broadcast control */
324 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
325 struct acpi_processor_cx *cx,
326 int broadcast)
328 int state = cx - pr->power.states;
330 if (state >= pr->power.timer_broadcast_on_state) {
331 unsigned long reason;
333 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER :
334 CLOCK_EVT_NOTIFY_BROADCAST_EXIT;
335 clockevents_notify(reason, &pr->id);
339 #else
341 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
342 struct acpi_processor_cx *cstate) { }
343 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { }
344 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
345 struct acpi_processor_cx *cx,
346 int broadcast)
350 #endif
353 * Suspend / resume control
355 static int acpi_idle_suspend;
357 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
359 acpi_idle_suspend = 1;
360 return 0;
363 int acpi_processor_resume(struct acpi_device * device)
365 acpi_idle_suspend = 0;
366 return 0;
369 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
370 static int tsc_halts_in_c(int state)
372 switch (boot_cpu_data.x86_vendor) {
373 case X86_VENDOR_AMD:
375 * AMD Fam10h TSC will tick in all
376 * C/P/S0/S1 states when this bit is set.
378 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
379 return 0;
380 /*FALL THROUGH*/
381 case X86_VENDOR_INTEL:
382 /* Several cases known where TSC halts in C2 too */
383 default:
384 return state > ACPI_STATE_C1;
387 #endif
389 #ifndef CONFIG_CPU_IDLE
390 static void acpi_processor_idle(void)
392 struct acpi_processor *pr = NULL;
393 struct acpi_processor_cx *cx = NULL;
394 struct acpi_processor_cx *next_state = NULL;
395 int sleep_ticks = 0;
396 u32 t1, t2 = 0;
399 * Interrupts must be disabled during bus mastering calculations and
400 * for C2/C3 transitions.
402 local_irq_disable();
404 pr = processors[smp_processor_id()];
405 if (!pr) {
406 local_irq_enable();
407 return;
411 * Check whether we truly need to go idle, or should
412 * reschedule:
414 if (unlikely(need_resched())) {
415 local_irq_enable();
416 return;
419 cx = pr->power.state;
420 if (!cx || acpi_idle_suspend) {
421 if (pm_idle_save)
422 pm_idle_save();
423 else
424 acpi_safe_halt();
426 if (irqs_disabled())
427 local_irq_enable();
429 return;
433 * Check BM Activity
434 * -----------------
435 * Check for bus mastering activity (if required), record, and check
436 * for demotion.
438 if (pr->flags.bm_check) {
439 u32 bm_status = 0;
440 unsigned long diff = jiffies - pr->power.bm_check_timestamp;
442 if (diff > 31)
443 diff = 31;
445 pr->power.bm_activity <<= diff;
447 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
448 if (bm_status) {
449 pr->power.bm_activity |= 0x1;
450 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
453 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
454 * the true state of bus mastering activity; forcing us to
455 * manually check the BMIDEA bit of each IDE channel.
457 else if (errata.piix4.bmisx) {
458 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
459 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
460 pr->power.bm_activity |= 0x1;
463 pr->power.bm_check_timestamp = jiffies;
466 * If bus mastering is or was active this jiffy, demote
467 * to avoid a faulty transition. Note that the processor
468 * won't enter a low-power state during this call (to this
469 * function) but should upon the next.
471 * TBD: A better policy might be to fallback to the demotion
472 * state (use it for this quantum only) istead of
473 * demoting -- and rely on duration as our sole demotion
474 * qualification. This may, however, introduce DMA
475 * issues (e.g. floppy DMA transfer overrun/underrun).
477 if ((pr->power.bm_activity & 0x1) &&
478 cx->demotion.threshold.bm) {
479 local_irq_enable();
480 next_state = cx->demotion.state;
481 goto end;
485 #ifdef CONFIG_HOTPLUG_CPU
487 * Check for P_LVL2_UP flag before entering C2 and above on
488 * an SMP system. We do it here instead of doing it at _CST/P_LVL
489 * detection phase, to work cleanly with logical CPU hotplug.
491 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
492 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
493 cx = &pr->power.states[ACPI_STATE_C1];
494 #endif
497 * Sleep:
498 * ------
499 * Invoke the current Cx state to put the processor to sleep.
501 if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) {
502 current_thread_info()->status &= ~TS_POLLING;
504 * TS_POLLING-cleared state must be visible before we
505 * test NEED_RESCHED:
507 smp_mb();
508 if (need_resched()) {
509 current_thread_info()->status |= TS_POLLING;
510 local_irq_enable();
511 return;
515 switch (cx->type) {
517 case ACPI_STATE_C1:
519 * Invoke C1.
520 * Use the appropriate idle routine, the one that would
521 * be used without acpi C-states.
523 if (pm_idle_save)
524 pm_idle_save();
525 else
526 acpi_safe_halt();
529 * TBD: Can't get time duration while in C1, as resumes
530 * go to an ISR rather than here. Need to instrument
531 * base interrupt handler.
533 * Note: the TSC better not stop in C1, sched_clock() will
534 * skew otherwise.
536 sleep_ticks = 0xFFFFFFFF;
537 if (irqs_disabled())
538 local_irq_enable();
540 break;
542 case ACPI_STATE_C2:
543 /* Get start time (ticks) */
544 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
545 /* Tell the scheduler that we are going deep-idle: */
546 sched_clock_idle_sleep_event();
547 /* Invoke C2 */
548 acpi_state_timer_broadcast(pr, cx, 1);
549 acpi_cstate_enter(cx);
550 /* Get end time (ticks) */
551 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
553 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
554 /* TSC halts in C2, so notify users */
555 if (tsc_halts_in_c(ACPI_STATE_C2))
556 mark_tsc_unstable("possible TSC halt in C2");
557 #endif
558 /* Compute time (ticks) that we were actually asleep */
559 sleep_ticks = ticks_elapsed(t1, t2);
561 /* Tell the scheduler how much we idled: */
562 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
564 /* Re-enable interrupts */
565 local_irq_enable();
566 /* Do not account our idle-switching overhead: */
567 sleep_ticks -= cx->latency_ticks + C2_OVERHEAD;
569 current_thread_info()->status |= TS_POLLING;
570 acpi_state_timer_broadcast(pr, cx, 0);
571 break;
573 case ACPI_STATE_C3:
574 acpi_unlazy_tlb(smp_processor_id());
576 * Must be done before busmaster disable as we might
577 * need to access HPET !
579 acpi_state_timer_broadcast(pr, cx, 1);
581 * disable bus master
582 * bm_check implies we need ARB_DIS
583 * !bm_check implies we need cache flush
584 * bm_control implies whether we can do ARB_DIS
586 * That leaves a case where bm_check is set and bm_control is
587 * not set. In that case we cannot do much, we enter C3
588 * without doing anything.
590 if (pr->flags.bm_check && pr->flags.bm_control) {
591 if (atomic_inc_return(&c3_cpu_count) ==
592 num_online_cpus()) {
594 * All CPUs are trying to go to C3
595 * Disable bus master arbitration
597 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
599 } else if (!pr->flags.bm_check) {
600 /* SMP with no shared cache... Invalidate cache */
601 ACPI_FLUSH_CPU_CACHE();
604 /* Get start time (ticks) */
605 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
606 /* Invoke C3 */
607 /* Tell the scheduler that we are going deep-idle: */
608 sched_clock_idle_sleep_event();
609 acpi_cstate_enter(cx);
610 /* Get end time (ticks) */
611 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
612 if (pr->flags.bm_check && pr->flags.bm_control) {
613 /* Enable bus master arbitration */
614 atomic_dec(&c3_cpu_count);
615 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
618 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
619 /* TSC halts in C3, so notify users */
620 if (tsc_halts_in_c(ACPI_STATE_C3))
621 mark_tsc_unstable("TSC halts in C3");
622 #endif
623 /* Compute time (ticks) that we were actually asleep */
624 sleep_ticks = ticks_elapsed(t1, t2);
625 /* Tell the scheduler how much we idled: */
626 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
628 /* Re-enable interrupts */
629 local_irq_enable();
630 /* Do not account our idle-switching overhead: */
631 sleep_ticks -= cx->latency_ticks + C3_OVERHEAD;
633 current_thread_info()->status |= TS_POLLING;
634 acpi_state_timer_broadcast(pr, cx, 0);
635 break;
637 default:
638 local_irq_enable();
639 return;
641 cx->usage++;
642 if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0))
643 cx->time += sleep_ticks;
645 next_state = pr->power.state;
647 #ifdef CONFIG_HOTPLUG_CPU
648 /* Don't do promotion/demotion */
649 if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) &&
650 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) {
651 next_state = cx;
652 goto end;
654 #endif
657 * Promotion?
658 * ----------
659 * Track the number of longs (time asleep is greater than threshold)
660 * and promote when the count threshold is reached. Note that bus
661 * mastering activity may prevent promotions.
662 * Do not promote above max_cstate.
664 if (cx->promotion.state &&
665 ((cx->promotion.state - pr->power.states) <= max_cstate)) {
666 if (sleep_ticks > cx->promotion.threshold.ticks &&
667 cx->promotion.state->latency <=
668 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) {
669 cx->promotion.count++;
670 cx->demotion.count = 0;
671 if (cx->promotion.count >=
672 cx->promotion.threshold.count) {
673 if (pr->flags.bm_check) {
674 if (!
675 (pr->power.bm_activity & cx->
676 promotion.threshold.bm)) {
677 next_state =
678 cx->promotion.state;
679 goto end;
681 } else {
682 next_state = cx->promotion.state;
683 goto end;
690 * Demotion?
691 * ---------
692 * Track the number of shorts (time asleep is less than time threshold)
693 * and demote when the usage threshold is reached.
695 if (cx->demotion.state) {
696 if (sleep_ticks < cx->demotion.threshold.ticks) {
697 cx->demotion.count++;
698 cx->promotion.count = 0;
699 if (cx->demotion.count >= cx->demotion.threshold.count) {
700 next_state = cx->demotion.state;
701 goto end;
706 end:
708 * Demote if current state exceeds max_cstate
709 * or if the latency of the current state is unacceptable
711 if ((pr->power.state - pr->power.states) > max_cstate ||
712 pr->power.state->latency >
713 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) {
714 if (cx->demotion.state)
715 next_state = cx->demotion.state;
719 * New Cx State?
720 * -------------
721 * If we're going to start using a new Cx state we must clean up
722 * from the previous and prepare to use the new.
724 if (next_state != pr->power.state)
725 acpi_processor_power_activate(pr, next_state);
728 static int acpi_processor_set_power_policy(struct acpi_processor *pr)
730 unsigned int i;
731 unsigned int state_is_set = 0;
732 struct acpi_processor_cx *lower = NULL;
733 struct acpi_processor_cx *higher = NULL;
734 struct acpi_processor_cx *cx;
737 if (!pr)
738 return -EINVAL;
741 * This function sets the default Cx state policy (OS idle handler).
742 * Our scheme is to promote quickly to C2 but more conservatively
743 * to C3. We're favoring C2 for its characteristics of low latency
744 * (quick response), good power savings, and ability to allow bus
745 * mastering activity. Note that the Cx state policy is completely
746 * customizable and can be altered dynamically.
749 /* startup state */
750 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
751 cx = &pr->power.states[i];
752 if (!cx->valid)
753 continue;
755 if (!state_is_set)
756 pr->power.state = cx;
757 state_is_set++;
758 break;
761 if (!state_is_set)
762 return -ENODEV;
764 /* demotion */
765 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
766 cx = &pr->power.states[i];
767 if (!cx->valid)
768 continue;
770 if (lower) {
771 cx->demotion.state = lower;
772 cx->demotion.threshold.ticks = cx->latency_ticks;
773 cx->demotion.threshold.count = 1;
774 if (cx->type == ACPI_STATE_C3)
775 cx->demotion.threshold.bm = bm_history;
778 lower = cx;
781 /* promotion */
782 for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) {
783 cx = &pr->power.states[i];
784 if (!cx->valid)
785 continue;
787 if (higher) {
788 cx->promotion.state = higher;
789 cx->promotion.threshold.ticks = cx->latency_ticks;
790 if (cx->type >= ACPI_STATE_C2)
791 cx->promotion.threshold.count = 4;
792 else
793 cx->promotion.threshold.count = 10;
794 if (higher->type == ACPI_STATE_C3)
795 cx->promotion.threshold.bm = bm_history;
798 higher = cx;
801 return 0;
803 #endif /* !CONFIG_CPU_IDLE */
805 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
808 if (!pr)
809 return -EINVAL;
811 if (!pr->pblk)
812 return -ENODEV;
814 /* if info is obtained from pblk/fadt, type equals state */
815 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
816 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
818 #ifndef CONFIG_HOTPLUG_CPU
820 * Check for P_LVL2_UP flag before entering C2 and above on
821 * an SMP system.
823 if ((num_online_cpus() > 1) &&
824 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
825 return -ENODEV;
826 #endif
828 /* determine C2 and C3 address from pblk */
829 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
830 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
832 /* determine latencies from FADT */
833 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency;
834 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency;
836 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
837 "lvl2[0x%08x] lvl3[0x%08x]\n",
838 pr->power.states[ACPI_STATE_C2].address,
839 pr->power.states[ACPI_STATE_C3].address));
841 return 0;
844 static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
846 if (!pr->power.states[ACPI_STATE_C1].valid) {
847 /* set the first C-State to C1 */
848 /* all processors need to support C1 */
849 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
850 pr->power.states[ACPI_STATE_C1].valid = 1;
852 /* the C0 state only exists as a filler in our array */
853 pr->power.states[ACPI_STATE_C0].valid = 1;
854 return 0;
857 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
859 acpi_status status = 0;
860 acpi_integer count;
861 int current_count;
862 int i;
863 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
864 union acpi_object *cst;
867 if (nocst)
868 return -ENODEV;
870 current_count = 0;
872 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
873 if (ACPI_FAILURE(status)) {
874 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
875 return -ENODEV;
878 cst = buffer.pointer;
880 /* There must be at least 2 elements */
881 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
882 printk(KERN_ERR PREFIX "not enough elements in _CST\n");
883 status = -EFAULT;
884 goto end;
887 count = cst->package.elements[0].integer.value;
889 /* Validate number of power states. */
890 if (count < 1 || count != cst->package.count - 1) {
891 printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
892 status = -EFAULT;
893 goto end;
896 /* Tell driver that at least _CST is supported. */
897 pr->flags.has_cst = 1;
899 for (i = 1; i <= count; i++) {
900 union acpi_object *element;
901 union acpi_object *obj;
902 struct acpi_power_register *reg;
903 struct acpi_processor_cx cx;
905 memset(&cx, 0, sizeof(cx));
907 element = &(cst->package.elements[i]);
908 if (element->type != ACPI_TYPE_PACKAGE)
909 continue;
911 if (element->package.count != 4)
912 continue;
914 obj = &(element->package.elements[0]);
916 if (obj->type != ACPI_TYPE_BUFFER)
917 continue;
919 reg = (struct acpi_power_register *)obj->buffer.pointer;
921 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
922 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
923 continue;
925 /* There should be an easy way to extract an integer... */
926 obj = &(element->package.elements[1]);
927 if (obj->type != ACPI_TYPE_INTEGER)
928 continue;
930 cx.type = obj->integer.value;
932 * Some buggy BIOSes won't list C1 in _CST -
933 * Let acpi_processor_get_power_info_default() handle them later
935 if (i == 1 && cx.type != ACPI_STATE_C1)
936 current_count++;
938 cx.address = reg->address;
939 cx.index = current_count + 1;
941 cx.entry_method = ACPI_CSTATE_SYSTEMIO;
942 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
943 if (acpi_processor_ffh_cstate_probe
944 (pr->id, &cx, reg) == 0) {
945 cx.entry_method = ACPI_CSTATE_FFH;
946 } else if (cx.type == ACPI_STATE_C1) {
948 * C1 is a special case where FIXED_HARDWARE
949 * can be handled in non-MWAIT way as well.
950 * In that case, save this _CST entry info.
951 * Otherwise, ignore this info and continue.
953 cx.entry_method = ACPI_CSTATE_HALT;
954 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
955 } else {
956 continue;
958 } else {
959 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x",
960 cx.address);
964 obj = &(element->package.elements[2]);
965 if (obj->type != ACPI_TYPE_INTEGER)
966 continue;
968 cx.latency = obj->integer.value;
970 obj = &(element->package.elements[3]);
971 if (obj->type != ACPI_TYPE_INTEGER)
972 continue;
974 cx.power = obj->integer.value;
976 current_count++;
977 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
980 * We support total ACPI_PROCESSOR_MAX_POWER - 1
981 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
983 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
984 printk(KERN_WARNING
985 "Limiting number of power states to max (%d)\n",
986 ACPI_PROCESSOR_MAX_POWER);
987 printk(KERN_WARNING
988 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
989 break;
993 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
994 current_count));
996 /* Validate number of power states discovered */
997 if (current_count < 2)
998 status = -EFAULT;
1000 end:
1001 kfree(buffer.pointer);
1003 return status;
1006 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
1009 if (!cx->address)
1010 return;
1013 * C2 latency must be less than or equal to 100
1014 * microseconds.
1016 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
1017 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1018 "latency too large [%d]\n", cx->latency));
1019 return;
1023 * Otherwise we've met all of our C2 requirements.
1024 * Normalize the C2 latency to expidite policy
1026 cx->valid = 1;
1028 #ifndef CONFIG_CPU_IDLE
1029 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1030 #else
1031 cx->latency_ticks = cx->latency;
1032 #endif
1034 return;
1037 static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
1038 struct acpi_processor_cx *cx)
1040 static int bm_check_flag;
1043 if (!cx->address)
1044 return;
1047 * C3 latency must be less than or equal to 1000
1048 * microseconds.
1050 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
1051 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1052 "latency too large [%d]\n", cx->latency));
1053 return;
1057 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
1058 * DMA transfers are used by any ISA device to avoid livelock.
1059 * Note that we could disable Type-F DMA (as recommended by
1060 * the erratum), but this is known to disrupt certain ISA
1061 * devices thus we take the conservative approach.
1063 else if (errata.piix4.fdma) {
1064 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1065 "C3 not supported on PIIX4 with Type-F DMA\n"));
1066 return;
1069 /* All the logic here assumes flags.bm_check is same across all CPUs */
1070 if (!bm_check_flag) {
1071 /* Determine whether bm_check is needed based on CPU */
1072 acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
1073 bm_check_flag = pr->flags.bm_check;
1074 } else {
1075 pr->flags.bm_check = bm_check_flag;
1078 if (pr->flags.bm_check) {
1079 if (!pr->flags.bm_control) {
1080 if (pr->flags.has_cst != 1) {
1081 /* bus mastering control is necessary */
1082 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1083 "C3 support requires BM control\n"));
1084 return;
1085 } else {
1086 /* Here we enter C3 without bus mastering */
1087 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1088 "C3 support without BM control\n"));
1091 } else {
1093 * WBINVD should be set in fadt, for C3 state to be
1094 * supported on when bm_check is not required.
1096 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
1097 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1098 "Cache invalidation should work properly"
1099 " for C3 to be enabled on SMP systems\n"));
1100 return;
1102 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
1106 * Otherwise we've met all of our C3 requirements.
1107 * Normalize the C3 latency to expidite policy. Enable
1108 * checking of bus mastering status (bm_check) so we can
1109 * use this in our C3 policy
1111 cx->valid = 1;
1113 #ifndef CONFIG_CPU_IDLE
1114 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1115 #else
1116 cx->latency_ticks = cx->latency;
1117 #endif
1119 return;
1122 static int acpi_processor_power_verify(struct acpi_processor *pr)
1124 unsigned int i;
1125 unsigned int working = 0;
1127 pr->power.timer_broadcast_on_state = INT_MAX;
1129 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1130 struct acpi_processor_cx *cx = &pr->power.states[i];
1132 switch (cx->type) {
1133 case ACPI_STATE_C1:
1134 cx->valid = 1;
1135 break;
1137 case ACPI_STATE_C2:
1138 acpi_processor_power_verify_c2(cx);
1139 if (cx->valid)
1140 acpi_timer_check_state(i, pr, cx);
1141 break;
1143 case ACPI_STATE_C3:
1144 acpi_processor_power_verify_c3(pr, cx);
1145 if (cx->valid)
1146 acpi_timer_check_state(i, pr, cx);
1147 break;
1150 if (cx->valid)
1151 working++;
1154 acpi_propagate_timer_broadcast(pr);
1156 return (working);
1159 static int acpi_processor_get_power_info(struct acpi_processor *pr)
1161 unsigned int i;
1162 int result;
1165 /* NOTE: the idle thread may not be running while calling
1166 * this function */
1168 /* Zero initialize all the C-states info. */
1169 memset(pr->power.states, 0, sizeof(pr->power.states));
1171 result = acpi_processor_get_power_info_cst(pr);
1172 if (result == -ENODEV)
1173 result = acpi_processor_get_power_info_fadt(pr);
1175 if (result)
1176 return result;
1178 acpi_processor_get_power_info_default(pr);
1180 pr->power.count = acpi_processor_power_verify(pr);
1182 #ifndef CONFIG_CPU_IDLE
1184 * Set Default Policy
1185 * ------------------
1186 * Now that we know which states are supported, set the default
1187 * policy. Note that this policy can be changed dynamically
1188 * (e.g. encourage deeper sleeps to conserve battery life when
1189 * not on AC).
1191 result = acpi_processor_set_power_policy(pr);
1192 if (result)
1193 return result;
1194 #endif
1197 * if one state of type C2 or C3 is available, mark this
1198 * CPU as being "idle manageable"
1200 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1201 if (pr->power.states[i].valid) {
1202 pr->power.count = i;
1203 if (pr->power.states[i].type >= ACPI_STATE_C2)
1204 pr->flags.power = 1;
1208 return 0;
1211 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset)
1213 struct acpi_processor *pr = seq->private;
1214 unsigned int i;
1217 if (!pr)
1218 goto end;
1220 seq_printf(seq, "active state: C%zd\n"
1221 "max_cstate: C%d\n"
1222 "bus master activity: %08x\n"
1223 "maximum allowed latency: %d usec\n",
1224 pr->power.state ? pr->power.state - pr->power.states : 0,
1225 max_cstate, (unsigned)pr->power.bm_activity,
1226 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY));
1228 seq_puts(seq, "states:\n");
1230 for (i = 1; i <= pr->power.count; i++) {
1231 seq_printf(seq, " %cC%d: ",
1232 (&pr->power.states[i] ==
1233 pr->power.state ? '*' : ' '), i);
1235 if (!pr->power.states[i].valid) {
1236 seq_puts(seq, "<not supported>\n");
1237 continue;
1240 switch (pr->power.states[i].type) {
1241 case ACPI_STATE_C1:
1242 seq_printf(seq, "type[C1] ");
1243 break;
1244 case ACPI_STATE_C2:
1245 seq_printf(seq, "type[C2] ");
1246 break;
1247 case ACPI_STATE_C3:
1248 seq_printf(seq, "type[C3] ");
1249 break;
1250 default:
1251 seq_printf(seq, "type[--] ");
1252 break;
1255 if (pr->power.states[i].promotion.state)
1256 seq_printf(seq, "promotion[C%zd] ",
1257 (pr->power.states[i].promotion.state -
1258 pr->power.states));
1259 else
1260 seq_puts(seq, "promotion[--] ");
1262 if (pr->power.states[i].demotion.state)
1263 seq_printf(seq, "demotion[C%zd] ",
1264 (pr->power.states[i].demotion.state -
1265 pr->power.states));
1266 else
1267 seq_puts(seq, "demotion[--] ");
1269 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n",
1270 pr->power.states[i].latency,
1271 pr->power.states[i].usage,
1272 (unsigned long long)pr->power.states[i].time);
1275 end:
1276 return 0;
1279 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file)
1281 return single_open(file, acpi_processor_power_seq_show,
1282 PDE(inode)->data);
1285 static const struct file_operations acpi_processor_power_fops = {
1286 .open = acpi_processor_power_open_fs,
1287 .read = seq_read,
1288 .llseek = seq_lseek,
1289 .release = single_release,
1292 #ifndef CONFIG_CPU_IDLE
1294 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1296 int result = 0;
1299 if (!pr)
1300 return -EINVAL;
1302 if (nocst) {
1303 return -ENODEV;
1306 if (!pr->flags.power_setup_done)
1307 return -ENODEV;
1309 /* Fall back to the default idle loop */
1310 pm_idle = pm_idle_save;
1311 synchronize_sched(); /* Relies on interrupts forcing exit from idle. */
1313 pr->flags.power = 0;
1314 result = acpi_processor_get_power_info(pr);
1315 if ((pr->flags.power == 1) && (pr->flags.power_setup_done))
1316 pm_idle = acpi_processor_idle;
1318 return result;
1321 #ifdef CONFIG_SMP
1322 static void smp_callback(void *v)
1324 /* we already woke the CPU up, nothing more to do */
1328 * This function gets called when a part of the kernel has a new latency
1329 * requirement. This means we need to get all processors out of their C-state,
1330 * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that
1331 * wakes them all right up.
1333 static int acpi_processor_latency_notify(struct notifier_block *b,
1334 unsigned long l, void *v)
1336 smp_call_function(smp_callback, NULL, 0, 1);
1337 return NOTIFY_OK;
1340 static struct notifier_block acpi_processor_latency_notifier = {
1341 .notifier_call = acpi_processor_latency_notify,
1344 #endif
1346 #else /* CONFIG_CPU_IDLE */
1349 * acpi_idle_bm_check - checks if bus master activity was detected
1351 static int acpi_idle_bm_check(void)
1353 u32 bm_status = 0;
1355 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
1356 if (bm_status)
1357 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
1359 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
1360 * the true state of bus mastering activity; forcing us to
1361 * manually check the BMIDEA bit of each IDE channel.
1363 else if (errata.piix4.bmisx) {
1364 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
1365 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
1366 bm_status = 1;
1368 return bm_status;
1372 * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state
1373 * @pr: the processor
1374 * @target: the new target state
1376 static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr,
1377 struct acpi_processor_cx *target)
1379 if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) {
1380 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
1381 pr->flags.bm_rld_set = 0;
1384 if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) {
1385 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
1386 pr->flags.bm_rld_set = 1;
1391 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry
1392 * @cx: cstate data
1394 * Caller disables interrupt before call and enables interrupt after return.
1396 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx)
1398 if (cx->entry_method == ACPI_CSTATE_FFH) {
1399 /* Call into architectural FFH based C-state */
1400 acpi_processor_ffh_cstate_enter(cx);
1401 } else if (cx->entry_method == ACPI_CSTATE_HALT) {
1402 acpi_safe_halt();
1403 } else {
1404 int unused;
1405 /* IO port based C-state */
1406 inb(cx->address);
1407 /* Dummy wait op - must do something useless after P_LVL2 read
1408 because chipsets cannot guarantee that STPCLK# signal
1409 gets asserted in time to freeze execution properly. */
1410 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
1415 * acpi_idle_enter_c1 - enters an ACPI C1 state-type
1416 * @dev: the target CPU
1417 * @state: the state data
1419 * This is equivalent to the HALT instruction.
1421 static int acpi_idle_enter_c1(struct cpuidle_device *dev,
1422 struct cpuidle_state *state)
1424 u32 t1, t2;
1425 struct acpi_processor *pr;
1426 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1428 pr = processors[smp_processor_id()];
1430 if (unlikely(!pr))
1431 return 0;
1433 local_irq_disable();
1435 /* Do not access any ACPI IO ports in suspend path */
1436 if (acpi_idle_suspend) {
1437 acpi_safe_halt();
1438 local_irq_enable();
1439 return 0;
1442 if (pr->flags.bm_check)
1443 acpi_idle_update_bm_rld(pr, cx);
1445 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1446 acpi_idle_do_entry(cx);
1447 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1449 local_irq_enable();
1450 cx->usage++;
1452 return ticks_elapsed_in_us(t1, t2);
1456 * acpi_idle_enter_simple - enters an ACPI state without BM handling
1457 * @dev: the target CPU
1458 * @state: the state data
1460 static int acpi_idle_enter_simple(struct cpuidle_device *dev,
1461 struct cpuidle_state *state)
1463 struct acpi_processor *pr;
1464 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1465 u32 t1, t2;
1466 int sleep_ticks = 0;
1468 pr = processors[smp_processor_id()];
1470 if (unlikely(!pr))
1471 return 0;
1473 if (acpi_idle_suspend)
1474 return(acpi_idle_enter_c1(dev, state));
1476 local_irq_disable();
1477 current_thread_info()->status &= ~TS_POLLING;
1479 * TS_POLLING-cleared state must be visible before we test
1480 * NEED_RESCHED:
1482 smp_mb();
1484 if (unlikely(need_resched())) {
1485 current_thread_info()->status |= TS_POLLING;
1486 local_irq_enable();
1487 return 0;
1491 * Must be done before busmaster disable as we might need to
1492 * access HPET !
1494 acpi_state_timer_broadcast(pr, cx, 1);
1496 if (pr->flags.bm_check)
1497 acpi_idle_update_bm_rld(pr, cx);
1499 if (cx->type == ACPI_STATE_C3)
1500 ACPI_FLUSH_CPU_CACHE();
1502 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1503 /* Tell the scheduler that we are going deep-idle: */
1504 sched_clock_idle_sleep_event();
1505 acpi_idle_do_entry(cx);
1506 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1508 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1509 /* TSC could halt in idle, so notify users */
1510 if (tsc_halts_in_c(cx->type))
1511 mark_tsc_unstable("TSC halts in idle");;
1512 #endif
1513 sleep_ticks = ticks_elapsed(t1, t2);
1515 /* Tell the scheduler how much we idled: */
1516 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1518 local_irq_enable();
1519 current_thread_info()->status |= TS_POLLING;
1521 cx->usage++;
1523 acpi_state_timer_broadcast(pr, cx, 0);
1524 cx->time += sleep_ticks;
1525 return ticks_elapsed_in_us(t1, t2);
1528 static int c3_cpu_count;
1529 static DEFINE_SPINLOCK(c3_lock);
1532 * acpi_idle_enter_bm - enters C3 with proper BM handling
1533 * @dev: the target CPU
1534 * @state: the state data
1536 * If BM is detected, the deepest non-C3 idle state is entered instead.
1538 static int acpi_idle_enter_bm(struct cpuidle_device *dev,
1539 struct cpuidle_state *state)
1541 struct acpi_processor *pr;
1542 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1543 u32 t1, t2;
1544 int sleep_ticks = 0;
1546 pr = processors[smp_processor_id()];
1548 if (unlikely(!pr))
1549 return 0;
1551 if (acpi_idle_suspend)
1552 return(acpi_idle_enter_c1(dev, state));
1554 if (acpi_idle_bm_check()) {
1555 if (dev->safe_state) {
1556 return dev->safe_state->enter(dev, dev->safe_state);
1557 } else {
1558 local_irq_disable();
1559 acpi_safe_halt();
1560 local_irq_enable();
1561 return 0;
1565 local_irq_disable();
1566 current_thread_info()->status &= ~TS_POLLING;
1568 * TS_POLLING-cleared state must be visible before we test
1569 * NEED_RESCHED:
1571 smp_mb();
1573 if (unlikely(need_resched())) {
1574 current_thread_info()->status |= TS_POLLING;
1575 local_irq_enable();
1576 return 0;
1579 acpi_unlazy_tlb(smp_processor_id());
1581 /* Tell the scheduler that we are going deep-idle: */
1582 sched_clock_idle_sleep_event();
1584 * Must be done before busmaster disable as we might need to
1585 * access HPET !
1587 acpi_state_timer_broadcast(pr, cx, 1);
1589 acpi_idle_update_bm_rld(pr, cx);
1592 * disable bus master
1593 * bm_check implies we need ARB_DIS
1594 * !bm_check implies we need cache flush
1595 * bm_control implies whether we can do ARB_DIS
1597 * That leaves a case where bm_check is set and bm_control is
1598 * not set. In that case we cannot do much, we enter C3
1599 * without doing anything.
1601 if (pr->flags.bm_check && pr->flags.bm_control) {
1602 spin_lock(&c3_lock);
1603 c3_cpu_count++;
1604 /* Disable bus master arbitration when all CPUs are in C3 */
1605 if (c3_cpu_count == num_online_cpus())
1606 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
1607 spin_unlock(&c3_lock);
1608 } else if (!pr->flags.bm_check) {
1609 ACPI_FLUSH_CPU_CACHE();
1612 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1613 acpi_idle_do_entry(cx);
1614 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1616 /* Re-enable bus master arbitration */
1617 if (pr->flags.bm_check && pr->flags.bm_control) {
1618 spin_lock(&c3_lock);
1619 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
1620 c3_cpu_count--;
1621 spin_unlock(&c3_lock);
1624 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1625 /* TSC could halt in idle, so notify users */
1626 if (tsc_halts_in_c(ACPI_STATE_C3))
1627 mark_tsc_unstable("TSC halts in idle");
1628 #endif
1629 sleep_ticks = ticks_elapsed(t1, t2);
1630 /* Tell the scheduler how much we idled: */
1631 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1633 local_irq_enable();
1634 current_thread_info()->status |= TS_POLLING;
1636 cx->usage++;
1638 acpi_state_timer_broadcast(pr, cx, 0);
1639 cx->time += sleep_ticks;
1640 return ticks_elapsed_in_us(t1, t2);
1643 struct cpuidle_driver acpi_idle_driver = {
1644 .name = "acpi_idle",
1645 .owner = THIS_MODULE,
1649 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
1650 * @pr: the ACPI processor
1652 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
1654 int i, count = CPUIDLE_DRIVER_STATE_START;
1655 struct acpi_processor_cx *cx;
1656 struct cpuidle_state *state;
1657 struct cpuidle_device *dev = &pr->power.dev;
1659 if (!pr->flags.power_setup_done)
1660 return -EINVAL;
1662 if (pr->flags.power == 0) {
1663 return -EINVAL;
1666 for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
1667 dev->states[i].name[0] = '\0';
1668 dev->states[i].desc[0] = '\0';
1671 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
1672 cx = &pr->power.states[i];
1673 state = &dev->states[count];
1675 if (!cx->valid)
1676 continue;
1678 #ifdef CONFIG_HOTPLUG_CPU
1679 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
1680 !pr->flags.has_cst &&
1681 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
1682 continue;
1683 #endif
1684 cpuidle_set_statedata(state, cx);
1686 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
1687 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1688 state->exit_latency = cx->latency;
1689 state->target_residency = cx->latency * latency_factor;
1690 state->power_usage = cx->power;
1692 state->flags = 0;
1693 switch (cx->type) {
1694 case ACPI_STATE_C1:
1695 state->flags |= CPUIDLE_FLAG_SHALLOW;
1696 if (cx->entry_method == ACPI_CSTATE_FFH)
1697 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1699 state->enter = acpi_idle_enter_c1;
1700 dev->safe_state = state;
1701 break;
1703 case ACPI_STATE_C2:
1704 state->flags |= CPUIDLE_FLAG_BALANCED;
1705 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1706 state->enter = acpi_idle_enter_simple;
1707 dev->safe_state = state;
1708 break;
1710 case ACPI_STATE_C3:
1711 state->flags |= CPUIDLE_FLAG_DEEP;
1712 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1713 state->flags |= CPUIDLE_FLAG_CHECK_BM;
1714 state->enter = pr->flags.bm_check ?
1715 acpi_idle_enter_bm :
1716 acpi_idle_enter_simple;
1717 break;
1720 count++;
1721 if (count == CPUIDLE_STATE_MAX)
1722 break;
1725 dev->state_count = count;
1727 if (!count)
1728 return -EINVAL;
1730 return 0;
1733 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1735 int ret;
1737 if (!pr)
1738 return -EINVAL;
1740 if (nocst) {
1741 return -ENODEV;
1744 if (!pr->flags.power_setup_done)
1745 return -ENODEV;
1747 cpuidle_pause_and_lock();
1748 cpuidle_disable_device(&pr->power.dev);
1749 acpi_processor_get_power_info(pr);
1750 acpi_processor_setup_cpuidle(pr);
1751 ret = cpuidle_enable_device(&pr->power.dev);
1752 cpuidle_resume_and_unlock();
1754 return ret;
1757 #endif /* CONFIG_CPU_IDLE */
1759 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
1760 struct acpi_device *device)
1762 acpi_status status = 0;
1763 static int first_run;
1764 struct proc_dir_entry *entry = NULL;
1765 unsigned int i;
1768 if (!first_run) {
1769 dmi_check_system(processor_power_dmi_table);
1770 max_cstate = acpi_processor_cstate_check(max_cstate);
1771 if (max_cstate < ACPI_C_STATES_MAX)
1772 printk(KERN_NOTICE
1773 "ACPI: processor limited to max C-state %d\n",
1774 max_cstate);
1775 first_run++;
1776 #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP)
1777 pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY,
1778 &acpi_processor_latency_notifier);
1779 #endif
1782 if (!pr)
1783 return -EINVAL;
1785 if (acpi_gbl_FADT.cst_control && !nocst) {
1786 status =
1787 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8);
1788 if (ACPI_FAILURE(status)) {
1789 ACPI_EXCEPTION((AE_INFO, status,
1790 "Notifying BIOS of _CST ability failed"));
1794 acpi_processor_get_power_info(pr);
1795 pr->flags.power_setup_done = 1;
1798 * Install the idle handler if processor power management is supported.
1799 * Note that we use previously set idle handler will be used on
1800 * platforms that only support C1.
1802 if ((pr->flags.power) && (!boot_option_idle_override)) {
1803 #ifdef CONFIG_CPU_IDLE
1804 acpi_processor_setup_cpuidle(pr);
1805 pr->power.dev.cpu = pr->id;
1806 if (cpuidle_register_device(&pr->power.dev))
1807 return -EIO;
1808 #endif
1810 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id);
1811 for (i = 1; i <= pr->power.count; i++)
1812 if (pr->power.states[i].valid)
1813 printk(" C%d[C%d]", i,
1814 pr->power.states[i].type);
1815 printk(")\n");
1817 #ifndef CONFIG_CPU_IDLE
1818 if (pr->id == 0) {
1819 pm_idle_save = pm_idle;
1820 pm_idle = acpi_processor_idle;
1822 #endif
1825 /* 'power' [R] */
1826 entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1827 S_IRUGO, acpi_device_dir(device));
1828 if (!entry)
1829 return -EIO;
1830 else {
1831 entry->proc_fops = &acpi_processor_power_fops;
1832 entry->data = acpi_driver_data(device);
1833 entry->owner = THIS_MODULE;
1836 return 0;
1839 int acpi_processor_power_exit(struct acpi_processor *pr,
1840 struct acpi_device *device)
1842 #ifdef CONFIG_CPU_IDLE
1843 if ((pr->flags.power) && (!boot_option_idle_override))
1844 cpuidle_unregister_device(&pr->power.dev);
1845 #endif
1846 pr->flags.power_setup_done = 0;
1848 if (acpi_device_dir(device))
1849 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1850 acpi_device_dir(device));
1852 #ifndef CONFIG_CPU_IDLE
1854 /* Unregister the idle handler when processor #0 is removed. */
1855 if (pr->id == 0) {
1856 pm_idle = pm_idle_save;
1859 * We are about to unload the current idle thread pm callback
1860 * (pm_idle), Wait for all processors to update cached/local
1861 * copies of pm_idle before proceeding.
1863 cpu_idle_wait();
1864 #ifdef CONFIG_SMP
1865 pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY,
1866 &acpi_processor_latency_notifier);
1867 #endif
1869 #endif
1871 return 0;