drivers/net/bfin_mac.h

   1 /*
   2  * File:        drivers/net/bfin_mac.c
   3  * Based on:
   4  * Maintainer:
   5  *              Bryan Wu <bryan.wu@analog.com>
   6  *
   7  * Original author:
   8  *              Luke Yang <luke.yang@analog.com>
   9  *
  10  * Created:
  11  * Description:
  12  *
  13  * Modified:
  14  *              Copyright 2004-2006 Analog Devices Inc.
  15  *
  16  * Bugs:        Enter bugs at http://blackfin.uclinux.org/
  17  *
  18  * This program is free software ;  you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation ;  either version 2, or (at your option)
  21  * any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY ;  without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program ;  see the file COPYING.
  30  * If not, write to the Free Software Foundation,
  31  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  32  */
  33
  34 /*
  35  * PHY REGISTER NAMES
  36  */
  37 #define PHYREG_MODECTL          0x0000
  38 #define PHYREG_MODESTAT         0x0001
  39 #define PHYREG_PHYID1           0x0002
  40 #define PHYREG_PHYID2           0x0003
  41 #define PHYREG_ANAR             0x0004
  42 #define PHYREG_ANLPAR           0x0005
  43 #define PHYREG_ANER             0x0006
  44 #define PHYREG_NSR              0x0010
  45 #define PHYREG_LBREMR           0x0011
  46 #define PHYREG_REC              0x0012
  47 #define PHYREG_10CFG            0x0013
  48 #define PHYREG_PHY1_1           0x0014
  49 #define PHYREG_PHY1_2           0x0015
  50 #define PHYREG_PHY2             0x0016
  51 #define PHYREG_TW_1             0x0017
  52 #define PHYREG_TW_2             0x0018
  53 #define PHYREG_TEST             0x0019
  54
  55 #define PHY_RESET               0x8000
  56 #define PHY_ANEG_EN             0x1000
  57 #define PHY_DUPLEX              0x0100
  58 #define PHY_SPD_SET             0x2000
  59
  60 #define BFIN_MAC_CSUM_OFFLOAD
  61
  62 struct dma_descriptor {
  63         struct dma_descriptor *next_dma_desc;
  64         unsigned long start_addr;
  65         unsigned short config;
  66         unsigned short x_count;
  67 };
  68
  69 struct status_area_rx {
  70 #if defined(BFIN_MAC_CSUM_OFFLOAD)
  71         unsigned short ip_hdr_csum;     /* ip header checksum */
  72         /* ip payload(udp or tcp or others) checksum */
  73         unsigned short ip_payload_csum;
  74 #endif
  75         unsigned long status_word;      /* the frame status word */
  76 };
  77
  78 struct status_area_tx {
  79         unsigned long status_word;      /* the frame status word */
  80 };
  81
  82 /* use two descriptors for a packet */
  83 struct net_dma_desc_rx {
  84         struct net_dma_desc_rx *next;
  85         struct sk_buff *skb;
  86         struct dma_descriptor desc_a;
  87         struct dma_descriptor desc_b;
  88         struct status_area_rx status;
  89 };
  90
  91 /* use two descriptors for a packet */
  92 struct net_dma_desc_tx {
  93         struct net_dma_desc_tx *next;
  94         struct sk_buff *skb;
  95         struct dma_descriptor desc_a;
  96         struct dma_descriptor desc_b;
  97         unsigned char packet[1560];
  98         struct status_area_tx status;
  99 };
 100
 101 struct bf537mac_local {
 102         /*
 103          * these are things that the kernel wants me to keep, so users
 104          * can find out semi-useless statistics of how well the card is
 105          * performing
 106          */
 107         struct net_device_stats stats;
 108
 109         int version;
 110
 111         int FlowEnabled;        /* record if data flow is active */
 112         int EtherIntIVG;        /* IVG for the ethernet interrupt */
 113         int RXIVG;              /* IVG for the RX completion */
 114         int TXIVG;              /* IVG for the TX completion */
 115         int PhyAddr;            /* PHY address */
 116         int OpMode;             /* set these bits n the OPMODE regs */
 117         int Port10;             /* set port speed to 10 Mbit/s */
 118         int GenChksums;         /* IP checksums to be calculated */
 119         int NoRcveLnth;         /* dont insert recv length at start of buffer */
 120         int StripPads;          /* remove trailing pad bytes */
 121         int FullDuplex;         /* set full duplex mode */
 122         int Negotiate;          /* enable auto negotiation */
 123         int Loopback;           /* loopback at the PHY */
 124         int Cache;              /* Buffers may be cached */
 125         int FlowControl;        /* flow control active */
 126         int CLKIN;              /* clock in value in MHZ */
 127         unsigned short IntMask; /* interrupt mask */
 128         unsigned char Mac[6];   /* MAC address of the board */
 129         spinlock_t lock;
 130 };
 131
 132 extern void get_bf537_ether_addr(char *addr);