?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
USB: Obscure Maxon BP3-USB Device Support 16d8:6280 for option driver
[linux-2.6/s3c2410-cpufreq.git] / drivers / w1 / masters / ds1wm.c
blob10211e493001582e0a5b27f549a4c9c00f3a6e5a
1 /*
2 * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
3 * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
4 * like hx4700).
5 *
6 * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
7 * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
8 *
9 * Use consistent with the GNU GPL is permitted,
10 * provided that this copyright notice is
11 * preserved in its entirety in all copies and derived works.
12 */
13
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/pm.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/delay.h>
22 #include <linux/ds1wm.h>
23
24 #include <asm/io.h>
25
26 #include "../w1.h"
27 #include "../w1_int.h"
28
29
30 #define DS1WM_CMD 0x00 /* R/W 4 bits command */
31 #define DS1WM_DATA 0x01 /* R/W 8 bits, transmit/receive buffer */
32 #define DS1WM_INT 0x02 /* R/W interrupt status */
33 #define DS1WM_INT_EN 0x03 /* R/W interrupt enable */
34 #define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
35
36 #define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */
37 #define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */
38 #define DS1WM_CMD_DQ_OUTPUT (1 << 2) /* write only - forces bus low */
39 #define DS1WM_CMD_DQ_INPUT (1 << 3) /* read only - reflects state of bus */
40 #define DS1WM_CMD_RST (1 << 5) /* software reset */
41 #define DS1WM_CMD_OD (1 << 7) /* overdrive */
42
43 #define DS1WM_INT_PD (1 << 0) /* presence detect */
44 #define DS1WM_INT_PDR (1 << 1) /* presence detect result */
45 #define DS1WM_INT_TBE (1 << 2) /* tx buffer empty */
46 #define DS1WM_INT_TSRE (1 << 3) /* tx shift register empty */
47 #define DS1WM_INT_RBF (1 << 4) /* rx buffer full */
48 #define DS1WM_INT_RSRF (1 << 5) /* rx shift register full */
49
50 #define DS1WM_INTEN_EPD (1 << 0) /* enable presence detect int */
51 #define DS1WM_INTEN_IAS (1 << 1) /* INTR active state */
52 #define DS1WM_INTEN_ETBE (1 << 2) /* enable tx buffer empty int */
53 #define DS1WM_INTEN_ETMT (1 << 3) /* enable tx shift register empty int */
54 #define DS1WM_INTEN_ERBF (1 << 4) /* enable rx buffer full int */
55 #define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */
56 #define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */
57
58
59 #define DS1WM_TIMEOUT (HZ * 5)
60
61 static struct {
62 unsigned long freq;
63 unsigned long divisor;
64 } freq[] = {
65 { 4000000, 0x8 },
66 { 5000000, 0x2 },
67 { 6000000, 0x5 },
68 { 7000000, 0x3 },
69 { 8000000, 0xc },
70 { 10000000, 0x6 },
71 { 12000000, 0x9 },
72 { 14000000, 0x7 },
73 { 16000000, 0x10 },
74 { 20000000, 0xa },
75 { 24000000, 0xd },
76 { 28000000, 0xb },
77 { 32000000, 0x14 },
78 { 40000000, 0xe },
79 { 48000000, 0x11 },
80 { 56000000, 0xf },
81 { 64000000, 0x18 },
82 { 80000000, 0x12 },
83 { 96000000, 0x15 },
84 { 112000000, 0x13 },
85 { 128000000, 0x1c },
86 };
87
88 struct ds1wm_data {
89 void __iomem *map;
90 int bus_shift; /* # of shifts to calc register offsets */
91 struct platform_device *pdev;
92 struct ds1wm_platform_data *pdata;
93 int irq;
94 int active_high;
95 struct clk *clk;
96 int slave_present;
97 void *reset_complete;
98 void *read_complete;
99 void *write_complete;
100 u8 read_byte; /* last byte received */
101 };
102
103 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
104 u8 val)
105 {
106 __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
107 }
108
109 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
110 {
111 return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
112 }
113
114
115 static irqreturn_t ds1wm_isr(int isr, void *data)
116 {
117 struct ds1wm_data *ds1wm_data = data;
118 u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
119
120 ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
121
122 if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
123 complete(ds1wm_data->reset_complete);
124
125 if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
126 complete(ds1wm_data->write_complete);
127
128 if (intr & DS1WM_INT_RBF) {
129 ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
130 DS1WM_DATA);
131 if (ds1wm_data->read_complete)
132 complete(ds1wm_data->read_complete);
133 }
134
135 return IRQ_HANDLED;
136 }
137
138 static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
139 {
140 unsigned long timeleft;
141 DECLARE_COMPLETION_ONSTACK(reset_done);
142
143 ds1wm_data->reset_complete = &reset_done;
144
145 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
146 (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
147
148 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
149
150 timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
151 ds1wm_data->reset_complete = NULL;
152 if (!timeleft) {
153 dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
154 return 1;
155 }
156
157 /* Wait for the end of the reset. According to the specs, the time
158 * from when the interrupt is asserted to the end of the reset is:
159 * tRSTH - tPDH - tPDL - tPDI
160 * 625 us - 60 us - 240 us - 100 ns = 324.9 us
161 *
162 * We'll wait a bit longer just to be sure.
163 */
164 udelay(500);
165
166 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
167 DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
168 (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
169
170 if (!ds1wm_data->slave_present) {
171 dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
172 return 1;
173 }
174
175 return 0;
176 }
177
178 static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
179 {
180 DECLARE_COMPLETION_ONSTACK(write_done);
181 ds1wm_data->write_complete = &write_done;
182
183 ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
184
185 wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
186 ds1wm_data->write_complete = NULL;
187
188 return 0;
189 }
190
191 static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
192 {
193 DECLARE_COMPLETION_ONSTACK(read_done);
194 ds1wm_data->read_complete = &read_done;
195
196 ds1wm_write(ds1wm_data, write_data);
197 wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
198 ds1wm_data->read_complete = NULL;
199
200 return ds1wm_data->read_byte;
201 }
202
203 static int ds1wm_find_divisor(int gclk)
204 {
205 int i;
206
207 for (i = 0; i < ARRAY_SIZE(freq); i++)
208 if (gclk <= freq[i].freq)
209 return freq[i].divisor;
210
211 return 0;
212 }
213
214 static void ds1wm_up(struct ds1wm_data *ds1wm_data)
215 {
216 int gclk, divisor;
217
218 if (ds1wm_data->pdata->enable)
219 ds1wm_data->pdata->enable(ds1wm_data->pdev);
220
221 gclk = clk_get_rate(ds1wm_data->clk);
222 clk_enable(ds1wm_data->clk);
223 divisor = ds1wm_find_divisor(gclk);
224 if (divisor == 0) {
225 dev_err(&ds1wm_data->pdev->dev,
226 "no suitable divisor for %dHz clock\n", gclk);
227 return;
228 }
229 ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
230
231 /* Let the w1 clock stabilize. */
232 msleep(1);
233
234 ds1wm_reset(ds1wm_data);
235 }
236
237 static void ds1wm_down(struct ds1wm_data *ds1wm_data)
238 {
239 ds1wm_reset(ds1wm_data);
240
241 /* Disable interrupts. */
242 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
243 ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
244
245 if (ds1wm_data->pdata->disable)
246 ds1wm_data->pdata->disable(ds1wm_data->pdev);
247
248 clk_disable(ds1wm_data->clk);
249 }
250
251 /* --------------------------------------------------------------------- */
252 /* w1 methods */
253
254 static u8 ds1wm_read_byte(void *data)
255 {
256 struct ds1wm_data *ds1wm_data = data;
257
258 return ds1wm_read(ds1wm_data, 0xff);
259 }
260
261 static void ds1wm_write_byte(void *data, u8 byte)
262 {
263 struct ds1wm_data *ds1wm_data = data;
264
265 ds1wm_write(ds1wm_data, byte);
266 }
267
268 static u8 ds1wm_reset_bus(void *data)
269 {
270 struct ds1wm_data *ds1wm_data = data;
271
272 ds1wm_reset(ds1wm_data);
273
274 return 0;
275 }
276
277 static void ds1wm_search(void *data, u8 search_type,
278 w1_slave_found_callback slave_found)
279 {
280 struct ds1wm_data *ds1wm_data = data;
281 int i;
282 unsigned long long rom_id;
283
284 /* XXX We need to iterate for multiple devices per the DS1WM docs.
285 * See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
286 if (ds1wm_reset(ds1wm_data))
287 return;
288
289 ds1wm_write(ds1wm_data, search_type);
290 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
291
292 for (rom_id = 0, i = 0; i < 16; i++) {
293
294 unsigned char resp, r, d;
295
296 resp = ds1wm_read(ds1wm_data, 0x00);
297
298 r = ((resp & 0x02) >> 1) |
299 ((resp & 0x08) >> 2) |
300 ((resp & 0x20) >> 3) |
301 ((resp & 0x80) >> 4);
302
303 d = ((resp & 0x01) >> 0) |
304 ((resp & 0x04) >> 1) |
305 ((resp & 0x10) >> 2) |
306 ((resp & 0x40) >> 3);
307
308 rom_id |= (unsigned long long) r << (i * 4);
309
310 }
311 dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
312
313 ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
314 ds1wm_reset(ds1wm_data);
315
316 slave_found(ds1wm_data, rom_id);
317 }
318
319 /* --------------------------------------------------------------------- */
320
321 static struct w1_bus_master ds1wm_master = {
322 .read_byte = ds1wm_read_byte,
323 .write_byte = ds1wm_write_byte,
324 .reset_bus = ds1wm_reset_bus,
325 .search = ds1wm_search,
326 };
327
328 static int ds1wm_probe(struct platform_device *pdev)
329 {
330 struct ds1wm_data *ds1wm_data;
331 struct ds1wm_platform_data *plat;
332 struct resource *res;
333 int ret;
334
335 if (!pdev)
336 return -ENODEV;
337
338 ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL);
339 if (!ds1wm_data)
340 return -ENOMEM;
341
342 platform_set_drvdata(pdev, ds1wm_data);
343
344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
345 if (!res) {
346 ret = -ENXIO;
347 goto err0;
348 }
349 ds1wm_data->map = ioremap(res->start, res->end - res->start + 1);
350 if (!ds1wm_data->map) {
351 ret = -ENOMEM;
352 goto err0;
353 }
354 plat = pdev->dev.platform_data;
355 ds1wm_data->bus_shift = plat->bus_shift;
356 ds1wm_data->pdev = pdev;
357 ds1wm_data->pdata = plat;
358
359 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
360 if (!res) {
361 ret = -ENXIO;
362 goto err1;
363 }
364 ds1wm_data->irq = res->start;
365 ds1wm_data->active_high = plat->active_high;
366
367 if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
368 set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
369 if (res->flags & IORESOURCE_IRQ_LOWEDGE)
370 set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
371
372 ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
373 "ds1wm", ds1wm_data);
374 if (ret)
375 goto err1;
376
377 ds1wm_data->clk = clk_get(&pdev->dev, "ds1wm");
378 if (IS_ERR(ds1wm_data->clk)) {
379 ret = PTR_ERR(ds1wm_data->clk);
380 goto err2;
381 }
382
383 ds1wm_up(ds1wm_data);
384
385 ds1wm_master.data = (void *)ds1wm_data;
386
387 ret = w1_add_master_device(&ds1wm_master);
388 if (ret)
389 goto err3;
390
391 return 0;
392
393 err3:
394 ds1wm_down(ds1wm_data);
395 clk_put(ds1wm_data->clk);
396 err2:
397 free_irq(ds1wm_data->irq, ds1wm_data);
398 err1:
399 iounmap(ds1wm_data->map);
400 err0:
401 kfree(ds1wm_data);
402
403 return ret;
404 }
405
406 #ifdef CONFIG_PM
407 static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
408 {
409 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
410
411 ds1wm_down(ds1wm_data);
412
413 return 0;
414 }
415
416 static int ds1wm_resume(struct platform_device *pdev)
417 {
418 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
419
420 ds1wm_up(ds1wm_data);
421
422 return 0;
423 }
424 #else
425 #define ds1wm_suspend NULL
426 #define ds1wm_resume NULL
427 #endif
428
429 static int ds1wm_remove(struct platform_device *pdev)
430 {
431 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
432
433 w1_remove_master_device(&ds1wm_master);
434 ds1wm_down(ds1wm_data);
435 clk_put(ds1wm_data->clk);
436 free_irq(ds1wm_data->irq, ds1wm_data);
437 iounmap(ds1wm_data->map);
438 kfree(ds1wm_data);
439
440 return 0;
441 }
442
443 static struct platform_driver ds1wm_driver = {
444 .driver = {
445 .name = "ds1wm",
446 },
447 .probe = ds1wm_probe,
448 .remove = ds1wm_remove,
449 .suspend = ds1wm_suspend,
450 .resume = ds1wm_resume
451 };
452
453 static int __init ds1wm_init(void)
454 {
455 printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
456 return platform_driver_register(&ds1wm_driver);
457 }
458
459 static void __exit ds1wm_exit(void)
460 {
461 platform_driver_unregister(&ds1wm_driver);
462 }
463
464 module_init(ds1wm_init);
465 module_exit(ds1wm_exit);
466
467 MODULE_LICENSE("GPL");
468 MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
469 "Matt Reimer <mreimer@vpop.net>");
470 MODULE_DESCRIPTION("DS1WM w1 busmaster driver");
cpufreq for S3C2410